Method for preparing a semiconductor structure, semiconductor structure and semiconductor memory

Abstract

Embodiments of the present application provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes: providing a substrate including a plurality of active regions; forming a plurality of bit line contact mask structures above the plurality of active regions, and each bit line contact mask structure covers at least one active region endpoint; etching downward along the bit line contact mask structures to form node contact holes in the active region endpoints, and filling semiconductor materials in the node contact holes to form first node contact structures; forming a plurality of bit line structures above the plurality of active regions, and continuously filling semiconductor materials in the gaps between the plurality of bit line structures until a second node contact structure is formed. The first node contact structure and the second node contact structure together constitute a node contact structure. In this way, by forming the node contact holes and the first node contact structures in advance, the problem that the node contact structure is prone to filling gaps can be improved, and the electrical performance of the semiconductor can be enhanced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technologies, and particularly to a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. Background Art

[0002] During the process of semiconductor manufacturing, the preparation of a Node Contact (NC) structure is often involved. In related technologies, generally, after preparing a bit line structure, the hole needs to be etched deeper along the NC hole towards the substrate, and polysilicon is filled to form an NC structure. However, in the above preparation process, the NC hole will be relatively long and narrow, and gaps are likely to occur when filling polysilicon, resulting in a decline in the electrical performance of the semiconductor. Summary of the Invention

[0003] This application provides a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory, which can better form a node contact structure and improve the electrical performance of the semiconductor.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of this application provides a method for preparing a semiconductor structure, the method including:

[0006] Providing a substrate, the substrate including a plurality of active regions;

[0007] Forming a plurality of bit line contact mask structures above the plurality of active regions, and each bit line contact mask structure covering at least one active region endpoint;

[0008] Etching downward along the bit line contact mask structure to form node contact holes in the active region endpoints, and filling semiconductor materials in the node contact holes to form a first node contact structure;

[0009] Forming a plurality of bit line structures above the plurality of active regions, and continuously filling semiconductor materials in the gaps between the plurality of bit line structures until a second node contact structure is formed, and the first node contact structure and the second node contact structure together constitute a node contact structure.

[0010] In some embodiments, the forming a plurality of bit line contact mask structures above the plurality of active regions includes: sequentially stacking a functional structure layer, a mask layer, and a pattern layer above the plurality of active regions; forming a preset pattern in the pattern layer, and the preset pattern dividing the pattern layer into a plurality of columnar structures; transferring the preset pattern to the functional structure layer through the mask layer, and removing the pattern layer and the mask layer to obtain a plurality of bit line contact mask structures presenting columnar structures.

[0011] In some embodiments, the pattern layer at least includes a photoresist layer.

[0012] In some embodiments, the mask layer includes a silicon oxynitride layer and a spin-on hard mask layer.

[0013] In some embodiments, the functional structure layer includes a dielectric layer, a conductive layer, and a barrier layer.

[0014] In some embodiments, the dielectric layer includes silicon oxide, the conductive layer includes polysilicon, and the barrier layer includes silicon nitride.

[0015] In some embodiments, the preset pattern includes a first graphic array and a second graphic array, and each of the first graphic array and the second graphic array includes a plurality of elliptical shapes, and the plurality of elliptical shapes in the first graphic array and the plurality of elliptical shapes in the second graphic array are cross-distributed.

[0016] In some embodiments, etching downward along the plurality of bit line contact mask structures to form node contact holes in the active region endpoints includes: forming a filling layer above the plurality of active regions, and the filling layer wraps the plurality of bit line contact mask structures; etching the plurality of bit line contact mask structures to form a plurality of columnar holes in the filling layer; continuing to etch the active region endpoints covered by the plurality of bit line contact mask structures along the columnar holes, and forming node contact holes in the active region endpoints; wherein, the columnar holes communicate with the node contact holes.

[0017] In some embodiments, filling a semiconductor material in the node contact holes to form a first node contact structure includes: filling the semiconductor material into the node contact holes through the plurality of columnar holes until the semiconductor material seals the plurality of columnar holes; etching the semiconductor material in the plurality of columnar holes and retaining the semiconductor material in the node contact holes to form a first node contact structure.

[0018] In some embodiments, forming a plurality of bit line structures above the plurality of active regions includes: filling a mask material in the plurality of columnar holes until the mask material seals the plurality of columnar holes; removing the filling layer to obtain a plurality of new bit line contact mask structures; and forming a plurality of bit line structures above the plurality of active regions based on the plurality of new bit line contact mask structures.

[0019] In some embodiments, a continuous covering layer is provided on the surfaces of the plurality of bit line structures; filling a semiconductor material in the gaps between the plurality of bit line structures includes: etching the covering layer at the bottom of the gaps between the plurality of bit line structures to expose the surface of the first node contact structure; and filling a semiconductor material in the gaps between the plurality of bit line structures so that the semiconductor material in the gaps between the plurality of bit line structures forms a second node contact structure.

[0020] In some embodiments, there is also a shallow trench isolation structure between the plurality of active regions;

[0021] Accordingly, the method further includes: during the process of etching the covering layer at the bottom of the gaps of multiple bit line structures, etching a part of the shallow trench isolation structure and a part of the first node contact structure to increase the contact area between the second node contact structure and the first node contact structure.

[0022] In some embodiments, the semiconductor material is polysilicon, the mask material includes silicon oxynitride, and the material of the filling layer includes silicon oxide.

[0023] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is obtained by the preparation method of the semiconductor structure according to any one of the first aspect.

[0024] In a third aspect, an embodiment of the present application provides a semiconductor memory, which includes the semiconductor structure as described in the second aspect.

[0025] An embodiment of the present application provides a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes: providing a substrate, where the substrate includes multiple active regions; forming multiple bit line contact mask structures above the multiple active regions, and each bit line contact mask structure covers at least one active region endpoint; etching downward along the bit line contact mask structure to form node contact holes in the active region endpoints, and filling semiconductor material in the node contact holes to form a first node contact structure; forming multiple bit line structures above the multiple active regions, and continuing to fill the semiconductor material in the gaps between the multiple bit line structures until a second node contact structure is formed. The first node contact structure and the second node contact structure together form a node contact structure. In this way, the node contact holes are formed in advance after the bit line contact mask structures are formed, and the node contact holes are filled to form the first node contact structure. Subsequently, there is no need to deepen the node contact holes by side etching, which can improve the problem that the node contact structure is prone to filling gaps and improve the electrical performance of the semiconductor. Description of the Drawings

[0026] Figure 1A Schematic diagram one of the preparation process of a node contact structure provided for the related art;

[0027] Figure 1B Schematic diagram of the preparation process of a node contact structure provided for the related art Figure 2 ;

[0028] Figure 1C Schematic diagram three of the preparation process of a node contact structure provided for the related art;

[0029] Figure 1D Schematic diagram of the preparation process of a node contact structure provided for the related art Figure 4 ;

[0030] Figure 2 Schematic structural diagram of a node contact hole provided for the related art;

[0031] Figure 3A Schematic diagram I of the filling process of polysilicon provided for the related art;

[0032] Figure 3B Schematic diagram of the filling process of polysilicon provided for the related art Figure 2 ;

[0033] Figure 3C Schematic diagram III of the filling process of polysilicon provided for the related art;

[0034] Figure 4 Schematic flow diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0035] Figure 5A Schematic diagram I of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0036] Figure 5B Schematic diagram of the preparation process of a first node contact structure provided by an embodiment of the present application Figure 2 ;

[0037] Figure 5C Schematic diagram III of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0038] Figure 5D Schematic diagram of the preparation process of a first node contact structure provided by an embodiment of the present application Figure 4 ;

[0039] Figure 5E Schematic diagram V of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0040] Figure 5F Schematic diagram VI of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0041] Figure 5G Schematic diagram VII of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0042] Figure 5H Schematic diagram VIII of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0043] Figure 5I Schematic diagram IX of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0044] Figure 5JSchematic diagram ten of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0045] Figure 5K Schematic diagram eleven of the preparation process of a first node contact structure provided by an embodiment of the present application;

[0046] Figure 6A Schematic diagram one of the preparation process of a second node contact structure provided by an embodiment of the present application;

[0047] Figure 6B Schematic diagram of the preparation process of a second node contact structure provided by an embodiment of the present application Figure 2 ;

[0048] Figure 6C Schematic diagram three of the preparation process of a second node contact structure provided by an embodiment of the present application;

[0049] Figure 7A Schematic diagram one of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0050] Figure 7B Schematic diagram of the preparation process of a bit line contact mask structure provided by an embodiment of the present application Figure 2 ;

[0051] Figure 7C Schematic diagram three of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0052] Figure 8A Schematic diagram of the preparation process of a bit line contact mask structure provided by an embodiment of the present application Figure 4 ;

[0053] Figure 8B Schematic diagram five of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0054] Figure 9A Schematic diagram six of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0055] Figure 9B Schematic diagram seven of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0056] Figure 9C Schematic diagram eight of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0057] Figure 10A Schematic diagram nine of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0058] Figure 10BSchematic diagram ten of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0059] Figure 10C Schematic diagram eleven of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0060] Figure 11A Schematic diagram twelve of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0061] Figure 11B Schematic diagram thirteen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0062] Figure 11C Schematic diagram fourteen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0063] Figure 12A Schematic diagram of the preparation process of a bit line contact mask structure provided by an embodiment of the present application Figure 15 ;

[0064] Figure 12B Schematic diagram sixteen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0065] Figure 13A Schematic diagram seventeen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0066] Figure 13B Schematic diagram eighteen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0067] Figure 14A Schematic diagram nineteen of the preparation process of a bit line contact mask structure provided by an embodiment of the present application;

[0068] Figure 14B Schematic diagram of the preparation process of a bit line contact mask structure provided by an embodiment of the present application Figure 2 ten;

[0069] Figure 15 Schematic diagram of the structure of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0070] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. Additionally, it should be noted that for the sake of description, only the parts related to the relevant application are shown in the drawings.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein are for the purpose of describing embodiments of this application only and are not intended to limit this application.

[0072] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0073] It should be noted that the terms "first / second / third" involved in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0074] It should be understood that in order to make the objectives, technical solutions and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of this application, many technical details are provided to help the reader better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0075] The following are the meanings of some English nouns and English abbreviations in the embodiments of this application.

[0076] NC (Node Contact): Node Contact

[0077] BLC (Bit Line Contact): Bit Line Contact

[0078] BLC Mask: Bit Line Contact Mask

[0079] BL (Bit Line): Bit Line

[0080] Oxide: In the embodiments of this application, it represents the oxidation of silicon, i.e., silicon oxide.

[0081] PR (Photo Resist): Photo Resist

[0082] SOH (Spin on Hardmask): Spin on Hardmask

[0083] DRAM (Dynamic Random Access Memory): Dynamic Random Access Memory

[0084] SRAM (Static Random Access Memory): Static Random Access Memory

[0085] NAND: Computer flash memory device

[0086] It should be understood that in the process of semiconductor preparation, the preparation of the NC structure is often involved. Refer to Figures 1A to 1D , which shows a schematic diagram of the preparation process of a node contact structure provided by the related art. The preparation process of the node contact structure includes:

[0087] (1) Forming a bit line structure: As Figure 1A shown, on a substrate (not shown in the figure) including an active region 110 and a shallow trench isolation structure 120, a plurality of bit line structures 200 are formed;

[0088] (2) Forming a covering layer, as Figure 1B shown, a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer are sequentially formed outside each bit line structure 200, thereby forming a covering layer 201;

[0089] (3) Forming a node contact hole (Storage Node Contact Hole, NC hole), as Figure 1C shown, continue to form some silicon oxide structures, thereby isolating a plurality of voids from the plurality of bit line structures 200, and the bottom of the void is the node contact hole 301. Refer to Figure 2 , which shows a schematic diagram of the structure of a node contact hole 301 provided by the related art. In particular, Figure 2 is Figure 1C a schematic cross-sectional view parallel to the upper surface of the substrate along the A-A' direction in Figure 2 shown. As

[0090] (4) Filling polysilicon (Poly), as Figure 1D shown, perform side etching along the node contact hole 301 into the active region 110 and etch deep into the shallow trench isolation structure 120, and then fill Poly into the node contact hole 301, thereby forming a node contact structure 300.

[0091] Specifically, during the process from Figures 1C to 1D , please refer to Figures 3A to 3C , which shows a schematic diagram of the filling process of a polysilicon provided by the related art. In particular, Figure 3A is Figure 1C a schematic cross-sectional view perpendicular to the upper surface of the substrate along the B-B' direction in Figure 3A shown. As Figure 3AAfter the part of the active region 110 and the shallow trench isolation structure 120 are etched away further downwards (the dotted circle in [reference]), a deepened node contact hole 301 is obtained (as shown in the dotted circle in [reference]). Figure 3B Then, into Figure 3B the node contact hole 301 shown in [reference], polysilicon is filled to obtain a node contact structure 300, specifically as shown in Figure 3C shown. Here, Figure 3C the structure shown in [reference] and Figure 1D the structure shown in [reference] are the same structure.

[0092] As shown in Figure 3C or Figure 1D shown, after the node contact hole 301 is prepared, the node contact hole 301 needs to be further etched laterally and deeper, so that the hole for accommodating polysilicon is relatively long and narrow as a whole. Therefore, gaps are likely to be generated during the process of filling polysilicon, as shown by the dotted circle in Figure 3C shown, which affects the electrical performance of the semiconductor.

[0093] Based on this, the embodiment of the present application provides a method for preparing a shallow trench isolation structure. A substrate is provided, and the substrate includes a plurality of active regions; a plurality of bit line contact mask structures are formed above the plurality of active regions, and each bit line contact mask structure covers at least one active region end point; etching is performed downward along the bit line contact mask structure to form a node contact hole in the active region end point, and a semiconductor material is filled in the node contact hole to form a first node contact structure; a plurality of bit line structures are formed above the plurality of active regions, and semiconductor material is continuously filled in the gaps between the plurality of bit line structures until a second node contact structure is formed. The first node contact structure and the second node contact structure together constitute a node contact structure. In this way, after the bit line contact mask structure is formed, the node contact hole is formed in advance, and the node contact hole is filled to form the first node contact structure. Subsequently, there is no need to etch laterally and deepen the node contact hole, which can improve the problem that the node contact structure is prone to filling gaps and improve the electrical performance of the semiconductor.

[0094] Hereinafter, each embodiment of the present application will be described in detail with reference to the drawings.

[0095] In an embodiment of the present application, referring to Figure 4 , it shows a schematic flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present application. As shown in Figure 4 shown, the method may include:

[0096] S101: Provide a substrate, and the substrate includes a plurality of active regions.

[0097] S102: Form a plurality of bit line contact mask structures above the plurality of active regions, and each bit line contact mask structure covers at least one active region end point.

[0098] It should be noted that the embodiments of the present application provide a method for manufacturing a semiconductor structure, specifically a method for manufacturing an NC structure. This semiconductor structure can be applied to semiconductor memories, such as DRAM, SRAM, NAND, etc.

[0099] For a substrate including multiple active regions, multiple bit - line contact mask structures are formed, and each bit - line contact mask structure covers at least one active - region endpoint. Here, the bit - line contact mask structure is subsequently used to form the bit - line structure.

[0100] In some embodiments, the bit - line contact mask structure can be a cylinder.

[0101] In some embodiments, forming multiple bit - line contact mask structures above the multiple active regions may include:

[0102] Stacking a functional - structure layer, a mask layer, and a pattern layer in sequence above the multiple active regions;

[0103] Forming a preset pattern in the pattern layer, and the preset pattern divides the pattern layer into multiple columnar structures;

[0104] Transfer the preset pattern to the functional - structure layer through the mask layer, and remove the pattern layer and the mask layer to obtain multiple bit - line contact mask structures presenting columnar structures.

[0105] It should be noted that a functional - structure layer, a mask layer, and a pattern layer are sequentially formed above the active region; then a preset pattern is formed in the pattern layer, and then the preset pattern is transferred to the functional - structure layer through the mask layer, and finally the pattern layer and the mask layer are removed, and the bit - line contact mask structure can be obtained. Here, the formation methods of the functional - structure layer, the mask layer, and the pattern layer can refer to the related technologies, and the embodiments of the present application will not elaborate.

[0106] In some embodiments, the pattern layer can include a photoresist layer.

[0107] In some embodiments, the mask layer can be a silicon oxynitride layer and a spin - on hard - mask layer

[0108] In some embodiments, the functional - structure layer can be a dielectric layer, a conductive layer, and a barrier layer.

[0109] In some embodiments, the dielectric layer can be silicon oxide SiO 2 , the conductive layer can include polysilicon Poly, and the barrier layer can include silicon nitride SiN.

[0110] In a specific embodiment, refer to Figures 5A to 5K, which shows a schematic diagram of the preparation process of a first node contact structure provided by an embodiment of the present application. Specifically, the preparation of the first node contact structure can be divided into several stages: (1) preparation of the bit line contact mask structure; (2) preparation of the node contact holes (please refer to the subsequent description); (3) filling of the first node contact structure (please refer to the subsequent description).

[0111] According to Figures 5A to 5C , the preparation process of the bit line contact mask structure includes:

[0112] (1) Provide a substrate 100, in which there are multiple active regions 110 and shallow trench isolation structures 120 for isolating the active regions. Above the active regions 110, there are a functional structure layer 101, a mask layer 102, and a pattern layer (not shown in the figure) in sequence. In particular, the semiconductor structure also includes a prepared word line structure 400. Since the word line structure 400 has nothing to do with the preparation process provided by the embodiment of the present application, only its position is shown and no further description is made.

[0113] (2) Form a preset pattern in the pattern layer and transfer the preset pattern downward to the mask layer 102. As Figure 5A shown, the mask layer 102 already has the preset pattern transferred from the pattern layer, which is specifically embodied as the mask layer 102 being etched into multiple mask pillars.

[0114] (3) Etch the functional structure layer 101 downward with the mask pillars as a mask, and then remove the mask layer 102, thereby obtaining the bit line contact mask structure 103 on the functional structure layer 101, as specifically shown in Figure 5B and 5C shown. Here, Figure 5C is Figure 5B a schematic cross-sectional view parallel to the upper surface of the substrate along the C-C' direction in Figure 5C shown. As

[0115] shown, each bit line contact mask structure 103 covers 1 to 2 active region endpoints (i.e., the endpoints of the active region 110). Here, the functional structure layer 101 includes a barrier layer, a conductive layer, and a barrier layer dielectric layer from bottom to top in sequence.

[0116] It should be noted that in some embodiments, the preset pattern includes a first graphic array and a second graphic array, and each of the first graphic array and the second graphic array includes a plurality of elliptical shapes, and the plurality of elliptical shapes in the first graphic array and the plurality of elliptical shapes in the second graphic array are cross-distributed.

[0116] As Figure 5C shown, all the bit line contact mask structures 103 in odd rows are prepared from the first graphic array, and all the bit line contact mask structures 103 in even rows are prepared from the second graphic array, as Figure 5CAs shown, the bit line contact mask structures 103 in odd rows and the bit line contact mask structures 103 in even rows are cross - distributed.

[0117] In addition, the cross - section of the bit line contact mask structure 103 can also be other shapes, such as circular.

[0118] In this way, through the foregoing steps, the bit line contact mask structure 103 located above the active region 110 is obtained.

[0119] S103: Etch downward along the bit line contact mask structure to form node contact holes within the active region endpoints, and fill the node contact holes with a semiconductor material to form a first node contact structure.

[0120] It should be noted that etching downward along the bit line contact mask structure means: etching the bit line contact mask structure and the active region endpoints covered under the bit line contact mask structure, so as to form node contact holes (i.e., NC holes) within the active region endpoints, and then filling the node contact holes with a semiconductor material to obtain the first node contact structure. At this time, the node contact holes are located at a relatively bottom position, so it is not easy to generate gaps when filling the semiconductor material.

[0121] In some embodiments, the semiconductor material is polysilicon (Poly).

[0122] In a specific embodiment, the etching downward along multiple bit line contact mask structures to form node contact holes within the active region endpoints may include:

[0123] Form a filling layer above multiple active regions, and the filling layer wraps multiple bit line contact mask structures;

[0124] Etch multiple bit line contact mask structures to form multiple columnar holes in the filling layer;

[0125] Continue to etch the active region endpoints covered by each of the multiple bit line contact mask structures along the columnar holes, and form node contact holes within the active region endpoints.

[0126] It should be noted that after forming multiple bit line contact mask structures above the active region, a filling layer is formed around the bit line contact mask structures, and then the bit line contact mask structures are etched, so as to obtain a filling layer with multiple columnar holes. Continuing to etch the active region endpoints covered by each of the multiple bit line contact mask structures along the columnar holes, the etched - away active region endpoints then form node contact holes.

[0127] In a specific embodiment, please refer to according to Figures 5D to 5F , the preparation process of the node contact holes includes:

[0128] (1) A filling layer 104 is formed around multiple bit-line contact mask structures 103, and the top of the filling layer is flush with the multiple bit-line contact mask structures 103 as much as possible. Specifically, as shown in Figure 5D .

[0129] (2) The multiple bit-line contact mask structures 103 are removed, and multiple columnar holes are formed at the positions of the original bit-line contact mask structures. The multiple columnar holes are further deepened until node contact holes 301 are formed within the active region endpoints (i.e., the endpoints of the active region 110). Specifically, as shown in Figure 5E and 5F . Here, Figure 5E the dotted circles indicate the columnar holes, and the columnar holes are connected to the node contact holes 301.

[0130] Here, Figure 5F is Figure 5E the schematic cross-sectional view parallel to the upper surface of the substrate along the D-D' direction in Figure 5F . In Figure 5F , the active region endpoints in each node contact hole 301 are etched downward by a certain amount to form the node contact holes 301. In this way, the node contact holes are prepared before the bit-line structure is formed, so that part of the Poly can be filled first, without the need for the etch depth step of the node contact holes, and the gaps caused during the overall filling process are avoided.

[0131] In another specific embodiment, please refer to Figures 5G to 5H , the filling process of the first node contact structure includes:

[0132] (1) After obtaining the node contact holes 301, semiconductor material (Poly) is filled into the multiple columnar cavities in Figure 5E until the Poly closes the multiple columnar holes. Specifically, as shown in Figure 5G .

[0133] (2) The Poly in the columnar holes is etched, and only the Poly in the node contact holes 301 is retained. At this time, the Poly in the node contact holes constitutes the first node contact structure 302. In addition, multiple columnar holes are formed again in the filling layer 104. Specifically, as shown by the dotted circles in Figure 5H .

[0134] Specifically, when filling Poly into the columnar holes, the node contact holes 301 are at the bottom of the columnar holes, and gaps may be generated in the middle section of the columnar holes. However, the polysilicon in the columnar holes is to be etched away, so the gaps in this process will not affect the semiconductor performance.

[0135] In this way, after preparing the bit-line contact mask structure and before the bit-line structure, node contact holes are formed at the active region endpoints, and semiconductor material is filled to form the first node contact structure.

[0136] S104: Form a plurality of bit line structures above the plurality of active regions, and continue to fill the semiconductor material in the gaps between the plurality of bit line structures until a second node contact structure is formed. The first node contact structure and the second node contact structure together constitute the node contact structure.

[0137] It should be noted that after forming the first node contact structure, continue to form a plurality of bit line structures above the plurality of active regions, and continue to form the second node contact structure in the gaps between the plurality of bit line structures, so as to obtain a complete node contact structure. Here, for the specific formation process of the bit line structure, refer to the related technology, and this application will not elaborate.

[0138] As described above, in the related technology, after preparing the bit line structure, it is necessary to form an NC hole and fill Poly in the NC hole to form an NC structure. However, it is easy to generate gaps during the process of filling Poly, which affects the electrical performance. In the embodiment of the present application, the NC hole is formed after preparing the bit line contact mask structure and before the bit line structure, realizing the preparation of the NC hole in advance, and at the same time, polysilicon can be filled in advance to form the first node contact structure. On the one hand, the node contact structure is prepared in two stages, and polysilicon is filled twice respectively. The depth of the hole filled with polysilicon each time is not large, avoiding the generation of filling gaps and improving the electrical performance; on the other hand, by preparing the NC hole in advance, the step of eating deep the NC hole (this step is caused by forming the bit line structure first and then the NC hole) is avoided, thereby further avoiding the generation of filling gaps and improving the electrical performance.

[0139] In some embodiments, forming a plurality of bit line structures above the plurality of active regions may include:

[0140] Fill the mask material in a plurality of columnar holes until the mask material closes the plurality of columnar holes;

[0141] Remove the filling layer to obtain a plurality of new bit line contact mask structures;

[0142] Based on the plurality of new bit line contact mask structures, form a plurality of bit line structures above the plurality of active regions.

[0143] It should be noted that the columnar holes of the filling layer are closed by the mask material, and then the filling layer is removed, so as to obtain a new bit line contact mask structure again for subsequent formation of a plurality of bit line structures above the plurality of active regions.

[0144] In a specific embodiment, please refer to Figures 5I to 5K , the preparation process of the new bit line contact mask structure includes:

[0145] (1) For Figure 5HMultiple columnar holes therein, and continue to fill the mask material therein until the mask material closes the multiple columnar holes, specifically as shown in Figure 5I shown.

[0146] (2) Etch the filling layer 104, and at this time, multiple columnar structures formed by the mask material are obtained, that is, the new bit line contact mask structure 103', specifically as shown in Figure 5J and Figure 5K shown.

[0147] In particular, Figure 5K is Figure 5J obtained by not drawing part of the shallow trench isolation structure 120 in Figure 5J and Figure 5K in order to better display the new bit line contact mask structure 103' and the first node contact structure 302. Here, Figure 5B the position and function of the new bit line contact mask structure 103' shown in Figure 5K are the same as those of the bit line contact mask structure 103 shown in

[0148] However, in

[0149] In some embodiments, a continuous covering layer is provided on the surfaces of the multiple bit line structures; the continuing to fill the semiconductor material in the gaps between the multiple bit line structures may include:

[0150] Etch the covering layer at the bottom of the gaps between the multiple bit line structures to expose the surface of the first node contact structure;

[0151] Continue to fill the semiconductor material in the gaps between the multiple bit line structures so that the semiconductor material in the gaps between the multiple bit line structures forms the second node contact structure.

[0152] It should be noted that referring to Figures 6A to 6C which shows a schematic diagram of the preparation process of the second node contact structure provided by the embodiments of the present application.

[0153] As Figure 6AAs shown, a plurality of bit line structures 200 are formed above the plurality of active regions. A continuous covering layer 201 exists on the surface of the plurality of bit line structures 200. The first node contact structure 302 is completely covered by the covering layer 201 and is not exposed. Therefore, continuing to refer to Figure 6B , it is necessary to etch away a part of the covering layer 201 at the bottom of the gap between different bit line structures 200 to expose the first node contact structure 302. Finally, referring to Figure 6C , at this time, polysilicon is filled into the gap between the plurality of bit line structures 200, so as to form a second node contact structure 303 above the first node contact structure 302, and the first node contact structure 302 and the second node contact structure 303 are in contact, thus constituting the overall node contact structure 300. Here, as Figure 6C shows, an edge line is drawn at the contact position of the first node contact structure 302 and the second node contact structure 303. The edge line here is only for better viewing of the first node contact structure and the second node contact structure and does not represent an actual existence.

[0154] In this way, compared with the related art, the NC preparation method provided by the embodiment of the present application can prepare the NC holes in advance, and there is no part for deepening the NC holes, avoiding the drawback of insufficient filling of the side wall holes and residual bubbles in the subsequent process.

[0155] In some embodiments, there is also a shallow trench isolation structure between the plurality of active regions. The method may further include:

[0156] During the process of etching the covering layer at the bottom of the gap between the plurality of bit line structures, a part of the shallow trench isolation structure and a part of the first node contact structure are etched to increase the contact area between the second node contact structure and the first node contact structure.

[0157] Specifically, in order to increase the contact area between the first node contact structure and the second node contact structure, referring to Figure 6B , during the process of etching the covering layer 201 at the bottom of the gap between the plurality of bit line structures 200, a part of the shallow trench isolation structure 120 and a part of the first node contact structure 302 are etched.

[0158] In some embodiments, the semiconductor material may include polysilicon (Poly), the mask material may include silicon oxynitride (SiON), and the material of the filling layer may include silicon oxide (SiO 2 .

[0159] In summary, in the embodiment of the present application, after forming the bit line contact mask structure, the node contact holes can be prepared by using the bit line contact mask structure, and the first Poly filling is performed to obtain the first node contact structure; then, the bit line contact mask structure is re-formed, and then the bit line structure is formed, and the second node contact structure is continuously formed between the bit line structures. In this way, by preparing the node contact holes in advance, the Poly can be filled in two times, and the step of etching deep into the node contact holes is not required, which can avoid generating gaps during the Poly filling process, thereby improving the electrical performance.

[0160] The embodiment of the present application provides a method for preparing a shallow trench isolation structure. A substrate is provided, and the substrate includes a plurality of active regions; a plurality of bit line contact mask structures are formed above the plurality of active regions, and each bit line contact mask structure covers at least one active region end point; etching is performed downward along the bit line contact mask structure to form node contact holes in the active region end points, and a semiconductor material is filled in the node contact holes to form a first node contact structure; a plurality of bit line structures are formed above the plurality of active regions, and a semiconductor material is continuously filled in the gaps between the plurality of bit line structures until a second node contact structure is formed. The first node contact structure and the second node contact structure together constitute the node contact structure. In this way, the node contact holes are formed in advance after the bit line contact mask structure is formed, and the node contact holes are filled. Subsequently, there is no need to etch the node contact holes laterally to deepen them, which can improve the problem that the node contact structure is prone to filling gaps and improve the electrical performance of the semiconductor.

[0161] In another embodiment of the present application, please refer to Figure 7A ~FIG. 14, which shows a schematic diagram of the preparation process of a bit line contact mask structure 103 provided by the embodiment of the present application. In Figure 7A ~FIG. 14, the front view schematic diagrams are all cross-sectional schematic diagrams along the X-X' direction in the top view schematic diagram, and the side view schematic diagrams are all cross-sectional schematic diagrams along the Y-Y' direction in the top view schematic diagram.

[0162] In the embodiment of the present application, a substrate 100 is provided. The substrate 100 includes a plurality of active regions 110 and a shallow trench isolation structure 120 disposed between different active regions 110. A functional structure layer 101, a first mask layer 1021, a second mask layer 1022, and a third mask layer 1023 are sequentially stacked above the plurality of active regions 110.

[0163] Among them, the functional structure layer 101 successively includes a SiN layer (i.e., the barrier layer), a Poly layer (i.e., the conductive layer), and an Oxide layer (i.e., the dielectric layer) from bottom to top. The first mask layer 1021 successively includes a SOH layer and a SiON layer from bottom to top. The second mask layer 1022 successively includes a SOH layer and a SiON layer from bottom to top. The third mask layer 1023 successively includes an Oxide layer, a SOH layer, a SiON layer, and a PR layer from bottom to top.

[0164] In the first stage, the preparation of the BLC mask structure.

[0165] In the first step, the preparation of the BLC1 pattern: Please refer to Figures 7A to 7C , for the third mask layer 1023, use a circular mask to form a plurality of circular patterns (equivalent to the aforementioned first graphic array) on the PR layer, etch these circular patterns, and form a plurality of columnar holes on the PR layer (as shown by the dashed box in Figure 7A ), thereby forming the BLC1 pattern. In particular, Figure 7A is a top view schematic diagram of the semiconductor structure after the first step, Figure 7B is a front view schematic diagram of the semiconductor structure after the first step, Figure 7C is a side view schematic diagram of the semiconductor structure after the first step.

[0166] In the second step, the transfer of the BLC1 pattern: Please refer to Figure 8A and Figure 8B , transfer the BLC1 pattern downward to the Oxide layer in the third mask layer 1023, that is, form a plurality of columnar holes in the Oxide layer in the third mask layer 1023 (as shown by the dashed box in Figure 8A ). In particular, Figure 8A is a front view schematic diagram of the semiconductor structure after the second step, Figure 8B is a side view schematic diagram of the semiconductor structure after the second step.

[0167] In the third step, the preparation of the BLC2 pattern: Please refer to Figure 9A , 9B and 9C, use a circular mask to form a plurality of circular patterns (equivalent to the aforementioned second graphic array) on the PR layer again, etch these circular patterns, and form some other columnar holes on the PR layer, thereby forming the BLC2 pattern. Here, the circles in the BLC1 pattern and the circles in the BLC2 pattern are in staggered positions. In particular, Figure 9A is a top view schematic diagram of the semiconductor structure after the third step, Figure 9B is a front view schematic diagram of the semiconductor structure after the third step, Figure 9C is a side view schematic diagram of the semiconductor structure after the third step.

[0168] In the fourth step, the transfer of the BLC2 pattern: Please refer toFigure 10A , 10B and 10C, transfer the BLC2 pattern to the Oxide layer in the third mask layer 1023, that is, form some additional columnar holes in the Oxide layer. At this time, in the Oxide layer, there are multiple columnar holes transferred from the BLC1 pattern and multiple columnar holes transferred from the BLC2, which together constitute the BLC pattern (as shown by the dashed boxes in Figure 10B and 10C ). In particular, Figure 10A is a top view schematic diagram of the semiconductor structure after the fourth step, Figure 10B is a front view schematic diagram of the semiconductor structure after the fourth step, Figure 10C is a side view schematic diagram of the semiconductor structure after the fourth step.

[0169] Fifth step, BLC pattern transfer: Please refer to Figure 11A , 11B and 11C, transfer the BLC pattern from the Oxide layer in the third mask layer 1023 downward to the SiON structure in the second mask layer 1022. At this time, multiple columnar holes are formed in the SiON layer, and the columnar holes penetrate the SiN layer below the SiON layer. In particular, Figure 11A is a top view schematic diagram of the semiconductor structure after the fifth step, Figure 11B is a front view schematic diagram of the semiconductor structure after the fifth step, Figure 11C is a side view schematic diagram of the semiconductor structure after the fifth step.

[0170] Sixth step, reverse pattern preparation one: As shown in Figure 12A and Figure 12B , fill SiO 2 in the columnar holes in the second mask layer 1022. In particular, Figure 12A is a top view schematic diagram of the semiconductor structure after the sixth step, Figure 12B is a front view schematic diagram of the semiconductor structure after the sixth step. In addition, it is also possible to choose to fill photoresist in the columnar holes.

[0171] Seventh step: Reverse pattern preparation two: As shown in Figure 13A and Figure 13B , remove the remaining SiON layer and SIN layer in the second mask layer 1022, and then multiple cylinders (equivalent to the pattern layer in the previous embodiment) are formed, which can also be called reverse transfer patterns. In other words, convert the multiple columnar holes originally located in the SiON layer and SIN layer into multiple cylinders. In particular, Figure 13A is a top view schematic diagram of the semiconductor structure after the seventh step, Figure 13B is a front view schematic diagram of the semiconductor structure after the seventh step.

[0172] Step 8: Forming a bit line contact mask structure: As shown in Figure 14A and Figure 14B , using multiple cylinders as masks, etch the functional structure layer 101 downward along the first mask layer 1021 (the dotted line position in Figure 13B ), and then remove the first mask layer 1021, thereby obtaining multiple cylinders formed by the original functional structure layer, which is the bit line contact mask structure 103. In particular, Figure 14A is a top view schematic diagram of the semiconductor structure after Step 8, and Figure 14B is a front view schematic diagram of the semiconductor structure after Step 8.

[0173] Second stage, preparation of the node contact structure.

[0174] As shown in Figure 5B , at this time Figure 5B describes a three-dimensional schematic diagram of the substrate 100 after forming the BLC mask structure. In other words, ignoring some details, Figure 5B represents the semiconductor structure in the same state as Figure 14. For Figure 5B , the first node contact structure is formed through the following steps.

[0175] First step, forming a filling layer: As shown in Figure 5D , deposit a filling layer 104 above the active region 110. The filling layer may include a silicon dioxide layer, and the filling layer 104 completely wraps the bit line contact mask structure 103.

[0176] Second step, forming node contact holes: As shown in Figure 5E and 5F , etch the bit line contact mask structure 103 to form multiple columnar holes in the filling layer 104, and use the filling layer 104 as a reverse mask to etch downward until part of the active region endpoints (i.e., the endpoints of the active region 110) are etched away. In this way, multiple columnar holes are formed in the filling layer 104, and the columnar holes penetrate into the active region 110 and the shallow trench isolation structure 120; in other words, part of the active region 110 endpoints are etched, and the etched active region 110 endpoints form the node contact holes 301.

[0177] Third step, forming the first node contact structure: As shown in Figures 5G to 5H , fill Poly into the columnar holes of the filling layer 104, and then remove the Poly in the columnar holes until contacting the SiN layer in the substrate 100 (equivalent to the top plane of the active region 110). At this time, the filling layer 104 reforms columnar holes, and at the same time, the Poly located in the node contact holes 301 is retained to form the first node contact structure 302.

[0178] Fourth step: Reforming a new bit line contact mask structure 103': As shown in Figures 5I to 5JAs shown, SiON is refilled in the columnar holes formed in the filling layer 104 as a mask, and then the filling layer 104 is etched away. At this time, a plurality of cylinders formed by SiON are obtained again as the new bit line contact mask structure 103'.

[0179] Step 5: Forming the bit line structure: As Figure 6A shown, the bit line structure 200 is formed by using the new bit line contact mask structure 103', and a continuous covering layer 201 is included outside the bit line structure 200. Here, the specific forming processes of the bit line structure 200 and the covering layer 201 can refer to the related technologies.

[0180] Step 6: Forming the second node contact structure I: As Figure 6B shown, for the bottom of the gap between different bit line structures 200, a part of the covering layer 201, SiO 2 (part of the shallow trench isolation structure 120) and Poly (part of the first node contact structure 302) are etched away to form a hole, and the hole is enlarged and deepened by further etching SiO 2 and Poly, so as to increase the exposed surface of the remaining first node contact structure 302, so that the Poly filled subsequently has a larger contact surface with the Poly in the first node contact structure 302.

[0181] Step 7: Forming the second node contact structure II: As Figure 6C shown, Poly is filled into the gap between different bit line structures to obtain the second node contact structure 303, and the second node contact structure 303 and the first node contact structure 302 together constitute the node contact structure 300.

[0182] The embodiment of the present application provides a preparation method of a shallow trench isolation structure. Through the further explanation of the foregoing embodiment by the embodiment of the present application, it can be seen that compared with the NC preparation method of directly filling Poly in the related technology, the NC preparation method provided by the embodiment of the present application does not need to further side-etch the active region (i.e., deepen the node contact hole) after forming the node contact hole, thereby avoiding the drawback of insufficient sidewall holes during the subsequent filling process. As Figure 3C shown, the NC preparation method in the related technology is very likely to generate bubbles on the sidewall. As Figure 6C shown, the NC preparation method in the embodiment of the present application does not need to etch the sidewall of the bottom of the NC, thereby improving the problem of bubble generation and improving the electrical performance of the node contact structure.

[0183] In another embodiment of the present application, a semiconductor structure is provided, and the semiconductor structure is obtained by the foregoing preparation method of the semiconductor structure.

[0184] Since the semiconductor structure adopts the foregoing preparation method, a node contact hole is formed in advance after forming the bit line contact mask structure, and the node contact hole is filled. Subsequently, there is no need to laterally etch to deepen the node contact hole, which can improve the problem that the node contact structure is prone to filling gaps and improve the electrical performance of the semiconductor.

[0185] In another embodiment of the present application, refer to Figure 15 , which shows a schematic structural diagram of a semiconductor memory 50 provided by an embodiment of the present application. As Figure 15 shown, the semiconductor memory 50 includes the foregoing semiconductor structure.

[0186] For the semiconductor memory 50, since it includes a semiconductor structure, and the semiconductor structure adopts the foregoing preparation method, a node contact hole is formed in advance after forming the bit line contact mask structure, and the node contact hole is filled. Subsequently, there is no need to laterally etch to deepen the node contact hole, which can improve the problem that the node contact structure is prone to filling gaps and improve the electrical performance of the semiconductor.

[0187] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application.

[0188] It should be noted that in the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0189] The serial numbers of the above embodiments of the present application are only for description and do not represent the superiority or inferiority of the embodiments.

[0190] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0191] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0192] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0193] The above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, the method comprises: providing a substrate, the substrate including a plurality of active regions; forming a plurality of bit line contact mask structures above the plurality of active regions, and each bit line contact mask structure covering at least one active region endpoint; etching downward along the bit line contact mask structures to form node contact holes in the active region endpoints, and filling semiconductor material in the node contact holes to form first node contact structures; forming a plurality of bit line structures above the plurality of active regions, and continuously filling the semiconductor material in the gaps between the plurality of bit line structures until a second node contact structure is formed, the first node contact structure and the second node contact structure jointly constituting a node contact structure.

2. The fabrication method according to claim 1, characterized in that, the forming a plurality of bit line contact mask structures above the plurality of active regions includes: sequentially stacking a functional structure layer, a mask layer, and a pattern layer above the plurality of active regions; forming a preset pattern in the pattern layer, and the preset pattern dividing the pattern layer into a plurality of columnar structures; transferring the preset pattern through the mask layer to the functional structure layer, and removing the pattern layer and the mask layer to obtain a plurality of bit line contact mask structures presenting columnar structures.

3. The fabrication method according to claim 2, characterized in that, the pattern layer at least includes a photoresist layer.

4. The fabrication method according to claim 2, characterized in that, the mask layer includes a silicon oxynitride layer and a spin-on hard mask layer.

5. The fabrication method according to claim 2, characterized in that, the functional structure layer includes a dielectric layer, a conductive layer, and a barrier layer.

6. The fabrication method according to claim 5, characterized in that, the dielectric layer includes silicon oxide, the conductive layer includes polysilicon, and the barrier layer includes silicon nitride.

7. The fabrication method according to claim 2, characterized in that, the preset pattern includes a first graphic array and a second graphic array, and each of the first graphic array and the second graphic array includes a plurality of elliptical shapes, and the plurality of elliptical shapes in the first graphic array and the plurality of elliptical shapes in the second graphic array are cross-distributed.

8. The fabrication method according to claim 1, characterized in that, the etching downward along the plurality of bit line contact mask structures to form node contact holes in the active region endpoints includes: forming a filling layer above the plurality of active regions, and the filling layer wrapping the plurality of bit line contact mask structures; etching the plurality of bit line contact mask structures to form a plurality of columnar holes in the filling layer; continuing to etch the active region endpoints covered by the plurality of bit line contact mask structures along the columnar holes, and forming the node contact holes in the active region endpoints; wherein, the columnar holes are communicated with the node contact holes.

9. The fabrication method according to claim 8, characterized in that, the filling semiconductor material in the node contact holes to form first node contact structures includes: Fill the node contact holes with the semiconductor material through the multiple columnar holes until the semiconductor material seals the multiple columnar holes; Etch the semiconductor material in the multiple columnar holes, and retain the semiconductor material in the node contact holes to form the first node contact structure.

10. The manufacturing method according to claim 9, wherein, forming multiple bit line structures above the multiple active regions includes: filling the multiple columnar holes with a mask material until the mask material seals the multiple columnar holes; removing the filling layer to obtain multiple new bit line contact mask structures; forming the multiple bit line structures above the multiple active regions based on the multiple new bit line contact mask structures.

11. The manufacturing method according to claim 10, wherein, a continuous covering layer is provided on the surfaces of the multiple bit line structures; filling the gaps between the multiple bit line structures with the semiconductor material further includes: etching the covering layer at the bottom of the gaps between the multiple bit line structures to expose the surface of the first node contact structure; continuing to fill the gaps between the multiple bit line structures with the semiconductor material so that the semiconductor material in the gaps between the multiple bit line structures forms the second node contact structure.

12. The manufacturing method according to claim 11, wherein, there is also a shallow trench isolation structure between the multiple active regions, and the method further includes: during the process of etching the covering layer at the bottom of the gaps between the multiple bit line structures, etching a part of the shallow trench isolation structure and a part of the first node contact structure to increase the contact area between the second node contact structure and the first node contact structure.

13. The manufacturing method according to claim 12, wherein, the semiconductor material includes polysilicon, the mask material includes silicon oxynitride, and the material of the filling layer includes silicon oxide.

14. A semiconductor structure, wherein, the semiconductor structure is obtained by the manufacturing method of the semiconductor structure according to any one of claims 1-13.

15. A semiconductor memory, wherein, the semiconductor memory includes the semiconductor structure according to claim 14.

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