Light-emitting substrate and display device

Abstract

This disclosure discloses a light-emitting substrate and a display device, including: a substrate; a first conductive layer located on the substrate; wherein the first conductive layer includes a plurality of driving voltage lines spaced apart from each other; a plurality of light-emitting units located on the side of the first conductive layer away from the substrate; wherein each light-emitting unit includes a plurality of light-emitting elements; the plurality of light-emitting elements are divided into a plurality of element groups; wherein in the same light-emitting unit, at least two element groups are electrically connected to different driving voltage lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to light-emitting substrates and display devices. Background Technology

[0002] With the development of LED technology, backlights using LEDs at the sub-millimeter or even micrometer scale have been widely adopted. This allows backlights that utilize transmissive displays to achieve the same contrast ratio as OLED displays, while retaining the technological advantages of liquid crystal displays (LCDs), thus enhancing the display effect and providing users with a superior visual experience. Summary of the Invention

[0003] The light-emitting substrate provided in this embodiment includes:

[0004] Substrate;

[0005] A first conductive layer is located on the substrate; wherein the first conductive layer includes a plurality of driving voltage lines arranged at intervals between each other;

[0006] Multiple light-emitting units are located on the side of the first conductive layer opposite to the substrate; wherein each light-emitting unit includes multiple light-emitting elements; the multiple light-emitting elements are divided into multiple element groups;

[0007] In the same light-emitting unit, at least two element groups are electrically connected to different driving voltage lines.

[0008] In some examples, one of the light-emitting units is connected to two driving voltage lines, one of which overlaps with the orthographic projection of the light-emitting unit on the substrate, and the other does not overlap with the orthographic projection of the light-emitting unit on the substrate.

[0009] In some examples, the light-emitting substrate further includes:

[0010] A first insulating layer is located between the first conductive layer and the plurality of light-emitting units;

[0011] The second conductive layer is located between the first insulating layer and the plurality of light-emitting units;

[0012] A second insulating layer is located between the second conductive layer and the plurality of light-emitting units;

[0013] The second conductive layer includes: multiple component traces spaced apart from each other;

[0014] In each of the aforementioned element groups, adjacent light-emitting elements are electrically connected through element traces.

[0015] In some examples, the first conductive layer further includes multiple common voltage lines and multiple source voltage lines spaced apart from each other;

[0016] The plurality of driving voltage lines, the plurality of common voltage lines, and the plurality of source voltage lines extend along a first direction, and are repeatedly arranged along a second direction according to the order of the driving voltage lines, the common voltage lines, and the source voltage lines;

[0017] There is a first cutout gap between adjacent driving voltage lines and common voltage lines, a second cutout gap between adjacent common voltage lines and source voltage lines, and a third cutout gap between adjacent source voltage lines and driving voltage lines.

[0018] The first, second, and third cutout gaps are each provided with a group of elements in a row of light-emitting units and element traces connecting adjacent light-emitting elements in the group of elements.

[0019] In some examples, different groups of the same light-emitting unit are arranged on both sides of the common voltage line; and the groups of elements located on both sides of the common voltage line are electrically connected to different driving voltage lines.

[0020] In some examples, different groups of elements in the same light-emitting unit are connected in parallel via a first connecting portion;

[0021] In the same light-emitting unit, the parallel connection point is where the voltage is lowest.

[0022] In some examples, the voltage at the first connection is less than or equal to the voltage of the common voltage line.

[0023] In some examples, the voltage on the common voltage line is the ground voltage.

[0024] In some examples, the voltage at the first connection is less than or equal to the voltage of the drive voltage line.

[0025] In some examples, the number of light-emitting units electrically connected to the second driving voltage line to the (N-1)th driving voltage line is the same; where N is the total number of driving voltage lines in the light-emitting substrate.

[0026] In some examples, the number of component groups electrically connected to the second drive voltage line through the (N-1)th drive voltage line is the same.

[0027] In some examples, the number of light-emitting elements electrically connected to the second driving voltage line through the (N-1)th driving voltage line is the same.

[0028] In some examples, a row of light-emitting units corresponds to a driving voltage line, a common voltage line, and a source voltage line; and, in the second direction, the last source voltage line is provided with a driving voltage line on the side opposite to the common voltage line.

[0029] The second conductive layer includes: a plurality of jumper wires; wherein, the component group located in the second cutout gap is electrically connected to the drive voltage line located on the side of the source voltage line opposite to the common voltage line through the jumper wires.

[0030] In some examples, the second conductive layer further includes a plurality of connection pads; one electrode of the light-emitting element is electrically connected to one connection pad;

[0031] The orthographic projection of the jumper wire onto the substrate does not overlap with the orthographic projection of the connection pad onto the substrate.

[0032] In some examples, the second conductive layer further includes: a plurality of second connection portions; wherein, in the same light-emitting unit, the component groups located on the side of the common voltage line facing the driving voltage line are respectively electrically connected to the same driving voltage line through the second connection portions;

[0033] The portion of the jumper wire near the electrically connected drive voltage line includes a first clearance portion and a second clearance portion; wherein the first clearance portion extends along a first direction, and the second clearance portion extends along a second direction; the length of the second clearance portion ranges from 3.0 mm to 3.1 mm.

[0034] In the same row, there is a first clearance gap between the side of the second connection portion that is electrically connected to the driving voltage line facing the second clearance portion and the side of the second clearance portion that is away from the second connection portion; the width of the first clearance gap is in the range of 0.9mm to 1.0mm.

[0035] In some examples, the orthographic projection of the jumper wire onto the substrate does not overlap with the orthographic projection of the common voltage line onto the substrate.

[0036] In some examples, each of the light-emitting units further includes a driving circuit; the driving circuit includes a common voltage terminal and an output terminal;

[0037] The common voltage terminal is electrically connected to the common voltage line;

[0038] In the same light-emitting unit, the last light-emitting element in different element groups is electrically connected to the output terminal.

[0039] In some examples, multiple light-emitting elements in the light-emitting unit are divided into M element groups, and each element group includes N light-emitting elements arranged along a first direction; the M element groups are arranged along a second direction; N is an integer greater than 0, and M is an integer greater than 0;

[0040] The multiple element groups in the light-emitting unit are sequentially numbered along the second direction, and the light-emitting unit columns are sequentially numbered along the second direction. The first light-emitting element in the k-th element group in the light-emitting unit numbered a is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a; the first light-emitting element in the M-th element group in the light-emitting unit numbered a is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a + 1;

[0041] In the light-emitting unit numbered a, the last light-emitting element in the k-th element group is electrically connected to the last light-emitting element in the (k + 1)-th element group through a first connection part; the last light-emitting element in the M-th element group in the light-emitting unit numbered a is electrically connected to the output end of the driving circuit;

[0042] where a is an integer greater than 0, 1 ≤ k < M and k is an integer.

[0043] In some examples, the cascading trace is located on the first conductive layer; the first conductive layer further includes a cascading connection line;

[0044] The second conductive layer further includes a cascading bridging part;

[0045] The first end of the cascading trace is electrically connected to the last light-emitting element in the M-th element group in the light-emitting unit numbered a, and the second end of the cascading trace is electrically connected to the first input end of the driving circuit in the light-emitting unit numbered a + 1;

[0046] The output end of the driving circuit in the light-emitting unit numbered a is electrically connected to the first end of the cascading connection line through a first cascading via, the second end of the cascading connection line is electrically connected to the first end of the cascading bridging part through a second cascading via, and the second end of the cascading bridging part is electrically connected to the first end of the cascading trace through a third cascading via.

[0047] In some examples, the cascading trace is located on the second conductive layer; the first end of the cascading trace is electrically connected to the output end of the driving circuit in the light-emitting unit numbered a, and the second end of the cascading trace is electrically connected to the first input end of the driving circuit in the light-emitting unit numbered a + 1;

[0048] The first conductive layer further includes a bridging cross part; the cross connection line includes a first cross connection line and a second cross connection line; where,

[0049] The first light-emitting element in the element group numbered M in the light-emitting unit numbered a is electrically connected to the first end of the first jumper wire. The second end of the first jumper wire is electrically connected to the first end of the jumper bridging part through the first jumper via. The second end of the jumper bridging part is electrically connected to the first end of the second jumper wire through the second jumper via. The second end of the second jumper wire is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a+1.

[0050] In some examples, the first connection is located in the second conductive layer.

[0051] In some examples, the first connection portion of the component group electrical connection located on both sides of the common voltage line is located in the first conductive layer;

[0052] The common voltage line is divided into multiple second segments, and the second conductive layer further includes a second segment bridging portion; wherein, the gap between adjacent second segments in the same common voltage line is provided with the first connecting portion; and, adjacent second segments in the same common voltage line are electrically connected through the second segment bridging portion.

[0053] In some examples, the common voltage line has a clearance zone;

[0054] The connection pads of the light-emitting elements located on both sides of the common voltage line are projected onto the substrate in the orthographic projection of the avoidance area within the orthographic projection of the substrate.

[0055] The display device provided in this disclosure includes the above-described light-emitting substrate. Attached Figure Description

[0056] Figure 1a This is a schematic diagram of the structure of a light-emitting substrate in related technologies;

[0057] Figure 1b This is a schematic diagram of a partial layout of a light-emitting substrate in a related technology;

[0058] Figure 2 This is a schematic diagram of the structure of the light-emitting substrate in the embodiments of this disclosure;

[0059] Figure 3 This is a partial structural schematic diagram of the light-emitting substrate in an embodiment of this disclosure;

[0060] Figure 4 A waveform diagram of the second input signal in the driving circuit provided in an embodiment of this disclosure;

[0061] Figure 5 Signal timing diagram of the driving circuit provided in the embodiments of this disclosure;

[0062] Figure 6 This is a schematic diagram of some partial layout of the light-emitting substrate in the embodiments of this disclosure;

[0063] Figure 7a for Figure 6 Enlarged layout diagram of the FB1 area;

[0064] Figure 7b for Figure 6 Enlarged layout diagram of the FB2 region;

[0065] Figure 8 This is a schematic diagram of some partial layout of the light-emitting substrate in the embodiments of this disclosure;

[0066] Figure 9a for Figure 8 Enlarged layout diagram of the FB3 region;

[0067] Figure 9b for Figure 8 Enlarged layout diagram of the FB4 region;

[0068] Figure 10 This is a partial layout diagram of the light-emitting substrate in an embodiment of this disclosure. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0071] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0072] Combination Figure 1a and Figure 1b A first conductive layer 02, an insulating layer 03, and a second conductive layer 04 are sequentially disposed on the substrate 01. The first conductive layer 02 has a driving voltage line 220 and a common voltage line 210. The second conductive layer 04 has metal connecting lines. Taking a light-emitting unit with nine light-emitting elements as an example, these nine light-emitting elements are connected in series via the metal connecting lines. The metal connecting lines between these nine light-emitting elements are divided into eight segments: segment A, segment B, segment C, segment D, segment E, segment F, and segment G. For example, the driving voltage line 220 transmits a voltage of 27V, the common voltage line 210 transmits a voltage of 0V, the metal connection line in segment A transmits a voltage of 24V, the metal connection line in segment B transmits a voltage of 21V, the metal connection line in segment C transmits a voltage of 18V, the metal connection line in segment D transmits a voltage of 15V, the metal connection line in segment E transmits a voltage of 12V, the metal connection line in segment F transmits a voltage of 9V, the metal connection line in segment G transmits a voltage of 6V, and the metal connection line in segment H transmits a voltage of 3V. Furthermore, the projection of the metal connection line in segment C onto the substrate overlaps with the projection of the driving voltage line 220 onto the substrate, and the projection of the metal connection line in segment F onto the substrate overlaps with the projection of the common voltage line 210 onto the substrate.

[0073] Because the voltage transmitted by the metal connection line in segment F is greater than the voltage transmitted by the common voltage line 210, the direction of the electric field between the overlapping area of ​​the metal connection line in segment F and the common voltage line 210 is from the second conductive layer to the first conductive layer. Since the second conductive layer is easily exposed and prone to introducing water and oxygen, and the materials of the first conductive layer 02 and the second conductive layer 04 are typically made of low-resistance Cu, Cu is relatively reactive and therefore prone to metal corrosion under the influence of an electric field. A potential difference exists between the metal connection line in segment F and the common voltage line 210, forming the anode and cathode for electrochemical corrosion. The metal connection line in segment F acts as the positive electrode undergoing oxidation, while the common voltage line 210 acts as the cathode undergoing reduction. The continuous electrochemical corrosion eventually leads to a short circuit between the metal connection line in segment F and the common voltage line 210. However, the presence of electrochemical corrosion in the light-emitting substrate will affect the light-emitting stability of the substrate.

[0074] Furthermore, since the voltage transmitted by the metal connection line in segment C is less than the voltage transmitted by the driving voltage line 220, the direction of the electric field between the overlapping area of ​​the metal connection line in segment C and the driving voltage line 220 is from the first conductive layer to the second conductive layer. The driving voltage line 220 is also protected by an insulating layer 03, and the intrusion path of water and oxygen is relatively long, thus reducing the likelihood of electrochemical corrosion. In view of this, at least one embodiment of this disclosure provides a light-emitting substrate and a display device that reduces the impact of electrochemical corrosion on the light-emitting substrate and improves light emission stability.

[0075] In some embodiments, such as Figure 2 As shown, the light-emitting substrate provided in at least one embodiment of this disclosure may include a substrate. The substrate may include a display area. Exemplarily, the material of the substrate may be selected from plastic, polyimide, silicon, ceramic, glass, quartz, etc., and the embodiments of this disclosure are not limited thereto.

[0076] In some embodiments, such as Figure 2 As shown, the display area may include multiple light-emitting units (PXs) arranged in an array. For example, the multiple light-emitting units (PXs) are arranged in multiple rows and columns. In practical applications, the number of light-emitting units (PXs) can be determined according to actual needs, such as the size of the light-emitting substrate and the required brightness. Figure 2 Only 6 rows and 5 columns of light-emitting units PX are shown in the image, but it should be understood that the number of light-emitting units PX is not limited to this.

[0077] In some embodiments, such as Figure 2 As shown, in the display area, the light-emitting units PX can be arranged in multiple rows and columns along the first direction F1 and the second direction F2. For example, the light-emitting substrate is rectangular, the first direction F1 can be parallel to the long side of the light-emitting substrate, and the second direction F2 can be parallel to the short side of the light-emitting substrate. Alternatively, the first direction F1 can also be parallel to the short side of the light-emitting substrate, and the second direction F2 can also be parallel to the long side of the light-emitting substrate. Of course, the embodiments of this disclosure are not limited to this; the first direction F1 and the second direction F2 can be any direction, as long as they intersect. Furthermore, the multiple light-emitting units PX are not limited to being arranged in a straight line; they can also be arranged along a broken line, in a ring, or in any other manner, depending on actual needs. The embodiments of this disclosure do not impose any limitations on this.

[0078] In some embodiments, such as Figure 2 and Figure 3As shown, each light-emitting unit PX may include a driving circuit QD0 and multiple light-emitting elements QD1. Exemplarily, the driving circuit QD0 may include a first input terminal Di, a second input terminal Pwr, an output terminal OT, and a common voltage terminal GND. In specific implementations, in the embodiments of this disclosure, mini light-emitting diodes (Mini-LEDs) or micro light-emitting diodes (Micro-LEDs) are small in size and high in brightness, and can be widely used in display devices or their backlight modules. By finely adjusting the backlight, high dynamic range (HDR) images can be displayed. For example, the typical size (e.g., length) of a Micro-LED is less than 100 micrometers, such as 10 micrometers to 80 micrometers; the typical size (e.g., length) of a Mini-LED is 80 micrometers to 350 micrometers, such as 80 micrometers to 120 micrometers. Exemplarily, the light-emitting element QD1 may be at least one of a Micro-LED or a Mini-LED.

[0079] In some examples, in specific implementations, the driving circuit QD0 can be configured to output a relay signal through the output terminal OT during a first time period based on a first input signal received at the first input terminal Di and a second input signal received at the second input terminal Pwr, and to form a current path with the series-connected light-emitting element QD1 through the output terminal OT during a second time period. Exemplarily, the first input terminal Di receives a first input signal, such as an address signal, to select the driving circuit QD0 corresponding to the specified address. For example, the addresses of different driving circuits QD0 may be the same or different. The first input signal can be an 8-bit address signal, and the address to be transmitted can be determined by parsing this address signal. The second input terminal Pwr receives a second input signal, such as a power line carrier communication signal. For example, the second input signal not only provides power to the driving circuit QD0 but also transmits communication data to the driving circuit QD0. This communication data can be used to control the light-emitting duration of the corresponding light-emitting unit PX, thereby controlling its visual brightness. The output terminal OT can output different signals during different time periods, such as a relay signal and a driving signal respectively. For example, the relay signal is an address signal provided to other driving circuits QD0. That is, the first input terminal Di of other driving circuits QD0 receives this relay signal as its first input signal, thereby obtaining the address signal. For example, the driving signal can be a driving current used to drive the light-emitting element QD1 to emit light. The common voltage terminal GND receives a common voltage signal, such as a ground signal.

[0080] Furthermore, the driving circuit QD0 is configured to output a relay signal through the output terminal OT during a first time period based on the first input signal received at the first input terminal Di and the second input signal received at the second input terminal Pwr, and to provide a driving signal through the output terminal OT to a plurality of sequentially connected light-emitting elements QD1 during a second time period. Specifically, during the first time period, the output terminal OT outputs a relay signal, which is provided to other driving circuits QD0 to provide address signals. During the second time period, the output terminal OT outputs a driving signal, which is provided to the plurality of sequentially connected light-emitting elements QD1, causing the light-emitting elements QD1 to emit light during the second time period. For example, the first time period and the second time period are different time periods; the first time period may, for example, be earlier than the second time period. The first time period may be consecutively connected to the second time period, with the end time of the first time period being the start time of the second time period; alternatively, there may be other time periods between the first and second time periods, which can be used to implement other required functions, or these other time periods may only be used to separate the first and second time periods to avoid interference between the signals from the output terminal OT during the first and second time periods.

[0081] It should be noted that when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light-emitting element QD1, or it can flow from the light-emitting element QD1 into the output terminal OT. The direction of the driving current flow can be determined according to actual needs, and the embodiments disclosed herein do not impose any restrictions on this. In this document, "output terminal OT outputs driving signal" means that the output terminal OT provides a driving signal, and the direction of the driving signal can be either from the output terminal OT or into the output terminal OT.

[0082] In some examples, during specific implementation, combined with Figure 2 and Figure 3 As shown, the relative positions of the driving circuit QD0 within the light-emitting unit PX can be different, or the positions of the driving circuit QD0 within the light-emitting unit PX can be the same. Furthermore, the relative positional relationship of the light-emitting elements QD1 in each light-emitting unit PX can be made the same. For example, the relative positional relationship of the light-emitting elements QD1 in a light-emitting unit PX can be used as a reference, and they can be periodically repeated along the first direction F1 and the second direction F2. For example, in a plurality of light-emitting units PX arranged in the first direction F1, the light-emitting elements QD1 located at the same position in each light-emitting unit PX can be arranged approximately along the same straight line along the first direction F1. In a plurality of light-emitting units PX arranged in the second direction F2, the light-emitting elements QD1 located at the same position in each light-emitting unit PX can be arranged approximately along the same straight line along the second direction F2.

[0083] In some examples, during specific implementation, the driving circuit QD0 may include a demodulation circuit, a physical layer interface circuit, a data processing and control circuit, a pulse width modulation circuit, a driving signal generation circuit, a relay signal generation circuit, and a power supply circuit.

[0084] Exemplarily, the demodulation circuit is electrically connected to the second input terminal Pwr and the physical layer interface circuit, and is configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit. For example, the second input signal input at the second input terminal Pwr is a power line carrier communication signal, and the power line carrier communication signal contains information corresponding to the communication data. For example, the communication data is data reflecting the light emitting duration, and thus represents the required light emitting brightness. Compared with the conventional Serial Peripheral Interface (SPI) protocol, in the embodiments of the present disclosure, by adopting the Power Line Carrier Communication (PLC) protocol, the communication data is superimposed on the power supply signal, thereby effectively reducing the number of signal lines.

[0085] As Figure 4 shown, the dashed ellipse represents an enlarged view of the corresponding waveform. When the second input signal is at a high level, the amplitude of its high level fluctuates near the threshold amplitude Vth. For example, it varies between the first amplitude V1 and the second amplitude V2, where V2 < Vth < V1. By modulating the variation law of the first amplitude V1 and the second amplitude V2, the communication data can be modulated into the second input signal, so that the second input signal transmits information corresponding to the communication data while transmitting electric energy. For example, the demodulation circuit filters out the DC power component of the second input signal, thereby obtaining the communication data. For a detailed description of the second input signal, reference can be made to the conventional power line carrier communication signal, which will not be elaborated here. Correspondingly, for a detailed description of the demodulation circuit, reference can also be made to the demodulation circuit of the conventional power line carrier communication signal, which will not be elaborated here.

[0086] Exemplarily, the physical layer interface circuit is also electrically connected to the data processing and control circuit, and is configured to process the communication data to obtain a data frame (such as frame frequency data), and transmit the data frame to the data processing and control circuit. The data frame obtained by the physical layer interface circuit contains information that needs to be transmitted to the driving circuit QD0, such as information related to the light emitting time (such as the specific duration of the light emitting time). For example, the physical layer interface circuit can be a conventional port physical layer (PHY), and for a detailed description, reference can be made to the conventional design, which will not be elaborated here.

[0087] For example, the data processing control circuit is also electrically connected to the first input terminal Di, the pulse width modulation circuit, and the relay signal generation circuit. The data processing control circuit is configured to generate a pulse width control signal based on a data frame and transmit the pulse width control signal to the pulse width modulation circuit, and to generate a relay control signal based on the first input signal and transmit the relay control signal to the relay signal generation circuit. For example, the required light-emitting duration of the light-emitting element QD1 connected to the driving circuit QD0 can be determined from the data frame, and a corresponding pulse width control signal is generated based on this light-emitting duration. For example, the relay control signal is a signal generated by the data processing control circuit after processing the first input signal. By processing the first input signal (e.g., parsing, latching, decoding, etc.), the address signal corresponding to the driving circuit QD0 can be determined, and a relay control signal corresponding to a subsequent address, which corresponds to another driving circuit QD0, will be generated. For example, the data processing control circuit can be implemented as a microcontroller, a central processing unit (CPU), a digital signal processor, etc.

[0088] Exemplarily, the pulse width modulation circuit is also electrically connected to the drive signal generation circuit and is configured to generate a pulse width modulation signal in response to a pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit. For example, the pulse width modulation signal generated by the pulse width modulation circuit corresponds to the light emission duration required by the light-emitting element QD1, such as the effective pulse width duration being equal to the light emission duration required by the light-emitting element QD1. For example, a detailed description of the pulse width modulation circuit can be found in conventional pulse width modulation circuits, and will not be detailed here.

[0089] For example, the drive signal generation circuit is also electrically connected to the output terminal OT and is configured to generate a drive signal in response to a pulse width modulation signal and output the drive signal from the output terminal OT. Here, outputting the drive signal from the output terminal OT can mean that the drive signal (e.g., drive current) flows from the output terminal OT to the light-emitting element QD1, or it can mean that the drive signal (e.g., drive current) flows from the light-emitting element QD1 into the output terminal OT; the specific direction of the current is not limited.

[0090] For example, in some examples, when the drive signal is a drive current, the drive signal generation circuit may include a current source and a metal-oxide-semiconductor (MOS) field-effect transistor (FET), referred to as a MOS transistor. The control terminal of the MOS transistor receives a pulse-width modulation (PWM) signal transmitted by the pulse-width modulation (PWM) circuit, thereby turning it on or off under the control of the PWM signal. The first terminal of the MOS transistor is connected to the output terminal OT, and the second terminal of the MOS transistor is connected to the first terminal of the current source. The second terminal of the current source is connected to the common voltage terminal GND to receive the common voltage. For example, the current source may be a constant current source.

[0091] When the pulse width modulation signal is at an active level, the MOSFET is turned on, and the current source provides drive current through the output terminal OT. When the pulse width modulation signal is at an inactive level, the MOSFET is turned off, and the output terminal OT does not provide drive current. The duration of the active level of the pulse width modulation signal is equal to the conduction duration of the MOSFET, and the conduction duration of the MOSFET is equal to the duration for which the output terminal OT provides drive current. Therefore, the emission duration of the light-emitting element QD1 can be further controlled, thereby controlling the visual brightness. For example, in some examples, when the MOSFET is turned on, the drive current flows from the OT terminal into the drive circuit QD0, and then sequentially through the MOSFET and the current source, before flowing into the ground terminal (e.g., the common voltage terminal GND). It should be noted that in the embodiments of this disclosure, the drive signal generation circuit can also adopt other circuit structures, and the embodiments of this disclosure are not limited in this regard.

[0092] Exemplarily, the relay signal generation circuit is also electrically connected to the output terminal OT and is configured to generate a relay signal based on a relay control signal and output the relay signal from the output terminal OT. For example, the relay control signal corresponds to a subsequent address, and the relay signal generated based on the relay control signal contains the subsequent address, which corresponds to another driving circuit QD0. After the relay signal is output from the output terminal OT, it is provided to the first input terminal Di of the separately provided driving circuit QD0. The relay signal is input to the separately provided driving circuit QD0 as a first input signal, thereby enabling the separately provided driving circuit QD0 to obtain the corresponding address signal. The relay signal generation circuit can be implemented by a latch, decoder, encoder, etc., and the embodiments of this disclosure are not limited thereto.

[0093] It should be noted that, in the embodiments of this disclosure, although both the drive signal generation circuit and the relay signal generation circuit are electrically connected to the output terminal OT, the drive signal generation circuit and the relay signal generation circuit output drive signals and relay signals at different time periods. The drive signals and relay signals are transmitted through the output terminal OT in a time-division manner, so they will not affect each other.

[0094] Exemplarily, the power supply circuit is electrically connected to both the demodulation circuit and the data processing control circuit, and is configured to receive electrical energy and supply power to the data processing control circuit. For example, if the second input signal is a power line carrier communication signal, after demodulation by the demodulation circuit, the DC power component (i.e., electrical energy) in the second input signal is transmitted to the power supply circuit, which then supplies power to the data processing control circuit. Of course, the embodiments of this disclosure are not limited to this; the power supply circuit can also be electrically connected to other circuits in the drive circuit QD0 to provide electrical energy. The power supply circuit can be implemented using a switching circuit, a voltage conversion circuit, a voltage regulator circuit, etc., and the embodiments of this disclosure do not limit this.

[0095] It should be noted that in the embodiments of this disclosure, the driving circuit QD0 may also include more circuits and components, not limited to the demodulation circuit, physical layer interface circuit, data processing control circuit, pulse width modulation circuit, driving signal generation circuit, relay signal generation circuit and power supply circuit mentioned above. This can be determined according to the functions to be implemented, and the embodiments of this disclosure do not limit this.

[0096] like Figure 5 As shown, when the drive circuit QD0 is working, it first powers on (i.e., is powered on) to complete initialization. Then, it performs an address write operation during time period S1. That is, during time period S1, the first input signal Di_1 is input to the drive circuit QD0 through the first input terminal Di, thereby writing the address. For example, the first input signal Di_1 is sent through a separately provided transmitter.

[0097] Next, during time period S2, drive configuration is performed, and a relay signal Di_2 is output through the output terminal OT. For example, the relay signal Di_2 is input as the first input signal to the first input terminal Di of the separately provided drive circuit QD0. For example, the aforementioned first time period is time period S2.

[0098] Then, during period S3, the drive voltage line 220 is energized. For example, after multiple drive circuits QD0 have acquired their corresponding addresses, period S3 begins approximately 10 microseconds later. At this time, the drive voltage provided by the drive voltage line 220 becomes high.

[0099] Next, during time period S4, the driving circuit QD0 is in normal operating mode, and the output terminal OT provides a driving signal (e.g., driving current) according to the required duration, so that the light-emitting element QD1 connected to the driving circuit QD0 emits light for the required duration. For example, the aforementioned second time period is time period S4. For example, in the case of a backlight unit of a display device, the light-emitting substrate using the driving circuit QD0 can achieve a high dynamic range effect by operating in local dimming mode.

[0100] Finally, during period S5, the system shuts down, that is, the drive circuit QD0 is de-energized, and the drive voltage provided by the drive voltage line 220 becomes low, and the light-emitting element QD1 stops emitting light.

[0101] It should be noted that the above workflow is merely illustrative and not restrictive. The actual workflow of the drive circuit QD0 can be determined according to actual needs, and the embodiments disclosed herein do not impose any limitations on it. Figure 5 In this diagram, VREG, POR, Vreg_1.8, OSC, and Re_B are all internal signals of the driver circuit QD0 and will not be input or output through the first input terminal Di, the second input terminal Pwr, the output terminal OT, or the common voltage terminal GND. Di_1 is the first input signal received by the driver circuit QD0, Di_2 is the relay signal output by the driver circuit QD0 (that is, the first input signal received by the next connected driver circuit QD0), and Di_n is the first input signal received by the nth driver circuit QD0 among multiple sequentially connected driver circuits QD0.

[0102] For example, in a specific implementation, the driving circuit QD0 can be configured as a chip. The chip size (e.g., length) can be tens of micrometers, and the chip area is approximately several hundred square micrometers or even smaller, similar in size to a Mini-LED. This miniaturization feature facilitates integration into the light-emitting substrate (e.g., bonding it to the surface of the light-emitting substrate), saving space on the printed circuit board, simplifying the structure, and contributing to a thinner and lighter design. Each driving circuit QD0 directly drives one light-emitting unit PX, avoiding the problems of complex operation and flickering inherent in line scanning control methods. Furthermore, the driving circuit QD0 has fewer ports, requires fewer signals, has a simple control method, simple wiring, and low cost.

[0103] In specific implementation, as described in the embodiments of this disclosure, Figures 6 to 7bAs shown, a buffer layer 400 is disposed on the substrate to improve the adhesion of the first conductive layer. The first conductive layer is located on the side of the buffer layer 400 facing away from the substrate. Exemplarily, the first conductive layer may include: a plurality of common voltage lines 210, a plurality of driving voltage lines 220, and a plurality of source voltage lines 230 disposed at intervals. Exemplarily, a row of light-emitting units PX may correspond to one common voltage line 210, one source voltage line 230, and one driving voltage line 220. Exemplarily, the plurality of common voltage lines 210, the plurality of driving voltage lines 220, and the plurality of source voltage lines 230 extend along a first direction F1. Furthermore, the plurality of common voltage lines 210, the plurality of driving voltage lines 220, and the plurality of source voltage lines 230 are arranged along a second direction F2. Exemplarily, the driving voltage lines 220, the common voltage lines 210, and the source voltage lines 230 may be repeatedly arranged along the second direction F2 in sequence. For example, for each column of light-emitting units PX, the common voltage line 210, the source voltage line 230, and the driving voltage line 220 are located between the driving voltage line 220 and the source voltage line 230 in the orthogonal projection of the common voltage line 210 onto the substrate.

[0104] For example, source voltage line 230 is electrically connected to the second input terminal Pwr of driver circuit QD0. This allows a second input signal to be transmitted to the second input terminal Pwr of driver circuit QD0 via source voltage line 230. In some examples, the second input terminal Pwr of driver circuit QD0 in a row of light-emitting units PX is electrically connected to the same source voltage line 230.

[0105] For example, the common voltage line 210 is electrically connected to the common voltage terminal GND of the driving circuit QD0, so that the voltage on the common voltage line 210 is a ground voltage, thereby providing a ground voltage signal to the common voltage terminal of the driving circuit QD0 through the common voltage line 210. In some examples, the common voltage terminal GND of the driving circuit QD0 in a row of light-emitting units PX is electrically connected to the same common voltage line 210.

[0106] It should be noted that by aligning the extension directions of most signal lines in the first conductive layer, wiring space can be rationally designed, reducing signal interference.

[0107] In some examples, in specific implementations, such as Figure 3 and Figure 6As shown, for a column of light-emitting units PX, the common voltage line 210, driving voltage line 220, and source voltage line 230 are located between the driving voltage line 220 and the source voltage line 230. For example, the width of the driving voltage line 220 in the second direction F2 is greater than the width of the source voltage line 230 in the second direction F2. The width of the source voltage line 230 in the second direction F2 is greater than the width of the cascaded trace 240 in the second direction F2.

[0108] In some examples, the first conductive layer may be a single-layer structure made of a metallic material. Alternatively, the first conductive layer may also be a multilayer structure made of a metallic material. For example, two first conductive layers made of metallic material may be used, having a C-1 layer and a C-2 layer. Exemplarily, the metallic material may include, but is not limited to, Cu.

[0109] In specific implementations, in the embodiments of this disclosure, a first insulating layer is formed on the first conductive layer, that is, the first insulating layer is located on the side of the first conductive layer facing away from the substrate. Exemplarily, the first insulating layer can be formed as a single-layer structure using inorganic, organic, or organic-inorganic composite materials. Alternatively, the first insulating layer can also be a multilayer structure formed using at least one of inorganic, organic, or organic-inorganic composite materials. For example, the first insulating layer can be formed using multiple layers of organic materials. It can also be formed using multiple layers of inorganic materials. Alternatively, it can be formed by stacking organic and inorganic materials. Exemplarily, the first insulating layer can include a first sub-insulating layer and a second sub-insulating layer. The material of the second sub-insulating layer can be an organic material, and the material of the first sub-insulating layer can be an inorganic material. Exemplarily, the inorganic material can be at least one of silicon nitride (SiNx), silicon oxide (SiOX), and silicon oxynitride (SiON). The organic material can be polyimide (PI), etc.

[0110] In some examples, in specific implementations, such as Figures 6 to 7bAs shown, a second conductive layer is formed on the first insulating layer, i.e., the second conductive layer is located on the side of the first insulating layer facing away from the substrate. A second insulating layer is also formed on the second conductive layer, i.e., the second insulating layer is located on the side of the second conductive layer facing away from the substrate. A light-emitting element QD1 is formed on the second insulating layer. Exemplarily, the second insulating layer can be formed as a single-layer structure using inorganic, organic, or organic-inorganic composite materials. Alternatively, the second insulating layer can also be a multilayer structure formed using at least one of inorganic, organic, or organic-inorganic composite materials. For example, the second insulating layer can be formed using multiple layers of organic materials. The second insulating layer can also be formed using multiple layers of inorganic materials. The second insulating layer can also be formed by stacking organic and inorganic materials. Exemplarily, the second insulating layer can include a third sub-insulating layer and a fourth sub-insulating layer. The material of the fourth sub-insulating layer can be an organic material, and the material of the third sub-insulating layer can be an inorganic material. Exemplarily, the inorganic material can be at least one of silicon nitride (SiNx), silicon oxide (SiOX), and silicon oxynitride (SiON). Organic materials can include polyimide (PI), etc.

[0111] Exemplarily, the second conductive layer may include: multiple connection pads (such as PDs) and multiple cascaded traces 240 spaced apart from each other. Exemplarily, the multiple cascaded traces 240 extend along a first direction F1. For example, along the first direction F1, the driving circuits QD0 in the light-emitting units PX in a column can be coupled to each other, and in a column, the driving circuits QD0 in adjacent light-emitting units PX are coupled through the cascaded traces 240. For example, the first row to the sixth row are defined along the direction indicated by the arrow in the first direction F1. The first column to the fifth column are defined along the direction indicated by the arrow in the second direction F2. Taking the first column as an example, the output terminal of the driving circuit QD0 in the first row of light-emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the second row of light-emitting units PX through a cascaded trace 240. The output terminal of the driving circuit QD0 in the second row of light-emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the third row of light-emitting units PX through a cascaded trace 240. The output of the driver circuit QD0 in the third row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the fourth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the fourth row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the fifth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the fifth row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the sixth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the sixth row of LED units PX is coupled to the cascaded output terminal via a cascaded output trace. This ensures that the cascaded trace 240 and the driver circuit QD0 are cascaded in the same direction, reducing signal overlap and interference.

[0112] In specific implementation, as described in the embodiments of this disclosure, Figure 7a and Figure 7b As shown, one electrode of the light-emitting element is electrically connected to a connection pad PD. For example, the positive electrode of the light-emitting element QD1 is electrically connected to one connection pad PD, and the negative electrode of the light-emitting element QD1 is electrically connected to another connection pad PD. The connection pads PD corresponding to the light-emitting elements QD1 arranged in series can be electrically connected through series trace 250. The connection pads PD corresponding to the light-emitting elements QD1 arranged in parallel can be electrically connected through the first connection part 110. The rest are similar and will not be described in detail here.

[0113] In specific implementations, in this embodiment of the disclosure, the multiple light-emitting elements QD1 in the light-emitting unit PX can be divided into multiple element groups, wherein at least two element groups in the same light-emitting unit PX are electrically connected to different driving voltage lines 220. For example, the multiple light-emitting elements QD1 in the light-emitting unit PX are divided into M element groups, each element group including N light-emitting elements QD1 arranged along a first direction F1; the M element groups are arranged along a second direction F2; N is an integer greater than 0, and M is an integer greater than 0. For example, as... Figure 3 and Figure 6 As shown, taking a light-emitting unit PX comprising nine light-emitting elements QD1, M=3, N=3 as an example, these nine light-emitting elements QD1 can be divided into three element groups Z-1, Z-2, and Z-3. Element groups Z-1, Z-2, and Z-3 are arranged along the second direction F2. Furthermore, element group Z-1 has three light-emitting elements QD1 arranged along the first direction F1, element group Z-2 also has three light-emitting elements QD1 arranged along the first direction F1, and element group Z-3 also has three light-emitting elements QD1 arranged along the first direction F1. Within the same light-emitting unit PX, element groups Z-1 and Z-2 are connected to the driving voltage line 220 on the left side of their respective light-emitting unit PX, while element group Z-3 is connected to the driving voltage line 220 on the right side of its respective light-emitting unit PX. This reduces the overlap area between the second conductive layer and the common voltage line 210.

[0114] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, a light-emitting unit PX can be connected to two driving voltage lines 220. The orthographic projection of one of the driving voltage lines 220 onto the substrate overlaps with the orthographic projection of the light-emitting unit PX onto the substrate, while the orthographic projection of the other driving voltage line 220 onto the substrate does not overlap with the orthographic projection of the light-emitting unit PX onto the substrate. For example, for the 2nd to the (N-1)th driving voltage lines 220, these driving voltage lines 220 are electrically connected to two adjacent rows of light-emitting units PX, respectively. This ensures that the load on the 2nd to the (N-1)th driving voltage lines 220 is approximately the same, improving the light emission stability. Here, N is the total number of driving voltage lines in the light-emitting substrate. In practical applications, the value of N can be determined according to the actual application requirements and is not limited here.

[0115] It should be noted that N driving voltage lines 220 are provided on the light-emitting substrate. The multiple driving voltage lines 220 provided on the light-emitting substrate can be defined and numbered in the direction indicated by the arrow in F2: the first driving voltage line 220 (e.g., the leftmost driving voltage line 220), the second driving voltage line 220, ..., the (N-1)th driving voltage line 220, and the Nth driving voltage line 220 (e.g., the rightmost driving voltage line 220).

[0116] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, the number of light-emitting units PX electrically connected to the 2nd to the (N-1)th driving voltage lines 220 can be the same. This further ensures that the load on the 2nd to the (N-1)th driving voltage lines 220 is approximately the same, further improving the light-emitting stability. Additionally, it reduces the design complexity of the light-emitting units PX.

[0117] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, the number of component groups electrically connected to the 2nd to the (N-1)th drive voltage lines 220 can be the same. This further makes the load on the 2nd to the (N-1)th drive voltage lines 220 approximately the same, further improving the light emission stability. It also further reduces the design complexity of the component groups.

[0118] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, the number of light-emitting elements QD1 electrically connected to the 2nd to the (N-1)th driving voltage lines 220 can be the same. This further makes the load on the 2nd to the (N-1)th driving voltage lines 220 approximately the same, further improving the light-emitting stability. Furthermore, it also further reduces the design complexity of the light-emitting elements QD1.

[0119] In specific implementation, as described in the embodiments of this disclosure, Figure 3 and Figure 6 As shown, different component groups within the same light-emitting unit PX can be connected in parallel. For example, the voltages across component groups Z-1, Z-2, and Z-3 are all the same. Alternatively, different component groups within the same light-emitting unit PX can be connected in parallel via a first connection. For example, the points where the voltages of component groups Z-1, Z-2, and Z-3 are lowest are connected in parallel via the first connection. That is, within the same light-emitting unit, the parallel connection point is where the voltage is lowest.

[0120] In specific implementation, as described in the embodiments of this disclosure, Figure 6As shown, in the same light-emitting unit PX, the last light-emitting element QD1 in different element groups can be electrically connected to the output terminal of the driving circuit QD0. Exemplarily, in the same light-emitting unit PX, the last light-emitting element QD1 in different element groups can be connected in parallel via the first connection portion 110. That is, in the same light-emitting unit PX, the last light-emitting element QD1 in different element groups can be electrically connected to the output terminal of the driving circuit QD0 via the first connection portion 110. For example, the last light-emitting element QD1 in element group Z-1 is electrically connected to the last light-emitting element QD1 in element group Z-2 via the first connection portion 110, and the last light-emitting element QD1 in element group Z-2 is electrically connected to the last light-emitting element QD1 in element group Z-3 via the first connection portion 110. The last light-emitting element QD1 in element group Z-3 is directly electrically connected to the output terminal of the driving circuit QD0. Exemplarily, the first connection portion 110 can be located in the second conductive layer.

[0121] In specific implementations, in this embodiment of the disclosure, within the same light-emitting unit PX, the voltage connected to the last light-emitting element QD1 in different element groups is the lowest, so that the current flow path in each element group leads to the last light-emitting element QD1 electrically connected to the output terminal of the driving circuit QD0. For example, the voltage connected to the last light-emitting element QD1 in element group Z-1 is the lowest. The voltage connected to the last light-emitting element QD1 in element group Z-2 is the lowest. The voltage connected to the last light-emitting element QD1 in element group Z-3 is the lowest.

[0122] In specific implementations, in the embodiments of this disclosure, the electrodes of the light-emitting elements QD1 connected in parallel in different element groups within the same light-emitting unit PX are of the same type. For example, the positive electrodes of the first light-emitting element QD1 in element group Z-1, the first light-emitting element QD1 in element group Z-2, and the first light-emitting element QD1 in element group Z-3 are connected in parallel. The negative electrodes of the last light-emitting element QD1 in element group Z-1, the last light-emitting element QD1 in element group Z-2, and the last light-emitting element QD1 in element group Z-3 are connected in parallel.

[0123] In specific implementations, in the embodiments of this disclosure, the voltage on the first connection portion 110 may be less than or equal to the voltage on the common voltage line 210.

[0124] In specific implementations, in the embodiments disclosed herein, the voltage on the first connection portion 110 may be less than or equal to the voltage on the driving voltage line 220.

[0125] In specific implementation, as described in the embodiments of this disclosure, Figure 6As shown, in the same element group, the light-emitting elements QD1 are arranged in series. Exemplarily, the second conductive layer may further include multiple element traces 250 spaced apart from each other; wherein, in each element group, adjacent light-emitting elements QD1 are electrically connected through the element traces 250. For example, each light-emitting element QD1 includes a positive electrode (+) and a negative electrode (-) (or, may also be referred to as an anode and a cathode). In the same element group, the positive and negative electrodes of the light-emitting elements QD1 are connected in series sequentially, and connected in series between the driving voltage line 220 and the output terminal OT, thereby forming a current flow path between the driving voltage line 220 and the output terminal OT. For example, in component group Z-1, the positive and negative terminals of the light-emitting element QD1 are connected in series sequentially, between the driving voltage line 220 and the output terminal OT. That is, the light-emitting element QD1 electrically connected to the driving voltage line 220 serves as the starting point of the series connection of these three light-emitting elements QD1 in component group Z-1, and the light-emitting element QD1 electrically connected to the output terminal OT serves as the ending point of the series connection of these three light-emitting elements QD1 in component group Z-1. Similarly, in component group Z-2, the positive and negative terminals of the light-emitting element QD1 are also connected in series sequentially, between the driving voltage line 220 and the output terminal OT. That is, the light-emitting element QD1 electrically connected to the driving voltage line 220 serves as the starting point of the series connection of these three light-emitting elements QD1 in component group Z-2, and the light-emitting element QD1 electrically connected to the output terminal OT serves as the ending point of the series connection of these three light-emitting elements QD1 in component group Z-2. The positive and negative terminals of the light-emitting element QD1 in component group Z-3 are also connected in series sequentially, and connected between the driving voltage line 220 and the output terminal OT. That is, the light-emitting element QD1 electrically connected to the driving voltage line 220 is taken as the starting point of the series connection of these three light-emitting elements QD1 in component group Z-3, and the light-emitting element QD1 electrically connected to the output terminal OT is taken as the ending point of the series connection of these three light-emitting elements QD1 in component group Z-3.

[0126] Furthermore, the second connection portion 130 corresponding to component group Z-1 and component group Z-2 is connected to the driving voltage line 220 on the left, and the second connection portion 130 corresponding to component group Z-3 is connected to the driving voltage line 220 on the right. In practical applications, the driving voltage line 220 can provide a driving voltage, for example, a high voltage during the period when the light-emitting element QD1 needs to emit light (the second period), and a low voltage during other periods. Thus, during the second period, the driving signal (e.g., driving current) flows from the driving voltage line 220 sequentially through the light-emitting element QD1 in each component and then into the output terminal OT of the driving circuit QD0. Furthermore, the light-emitting element QD1 emits light when the driving current flows, and by controlling the duration of the driving current, the light-emitting duration of the light-emitting element QD1 can be controlled, thereby controlling the visual brightness of the light emission.

[0127] Of course, the connection method of the light-emitting elements QD1 in the component group can also be to first connect some of the light-emitting elements QD1 in parallel and then connect them in series. Alternatively, the connection method of the light-emitting elements QD1 in the component group can also be to first connect some of the light-emitting elements QD1 in series and then connect them in parallel. In practical applications, the design can be determined according to actual needs, and no limitation is made here.

[0128] It should be noted that, in the embodiments of this disclosure, the number of light-emitting elements QD1 in each light-emitting unit PX is not limited, and can be any number such as 6, 8, or 12, but is not limited to 9. Multiple light-emitting elements QD1 can be arranged in any manner, such as according to a desired pattern, and are not limited to a matrix arrangement. Furthermore, the placement of the driving circuit QD0 is not limited; it can be placed in any gap between the light-emitting elements QD1, depending on actual needs. The embodiments of this disclosure do not impose any limitations on this.

[0129] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, there is a first slot between adjacent driving voltage lines 220 and common voltage lines 210, a second slot between adjacent common voltage lines 210 and source voltage lines 230, and a third slot between adjacent source voltage lines 230 and driving voltage lines 220. The first, second, and third slots each house a component group from a row of light-emitting units PX and a component trace 250 connecting adjacent light-emitting elements QD1 within the component group. For example, component group Z-2 is housed in the first slot, component group Z-3 in the second slot, and component group Z-1 in the third slot.

[0130] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, different component groups are arranged on both sides of the common voltage line 210; and the component groups located on both sides of the common voltage line 210 are electrically connected to different driving voltage lines 220. For example, two component groups in the same light-emitting unit PX are arranged on both sides of a common voltage line 210. For instance, component group Z-2 is arranged on the side of the common voltage line 210 facing the driving voltage line 220, and component group Z-3 is arranged on the side of the common voltage line 210 facing the source voltage line 230. Furthermore, component group Z-2 on the side of the common voltage line 210 facing the driving voltage line 220 is electrically connected to the driving voltage line 220 on the side of the common voltage line 210 away from the source voltage line 230, and component group Z-3 on the side of the common voltage line 210 facing the source voltage line 230 is electrically connected to the driving voltage line 220 on the side of the source voltage line 230 away from the common voltage line 210.

[0131] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, in the second direction F2, a driving voltage line 220 is provided on the side of the last source voltage line 230 facing away from the common voltage line 210. The second conductive layer may further include: a plurality of jumper wires 120; wherein, the component group located in the second cutout gap is electrically connected to the driving voltage line 220 located on the side of the source voltage line 230 facing away from the common voltage line 210 through the jumper wires 120. For example, if the component group located in the second cutout gap is Z-3, then the component group Z-3 is electrically connected to the driving voltage line 220 located on the side of the source voltage line 230 facing away from the common voltage line 210 through the jumper wires 120.

[0132] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, the orthographic projection of the jumper wire 120 onto the substrate does not overlap with the orthographic projection of the common voltage line 210 onto the substrate.

[0133] In specific implementation, as described in the embodiments of this disclosure, Figure 6 As shown, the second conductive layer may further include a plurality of second connection portions 130; wherein, in the same light-emitting unit PX, the component groups located on the side of the common voltage line 210 facing the driving voltage line 220 are respectively electrically connected to the same driving voltage line 220 through the second connection portions 130. For example, component group Z-1 is electrically connected to the driving voltage line 220 through one second connection portion 130, and component group Z-2 is electrically connected to the same driving voltage line 220 through one second connection portion 130.

[0134] Combination Figure 1a and Figure 1b In practical applications, the first conductive layer 01 and the second conductive layer 02 are typically made of low-resistance Cu. Because Cu is relatively reactive, it is prone to corrosion under an electric field. A potential difference exists between the first conductive layer 02 and the second conductive layer 04, forming the anode and cathode for electrochemical corrosion. The second conductive layer 04 acts as the positive electrode undergoing oxidation, while the first conductive layer 02 acts as the cathode undergoing reduction. The continuous electrochemical corrosion eventually leads to a short circuit between the first conductive layer 02 and the second conductive layer 04. However, the presence of electrochemical corrosion in the light-emitting substrate will affect the light-emitting stability of the substrate.

[0135] In this embodiment, since the voltage applied to the driving voltage line is greater than the voltage applied to the common voltage line, and both the second connection portion 130 and the jumper wire 120 are electrically connected to the driving voltage line, the voltages on both the second connection portion 130 and the jumper wire 120 are greater than the voltage applied to the common voltage line. In this embodiment, by connecting the light-emitting elements on both sides of the common voltage line to the driving voltage lines located on both sides of the common voltage line, the orthogonal projection of the jumper wire onto the substrate and the orthogonal projection of the common voltage line onto the substrate can be avoided. This prevents the jumper wire and the common voltage line from having directly opposite areas, thus preventing the jumper wire from undergoing a reduction reaction as a cathode and the common voltage line from undergoing an oxidation reaction as a positive electrode. Furthermore, the jumper wire is protected by a second insulating layer, and the path for moisture intrusion is relatively long. Therefore, electrochemical corrosion can be effectively reduced.

[0136] In practical applications, the thickness and number of layers of the first insulating layer can be increased to reduce electrochemical corrosion. However, in this embodiment, the orthographic projection of the jumper wire onto the substrate overlaps with the orthographic projection of the common voltage line onto the substrate. This avoids direct contact between the jumper wire and the common voltage line, thus preventing the jumper wire from acting as a cathode and undergoing a reduction reaction, and also preventing the common voltage line from acting as a cathode and undergoing an oxidation reaction. This effectively reduces electrochemical corrosion. Therefore, it is not necessary to further increase the thickness and number of layers of the first insulating layer, saving production capacity.

[0137] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7a As shown, the orthographic projection of the jumper 120 onto the substrate does not overlap with the orthographic projection of the connection pad PD onto the substrate. For example, as... Figure 6 and Figure 7a As shown, the portion BG of the jumper wire near the drive voltage line of the electrical connection may include a first clearance portion 121 and a second clearance portion 122; wherein, the first clearance portion 121 extends along a first direction F1, and the second clearance portion 122 extends along a second direction F2; the length H1 of the second clearance portion 122 ranges from 3.0 mm to 3.1 mm. For example, the length H1 of the second clearance portion 122 can be 3.0 mm. The length H1 of the second clearance portion 122 can also be 3.05 mm. The length H1 of the second clearance portion 122 can also be 3.1 mm. Of course, in practical applications, the length H1 of the second clearance portion 122 can be designed and determined according to the actual application requirements, and is not limited here.

[0138] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7aAs shown, in the same row, there is a first avoidance gap between the side of the second connection portion 130 electrically connected to the driving voltage line 220 facing the second avoidance portion 122 and the side of the second avoidance portion 122 facing away from the second connection portion 130; the width H2 of the first avoidance gap ranges from 0.9 mm to 1.0 mm. Exemplarily, the width H2 of the first avoidance gap can be 0.9 mm. The width H2 of the first avoidance gap can also be 0.95 mm. The width H2 of the first avoidance gap can also be 1.0 mm. Of course, in practical applications, the width H2 of the first avoidance gap can be designed and determined according to the requirements of practical applications, and is not limited herein.

[0139] In specific implementation, in the embodiments of the present disclosure, as Figure 6 shown, the multiple element groups in the light-emitting unit PX are sequentially numbered along the second direction F2, and the columns of the light-emitting unit PX are sequentially numbered along the second direction F2. The first light-emitting element QD1 in the element group numbered k in the light-emitting unit PX numbered a is electrically connected to the driving voltage line 220 corresponding to the light-emitting unit PX numbered a; the first light-emitting element QD1 in the element group numbered M in the light-emitting unit PX numbered a is electrically connected to the driving voltage line 220 corresponding to the light-emitting unit PX numbered a + 1. Wherein, a is an integer greater than 0, 1 ≤ k < M and k is an integer. Exemplarily, taking the light-emitting unit PX including 9 light-emitting elements QD1, M = 3, N = 3, k = 1, k = 2 as an example, as Figure 6 shown, the element group numbered 1 is Z-1, the element group numbered 2 is Z-2, and the element group numbered 3 is Z-3. In the light-emitting unit PX numbered a, the negative electrode of the last light-emitting element QD1 in the element group Z-1 numbered 1 is electrically connected to the negative electrode of the last light-emitting element QD1 in the element group Z-2 numbered 2 through a first connection portion 110. And, in the light-emitting unit PX numbered a, the negative electrode of the last light-emitting element QD1 in the element group Z-2 numbered 2 is electrically connected to the negative electrode of the last light-emitting element QD1 in the element group Z-3 numbered 3 through a first connection portion 110. And, the negative electrode of the last light-emitting element QD1 in the element group Z-3 numbered 3 in the light-emitting unit PX numbered a is electrically connected to the output end of the driving circuit QD0. Of course, in practical applications, the specific values of a, k, and M can be set according to the requirements of practical applications, and are not limited herein.

[0140] In specific implementation, in the embodiments of the present disclosure, as Figure 6As shown, the light-emitting units PX in a column are numbered sequentially along the first direction F1. The output terminal of the driving circuit QD0 of the light-emitting unit PX numbered b is coupled to the first input terminal of the driving circuit QD0 of the light-emitting unit PX numbered b+1 through a cascaded trace 240; where b is an integer greater than 0. For example, when b=1, the output terminal of the driving circuit QD0 of the light-emitting unit PX numbered 1 is coupled to the first input terminal of the driving circuit QD0 of the light-emitting unit PX numbered 2 through a cascaded trace 240. When b=2, the output terminal of the driving circuit QD0 of the light-emitting unit PX numbered 2 is coupled to the first input terminal of the driving circuit QD0 of the light-emitting unit PX numbered 3 through a cascaded trace 240. When b=3, the output terminal of the driving circuit QD0 of the light-emitting unit PX numbered 3 is coupled to the first input terminal of the driving circuit QD0 of the light-emitting unit PX numbered 4 through a cascaded trace 240. When b=4, the output terminal of the driving circuit QD0 of the light-emitting unit PX numbered 4 is coupled to the first input terminal of the driving circuit QD0 of the light-emitting unit PX numbered 5 through cascaded wiring 240. Of course, in practical applications, the specific value of b can be designed according to the actual application requirements, and is not limited here.

[0141] In specific implementation, as described in the embodiments of this disclosure, Figure 3 , Figure 6 and Figure 7b As shown, the cascaded trace 240 can be located in the first conductive layer. The first conductive layer also includes a cascaded connection line 241, and the second conductive layer includes a cascaded bridging portion 242. The first end of the cascaded trace 240 is electrically connected to the last light-emitting element QD1 in element group M of light-emitting unit PX numbered a, and the second end of the cascaded trace 240 is electrically connected to the first input terminal of the driving circuit QD0 in light-emitting unit PX numbered a+1. Furthermore, the output terminal of the driving circuit QD0 in light-emitting unit PX numbered a is electrically connected to the first end of the cascaded connection line 241 through a first cascade via GL1, the second end of the cascaded connection line 241 is electrically connected to the first end of the cascaded bridging portion 242 through a second cascade via GL2, and the second end of the cascaded bridging portion 242 is electrically connected to the first end of the cascaded trace 240 through a third cascade via GL3. For example, the second end of the cascaded trace 240 is electrically connected to the first input terminal of the driving circuit QD0 in the light-emitting unit PX numbered a+1 through the fourth cascaded via GL4.

[0142] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7bAs shown, the second conductive layer also includes a common bridging portion 211; the first end of the common bridging portion 211 is electrically connected to the common voltage terminal of the driving circuit QD0 through the first common via ND1, and the second end of the common bridging portion 211 is electrically connected to the common voltage line 210 through the second common via ND2.

[0143] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7b As shown, the first conductive layer also includes a source connection line 231; the first end of the source connection line 231 is electrically connected to the second input terminal Pwr of the driving circuit QD0 through a source via WR, and the second end of the source connection line 231 is directly electrically connected to the source voltage line 230. Exemplarily, the orthographic projection of the source connection line 231 on the substrate overlaps with the orthographic projection of the cascaded bridge portion 242 on the substrate.

[0144] In specific implementation, as described in the embodiments of this disclosure, Figures 6 to 7b As shown, the common voltage line 210 has avoidance areas on both sides, and the connection pads PD on both sides of the common voltage line 210 are located within these avoidance areas. For example, the connection pad for the light-emitting element QD1 electrically connected in component group Z-2 (numbered 2) is located in the avoidance area on the side of the common voltage line 210 facing the driving voltage line 220, while the connection pad for the light-emitting element QD1 electrically connected in component group Z-3 (numbered 3) is located in the avoidance area on the side of the common voltage line 210 away from the driving voltage line 220. In other words, the orthographic projection of the common voltage line 210 onto the substrate does not overlap with the orthographic projections of the connection pads for the light-emitting element QD1 electrically connected in component group Z-2 (numbered 2) and component group Z-3 (numbered 3).

[0145] This disclosure provides structural schematic diagrams of other light-emitting substrates, such as... Figures 8 to 9b As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0146] In specific implementation, as described in the embodiments of this disclosure, Figure 8 and Figure 9aAs shown, the first end of the cascaded trace 240 is electrically connected to the output terminal of the driving circuit QD0 in the light-emitting unit PX numbered a, and the second end of the cascaded trace 240 is electrically connected to the first input terminal of the driving circuit QD0 in the light-emitting unit PX numbered a+1. The cascaded trace 240 can be located on the second conductive layer. Furthermore, the first end of the cascaded trace 240 is electrically connected to the output terminal of the driving circuit QD0 in the light-emitting unit PX numbered a through the fourth cascaded via GL4, and the second end of the cascaded trace 240 is electrically connected to the first input terminal of the driving circuit QD0 in the light-emitting unit PX numbered a+1 through the fifth cascaded via GL5.

[0147] In specific implementation, as described in the embodiments of this disclosure, Figure 8 and Figure 9a As shown, the first conductive layer may further include a bridging portion 241; the bridging wire 120 includes a first bridging wire 1201 and a second bridging wire 1202; wherein the second bridging wire 1202 has an avoidance pattern BG. Furthermore, the first light-emitting element QD1 in the element group numbered M of the light-emitting unit PX numbered a is electrically connected to the first end of the first bridging wire 1201, the second end of the first bridging wire 1201 is electrically connected to the first end of the bridging portion 241 through the first bridging via KJ1, the second end of the bridging portion 242 is electrically connected to the first end of the second bridging wire 1202 through the second bridging via KJ2, and the second end of the second bridging wire 1202 is electrically connected to the driving voltage line 220 corresponding to the light-emitting unit PX numbered a+1. The first bridging via KJ1 and the second bridging via KJ2 respectively penetrate the first insulating layer.

[0148] In specific implementation, as described in the embodiments of this disclosure, Figure 8 and Figure 9b As shown, the orthographic projection of the bridging portion 241 on the substrate overlaps with the orthographic projection of the cascaded trace 240 on the substrate. However, the orthographic projection of the bridging line 120 on the substrate does not overlap with the orthographic projection of the cascaded trace on the substrate.

[0149] This disclosure provides structural schematic diagrams of other light-emitting substrates, such as... Figure 10 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0150] In specific implementation, as described in the embodiments of this disclosure, Figure 10 As shown, a portion of the first connection portion 110 may be located in the first conductive layer. For example, the first connection portion 110 of the component group electrically connected on both sides of the common voltage line 210 may be located in the first conductive layer.

[0151] The adapter portion connecting the negative terminal of the last light-emitting element QD1 in element group Z-2 and the adapter portion connecting the negative terminal of the last light-emitting element QD1 in element group Z-3 are electrically connected through a first connection portion 110 located in the first conductive layer. For example, regarding the first connection portion 110 connecting element group Z-2 and element group Z-3, the adapter portion connecting the negative terminal of the last light-emitting element QD1 in element group Z-2 is electrically connected to the first end of the first connection portion 110 through a via ZL3, and the adapter portion connecting the negative terminal of the last light-emitting element QD1 in element group Z-3 is electrically connected to the second end of the first connection portion 110 through a via ZL4.

[0152] In specific implementation, as described in the embodiments of this disclosure, Figure 10 As shown, the common voltage line 210 is divided into multiple second segments, and the second conductive layer further includes a second segment bridging portion 113. A first connection portion 110 is provided between adjacent second segments in the same common voltage line 210. Furthermore, adjacent second segments in the same common voltage line 210 are electrically connected through the second segment bridging portion 113. For example, for two adjacent second segments in the same common voltage line 210, the first end of the second segment bridging portion 113 is electrically connected to one second segment through a via QL3, and the second end of the second segment bridging portion 113 is electrically connected to the other second segment through a via QL4.

[0153] In specific implementation, as described in the embodiments of this disclosure, Figure 10 As shown, the orthographic projection of the second line segment bridging portion 113 on the substrate overlaps with the orthographic projection of the first connecting portion 110 on the substrate. Furthermore, the orthographic projection of the first connecting portion 110 on the substrate does not overlap with the orthographic projection of the common voltage line 210 on the substrate.

[0154] Based on the same disclosed concept, this disclosure also provides a display device, including the light-emitting substrate described above. The principle by which this display device solves the problem is similar to that of the aforementioned light-emitting substrate; therefore, the implementation of this display device can refer to the implementation of the aforementioned light-emitting substrate, and the repetitions will not be repeated here.

[0155] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0156] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A light-emitting substrate, comprising: Substrate; A first conductive layer is located on the substrate; wherein the first conductive layer includes a plurality of driving voltage lines, a plurality of common voltage lines and a plurality of source voltage lines arranged at intervals between each other, the plurality of driving voltage lines, the plurality of common voltage lines and the plurality of source voltage lines extending along a first direction, and repeatedly arranged along a second direction according to the order of the driving voltage lines, the common voltage lines and the source voltage lines; Multiple light-emitting units are located on the side of the first conductive layer away from the substrate. A first insulating layer is located between the first conductive layer and the plurality of light-emitting units; A second conductive layer is located between the first insulating layer and the plurality of light-emitting units; wherein, the second conductive layer includes a plurality of jumper wires and a plurality of component traces arranged at intervals between each other; A second insulating layer is located between the second conductive layer and the plurality of light-emitting units; Each of the light-emitting units includes a driving circuit and multiple light-emitting elements; the multiple light-emitting elements in the light-emitting unit are divided into M element groups, and each element group includes N light-emitting elements arranged along a first direction; the M element groups are arranged along a second direction; N is an integer greater than 0, and M is an integer greater than 0; in each element group, two adjacent light-emitting elements are electrically connected through the element wiring. In the same light-emitting unit, at least two element groups are electrically connected to different driving voltage lines; In the same light-emitting unit, the last light-emitting element in different element groups is electrically connected to the output terminal of the driving circuit through cascaded wiring; In the same column of light-emitting units, the driving circuits in adjacent light-emitting units are electrically connected through the cascaded wiring; At least one of the driving voltage lines is electrically connected to two adjacent columns of light-emitting units; Each row of light-emitting units corresponds to one driving voltage line, one common voltage line, and one source voltage line; and, in the second direction, the last source voltage line is provided with a driving voltage line on the side away from the common voltage line. The first conductive layer further includes a bridging portion, wherein the bridging wire includes a first bridging wire and a second bridging wire; In the two adjacent columns of light-emitting units electrically connected by the driving voltage line, two adjacent light-emitting units in the same row, one of which is electrically connected to one end of the bridging portion through the first jumper wire, and the other end of the bridging portion is electrically connected to the driving voltage line corresponding to the other light-emitting unit through the second jumper wire.

2. The light-emitting substrate as described in claim 1, wherein, One of the light-emitting units is connected to two driving voltage lines. The orthographic projection of one of the driving voltage lines on the substrate overlaps with the orthographic projection of the light-emitting unit on the substrate, while the orthographic projection of the other driving voltage line on the substrate does not overlap with the orthographic projection of the light-emitting unit on the substrate.

3. The light-emitting substrate as described in claim 2, wherein, There is a first cutout gap between adjacent driving voltage lines and common voltage lines, a second cutout gap between adjacent common voltage lines and source voltage lines, and a third cutout gap between adjacent source voltage lines and driving voltage lines. The first, second, and third cutout gaps are each provided with a group of elements in a row of light-emitting units and element traces connecting adjacent light-emitting elements in the group of elements.

4. The light-emitting substrate as described in claim 3, wherein, Different groups of elements of the same light-emitting unit are arranged on both sides of the common voltage line; and the groups of elements located on both sides of the common voltage line are electrically connected to different driving voltage lines.

5. The light-emitting substrate according to any one of claims 1-4, wherein, In the same light-emitting unit, different groups of elements are connected in parallel through a first connecting part; In the same light-emitting unit, the parallel connection point is where the voltage is lowest.

6. The light-emitting substrate as described in claim 5, wherein, The voltage at the first connection is less than or equal to the voltage of the common voltage line.

7. The light-emitting substrate as claimed in claim 6, wherein, The voltage on the common voltage line is the ground voltage.

8. The light-emitting substrate as described in claim 5, wherein, The voltage on the first connection is less than or equal to the voltage of the driving voltage line.

9. The light-emitting substrate according to any one of claims 1-4, wherein, The number of light-emitting units electrically connected to the second driving voltage line to the (N-1)th driving voltage line is the same; where N is the total number of driving voltage lines in the light-emitting substrate.

10. The light-emitting substrate as claimed in claim 9, wherein, The number of component groups electrically connected to the second drive voltage line to the (N-1)th drive voltage line is the same.

11. The light-emitting substrate as claimed in claim 10, wherein, The number of light-emitting elements electrically connected to the second driving voltage line to the (N-1)th driving voltage line is the same.

12. The light-emitting substrate according to any one of claims 1-4, wherein, The component group located in the second cutout gap is electrically connected to the drive voltage line located on the side of the source voltage line opposite to the common voltage line via the jumper wire.

13. The light-emitting substrate as claimed in claim 12, wherein, The second conductive layer also includes a plurality of connection pads; one electrode of the light-emitting element is electrically connected to one connection pad; The orthographic projection of the jumper wire onto the substrate does not overlap with the orthographic projection of the connection pad onto the substrate.

14. The light-emitting substrate as claimed in claim 13, wherein, The second conductive layer further includes: a plurality of second connection portions; wherein, in the same light-emitting unit, the component groups located on the side of the common voltage line facing the driving voltage line are respectively electrically connected to the same driving voltage line through the second connection portions; The portion of the jumper wire near the electrically connected drive voltage line includes a first clearance portion and a second clearance portion; wherein the first clearance portion extends along a first direction, and the second clearance portion extends along a second direction; the length of the second clearance portion ranges from 3.0 mm to 3.1 mm. In the same row, there is a first clearance gap between the side of the second connection portion that is electrically connected to the driving voltage line facing the second clearance portion and the side of the second clearance portion that is away from the second connection portion; the width of the first clearance gap is in the range of 0.9mm to 1.0mm.

15. The light-emitting substrate as claimed in claim 14, wherein, The projection of the jumper wire onto the substrate does not overlap with the projection of the common voltage line onto the substrate.

16. The light-emitting substrate according to any one of claims 1-4, wherein, The driving circuit includes a common voltage terminal, which is electrically connected to the common voltage line.

17. The light-emitting substrate as claimed in claim 5, wherein, The multiple element groups in the light-emitting unit are sequentially numbered along the second direction, and the light-emitting unit columns are sequentially numbered along the second direction. The first light-emitting element in the element group numbered k in the light-emitting unit numbered a is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a; the first light-emitting element in the element group numbered M in the light-emitting unit numbered a is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a + 1; In the light-emitting unit numbered a, the last light-emitting element in the element group numbered k is electrically connected to the last light-emitting element in the element group numbered k + 1 through the first connection portion; the last light-emitting element in the element group numbered M in the light-emitting unit numbered a is electrically connected to the output end of the driving circuit; where a is an integer greater than 0, 1 ≤ k < M and k is an integer.

18. The light-emitting substrate as claimed in claim 17, wherein, The cascading trace is located in the first conductive layer; the first conductive layer further includes a cascading connection line; The second conductive layer further includes a cascading bridging portion; The first end of the cascading trace is electrically connected to the last light-emitting element in the element group numbered M in the light-emitting unit numbered a, and the second end of the cascading trace is electrically connected to the first input end of the driving circuit in the light-emitting unit numbered a + 1; The output end of the driving circuit in the light-emitting unit numbered a is electrically connected to the first end of the cascading connection line through a first cascading via, the second end of the cascading connection line is electrically connected to the first end of the cascading bridging portion through a second cascading via, and the second end of the cascading bridging portion is electrically connected to the first end of the cascading trace through a third cascading via.

19. The light-emitting substrate as claimed in claim 18, wherein, The cascading trace is located in the second conductive layer; the first end of the cascading trace is electrically connected to the output end of the driving circuit in the light-emitting unit numbered a, and the second end of the cascading trace is electrically connected to the first input end of the driving circuit in the light-emitting unit numbered a + 1; The first light-emitting element in the element group numbered M in the light-emitting unit numbered a is electrically connected to the first end of the first jumper wire, the second end of the first jumper wire is electrically connected to the first end of the bridging portion through a first jumper via, the second end of the bridging portion is electrically connected to the first end of the second jumper wire through a second jumper via, and the second end of the second jumper wire is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a + 1.

20. The light-emitting substrate as claimed in claim 17, wherein, The first connection portion is located in the second conductive layer.

21. The light-emitting substrate as claimed in claim 17, wherein, The first connection portions for electrically connecting the element groups on both sides of the common voltage line are located in the first conductive layer; The common voltage line is divided into multiple second line segments, and the second conductive layer further includes a second line segment bridging portion; wherein, the first connection portions are arranged in the gaps between adjacent second line segments in the same common voltage line; and, in the same common voltage line, adjacent second line segments are electrically connected through the second line segment bridging portion.

22. The light-emitting substrate as claimed in claim 13, wherein, The common voltage line has an avoidance area; The orthographic projection of the connection pads for electrically connecting the light-emitting elements on both sides of the common voltage line on the substrate is located within the orthographic projection of the avoidance area on the substrate.

23. A display device comprising a light-emitting substrate as described in any one of claims 1-22.

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