Display panel and manufacturing method thereof

Abstract

A display panel includes a first substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel structures disposed on the first substrate. The pixel structures are electrically connected to the data lines and the scan lines. A pixel structure includes at least one active element, at least one pixel electrode, a first common electrode and a second common electrode. The at least one pixel electrode includes a first sub-electrode, a second sub-electrode and a third sub-electrode. The first sub-electrode is electrically connected to a corresponding one of the at least one active element and the second sub-electrode. The third sub-electrode is electrically connected to the second sub-electrode. The first sub-electrode, the second sub-electrode and the third sub-electrode are different film layers. The first common electrode is disposed between the first sub-electrode and the first substrate and overlaps the first sub-electrode. The second common electrode is disposed between the first sub-electrode and the third sub-electrode and overlaps the first sub-electrode and the third sub-electrode. The second sub-electrode and the second common electrode are the same film layer and are electrically insulated from each other.

Description

TECHNICAL FIELD

[0001] The present application relates to a display technology, and in particular, to a display panel and a manufacturing method thereof. BACKGROUND

[0002] Display screens are ubiquitous in today's life. Liquid crystal display panels still maintain a dominant position in the market due to their mature technology and low cost. Generally, the display pixels of a liquid crystal display panel rely on the setting of storage capacitors to maintain the required driving voltage within a frame period. In recent years, the emergence of retina display requirements, such as smart phones, tablets, or head-mounted display devices, has driven manufacturers to invest a large amount of resources in the development of retina displays with ultra-high resolution. However, as the resolution of the display increases, the size of the display pixels is continuously reduced, resulting in insufficient storage capacity of the display pixels. When the liquid crystal display panel operates in a low-frequency mode, the driving voltage of the display pixels is easily attenuated within a frame period, affecting the display quality. SUMMARY

[0003] The present application is directed to a display panel with better display quality when driven at a low frequency.

[0004] The present application is directed to a manufacturing method of a display panel with higher process integration of multiple storage capacitors.

[0005] According to an embodiment of the present application, a display panel includes a first substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel structures. The scan lines and the data lines are disposed on the first substrate and intersect each other to define a plurality of pixel regions. The pixel structures are disposed within the pixel regions and electrically connected to the data lines and the scan lines. The pixel structures each include at least one active element, at least one pixel electrode, a first common electrode, and a second common electrode. The at least one pixel electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode. The first sub-electrode is electrically connected to a corresponding one of the at least one active element. The second sub-electrode is electrically connected to the first sub-electrode. The third sub-electrode is electrically connected to the second sub-electrode. The first sub-electrode, the second sub-electrode, and the third sub-electrode are different film layers. The first common electrode is disposed between the first sub-electrode and the first substrate and overlaps the first sub-electrode. The second common electrode is disposed between the first sub-electrode and the third sub-electrode and overlaps the first sub-electrode and the third sub-electrode. The second sub-electrode and the second common electrode are the same film layer and are electrically insulated from each other.

[0006] In an embodiment according to the present application, the display panel further includes a first insulating layer disposed between the first sub-electrode and the first common electrode, and at least a portion of the first sub-electrode, the first insulating layer, and the first common electrode form a first storage capacitor.

[0007] In embodiments according to the present application, the display panel further comprises a second insulating layer disposed between the first sub-electrode and the second sub-electrode, and at least a portion of the first sub-electrode and the second insulating layer form a second storage capacitor with the second common electrode.

[0008] In embodiments according to the present application, the second insulating layer has a first opening overlapping the first sub-electrode. The second sub-electrode is disposed on the second insulating layer, and a portion of the second sub-electrode extends into the first opening and covers a surface of the first sub-electrode exposed by the first opening.

[0009] In embodiments according to the present application, the display panel further comprises a third insulating layer disposed between the second sub-electrode and a third sub-electrode, and at least a portion of the third sub-electrode and the third insulating layer form a third storage capacitor with the second common electrode.

[0010] In embodiments according to the present application, the third insulating layer has a second opening overlapping the first opening. The third sub-electrode is disposed on the third insulating layer, and is electrically connected to the second sub-electrode via the second opening.

[0011] In the display panel according to embodiments of the present application, at least a portion of the first sub-electrode and the second insulating layer form a second storage capacitor with the second common electrode, and at least a portion of the third sub-electrode and the third insulating layer form a third storage capacitor with the second common electrode.

[0012] In the display panel according to embodiments of the present application, the second common electrode overlaps the first common electrode.

[0013] In the display panel according to embodiments of the present application, the second common electrodes of the plurality of pixel structures are connected to each other, and overlap the plurality of data lines and the plurality of scan lines.

[0014] In the display panel according to embodiments of the present application, the second common electrode of each pixel structure has a first opening overlapping the second sub-electrode and a second opening overlapping at least one active element.

[0015] In the display panel according to embodiments of the present application, the at least one pixel electrode comprises a first pixel electrode, a second pixel electrode, and a third pixel electrode. The second pixel electrode and the third pixel electrode are electrically connected to each other. The at least one active element comprises a first active element and a second active element. The plurality of scan lines comprises a first scan line and a second scan line. The first active element is electrically connected to one of the data lines, the first pixel electrode, and the first scan line. The second active element is electrically connected to the one of the data lines, the second pixel electrode, the third pixel electrode, and the second scan line.

[0016] In the display panel according to the embodiment of the present application, the first common electrode and the second common electrode each overlap the first pixel electrode, the second pixel electrode and the third pixel electrode.

[0017] In the display panel according to the embodiment of the present application, the first common electrode and the second common electrode each include a first sub common electrode, a second sub common electrode and a third sub common electrode. The first sub common electrode, the second sub common electrode and the third sub common electrode of the first common electrode are electrically connected to each other and respectively overlap the first sub electrode of the first pixel electrode, the first sub electrode of the second pixel electrode and the first sub electrode of the third pixel electrode. The first sub common electrode, the second sub common electrode and the third sub common electrode of the second common electrode are electrically connected to each other and respectively overlap the second sub electrode of the first pixel electrode, the second sub electrode of the second pixel electrode and the second sub electrode of the third pixel electrode. The first sub common electrode, the second sub common electrode and the third sub common electrode of the second common electrode are electrically connected to each other and respectively overlap the third sub electrode of the first pixel electrode, the third sub electrode of the second pixel electrode and the third sub electrode of the third pixel electrode.

[0018] In the display panel according to the embodiment of the present application, the first scan line and the second scan line each extend along a first direction. The first pixel electrode is disposed between the second pixel electrode and the third pixel electrode in a second direction. The first sub common electrode of the first common electrode is disposed between the second sub common electrode of the first common electrode and the third sub common electrode of the first common electrode in the second direction. The first sub common electrode of the second common electrode is disposed between the second sub common electrode of the second common electrode and the third sub common electrode of the second common electrode in the second direction. The second direction is perpendicular to the first direction.

[0019] In the display panel according to the embodiment of the present application, the areas of the third sub electrode of the first pixel electrode, the third sub electrode of the second pixel electrode and the third sub electrode of the third pixel electrode are the same as each other.

[0020] In the display panel according to the embodiment of the present application, the first sub electrode of the second pixel electrode and the first sub electrode of the third pixel electrode are connected to each other by a connection electrode, and the connection electrode extends along the second direction.

[0021] In the display panel according to the embodiment of the present application, the connection electrode, the first sub electrode of the second pixel electrode and the first sub electrode of the third pixel electrode are the same film layer. The connection electrode overlaps the first sub common electrode of the first common electrode and the first sub common electrode of the second common electrode. The third sub electrode of the first pixel electrode overlaps and covers the connection electrode.

[0022] In the display panel according to the embodiment of the present application, the plurality of second common electrodes of the plurality of pixel structures are connected to each other and overlap the plurality of data lines and the plurality of scan lines.

[0023] In the display panel according to the embodiment of the present application, the second common electrode of each pixel structure has two first openings overlapping the second sub-electrode of the first pixel electrode and the second sub-electrode of the second pixel electrode, and two second openings overlapping the first active element and the second active element.

[0024] In the display panel according to the embodiment of the present application, the third sub-electrode of at least one pixel electrode of each of the plurality of pixel structures covers at least one active element, a corresponding one of the plurality of scan lines, and a corresponding one of the plurality of data lines.

[0025] In the display panel according to the embodiment of the present application, the display panel further comprises a second substrate, a third common electrode, and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The third common electrode is disposed on a surface of the second substrate facing the first substrate. The liquid crystal layer is disposed between the third sub-electrode of the pixel electrode and the second substrate. The third sub-electrode is a reflective electrode.

[0026] According to the embodiment of the present application, the method for manufacturing the display panel comprises: forming a first metal layer on a first substrate, forming a first insulating layer on the first metal layer, forming a second metal layer on the first insulating layer, forming a second insulating layer on the second metal layer, forming a first opening in the second insulating layer, forming a first transparent conductive layer on the second insulating layer, forming a third insulating layer on the first transparent conductive layer, forming a second opening in the third insulating layer, and forming a third metal layer on the third insulating layer. The first metal layer comprises scan lines and a first common electrode. The second metal layer comprises data lines, drains and sources of active elements, and first sub-electrodes of pixel electrodes, and the first sub-electrodes overlap the first common electrode. The first opening exposes a part of the first sub-electrode. The first transparent conductive layer comprises a second common electrode and second sub-electrodes of the pixel electrodes. The second common electrode overlaps the first sub-electrode. The second sub-electrodes are electrically connected to the first sub-electrodes through the first opening. The second opening exposes at least a part of the second sub-electrode. The third metal layer comprises third sub-electrodes of the pixel electrodes. The second common electrode overlaps the third sub-electrode, and the third sub-electrodes are electrically connected to the second sub-electrodes through the second opening.

[0027] In the method for manufacturing the display panel according to the embodiment of the present application, the method further comprises forming a second transparent conductive layer on a second substrate, and assembling the first substrate and the second substrate, so that the first substrate and the second substrate are disposed opposite to each other, and a liquid crystal layer is arranged between the first substrate and the second substrate.

[0028] Based on the above, in the display panel of the embodiments of the present invention, the pixel electrode of the pixel structure has three sub-electrodes electrically connected to each other. These sub-electrodes belong to different film layers, and two common electrodes are provided between these sub-electrodes. The storage capacitor formed by these common electrodes and these sub-electrodes has a large storage capacitance. Accordingly, the voltage retention rate when the pixel structure is driven can be effectively increased, thereby improving the display quality of the display panel during low-frequency operation. On the other hand, since one of the two common electrodes and one of these sub-electrodes are formed in the same film layer, the integration with existing display panel manufacturing processes is also high. In other words, without adding additional processes, the display panel of the present invention can combine better display quality and cost advantages. Attached Figure Description

[0029] Figure 1 This is a top view schematic diagram of the display panel according to the first embodiment of the present invention;

[0030] Figure 2 yes Figure 1 A cross-sectional view of the display panel;

[0031] Figures 3A to 31 yes Figure 2 A cross-sectional view illustrating the manufacturing process of the display panel;

[0032] Figures 4A to 4G yes Figure 1 A top view of the various film layers of the display panel;

[0033] Figure 5 This is a cross-sectional schematic diagram of the display panel according to the second embodiment of the present invention;

[0034] Figure 6 This is a cross-sectional schematic diagram of the display panel according to the third embodiment of the present invention;

[0035] Figure 7 This is a top view schematic diagram of the display panel according to the fourth embodiment of the present invention;

[0036] Figure 8 yes Figure 7 A top view of the second common electrode of the display panel;

[0037] Figure 9 This is a top view schematic diagram of the display panel according to the fifth embodiment of the present invention;

[0038] Figure 10A yes Figure 9 A cross-sectional view of the display panel along section line B-B';

[0039] Figure 10B yes Figure 9 A cross-sectional view of the display panel along section line C-C';

[0040] Figures 11A to 11D is Figure 9 a plan view of each film layer of a display panel of

[0041] Figure 12 is a plan view of a display panel of the sixth embodiment of the present application;

[0042] Figure 13 is Figure 12 a plan view of a second common electrode of a display panel of

[0043] BRIEF DESCRIPTION OF DRAWINGS

[0044] 10, 10A, 10B, 20, 30, 30A: display panel

[0045] 101: first substrate

[0046] 102: second substrate

[0047] CE1, CE1-B: first common electrode

[0048] CE1a, CE2a: first sub common electrode

[0049] CE1b, CE2b: second sub common electrode

[0050] CE1c, CE2c: third sub common electrode

[0051] CE2, CE2-A, CE2-B, CE2-C: second common electrode

[0052] CE3: third common electrode

[0053] CF: colored material layer

[0054] DE: drain

[0055] DL, DL-A: data line

[0056] GE: gate

[0057] GL, GL1, GL2: scan line

[0058] IE: connection electrode

[0059] INS1, INS2, INS3, INS4, INS3-A: insulating layer

[0060] LCL: liquid crystal layer

[0061] L-CE2, L-CE2-B: connection line

[0062] ML1, ML2, ML3: metal layer

[0063] MS: optical microstructure;

[0064] TH1, TH2: opening hole;

[0065] OP1, OP2, OP1-A, OP2-A: opening;

[0066] PA: pixel area;

[0067] PE, PE1, PE2, PE3: pixel electrode;

[0068] PEa, PE1a, PE2a, PE3a: first sub-electrode;

[0069] PEb, PE1b, PE2b, PE3b: second sub-electrode;

[0070] PEc, PE1c, PE2c, PE3c: third sub-electrode;

[0071] PX, PX-A, PX-B, PX-C: pixel structure;

[0072] SC: semiconductor pattern;

[0073] SE: source electrode;

[0074] T, T1, T2: active element;

[0075] TCL1, TCL2: transparent conductive layer;

[0076] X, Y, Z: direction;

[0077] A-A', B-B', C-C': section line. DETAILED DESCRIPTION

[0078] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0079] Figure 1 is a top view schematic diagram of a display panel of the first embodiment of the present application. Figure 2 is a sectional view schematic diagram of the display panel of Figure 1 . Figure 2 corresponds to Figure 1 sectional line A-A' of Figures 3A to 31 is a top view schematic diagram of the display panel of Figure 2 . Figures 4A to 4G is a flow sectional view of the manufacturing method of the display panel of Figure 1 . Figure 1 is not shown Figure 2The liquid crystal layer LCL, the second substrate 102, the fourth insulating layer INS4 and the third common electrode CE3.

[0080] Please refer to Figure 1 and Figure 2 The display panel 10 includes a first substrate 101 and a plurality of scan lines GL, a plurality of data lines DL and a plurality of pixel structures PX disposed on the first substrate 101. In the present embodiment, the data lines DL can be arranged along a direction X and each data line DL extends toward a direction Y, and the scan lines GL can be arranged along the direction Y and each scan line GL extends toward the direction X, wherein the direction X is perpendicular to the direction Y. More specifically, the scan lines GL intersect the data lines DL and define a plurality of pixel areas PA. The pixel structures PX are disposed within the pixel areas PA and electrically connect the data lines DL and the scan lines GL.

[0081] The pixel structure PX includes a thin film transistor T, a pixel electrode PE, a first common electrode CE1 and a second common electrode CE2. The pixel electrode PE is electrically connected to the thin film transistor T and is electrically insulated from the first common electrode CE1 and the second common electrode CE2. For example, the thin film transistor T includes a semiconductor pattern SC as a channel layer, a source electrode SE and a drain electrode DE electrically connected to different regions of the semiconductor pattern SC. In some embodiments, an ohmic contact layer is further provided between the source electrode SE and the semiconductor pattern SC and between the drain electrode DE and the semiconductor pattern SC, and the material of the ohmic contact layer can be, for example, a doped amorphous silicon layer, but is not limited thereto. In the present embodiment, a first insulating layer INS1 is provided between the gate electrode GE and the semiconductor pattern SC, and the gate electrode GE is optionally disposed below the semiconductor pattern SC to form a bottom-gate type thin film transistor. The first insulating layer INS1 is, for example, a gate insulating layer, and the material thereof can include silicon oxide, silicon nitride or other suitable dielectric materials. However, the present application is not limited thereto. In other embodiments, the gate electrode GE can also be disposed above the semiconductor pattern SC to form a top-gate type thin film transistor. In the present embodiment, the thin film transistor T is, for example, an amorphous silicon thin film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the thin film transistor T can also be a polycrystalline silicon thin film transistor (poly-Si TFT) or a metal oxide semiconductor thin film transistor.

[0082] Further, the pixel electrode PE includes a first sub-electrode PEa, a second sub-electrode PEb, and a third sub-electrode PEc, which are electrically connected to each other. The first sub-electrode PEa is coupled to the drain DE of the active element T. The second sub-electrode PEb is coupled to the first sub-electrode PEa. The third sub-electrode PEc is coupled to the second sub-electrode PEb. It is particularly noted that the first sub-electrode PEa, the second sub-electrode PEb, and the third sub-electrode PEc belong to different film layers, respectively. In the present embodiment, the first sub-electrode PEa, the source SE, and the drain DE of the active element T are in the same film layer. The second sub-electrode PEb and the third sub-electrode PEc are separated by the second insulating layer INS2. The second insulating layer INS2 has a first opening TH1 overlapping the first sub-electrode PEa. The second sub-electrode PEb is disposed on the second insulating layer INS2, and a portion of the second sub-electrode PEb extends into the first opening TH1 and covers the surface of the first sub-electrode PEa exposed by the first opening TH1, so as to electrically connect the first sub-electrode PEa. The third insulating layer INS2 has a second opening TH2 overlapping the second sub-electrode PEb. The third sub-electrode PEc is disposed on the third insulating layer INS3, and a portion of the third sub-electrode PEc extends into the second opening TH2 and covers the surface of the second sub-electrode PEb exposed by the second opening TH2, so as to electrically connect the second sub-electrode PEb via the second opening TH2. In the present embodiment, the second opening TH2 overlaps the first opening TH1 and the second sub-electrode PEb, and exposes the surface of a portion of the second sub-electrode PEb, but the present disclosure is not limited thereto. In other embodiments, the second opening TH2 overlaps the second sub-electrode PEb and exposes the surface of a portion of the second sub-electrode PEb2, but the second opening TH2 does not overlap the first opening TH1, and the third sub-electrode PEc can also be electrically connected to the second sub-electrode PEb via the second opening TH2. In the present embodiment, the third sub-electrode PEc of the pixel electrode PE optionally covers the corresponding active element T, data line DL, and scan line GL, but the present disclosure is not limited thereto.

[0083] It is noted that the overlapping relationship between the two components is, for example, that the projections of the two components along the direction Z (perpendicular to the first substrate 101) overlap each other. Hereinafter, unless otherwise specified, the overlapping relationship between the components is the projection direction Z, which will not be described again.

[0084] In the present embodiment, the second insulating layer INS2 can be a passivation layer, and its material can include, for example, silicon nitride, silicon oxide, silicon carbide, or aluminum oxide, but the material of the second insulating layer INS2 is not limited thereto. The material of the third insulating layer INS3 can include an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable material, or a stack layer of at least two of the above), an organic material (for example, polyester, polyolefin, polyacryl, polycarbonate, polyalkylene oxide, polyphenylene, polyether, polyketone, polyalcohol, polyaldehyde, or other suitable material, or a combination of the above), or other suitable material, or a combination of the above. For example, the material of the third insulating layer INS3 can include an organic material as a planarization layer, but is not limited thereto.

[0085] On the other hand, the pixel structure PX further includes a first common electrode CE1 and a second common electrode CE2. In the present embodiment, the first common electrode CE1 overlaps the second common electrode CE2, but is not limited thereto. The first common electrode CE1 is disposed between the first sub-electrode PEa and the first substrate 101, and overlaps the first sub-electrode PEa of the pixel electrode PE. The second common electrode CE2 is disposed between the first sub-electrode PEa and the third sub-electrode PEc, and overlaps the first sub-electrode PEa and the third sub-electrode PEc. It is particularly noted that the first sub-electrode PEa of the pixel electrode PE, the first common electrode CE1, and the portion of the first insulating layer INS1 overlapping the first sub-electrode PEa and the first common electrode CE1 can form a first storage capacitor of the pixel structure PX. The first sub-electrode PEa of the pixel electrode PE, the portion of the second insulating layer INS2 overlapping the second common electrode CE2 and the first sub-electrode PEa, and the second common electrode CE2 can form a second storage capacitor of the pixel structure PX. The third sub-electrode PEc of the pixel electrode PE, the second common electrode CE2, and the portion of the third insulating layer INS3 overlapping the second common electrode CE2 and the third sub-electrode PEc can form a third storage capacitor of the pixel structure PX.

[0086] Compared with the prior art in which only two conductor layers and the insulating layer interposed therebetween are used to form a storage capacitor in each pixel structure, each pixel structure PX in the present application has three storage capacitors. Since the storage capacity between the common electrodes and the sub-electrodes of the pixel electrode in the present application is large, the voltage retention rate when the pixel structure PX is driven can be increased, thereby improving the display quality of the display panel 10 when operating at low frequency. In particular, when the size of the pixel structure PX is reduced to meet the demand for high-resolution display screens, the arrangement of the above-mentioned multiple storage capacitors is more significant for improving the display quality when operating at low frequency.

[0087] In the present embodiment, the first common electrode CE1 and the gate electrode GE of the active element T are the same film layer and are electrically insulated from each other. The second common electrode CE2 and the second sub-electrode PEb of the pixel electrode PE are the same film layer and are electrically insulated from each other. That is, the two common electrodes of the pixel structure PX of the present disclosure have high integration with the current panel manufacturing process. Therefore, the display panel 10 of the present disclosure can have both cost advantage and better display quality in low frequency operation without adding additional manufacturing process.

[0088] For example, in the present embodiment, the plurality of first common electrodes CE1 of the plurality of pixel structures PX arranged along the direction X can be connected to each other to have a common potential; similarly, the plurality of second common electrodes CE2 of the pixel structures PX can also be connected to each other to have the same common potential as the first common electrodes CE1 or another different common potential, but not limited thereto.

[0089] Further, the display panel 10 further includes a second substrate 102, a third common electrode CE3 and a liquid crystal layer LCL. The second substrate 102 is arranged opposite to the first substrate 101. The third common electrode CE3 is arranged on the surface of the second substrate 102 facing the first substrate 101. The liquid crystal layer LCL is arranged between the third sub-electrode PEc of the pixel electrode PE and the third common electrode CE3. In the present embodiment, the third sub-electrode PEc of the pixel electrode PE is, for example, a reflective electrode for reflecting ambient light. The material of the reflective electrode can include a metal material with high reflectivity or other suitable material. That is, the display panel 10 of the present embodiment is a reflective liquid crystal display panel. However, the present disclosure is not limited thereto. In other embodiments, the three storage capacitances of the present disclosure can also be applied to the pixel structure of other types of display panels, for example, to the pixel structure having a reflective electrode in the reflective area of a display panel (such as a semi-transmissive-semi-reflective liquid crystal display panel), but the present disclosure is not limited thereto.

[0090] The manufacturing method of the display panel 10 will be described below by way of example.

[0091] Please refer to Figure 1 , Figure 3A and Figure 4A , Figure 4A is a top view schematic diagram of the first metal layer ML1. First, the first metal layer ML1 is formed on the first substrate 101. The first metal layer ML1 includes the gate electrode GE, the scan line GL and the first common electrode CE1. The material of the first metal layer ML1 includes, for example, molybdenum, aluminum, copper, nickel, chromium, an alloy thereof, or a laminated structure thereof. Then, the first insulating layer INS1 is formed on the first metal layer ML1, such as Figure 3BAs shown. In this embodiment, after forming the first insulating layer INS1, a semiconductor pattern SC can be formed on the first insulating layer INS1. A top view of the semiconductor pattern SC is shown below. Figure 4B As shown. The materials of the semiconductor pattern SC include, for example, amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, or metal oxide semiconductors.

[0092] Please refer to Figure 1 , Figure 3C and Figure 4C A second metal layer ML2 is formed on the first insulating layer INS1. A top view of the second metal layer ML2 is shown below. Figure 4C As shown. The second metal layer ML2 includes a data line DL, a drain DE, a source SE, and a first sub-electrode PEa. The first sub-electrode PEa overlaps the first common electrode CE1 and is electrically connected to the drain DE. Specifically, the source SE, drain DE, gate GE, semiconductor pattern SC, and a portion of the first insulating layer INS1 can form the active element T in this embodiment. The material of the second metal layer ML2 includes, for example, molybdenum, aluminum, copper, nickel, chromium, the aforementioned alloys, or the aforementioned laminated structure.

[0093] In embodiments where an ohmic contact layer is also provided between the source SE and the semiconductor pattern SC, and between the drain DE and the semiconductor pattern SC, for example in Figure 3B The step also involves forming a doped amorphous silicon layer on the semiconductor pattern SC, and then forming... Figure 3C When the second metal layer ML2 is in the middle, the doped amorphous silicon layer not covered by the drain DE and source SE is removed, and the doped amorphous silicon layer covered by the drain DE and source SE is left as an ohmic contact layer, but not limited to this.

[0094] After completing the second metal layer ML2, a second insulating layer INS2 is formed on the second metal layer ML2, such as... Figure 3D As shown. Next, a first opening TH1 is formed in the second insulating layer INS2, and this first opening TH1 exposes a portion of the first sub-electrode PEa. A top view of the first opening TH1 is shown below. Figure 4D As shown.

[0095] Please refer to Figure 3E and Figure 4E A first transparent conductive layer TCL1 is formed on the second insulating layer INS2. A top view of the first transparent conductive layer TCL1 is shown below. Figure 4EThe first transparent conductive layer TCL1 includes a second common electrode CE2 and a second sub-electrode PEb. The second common electrode CE2 overlaps the first sub-electrode PEa, and the second sub-electrode PEb is electrically connected to the first sub-electrode PEa through the first opening TH1. Next, a third insulating layer INS3 is formed on the first transparent conductive layer TCL1, as shown in Figure 3F Next, a second opening TH2 is formed in the third insulating layer INS3, and the second opening TH2 exposes at least a portion of the second sub-electrode PEb. A top view of the second opening TH2 is shown in Figure 4F

[0096] Please refer to Figure 3G and Figure 4G After the third insulating layer INS3 is completed, a third metal layer ML3 is formed on the third insulating layer INS3. A top view of the third metal layer ML3 is shown in Figure 4G The third metal layer ML3 includes a third sub-electrode PEc, and the second common electrode CE2 overlaps the third sub-electrode PEc. The third sub-electrode PEc is electrically connected to the second sub-electrode PEb through the second opening TH2. It is particularly noted that the first sub-electrode PEa, the second sub-electrode PEb, and the third sub-electrode PEc, which are electrically connected to each other and located in different film layers, can constitute a pixel electrode PE. The pixel electrode PE, the active element T, the first common electrode CE1, and the second common electrode CE2 can constitute a pixel structure PX.

[0097] Please refer to Figure 3H and Figure 3I The manufacturing method of the display panel 10 further includes forming a second transparent conductive layer TCL2 on the second substrate 102, wherein the second transparent conductive layer TCL2 includes a third common electrode CE3. After the second transparent conductive layer TCL2 is completed, the first substrate 101 and the second substrate 102 are assembled, so that the first substrate 101 and the second substrate 102 are arranged opposite to each other, and a liquid crystal layer LCL is arranged between the first substrate 101 and the second substrate 102. For example, in the present embodiment, a fourth insulating layer INS4 can be further formed between the second transparent conductive layer TCL2 and the second substrate 102, but the present disclosure is not limited thereto. In this way, the manufacturing of the display panel 10 of the present embodiment is completed.

[0098] Some other embodiments will be described in detail below, in which the same components will be denoted by the same symbols, and the description of the same technical content will be omitted. For details, please refer to the foregoing embodiments, which will not be described herein.

[0099] Figure 5 is a cross-sectional view of a display panel of a second embodiment of the present disclosure. Please refer to Figure 5 The display panel 10A of the present embodiment and Figure 2 ​The display panel 10A differs from the display panel 10 in that the surface configuration of the third insulating layer is different. Specifically, the connecting surface of the third insulating layer INS3-A of the display panel 10A to the third sub-electrode PEc of the pixel electrode PE is non-planar. In another aspect, the side of the third insulating layer INS3-A of the present embodiment facing the third sub-electrode PEc is optionally provided with a plurality of optical microstructures MS. For example, the side of the third insulating layer INS3-A facing the third sub-electrode PEc can have a concave-convex surface. Thus, the film surface of the third sub-electrode PEc covering the optical microstructures MS is substantially conformal to the optical microstructures MS. For example, when the display panel 10A is a reflective liquid crystal display panel (i.e., the third sub-electrode PEc is a reflective electrode), the visual angle range of the display panel 10A can be increased by the provision of the optical microstructures MS.

[0100] Figure 6 is a cross-sectional view of a display panel of a third embodiment of the present application. Please refer to Figure 6 , the display panel 10B of the present embodiment differs from the display panel 10 of Figure 2 in that the display panel 10B can further include a colored material layer CF disposed between the second substrate 102 and the fourth insulating layer INS4. That is, the display panel 10B of the present embodiment can be a reflective liquid crystal display panel with color display function.

[0101] Figure 7 is a top view of a display panel of a fourth embodiment of the present application, Figure 8 is a top view of a second common electrode of a display panel, Figure 7 Please refer to Figure 7 and Figure 8 , the display panel 20 of the present embodiment differs from the display panel 10 of Figure 1 in that the configuration of the second common electrode is different. Please refer to Figure 1 , Figure 4E , Figure 7 and Figure 8 . As shown in Figure 1 and Figure 4E , each pixel structure PX of the display panel 10 includes a second common electrode CE2, the second common electrode CE2 does not overlap the active element T, the scan line GL and the data line DL, the second common electrodes CE2 of two pixel structures PX adjacent along the direction X are electrically connected to each other by a connecting line L-CE2 extending along the direction X, and the connecting line L-CE2 is staggeredly overlapped with a portion of the data line DL located between the two pixel structures PX adjacent along the direction X. On the other hand, as shown in Figure 7 and Figure 8As shown, in this embodiment, each pixel structure PX-A of the display panel 20 includes a second common electrode CE2-A. The second common electrode CE2-A has a first opening OP1 overlapping the second sub-electrode PEb and a second opening OP2 overlapping the active element T. The second common electrode CE2-A also overlaps with multiple scan lines GL and multiple data lines DL of the display panel 20. More specifically, these second common electrodes CE2-A are generally disposed on the second insulating layer INS2 in the display area of ​​the display panel 20, and have a first opening OP1 overlapping the second sub-electrode PEb and a second opening OP2 overlapping the active element T.

[0102] Figure 9 This is a top view of the display panel according to the fifth embodiment of the present invention. Figure 10A and Figure 10B They are Figure 9 A cross-sectional view of the display panel along sections B-B' and C-C'. Figures 11A to 11D yes Figure 9 A top view of the various film layers of the display panel. Figure 11A for Figure 9 A top view of the first metal layer ML1 and semiconductor pattern SC of the display panel. Figure 11B This is a top view of the second metal layer ML2 and the first opening TH1. Figure 11C This is a top view of the first transparent conductive layer TCL1 and the second opening TH2. Figure 11D This is a top view of the third metal layer, ML3. Please refer to... Figure 9 , Figure 10A , Figure 10B and Figures 11A to 11D The display panel 30 in this embodiment and Figure 1 The difference in the display panel 10 is that, in order to increase the tonal gradations of the display pixels, the pixel structure PX-B of the display panel 30 has three pixel electrodes and two active elements, namely a first pixel electrode PE1, a second pixel electrode PE2, a third pixel electrode PE3, a first active element T1, and a second active element T2. In this embodiment, the first pixel electrode PE1 is electrically connected to a corresponding data line DL-A and a first scan line GL1 via the first active element T1. The second pixel electrode PE2 and the third pixel electrode PE3 are electrically connected to a corresponding data line DL-A and a second scan line GL2 via the second active element T2. Since the first active element T1 and the second active element T2 in this embodiment are similar to... Figure 1 The active element T is described in detail in the relevant paragraphs of the foregoing embodiments, and will not be repeated here.

[0103] In this embodiment, the pixel structure PX-B has a display region including a region corresponding to the first pixel electrode PE1, a region corresponding to the second pixel electrode PE2, and a region corresponding to the third pixel electrode PE3. The region of the pixel structure PX-B corresponding to the first pixel electrode PE1 can be referred to as a first sub-display region of the pixel structure PX-B, and the regions of the pixel structure PX-B corresponding to the second pixel electrode PE2 and the third pixel electrode PE3 can be referred to as a second sub-display region of the pixel structure PX-B, and the area of the second sub-display region is twice that of the first sub-display region. Because the first active element T1 is coupled to the first pixel electrode PE1, the second active element T2 is coupled to the second pixel electrode PE2 and the third pixel electrode PE3, the first active element T1 and the second active element T2 are coupled to the same data line DL-A, and the first active element T1 and the second active element T2 are coupled to the first scan line GL1 and the second scan line GL2, respectively, the first active element T1 and the second active element T2 can be controlled to be both on, one on and the other off, or both off, and the corresponding data signal is input from the data line DL-A, so that the first sub-display region and the second sub-display region are both in a dark state (i.e., the entire display region of the pixel structure PX-B is in a dark state), are in a bright state and a dark state, respectively (i.e., one-third of the display region of the pixel structure PX-B is in a bright state), are in a dark state and a bright state, respectively (i.e., two-thirds of the display region of the pixel structure PX-B is in a bright state), or are both in a bright state (i.e., the entire display region of the pixel structure PX-B is in a bright state), that is, the pixel structure PX-B can be four-level modulated. If the pixel structure PX-B is used as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, each of which can be four-level modulated, a pixel composed of three sub-pixels of different colors can be 64-level modulated. Figure 9

[0104] It is particularly noted that the first common electrode CE1-B and the second common electrode CE2-B each overlap the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In detail, the first common electrode CE1-B includes a first sub-common electrode CE1a, a second sub-common electrode CE1b, and a third sub-common electrode CE1c that are electrically connected to each other, and the first sub-common electrode CE1a, the second sub-common electrode CE1b, and the third sub-common electrode CE1c overlap the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. Similarly, the second common electrode CE2-B includes a first sub-common electrode CE2a, a second sub-common electrode CE2b, and a third sub-common electrode CE2c that are electrically connected to each other, and the first sub-common electrode CE2a, the second sub-common electrode CE2b, and the third sub-common electrode CE2c overlap the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively.

[0105] ​From another point of view, the first scan line GL1 and the second scan line GL2 each extend toward the direction X, and the first pixel electrode PE1 is disposed between the second pixel electrode PE2 and the third pixel electrode PE3 in the direction Y. The first sub-common electrode CE1a of the first common electrode CE1-B is disposed between the second sub-common electrode CE1b and the third sub-common electrode CE1c in the direction Y. The first sub-common electrode CE2a of the second common electrode CE2-B is disposed between the second sub-common electrode CE2b and the third sub-common electrode CE2c in the direction Y. Due to the layering relationship of each pixel electrode with the corresponding two sub-common electrodes of the common electrodes similar to that of the pixel structure PX of the display panel 10 of FIG. 1, please refer to the relevant paragraphs of the foregoing embodiments for detailed description, which will not be repeated here. Figure 2 Due to the layering relationship of each pixel electrode with the corresponding two sub-common electrodes of the common electrodes similar to that of the pixel structure PX of the display panel 10 of FIG. 1, please refer to the relevant paragraphs of the foregoing embodiments for detailed description, which will not be repeated here.

[0106] In the present embodiment, the first sub-electrode PE2a of the second pixel electrode PE2 is electrically connected with the first sub-electrode PE3a of the third pixel electrode PE3 through the connection electrode IE, and is electrically insulated from the first sub-electrode PE1a of the first pixel electrode PE1. For example, the connection electrode IE can extend toward the direction Y, and the connection electrode IE, the first sub-electrode PE2a of the second pixel electrode PE2 and the first sub-electrode PE3a of the third pixel electrode PE3 can be the same film layer, but not limited thereto. It is particularly noted that the connection electrode IE overlaps the first sub-common electrode CE1a of the first common electrode CE1-B and the first sub-common electrode CE2a of the second common electrode CE2-B. Accordingly, the total capacitance of the storage capacitor connecting the second pixel electrode PE2 and the third pixel electrode PE3 can be further increased. On the other hand, by overlapping and covering the connection electrode IE with the third sub-electrode PE1c of the first pixel electrode PE1, the electric field of the connection electrode IE can be prevented from escaping and coupling with the electric field of the third common electrode (not shown) on the second substrate (not shown) to affect the driving of the liquid crystal layer LCL.

[0107] In the present embodiment, the areas of the third sub-electrodes PE1c of the first pixel electrode PE1, the third sub-electrodes PE2c of the second pixel electrode PE2, and the third sub-electrodes PE3c of the third pixel electrode PE3 can be the same as each other, but are not limited thereto. As previously described, the area of the pixel structure PX-B corresponding to the first pixel electrode PE1 is the first sub-display area of the pixel structure PX-B, and the area of the pixel structure PX-B corresponding to the second pixel electrode PE2 and the third pixel electrode PE3 is the second sub-display area of the pixel structure PX-B. Since the areas of the third sub-electrodes PE1c of the first pixel electrode PE1, the third sub-electrodes PE2c of the second pixel electrode PE2, and the third sub-electrodes PE3c of the third pixel electrode PE3 can be the same as each other, the area of the second sub-display area of the present embodiment can be twice the area of the first sub-display area, but is not limited thereto. In the present embodiment, the connection and configuration relationship of the three sub-electrodes of each pixel electrode are similar to those of the pixel electrode PE of the display panel 10 of FIG. 1. Figure 1 For example, the third sub-electrode PE1c of the first pixel electrode PE1 is electrically connected to the first sub-electrode PE1a via the second sub-electrode PE1b, the third sub-electrode PE2c of the second pixel electrode PE2 is electrically connected to the first sub-electrode PE2a via the second sub-electrode PE2b, and the third sub-electrode PE3c of the third pixel electrode PE3 is electrically connected to the first sub-electrode PE3a via the second sub-electrode PE3b.

[0108] The first metal layer ML1 includes the gate electrodes GE of the first and second active elements T1 and T2, the first and second scan lines GL1 and GL2, and the first common electrode CE1-B.

[0109] The second metal layer ML2 includes the data line DL-A, the drain electrodes DE and the source electrodes SE of the first and second active elements T1 and T2, the first sub-electrodes PE1a of the first pixel electrode PE1, the first sub-electrodes PE2a of the second pixel electrode PE2, the first sub-electrodes PE3a of the third pixel electrode PE3, and the connection electrode IE, and the first, second, and third sub-common electrodes CE1a, CE1b, and CE1c of the first common electrode CE1-B respectively overlap the first sub-electrodes PE1a, PE2a, and PE3a.

[0110] The three first openings TH1 of the second insulating layer INS2 in each pixel structure PX-B respectively expose a portion of the first sub-electrode PE1a, a portion of the first sub-electrode PE2a, and a portion of the first sub-electrode PE3a.

[0111] The first transparent conductive layer TCL1 includes the second common electrode CE2-B, the second sub-electrode PE1b of the first pixel electrode PE1, the second sub-electrode PE2b of the second pixel electrode PE2, the second sub-electrode PE3b of the third pixel electrode PE3, and the connection line L-CE2-B. The first sub-common electrode CE2a, the second sub-common electrode CE2b, and the third sub-common electrode CE2c of the second common electrode CE2-B respectively overlap the first sub-electrode PE1a, the first sub-electrode PE2a, and the first sub-electrode PE3a, and the second sub-electrode PE1b, the second sub-electrode PE2b, and the second sub-electrode PE3b are respectively electrically connected to the first sub-electrode PE1a, the first sub-electrode PE2a, and the first sub-electrode PE3a through the corresponding first through holes TH1. The second common electrodes CE2-B of two pixel structures PX-B adjacent along the direction X are electrically connected to each other through the connection line L-CE2-B extending along the direction X

[0112] The three second through holes TH2 of the three insulating layers INS3 in each pixel structure PX-B respectively expose at least a portion of the second sub-electrode PE1b, at least a portion of the second sub-electrode PE2b, and at least a portion of the second sub-electrode PE3b.

[0113] The third metal layer ML3 includes the third sub-electrode PE1c of the first pixel electrode PE1, the third sub-electrode PE2c of the second pixel electrode PE2, and the third sub-electrode PE3c of the third pixel electrode PE3, the first sub-common electrode CE2a, the second sub-common electrode CE2b, and the third sub-common electrode CE2c of the second common electrode CE2-B respectively overlap the third sub-electrode PE1c, the third sub-electrode PE2c, and the third sub-electrode PE3c, and the third sub-electrode PE1c, the third sub-electrode PE2c, and the third sub-electrode PE3c are respectively electrically connected to the second sub-electrode PE1b, the second sub-electrode PE2b, and the second sub-electrode PE3b through the corresponding second through holes TH2.

[0114] The flow of the manufacturing method of the display panel 30 of the present embodiment is similar to that of the first embodiment Figures 3A to 31 and will not be described here again.

[0115] Since the sub-electrodes of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 have relatively large storage capacitances with the two common electrodes, the voltage retention rate when the pixel structure PX-B is driven can be increased, thereby improving the display quality of the display panel 30 when operating at low frequencies. In particular, when the size of the pixel structure PX-B is reduced to meet the requirements of a high-resolution display screen, the arrangement of the above-mentioned multiple storage capacitors is more significant for improving the display quality when operating at low frequencies.

[0116] On the other hand, the first common electrode CE1-B, the gate GE of the first active element T1, and the gate GE of the second active element T2 are on the same film layer and are electrically insulated from each other. The second common electrode CE2-B, the second sub-electrode PE1b of the first pixel electrode PE1, the second sub-electrode PE2b of the second pixel electrode PE2, and the second sub-electrode PE3b of the third pixel electrode PE3 are on the same film layer and are electrically insulated from each other. In other words, the two common electrodes of the pixel structure PX-B of this disclosure have a high degree of integration with existing panel manufacturing processes. Therefore, without adding additional processes, the display panel 30 of this disclosure can combine cost advantages with better display quality at low frequency operation.

[0117] Figure 12 This is a top view schematic diagram of the display panel according to the sixth embodiment of the present invention. Figure 13 yes Figure 12 A top view of the second common electrode of the display panel. Please refer to... Figure 12 and Figure 13 The display panel 30A in this embodiment and Figure 9 The difference in display panel 30 lies in the configuration of the second common electrode. Please also refer to... Figure 9 , Figure 11C , Figure 12 and Figure 13 .like Figure 9 and Figure 11C As shown, each pixel structure PX-B of the display panel 30 includes a second common electrode CE2-B. The second common electrode CE2-B does not overlap with the active element T, the scan line GL, and the data line DL. The second common electrodes CE2-B of two adjacent pixel structures PX along the direction X are electrically connected to each other by a connecting line L-CE2-B extending along the direction X, and the connecting line L-CE2-B interleaves and overlaps with a portion of the data line DL located between the two adjacent pixel structures PX. On the other hand, as Figure 12 and Figure 13As shown, in the present embodiment, each pixel structure PX-C of the display panel 30A includes a second common electrode CE2-C having a plurality of first openings OP1-A overlapping the second sub-electrodes PE1b, PE2b, PE3b of the first, second and third pixel electrodes PE1, PE2, PE3, respectively, and a plurality of second openings OP2-A overlapping the first and second active elements T1, T2, respectively, and overlapping a plurality of scan lines (e.g. scan line GL1 and scan line GL2) and a plurality of data lines DL-A of the display panel 30A. More specifically, the second common electrodes CE2-C are substantially formed on the second insulating layer INS2 in the display region of the display panel 30A, and have the plurality of first openings OP1-A and the plurality of second openings OP2-A. The first openings OP1-A overlap the second sub-electrodes PE1b, PE2b, PE3b of the first, second and third pixel electrodes PE1, PE2, PE3, respectively. The second openings OP2-A overlap the first and second active elements T1, T2 of the pixel structures PX-C, respectively.

[0118] As described above, in the display panel of the embodiments of the present application, the pixel electrode of the pixel structure has three sub-electrodes electrically connected to each other. The sub-electrodes belong to different film layers, and two common electrodes are arranged between the sub-electrodes. The storage capacitor formed by the common electrodes and the sub-electrodes has a large storage capacity. Accordingly, the voltage retention rate of the pixel structure when being driven can be effectively increased, so as to improve the display quality of the display panel when operating at a low frequency. On the other hand, since one of the two common electrodes and one of the sub-electrodes are formed in the same film layer, the integration degree with the current display panel manufacturing process is also higher. In other words, without adding additional processes, the display panel of the present application can have better display quality and cost advantage.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacements for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, Comprising: a first substrate; a plurality of scan lines and a plurality of data lines disposed on the first substrate, the plurality of scan lines intersecting the plurality of data lines and defining a plurality of pixel regions; and a plurality of pixel structures disposed within the plurality of pixel regions and electrically connected to the plurality of data lines and the plurality of scan lines, each of the plurality of pixel structures comprising: at least one active element; at least one pixel electrode, wherein each of the at least one pixel electrode comprises: a first sub-electrode electrically connected to a corresponding one of the at least one active element; a second sub-electrode electrically connected to the first sub-electrode; and a third sub-electrode electrically connected to the second sub-electrode, the first sub-electrode, the second sub-electrode, and the third sub-electrode being different film layers, the third sub-electrode covering the at least one active element, one of the plurality of data lines, and one of the plurality of scan lines; a first common electrode disposed between the first sub-electrode and the first substrate and overlapping the first sub-electrode; and a second common electrode disposed between the first sub-electrode and the third sub-electrode and overlapping the first sub-electrode and the third sub-electrode, wherein the second sub-electrode and the second common electrode are the same film layer and electrically isolated from each other.

2. The display panel of claim 1, wherein, Further comprising: a first insulating layer disposed between the first sub-electrode and the first common electrode, and at least a portion of the first sub-electrode, the first insulating layer, and the first common electrode forming a first storage capacitor.

3. The display panel of claim 1, wherein, Further comprising: a second insulating layer disposed between the first sub-electrode and the second sub-electrode, and at least a portion of the first sub-electrode, the second insulating layer, and the second common electrode forming a second storage capacitor.

4. The display panel of claim 3, wherein, The second insulating layer has a first opening overlapping the first sub-electrode, wherein the second sub-electrode is disposed on the second insulating layer, and a portion of the second sub-electrode extends into the first opening and covers a surface of the first sub-electrode exposed by the first opening.

5. The display panel of claim 4, wherein, Further comprising: a third insulating layer disposed between the second sub-electrode and the third sub-electrode, and at least a portion of the third sub-electrode, the third insulating layer, and the second common electrode forming a third storage capacitor.

6. The display panel of claim 5, wherein, The third insulating layer has a second opening overlapping the first opening, wherein the third sub-electrode is disposed on the third insulating layer and electrically connected to the second sub-electrode via the second opening.

7. The display panel of claim 1, wherein, The at least one pixel electrode comprises a first pixel electrode, a second pixel electrode, and a third pixel electrode, the second pixel electrode and the third pixel electrode being electrically connected to each other, the at least one active element comprises a first active element and a second active element, the plurality of scan lines comprises a first scan line and a second scan line, wherein the first active element is electrically connected to one of the plurality of data lines, the first pixel electrode, and the first scan line, the second active element is electrically connected to the one of the plurality of data lines, the second pixel electrode, the third pixel electrode, and the second scan line.

8. The display panel of claim 7, wherein, The first common electrode and the second common electrode each include a first sub-common electrode, a second sub-common electrode, and a third sub-common electrode, the first sub-common electrode, the second sub-common electrode, and the third sub-common electrode of the first common electrode are electrically connected to each other and respectively overlap the first sub-electrode of the first pixel electrode, the first sub-electrode of the second pixel electrode, and the first sub-electrode of the third pixel electrode, the first sub-common electrode, the second sub-common electrode, and the third sub-common electrode of the second common electrode are electrically connected to each other and respectively overlap the first sub-electrode of the first pixel electrode, the first sub-electrode of the second pixel electrode, and the first sub-electrode of the third pixel electrode, and the first sub-common electrode, the second sub-common electrode, and the third sub-common electrode of the second common electrode respectively overlap the third sub-electrode of the first pixel electrode, the third sub-electrode of the second pixel electrode, and the third sub-electrode of the third pixel electrode.

9. The display panel of claim 1, wherein, Also included are: a second substrate disposed opposite the first substrate; a third common electrode disposed on a surface of the second substrate facing the first substrate; and a liquid crystal layer disposed between the third sub-electrode and the second substrate, wherein the third sub-electrode is a reflective electrode.

10. A manufacturing method of a display panel, comprising: Included are: forming a first metal layer on a first substrate, the first metal layer including scan lines and a first common electrode; forming a first insulating layer on the first metal layer; forming a second metal layer on the first insulating layer, the second metal layer including data lines, drains and sources of active elements, and first sub-electrodes of pixel electrodes, and the first sub-electrodes overlapping the first common electrode; forming a second insulating layer on the second metal layer; forming a first opening in the second insulating layer, the first opening exposing a portion of the first sub-electrode; forming a first transparent conductive layer on the second insulating layer, the first transparent conductive layer including a second common electrode overlapping the first sub-electrode and second sub-electrodes of the pixel electrodes, the second sub-electrodes being electrically connected to the first sub-electrodes through the first opening; forming a third insulating layer on the first transparent conductive layer; forming a second opening in the third insulating layer, the second opening exposing at least a portion of the second sub-electrode; and forming a third metal layer on the third insulating layer, the third metal layer including third sub-electrodes of the pixel electrodes, the second common electrode overlapping the third sub-electrodes, and the third sub-electrodes being electrically connected to the second sub-electrodes via the second opening, the third sub-electrodes covering the active elements, the data lines, and the scan lines.

Images