Soft-start circuits, low-dropout linear regulators, chips and electronic equipment

Abstract

Embodiments of this disclosure provide a soft-start circuit, a low-dropout linear regulator, a chip, and an electronic device. The soft-start circuit includes: first and second current source circuits, first and second energy storage circuits, and an operational amplifier. The first current source circuit generates a first current under the control of a first voltage from a first voltage terminal and provides the first current to the first energy storage circuit via a first node. The first energy storage circuit stores charge from the first current to generate a ramp signal. A first input terminal of the operational amplifier is coupled to the first node. A second input terminal of the operational amplifier is coupled to a second node. The output terminal of the operational amplifier is coupled to the second current source circuit. The second current source circuit generates a second current under the control of the output signal of the operational amplifier and a reference voltage from a reference voltage terminal, and provides the second current to the second energy storage circuit via a second node. The second energy storage circuit stores charge from the second current to generate a soft-start signal at the second node.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to soft-start circuits, low-dropout linear regulators, chips, and electronic devices. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in integrated circuits to provide the power supply voltage required within the circuitry. During the startup phase of an LDO, it is desirable for the internal loop to establish slowly to prevent large inrush currents at the LDO output. Therefore, a soft-start circuit can be incorporated into the LDO to facilitate a slow startup. Summary of the Invention

[0003] The embodiments described herein provide a soft-start circuit, a low-dropout linear regulator, a chip, and an electronic device.

[0004] According to a first aspect of this disclosure, a soft-start circuit is provided. The soft-start circuit includes: a first current source circuit, a second current source circuit, a first energy storage circuit, a second energy storage circuit, and an operational amplifier. The first current source circuit is configured to generate a first current under the control of a first voltage from a first voltage terminal and provide the first current to the first energy storage circuit via a first node. The first energy storage circuit is configured to store charge from the first current to generate a ramp signal. A first input terminal of the operational amplifier is coupled to the first node. A second input terminal of the operational amplifier is coupled to a second node. The output terminal of the operational amplifier is coupled to the second current source circuit. The second current source circuit is configured to generate a second current under the control of the output signal of the operational amplifier and a reference voltage from a reference voltage terminal and provide the second current to the second energy storage circuit via a second node. The second energy storage circuit is configured to store charge from the second current to generate a soft-start signal at a second node.

[0005] In some embodiments of this disclosure, the first current source circuit includes a first transistor. The control electrode of the first transistor is coupled to a bias voltage terminal. The first electrode of the first transistor is coupled to a first voltage terminal. The second electrode of the first transistor is coupled to a first node.

[0006] In some embodiments of this disclosure, the second current source circuit includes a second transistor. The control electrode of the second transistor is coupled to the output terminal of the operational amplifier. The first electrode of the second transistor is coupled to a reference voltage terminal. The second electrode of the second transistor is coupled to a second node.

[0007] In some embodiments of this disclosure, the first energy storage circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a first node. A second terminal of the first capacitor is coupled to a second voltage terminal.

[0008] In some embodiments of this disclosure, the second energy storage circuit includes a second capacitor. A first terminal of the second capacitor is coupled to a second node. A second terminal of the second capacitor is coupled to a second voltage terminal.

[0009] In some embodiments of this disclosure, the first input terminal of the operational amplifier is an inverting input terminal. The second input terminal of the operational amplifier is a non-inverting input terminal.

[0010] According to a second aspect of this disclosure, a soft-start circuit is provided. The soft-start circuit includes: a first transistor, a second transistor, a first capacitor, a second capacitor, and an operational amplifier. The control electrode of the first transistor is coupled to a bias voltage terminal. The first electrode of the first transistor is coupled to a first voltage terminal. The second electrode of the first transistor is coupled to the inverting input terminal of the operational amplifier and a first terminal of the first capacitor. The control electrode of the second transistor is coupled to the output terminal of the operational amplifier. The first electrode of the second transistor is coupled to a reference voltage terminal. The second electrode of the second transistor is coupled to the non-inverting input terminal of the operational amplifier and a first terminal of the second capacitor. The second terminal of the first capacitor is coupled to a second voltage terminal. The second terminal of the second capacitor is coupled to a second voltage terminal.

[0011] According to a third aspect of this disclosure, a low-dropout linear regulator is provided. The low-dropout linear regulator includes a soft-start circuit as described in a first or second aspect of this disclosure.

[0012] According to a fourth aspect of this disclosure, a chip is provided. The chip includes a low-dropout linear regulator as described in a third aspect of this disclosure.

[0013] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0015] Figure 1 This is an exemplary circuit diagram of a soft-start circuit and a low-dropout linear regulator;

[0016] Figure 2 yes Figure 1 The equivalent circuit diagram of the low dropout linear regulator is shown below;

[0017] Figure 3 It is used for Figure 1 The timing diagram of some signals of the low dropout linear regulator is shown.

[0018] Figure 4 This is a schematic block diagram of a soft-start circuit according to an embodiment of the present disclosure;

[0019] Figure 5 yes Figure 4 The illustrated embodiment shows an exemplary circuit diagram of a soft-start circuit and a low-dropout linear regulator; and

[0020] Figure 6 It is used for Figure 5 The timing diagram shows some signals of the low dropout linear regulator.

[0021] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0024] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0025] Figure 1 An exemplary circuit diagram of a soft-start circuit 120 and a low-dropout linear regulator 110 is shown. Although in Figure 1The soft-start circuit 120 is shown as independent of the low-dropout linear regulator 110. Figure 1 In alternative examples, the soft-start circuit 120 can also be considered as part of the low-dropout linear regulator 110.

[0026] exist Figure 1 In the example, current source I1 charges capacitor C to generate a ramp signal Vsl on the upper plate of capacitor C. The ramp signal Vsl is provided to the control electrode of transistor Mp1. The control electrode of transistor Mp2 is provided with a fixed reference voltage Vref. The control electrode of transistor Mp3 is provided with a feedback voltage Vfb. The feedback voltage Vfb is the output voltage V of the low-dropout linear regulator 110, which is obtained through resistors R1 and R2. LDO This is achieved through voltage division. Transistors Mp1, Mp2, and Mp3 have the same width-to-length ratio.

[0027] When the voltage of the ramp signal Vsl is much smaller than the reference voltage Vref, it can be seen from the circuit connection that nearly half of the current in the op-amp tail current flows into transistor Mp1, and the other half flows into transistor Mp3, while transistor Mp2 has no effect at this time. In the overall closed-loop structure, the feedback voltage Vfb = Vsl.

[0028] When the voltage of the ramp signal Vsl is much greater than the reference voltage Vref, nearly half of the current in the op-amp tail current flows into transistor Mp2, and the other half flows into transistor Mp3. At this time, under the closed-loop effect of the overall structure, Vfb = Vref.

[0029] Figure 1 The structure shown has the following problem: when Vsl = Vref, Figure 1 The circuit structure shown can be equivalent to, for example, the circuit structure shown. Figure 2 As shown. Transistors Mp1 and Mp2 can be equivalent to transistor Mc. Transistor Mc and transistor Mp3 form an operational amplifier input pair. The aspect ratio of transistor Mc becomes twice that of transistor Mp1 (or transistor Mp2). Therefore, the aspect ratio of transistor Mc is also twice that of transistor Mp3. Under the closed-loop operation of the overall structure, the current flowing through transistor Mc and transistor Mp3 is equal, but because the aspect ratio of transistor Mc is greater than that of transistor Mp3, it is equivalent to artificially introducing a mismatch. According to the current formula of MOSFET, we know:

[0030] |Vgs_Mc|<|Vgs_Mp3|, that is, |Vsl-Vs|<|Vfb-Vs|.

[0031] Among them, Vgs_Mc represents the gate-source voltage of transistor Mc, Vgs_Mp3 represents the gate-source voltage of transistor Mp3, and Vs represents the source voltage of transistor Mc (or the source voltage of transistor Mp3).

[0032] It can be seen from the above formula that the relationship between Vfb and Vsl is:

[0033] Vfb < Vsl = Vref.

[0034] Since the output voltage V LDO of the LDO is a multiple of the feedback voltage Vfb (for example, β times), so at this time the output voltage V LDO of the LDO < Vref × β, and the waveform of the output voltage of the LDO will show an interval with an "arc" shape as shown in Figure 3 until the ramp signal Vsl rises far above the reference voltage Vref (at this time, almost no current flows through transistor Mp1), and the "arc" shape will disappear.

[0035] To avoid the non-linearity problem of the output voltage V LDO of the LDO caused by the above mismatch problem, an embodiment of the present disclosure proposes a soft-start circuit. Figure 4 FIG. shows a schematic block diagram of a soft-start circuit 420 according to an embodiment of the present disclosure. The soft-start circuit 420 includes: a first current source circuit 421, a second current source circuit 423, a first energy storage circuit 422, a second energy storage circuit 424, and an operational amplifier A.

[0036] The first current source circuit 421 is coupled to the first energy storage circuit 422 and the first input terminal of the operational amplifier A via a first node N1. The first current source circuit 421 is also coupled to a first voltage terminal V1. The first current source circuit 421 is configured to: generate a first current I1 under the control of a first voltage from the first voltage terminal V1, and provide the first current I1 to the first energy storage circuit 422 via the first node N1.

[0037] The first energy storage circuit 422 is coupled to the first current source circuit 421 and the first input terminal of the operational amplifier A via a first node N1. The first energy storage circuit 422 is also coupled to a second voltage terminal V2. The first energy storage circuit 422 is configured to store the charge from the first current I1 to generate a ramp signal Vsl.

[0038] The first input terminal of the operational amplifier A is coupled to the first node N1. The second input terminal of the operational amplifier A is coupled to a second node N2. The output terminal of the operational amplifier A is coupled to the second current source circuit 423.

[0039] The second current source circuit 423 is coupled to the second energy storage circuit 424 and the second input terminal of operational amplifier A via the second node N2. The second current source circuit 423 is also coupled to the reference voltage terminal Vref and the output terminal of operational amplifier A. The second current source circuit 423 is configured to generate a second current I2 under the control of the output signal of operational amplifier A (i.e., the signal output from the output terminal of operational amplifier A) and the reference voltage Vref from the reference voltage terminal Vref, and to provide the second current I2 to the second energy storage circuit 424 via the second node N2.

[0040] The second energy storage circuit 424 is coupled to the second current source circuit 423 and the second input terminal of operational amplifier A via the second node N2. The second energy storage circuit 424 is configured to store charge from the second current I2 to generate a soft-start signal at the second node N2.

[0041] Initially, under the clamping effect of operational amplifier A, the voltage of the first node N1 is equal to the voltage of the second node N2. Therefore, the soft-start signal initially has the same slope as the ramp signal Vsl. When the voltage of the first node N1 exceeds the voltage of the second node N2, operational amplifier A switches from closed-loop mode to open-loop mode. The voltage of the second node N2 can at most be equal to the reference voltage Vref.

[0042] The soft-start signal can be provided to one input of the error amplifier in the LDO (e.g., Figure 1 The control electrode of transistor Mp2 in the LDO is used to slowly start the LDO.

[0043] In some embodiments of this disclosure, the first input terminal of operational amplifier A is an inverting input terminal. The second input terminal of operational amplifier A is a non-inverting input terminal.

[0044] Figure 5 Show Figure 4 An exemplary circuit diagram of the soft-start circuit 520 of the illustrated embodiment is shown. The first current source circuit 521 includes a first transistor M1. The control electrode of the first transistor M1 is coupled to a bias voltage terminal Vb. The first electrode of the first transistor M1 is coupled to a first voltage terminal V1. The second electrode of the first transistor M1 is coupled to a first node N1. The magnitude of the first current I1 can be adjusted by adjusting the magnitude of the bias voltage at the bias voltage terminal Vb, thereby adjusting the slope of the ramp signal Vsl.

[0045] The second current source circuit 523 includes a second transistor M2. The control electrode of the second transistor M2 is coupled to the output terminal of operational amplifier A. The first electrode of the second transistor M2 is coupled to the reference voltage terminal Vref. The second electrode of the second transistor M2 is coupled to the second node N2.

[0046] The first energy storage circuit 522 includes a first capacitor C1. A first terminal of the first capacitor C1 is coupled to a first node N1. A second terminal of the first capacitor C1 is coupled to a second voltage terminal V2.

[0047] The second energy storage circuit 524 includes a second capacitor C2. The first terminal of the second capacitor C2 is coupled to the second node N2. The second terminal of the second capacitor C2 is coupled to the second voltage terminal V2.

[0048] A first current I1 is injected into the first capacitor C1, generating the ramp signal Vsl required for soft start-up. Under the clamping effect of operational amplifier A, the voltage at the first node N1 is equal to the voltage at the second node N2. It can be seen that the voltage at the second node N2 rises at the same slope as the voltage at the first node N1 until it equals the reference voltage Vref, and then stops increasing. However, the voltage at the first node N1 continues to rise under the charging effect of the first current I1 on the first capacitor C1. When the voltage at the first node N1 exceeds the voltage at the second node N2, operational amplifier A switches from closed-loop mode to open-loop mode. Operational amplifier A outputs a low level, fully turning on the second transistor M2, and the voltage at the second node N2 equals the reference voltage Vref. Meanwhile, the voltage at the first node N1 continues to rise to the first voltage V1.

[0049] exist Figure 1 In the scheme shown, the control electrode of transistor Mp2 is provided with a fixed reference voltage Vref, while... Figure 5 In the illustrated scheme, the control electrode of transistor Mp2 is supplied with a voltage signal that has a slow start-up process and a final value equal to Vref. The width-to-length ratio of the input pair (transistors Mp2 and Mp3) of the LDO 510 remains 1:1, and there is no artificially introduced mismatch. According to the LDO's output voltage relationship V... LDO =vfb×(R1+R2) / R1=vref×(R1+R2) / R1, we know that Figure 5 The scheme shown allows the LDO output voltage V to be... LDO The voltage waveform is as follows Figure 6 As shown. Figure 5 The proposed solution eliminates Figure 1 The problems existing in the proposed solution are as follows. Figure 6 As shown, the output voltage V of the LDO LDO There is no "curved" shaped interval.

[0050] exist Figure 5 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The voltage value of the high-voltage signal input from the first voltage terminal V1 is higher than the reference voltage Vref. The first transistor M1 and the second transistor M2 are PMOS transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 5 The examples shown have different settings.

[0051] Embodiments of this disclosure also provide an LDO. The LDO includes a soft-start circuit according to embodiments of this disclosure. One input terminal of the LDO's input pair is coupled to the output terminal of the soft-start circuit, thereby using a soft-start signal output by the soft-start circuit to slowly start the LDO.

[0052] Embodiments of this disclosure also provide a chip. This chip includes an LDO according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0053] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0054] In summary, the soft-start circuit according to the embodiments of this disclosure can avoid introducing mismatch into its coupled LDO, thereby ensuring that the output voltage of the LDO has no nonlinear range.

[0055] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0056] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0057] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0058] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A soft-start circuit, comprising: a first current source circuit, a second current source circuit, a first energy storage circuit, a second energy storage circuit, and an operational amplifier, wherein the first current source circuit is configured to generate a first current under control of a first voltage from a first voltage terminal and provide the first current to the first energy storage circuit via a first node; the first energy storage circuit is configured to store charges from the first current to generate a ramp signal; a first input terminal of the operational amplifier is coupled to the first node, a second input terminal of the operational amplifier is coupled to a second node, and an output terminal of the operational amplifier is coupled to the second current source circuit; wherein the first input terminal of the operational amplifier is an inverting input terminal, and the second input terminal of the operational amplifier is a non-inverting input terminal; the second current source circuit is configured to generate a second current under control of an output signal of the operational amplifier and a reference voltage from a reference voltage terminal, and provide the second current to the second energy storage circuit via the second node; the first voltage from the first voltage terminal is higher than the reference voltage from the reference voltage terminal; the second energy storage circuit is configured to store charges from the second current to generate a slow start signal at the second node; wherein the first current source circuit comprises a first transistor, wherein a control terminal of the first transistor is coupled to a bias voltage terminal, a first terminal of the first transistor is coupled to the first voltage terminal, and a second terminal of the first transistor is coupled to the first node; wherein the second current source circuit comprises a second transistor, wherein a control terminal of the second transistor is coupled to the output terminal of the operational amplifier, a first terminal of the second transistor is coupled to the reference voltage terminal, and a second terminal of the second transistor is coupled to the second node.

2. The soft-start circuit of claim 1, wherein, the first energy storage circuit comprises a first capacitor, wherein a first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second voltage terminal.

3. The soft-start circuit of claim 1, wherein, the second energy storage circuit comprises a second capacitor, wherein a first terminal of the second capacitor is coupled to the second node, and a second terminal of the second capacitor is coupled to the second voltage terminal.

4. A soft start circuit, comprising: a first transistor, a second transistor, a first capacitor, a second capacitor, and an operational amplifier, wherein a control terminal of the first transistor is coupled to a bias voltage terminal, a first terminal of the first transistor is coupled to a first voltage terminal, and a second terminal of the first transistor is coupled to an inverting input terminal of the operational amplifier and a first terminal of the first capacitor; a control terminal of the second transistor is coupled to an output terminal of the operational amplifier, a first terminal of the second transistor is coupled to a reference voltage terminal, and a second terminal of the second transistor is coupled to a non-inverting input terminal of the operational amplifier and a first terminal of the second capacitor; the first voltage from the first voltage terminal is higher than the reference voltage from the reference voltage terminal; a second terminal of the first capacitor is coupled to a second voltage terminal; a second terminal of the second capacitor is coupled to the second voltage terminal.

5. A low-dropout linear regulator comprising: The slow start circuit according to any one of claims 1-4.

6. A chip comprising: The low dropout linear regulator according to claim 5.

7. An electronic device comprising: The chip according to claim 6.

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