A digital domain in-memory computing circuit and method based on a bcd encoding scheme

Abstract

The application is a digital domain in-memory computing circuit and method based on a Booth encoding scheme, which is composed of a plurality of memory and computing units arranged repeatedly in columns, each memory and computing unit comprising four SRAM memory unit arrays, four Booth multiplication unit arrays, four multi-channel addition tree units, and one external shift addition unit, and the plurality of memory and computing units arranged repeatedly in columns share one Booth encoding input unit. The SRAM memory unit arrays are used to store weight data required during computation. The Booth encoding input unit performs Booth encoding on external input, the Booth multiplication unit performs multiplication operation, the multi-channel addition tree unit accumulates a plurality of Booth multiplication results, and the external shift addition unit performs shift addition on the outputs of the four addition trees to combine and output a multi-bit computation result. The application has small influence by process, voltage, and temperature, high speed and accuracy of computation, breaks through the bottleneck of long computation period in the digital domain, improves the throughput, and realizes full-precision computation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a digital domain in-memory computing circuit based on a Potts coding scheme. BACKGROUND

[0002] In the traditional von Neumann architecture, the central processing unit and the memory are separated, and the two transmit data through an interface with limited bandwidth. With the continuous development of integrated circuit design technology and manufacturing process, the performance of the processor is greatly improved, while the memory bandwidth is limited, so the problem of data transmission delay and high energy consumption is more serious, and the performance of the memory restricts the further improvement of the overall performance of the system, which is also known as the memory wall problem of the von Neumann architecture. In addition, the rapid development of artificial intelligence technology greatly increases the computing load of the processor. For the traditional von Neumann architecture processor, a large amount of energy and time is consumed in data transmission, and the processor often fails to meet the demand of neural networks for computing power and energy efficiency.

[0003] Computing-in-Memory (CIM) is a feasible method to solve the memory wall problem. Under the memory-computing integrated architecture, the memory not only retains the functions of storage and read-write, but also can support some common logic or multiply-add operations in neural networks. The processor and the memory transmit the results of in-memory computing, reducing the amount of data transmission between the two, reducing the impact of low memory bandwidth on the overall throughput of the system, and also reducing the energy consumption spent on data transmission, improving the energy efficiency of the system.

[0004] Static Random Access Memory (SRAM) is a kind of volatile memory, which has the advantages of CMOS process compatibility, fast access speed, low static power consumption, high durability, etc., and is a common memory for in-memory computing. At present, SRAM-CIM can be divided into time domain, analog domain and digital domain computing according to the computing method.

[0005] The mainstream scheme of time domain calculation is usually to use an inverter chain to realize delay, and input and weight values control the length of delay, and the delay is accumulated through the inverter chain and then quantized into a digital domain result through a time to digital convertor (TDC). Time domain calculation uses delay length to represent calculation results, and breaks through the limitation of working voltage on calculation precision in an analog domain. However, the time sequence memory-in-computing scheme is seriously affected by process, voltage and temperature (PVT), and if the linearity and matching degree of the delay unit are poor, the result accumulated through the delay chain is difficult to be correctly quantized through the TDC. Moreover, the TDC has a large area overhead, and has high requirements for the frequency and stability of a reference clock. In order to reduce the influence of the on-chip clock, some TDC designs introduce an internal delay chain or a phase-locked loop structure, which further increases the area and power consumption overhead of the TDC.

[0006] Analog domain calculation converts input data and stored weights from a digital domain into analog quantities such as voltage and current for calculation, and then quantizes the result into a digital domain after the calculation is completed. With the improvement of the accuracy of memory-in-computing, due to the upper limit of the working voltage of the circuit, the signal margin of the analog signal is further compressed, and the accuracy of analog to digital conversion is extremely high, and a high-precision analog to digital converter (ADC) and a digital to analog converter (DAC) will bring huge delay and power consumption overhead, reducing the system algorithm energy ratio. Therefore, for analog domain memory-in-computing, high precision and high algorithm energy ratio are mutually restrictive.

[0007] Digital domain calculation only involves digital logic during calculation, and has high precision and accuracy, but the adder used in the accumulation process has problems such as large power consumption and area overhead. Digital logic calculation can only implement single-bit multiplication or addition in one operation, and has low parallelism, and many logic circuits and connections are required for multiplication calculation, which will lead to difficult layout wiring and large area overhead. SUMMARY

[0008] Technical problem: The purpose of the present application is to provide a digital domain memory-in-computing circuit and method based on a Booth encoding scheme, which can realize high-speed, high-precision and high-accuracy calculation. The product of the input and the weight determines the result entering the adder tree circuit in the circuit, and the result is calculated by using a combination circuit. Compared with ordinary digital domain calculation, the circuit uses Booth encoding to realize multiplication operation, reduces the number of transistors of the multiplication unit, and reduces the period number. Compared with the analog domain, the limitation of working voltage on calculation precision is broken. Compared with the time domain, the circuit reduces the single-period time. Compared with the ADC of the analog domain and the TDC of the time domain, the present application can realize bit widening by using an external shift adder unit, the structure is simpler, high-bit output is easier to realize, and the calculation precision is improved.

[0009] Technical scheme: The digital domain memory computing circuit based on the pozz coding scheme comprises a global word line driving module, a read-write port, timing control, memory computing control, a pozz coding input unit, an external shift addition unit and 8 memory computing units arranged repeatedly in a column; each memory computing unit comprises 4 SRAM memory unit arrays, 4 pozz multiplication unit arrays, 4 multi-channel addition tree units and an external shift addition unit, and a plurality of memory computing units arranged repeatedly in a column share one pozz coding input unit.

[0010] The SRAM memory unit array comprises a plurality of split word line SRAM memory units, a local bit line, a complementary local bit line, a global bit line, a complementary global bit line, a transverse word line, a word line, a read word line, a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube; the data storage nodes of the SRAM memory units are connected with the local bit line, and the complementary data storage nodes of the SRAM memory units are connected with the complementary local bit line; the source of the first NMOS tube is connected with the global bit line, the drain is connected with the local bit line, and the gate is connected with the transverse word line; the source of the second NMOS tube is connected with the complementary global bit line, the drain is connected with the complementary local bit line, and the gate is connected with the transverse word line.

[0011] The Boz multiplication unit array includes a plurality of Boz multiplication units, a shift complement of a Boz encoding input unit, a zero setting ZERO, a result negation, and five input control lines; a Boz multiplication unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a first inverter, a second inverter, a shift unit including a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; wherein the source of the third NMOS transistor is connected to a local bit line, the drain is connected to a global bit line, and the gate is connected to a horizontal word line; the source of the fourth NMOS transistor is connected to a complementary local bit line, the drain is connected to a complementary global bit line, and the gate is connected to a horizontal word line; the source of the fifth NMOS transistor is connected to a local bit line, and the gate is connected to a global bit line, and the drain is connected to the drain of the sixth NMOS transistor, the drain of the ninth NMOS transistor, the input end of the first transmission gate, and the input end of the third transmission gate; the source of the sixth NMOS transistor is connected to the output end of the first inverter, and the gate is connected to a complementary global bit line; the source of the seventh NMOS transistor is connected to a complementary local bit line, and the gate is connected to a global bit line, and the drain is connected to the drain of the eighth NMOS transistor, the drain of the tenth NMOS transistor, the input end of the second transmission gate, and the input end of the fourth transmission gate; the source of the eighth NMOS transistor is connected to the output end of the second inverter, and the gate is connected to a complementary global bit line; the source of the ninth NMOS transistor is connected to ground, and the gate is connected to a zero setting; the source of the tenth NMOS transistor is connected to ground, and the gate is connected to a zero setting; the source of the eleventh NMOS transistor is connected to ground, the drain is connected to the highest bit PP2 of a partial product [2:0], and the gate is connected to a shift complement; the source of the twelfth NMOS transistor is connected to ground, the drain is connected to the lowest bit PP0 of a partial product [2:0], and the gate is connected to a shift; the input end of the first inverter is connected to a local bit line; the input end of the second inverter is connected to a complementary local bit line, and the output end is connected to the source of the eighth NMOS transistor; the output end of the first transmission gate is connected to the highest bit PP2 of a partial product [2:0], the control end is connected to a shift, and the complementary control end is connected to a shift complement; the output end of the second transmission gate is connected to the middle bit PP1 of a partial product [2:0], the control end is connected to a shift, and the complementary control end is connected to a shift complement; the output end of the third transmission gate is connected to the middle bit PP1 of a partial product [2:0], the control end is connected to a shift complement, and the complementary control end is connected to a shift; the output end of the fourth transmission gate is connected to the lowest bit PP0 of a partial product [2:0], the control end is connected to a shift complement, and the complementary control end is connected to a shift.

[0012] The multi-channel adder tree unit includes 7-stage adders, and 128 3-bit data are added; 128 3-bit input data PP[2:0] are input into the first-stage adders to add the 3-bit data, and 64 4-bit output data PP[3:0] of the first-stage adders are obtained; 64 4-bit data PP[3:0] are input into the second-stage adders to add the 4-bit data, and 32 5-bit output data PP[4:0] of the second-stage adders are obtained; and the above process is repeated until a 10-bit data output PP[9:0] is obtained.

[0013] The external shift adder unit includes two-stage shift adder structures, and the 4 adder tree output results of each memory and calculation unit are shifted and added to finally obtain an 18-bit data output calculation result, which represents the result of adding the multiplication of 128 channels of 3-bit input and 8-bit weight.

[0014] The Boz encoding input unit array includes a plurality of Boz encoding input units, each of which converts input 3-bit feature data INPUT[2:0] into 5-bit feature data through Boz encoding, including shift complement SHIFTB, negation and zero setting, and drives the data to the memory and calculation unit.

[0015] Each Boz multiplication unit in the Boz multiplication unit array corresponds to one Boz encoding input unit; the connection relationship between the 128 Boz multiplication units and the multi-channel adder tree unit is that the partial products PP0, PP1 and PP2 of each Boz multiplication unit are connected to the 3-bit input data PP0, PP1 and PP2 of the multi-channel adder tree unit; the 3-bit input data PP0, PP1 and PP2 of the 2n Boz multiplication unit and the 3-bit input data PP0, PP1 and PP2 of the 2n+1 Boz multiplication unit are added to obtain new 4-bit output data PP0, PP1, PP2 and PP3, and n=0, 1, …, 63.

[0016] The calculation method of the digital domain memory and calculation circuit based on the Boz encoding scheme is as follows: when the calculation period of the memory and calculation unit starts, the horizontal word line HWL is first set to low level, and the word line WL<2m> and the read word line RWL<2m+1> are opened; the high and low bit data stored in the split word line SRAM storage unit are read to the local word line LBL and the complementary local bit line LBLB, respectively; the Boz encoding signals shift SHIFTB, negation and zero setting are input from the Boz encoding input unit to the Boz multiplication module in the memory and calculation unit, and the outputs PP0, PP1 and PP2 are 3-bit Boz multiplication results; and the 128 PP0, PP1 and PP2 arranged in horizontal rows are input into the multi-channel adder tree unit, and the output results reflect the cumulative sum of the 128 memory and calculation units.

[0017] Each of the in-memory computing circuits is capable of computing 2-bit weight multiplied by 3-bit input signal, each in-memory computing circuit includes 1 Booth-coded input unit; the output signal of the in-memory computing circuit is Pout of the external shift-addition unit <n>digital domain result.

[0018] Beneficial effects: As can be seen from the technical solutions provided by the above application, the digital domain in-memory computing circuit based on the Potts coding scheme provided by the application realizes multiplication operation by Potts coding, reduces the number of transistors of the multiplication unit, and reduces the number of periods. Compared with the analog domain, the limitation of working voltage on the calculation accuracy is broken. Compared with the time domain, the circuit reduces the single-period time. Compared with the ADC in the analog domain and the TDC in the time domain, the application can realize bit widening by using external shift addition units, the structure is simpler, it is easier to realize high-bit output, and the calculation accuracy is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings described below are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0020] Figure 1 The structure schematic diagram of the digital domain in-memory computing circuit based on the Potts coding scheme provided by the embodiment of the application is shown in the figure.

[0021] Figure 2 The structure schematic diagram of the memory and calculation unit of the digital domain in-memory computing circuit based on the Potts coding scheme provided by the embodiment of the application is shown in the figure.

[0022] Figure 3 The working waveform schematic diagram of the digital domain in-memory computing circuit based on the Potts coding scheme provided by the embodiment of the application is shown in the figure.

[0023] In the figure: local bit line LBL, complementary local bit line LBLB, global bit line GBL, complementary global bit line GBLB, horizontal word line HWL, word line WL, read word line RWL, shift SHIFT, shift complement SHIFTB, zero ZERO, power supply VDD, ground VSSm; first NMOS transistor N1, second NMOS transistor N2, first PMOS transistor P1, second PMOS transistor P2, third NMOS transistor N3, fourth NMOS transistor N4, fifth NMOS transistor N5, sixth NMOS transistor N6, seventh NMOS transistor N7, eighth NMOS transistor N8, ninth NMOS transistor N9, tenth NMOS transistor N10, eleventh NMOS transistor N11, twelfth NMOS transistor N12, first inverter INV1, second inverter INV2, first transmission gate TG1, second transmission gate TG2, third transmission gate TG3, fourth transmission gate TG4. DETAILED DESCRIPTION

[0024] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0025] Embodiment

[0026] The present application is a digital domain in-memory computing circuit based on a Potts encoding scheme, the memory computing circuit is composed of 8 memory computing units arranged repeatedly in columns; the memory computing unit includes 4 SRAM memory unit arrays, 4 Potts multiplication unit arrays, 4 multi-channel addition tree units, and 1 external shift addition unit, and the plurality of memory computing units arranged repeatedly in columns share 1 Potts encoding input unit.

[0027] The SRAM memory unit array includes sixteen split word line SRAM memory units, a local bit line LBL, a complementary local bit line LBLB, a global bit line GBL, a complementary global bit line GBLB, a horizontal word line HWL, a word line WL, a read word line RWL, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2; the weight storage nodes of the SRAM memory units are connected to the local bit line LBL, the complementary weight storage nodes of the SRAM memory units are connected to the complementary local bit line LBLB, the source of the first NMOS transistor N1 is connected to the global bit line GBL, the drain is connected to the local bit line LBL, and the gate is connected to the horizontal word line HWL; the source of the second NMOS transistor N2 is connected to the complementary global bit line GBLB, the drain is connected to the complementary local bit line LBLB, and the gate is connected to the horizontal word line HWL.

[0028] Further, the SRAM memory unit is a split word line 6T-SRAM memory unit.

[0029] Further, the 6T-SRAM memory unit further includes a first NMOS transistor N1, a second NMOS transistor N2, a first inverter INV1, and a second inverter INV2. The source of the first NMOS transistor N1 is connected to the local bit line LBL, the gate is connected to the word line WL, and the drain is connected to the input end of the first inverter INV1 and the output end of the second inverter INV2, respectively; the source of the second NMOS transistor N2 is connected to the complementary local bit line LBLB, the gate is connected to the read word line RWL, and the drain is connected to the output end of the first inverter INV1 and the input end of the second inverter INV2, respectively.

[0030] Further, the first inverter INV1 comprises a first PMOS tube P1 and a first NMOS tube N1.

[0031] The wave multiplication unit array comprises a plurality of wave multiplication units, each of which comprises: a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, a first inverter INV1, a second inverter INV2, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, and a fourth transmission gate TG4. The source of the first NMOS tube N1 is connected to a local bit line LBL, the drain is connected to a global bit line GBL, and the gate is connected to a horizontal word line HWL; the source of the second NMOS tube N2 is connected to a complementary local bit line LBLB, the drain is connected to a complementary global bit line GBLB, and the gate is connected to the horizontal word line HWL; the source of the third NMOS tube N3 is connected to the local bit line LBL, the gate is connected to the global bit line GBL, and the drain is connected to the drain of the fourth NMOS tube N4, the drain of the seventh NMOS tube N7, the input end of the first transmission gate TG1, and the input end of the third transmission gate TG3; the source of the fourth NMOS tube N4 is connected to the output end of the first inverter INV1, and the gate is connected to the complementary global bit line GBLB; the source of the fifth NMOS tube N5 is connected to the complementary local bit line LBLB, the gate is connected to the global bit line GBL, and the drain is connected to the drain of the sixth NMOS tube N6, the drain of the eighth NMOS tube N8, the input end of the second transmission gate TG2, and the input end of the fourth transmission gate TG4; the source of the sixth NMOS tube N6 is connected to the output end of the second inverter INV2, and the gate is connected to the complementary global bit line GBLB; the source of the seventh NMOS tube N7 is connected to VSSm, and the gate is connected to ZERO; the source of the eighth NMOS tube N8 is connected to VSSm, and the gate is connected to ZERO; the source of the ninth NMOS tube N9 is connected to VSSm, the drain is connected to PP2, and the gate is connected to a shift complement SHIFTB; the source of the tenth NMOS tube N10 is connected to VSSm, the drain is connected to PP0, and the gate is connected to a shift SHIFT; the input end of the first inverter INV1 is connected to the local bit line LBL, and the output end is connected to the source of the fourth NMOS tube N4; the input end of the second inverter INV2 is connected to the complementary local bit line LBLB, and the output end is connected to the source of the sixth NMOS tube N6; the output end of the first transmission gate TG1 is connected to PP2, the control end is connected to the shift SHIFT, and the complementary control end is connected to the shift complement SHIFTB; the output end of the second transmission gate TG2 is connected to PP1, the control end is connected to the shift SHIFT, and the complementary control end is connected to the shift complement SHIFTB; the output end of the third transmission gate TG3 is connected to PP1, the control end is connected to the shift complement SHIFTB, and the complementary control end is connected to the shift SHIFT; the output end of the fourth transmission gate TG4 is connected to PP0, the control end is connected to the shift complement SHIFTB, and the complementary control end is connected to the shift SHIFT.

[0032] The multi-channel adder tree unit includes a 7-stage adder, which realizes addition of 128 3-bit data. The first-stage adder inputs 128 IN0, IN1, IN2 to realize addition of 3-bit data, and obtains 64 4-bit data PP0, PP1, PP2, PP3; the second-stage adder inputs IN0, IN1, IN2 to realize addition of 4-bit data, and obtains 32 5-bit data PP0, PP1, PP2, PP3, PP4, and so on, and finally obtains a 10-bit data output. Further, the external shift adder unit includes a two-stage shift adder structure, which shifts and adds the 4 adder tree output results of each storage and calculation unit, and finally obtains an 18-bit data output calculation result, which represents the result of multiplication and addition of 128 channels of 3-bit input and 8-bit weight.

[0033] Further, each stage of the in-memory computing circuit has a corresponding 1 Boz encoding input unit, and the connection relationship between the 128 Boz multiplication units and the multi-channel addition tree unit is as follows: the first addition realizes the addition of the PP0, PP1, PP2 signals of the 2n-th memory computing unit and the PP0, PP1, PP2 signals of the 2n+1-th memory computing unit to obtain new PP0, PP1, PP2, PP3; the second addition realizes the addition of the PP0, PP1, PP2, PP3 signals output by the 2n-th first adder and the PP0, PP1, PP2, PP3 signals output by the 2n+1-th first adder to obtain new PP0, PP1, PP2, PP3, PP4; the third addition realizes the addition of the PP0, PP1, PP2, PP3, PP4 signals output by the 2n-th second adder and the PP0, PP1, PP2, PP3, PP4 signals output by the 2n+1-th second adder to obtain new PP0, PP1, PP2, PP3, PP4, PP5; the fourth addition realizes the addition of the PP0, PP1, PP2, PP3, PP4, PP5 signals output by the 2n-th third adder and the PP0, PP1, PP2, PP3, PP4, PP5 signals output by the 2n+1-th third adder to obtain new PP0, PP1, PP2, PP3, PP4, PP5, PP6; the fifth addition realizes the addition of the PP0, PP1, PP2, PP3, PP4, PP5, PP6 signals output by the 2n-th fourth adder and the PP0, PP1, PP2, PP3, PP4, PP5, PP6 signals output by the 2n+1-th fourth adder to obtain new PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7; the sixth addition realizes the addition of the PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7 signals output by the 2n-th fifth adder and the PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7 signals output by the 2n+1-th fifth adder to obtain new PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8; the seventh addition realizes the addition of the PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8 signals output by the 2n-th sixth adder and the PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8 signals output by the 2n+1-th sixth adder to obtain new PP0, PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8, PP9; and the output after the inverter chain is SOUT<9:0>, where n=0, 1, …, k / 2.

[0034] Further, the connection relationship of the external shift addition unit of the memory computing unit in the in-memory computing circuit is as follows:

[0035] The first stage addition implements the shift addition of the outputs SOUT0<9:0> and SOUT1<9:0> of two multi-channel addition tree units, the SOUT1<9:0> of the second storage and calculation circuit output in the two 10-bit data is right shifted by two bits to obtain a new 13-bit A<12:0> with the SOUT0<9:0>, the second stage addition implements the shift addition of the first stage output A0<12:0> and the first stage output A1<12:0> of the second, the A1<12:0> of the first stage output of the second in the two 13-bit data is right shifted by four bits to obtain a new 18-bit A<17:0> with the A0<12:0>, and the 128-channel 8-bit weight and 3-bit input Boz multiplication accumulation sum are obtained.

[0036] Further, the Boz encoding input unit array includes a plurality of Boz encoding input units, each of which Boz encodes input 3-bit feature data into 5-bit feature data, including shift complement SHIFTB, negation, zeroing ZERO, and driving to the storage and calculation unit. Wherein, SHIFTB controls the shift, the complementary global bit line GBLB controls the negation, and ZERO controls the zeroing signal; when the Boz encoding is +2 or -2, the shift SHIFT is high; when the Boz encoding corresponds to -1 or -2, the complementary global bit line GBLB is high; when the Boz encoding corresponds to 0, the zeroing ZERO is high, and zeroing is performed.

[0037] Based on the above-mentioned digital domain storage calculation method of the calculation circuit, including the following steps: when the calculation period of the storage and calculation unit starts, first, the horizontal word line HWL is set to low, and the word line WL<2m> and the read word line RWL<2m+1> are opened, the high and low bit data stored in the split word line SRAM storage unit are read to the local bit line LBL and the complementary local bit line LBLB, respectively, the Boz encoding signal shift complement SHIFTB, negation RESERVE(B), and zeroing ZERO are input from the Boz encoding input unit to the Boz multiplication module in the storage and calculation unit, and the output PP0, PP1, and PP2 are 3-bit Boz multiplication results, the k PP0, PP1, and PP2 arranged horizontally in rows are input to the multi-channel addition tree unit, and the output result reflects the accumulation sum of the k storage and calculation units.

[0038] Further, each Boz multiplication unit of the storage calculation circuit can calculate 2-bit weight multiplied by 3-bit input signal, and each Boz multiplication unit corresponds to one Boz encoding input unit; the output signal of the storage and calculation circuit is Pout <n>the digital domain result.

[0039] Figure Three A working waveform of the embodiment is shown. When the calculation period of the storage and calculation unit starts, the weight data stored in the SRAM storage unit is first read to the local bit line LBL and the complementary word line LBLB. After the external input three-bit data arrives, the reset signal Reset is high at this time; when the Reset signal changes from high to low, it marks the end of a calculation period.

[0040] Further, each Booth multiplication unit can calculate 2bit weight multiplied by 3bit input, each storage and calculation unit includes a Booth encoding input unit, and the storage and calculation circuit composed of k storage and calculation units can calculate the sum of k 3bit weights multiplied by 2bit input. The external shift addition unit realizes the shift sum of four k storage and calculation circuits. It should be noted that the output signal of the circuit is Pout of the external shift addition unit <n>The 18-digit domain result of the

[0041] The details of the application are known.

[0042] The above description is only the preferred embodiment of the application, but the protection scope of the application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the application, which should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.< / n> < / n> < / n>

Claims

1. A digital domain in-memory computing circuit based on a Potts encoding scheme, characterized by: The circuit comprises a global word line driving module, a read-write port, timing control, storage-computation control, a Booth encoding input unit, an external shift addition unit, and eight storage-computation units arranged repeatedly in columns; each storage-computation unit comprises four SRAM storage unit arrays, four Booth multiplication unit arrays, four multi-channel addition tree units, and one external shift addition unit; the multiple storage-computation units arranged repeatedly in columns share one Booth encoding input unit; The Booth encoding input unit array comprises multiple Booth encoding input units, each of which encodes the input 3-bit feature data INPUT[2:0] into 5-bit feature data, including shift complement SHIFT(B), negation RESERVE(B), and zeroing ZERO, and drives the data to the storage-computation unit. Each level of the Booth multiplication unit array corresponds to one Booth encoding input unit; the connection relationship between the 128 Booth multiplication units and the multi-channel addition tree units is that the partial product PP0, PP1, PP2 signals of each Booth multiplication unit are connected to the 3-bit input data PP0, PP1, PP2 of the multi-channel addition tree unit; the 3-bit output data PP0, PP1, PP2 signals of the 2n-th Booth multiplication unit are added to the 3-bit output data PP0, PP1, PP2 signals of the 2n+1-th Booth multiplication unit to obtain new 4-bit multi-channel addition tree output data PP0, PP1, PP2, PP3, n=0, 1, …, 63.

2. The digital in-memory computing circuit based on a polar encoding scheme according to claim 1, wherein, The SRAM storage unit array comprises multiple split word line SRAM storage units, local bit lines (LBL), complementary local bit lines (LBLB), global bit lines (GBL), complementary global bit lines (GBLB), horizontal word lines (HWL), word lines (WL), read word lines (RWL), first NMOS tubes (N1), second NMOS tubes (N2), first PMOS tubes (P1), and second PMOS tubes (P2); the data storage nodes of the SRAM storage units are connected to the local bit lines (LBL), and the complementary data storage nodes of the SRAM storage units are connected to the complementary local bit lines (LBLB); the source of the first NMOS tube (N1) is connected to the global bit line (GBL), the drain is connected to the local bit line (LBL), and the gate is connected to the horizontal word line (HWL); the source of the second NMOS tube (N2) is connected to the complementary global bit line (GBLB), the drain is connected to the complementary local bit line (LBLB), and the gate is connected to the horizontal word line (HWL).

3. The digital in-memory computing circuit based on a polar encoding scheme according to claim 1, wherein, The wave multiplication unit array comprises a plurality of wave multiplication units, and the shift complement (SHIFTB), the zero (ZERO), and the result of the inverse of the wave encoding input unit are simultaneously input to the plurality of wave multiplication units as five input control lines; one wave multiplication unit comprises a third NMOS tube (N3), a fourth NMOS tube (N4), a fifth NMOS tube (N5), a sixth NMOS tube (N6), a seventh NMOS tube (N7), an eighth NMOS tube (N8), a ninth NMOS tube (N9), a tenth NMOS tube (N10), an eleventh NMOS tube (N11), a twelfth NMOS tube (N12), a first inverter (INV1), and a second inverter (INV2), and the shift unit comprises a first transmission gate (TG1), a second transmission gate (TG2), a third transmission gate (TG3), and a fourth transmission gate (TG4); wherein the source of the third NMOS tube (N3) is connected to a local bit line (LBL), the drain is connected to a global bit line (GBL), and the gate is connected to a horizontal word line (HWL); the source of the fourth NMOS tube (N4) is connected to a complementary local bit line (LBLB), the drain is connected to a complementary global bit line (GBLB), and the gate is connected to the horizontal word line (HWL); the source of the fifth NMOS tube (N5) is connected to the local bit line (LBL), and the gate is connected to the global bit line (GBL); the drain is connected to the drain of the sixth NMOS tube (N6), the drain of the ninth NMOS tube (N9), the input end of the first transmission gate (TG1), and the input end of the third transmission gate (TG3); the source of the sixth NMOS tube (N6) is connected to the output end of the first inverter (INV1), and the gate is connected to the complementary global bit line (GBLB); the source of the seventh NMOS tube (N7) is connected to the complementary local bit line (LBLB), and the gate is connected to the global bit line (GBL); the drain is connected to the drain of the eighth NMOS tube (N8), the drain of the tenth NMOS tube (N10), the input end of the second transmission gate (TG2), and the input end of the fourth transmission gate (TG4); the source of the eighth NMOS tube (N8) is connected to the output end of the second inverter (INV2), and the gate is connected to the complementary global bit line (GBLB); the source of the ninth NMOS tube (N9) is connected to ground (VSSm), and the gate is connected to the zero (ZERO); the source of the tenth NMOS tube (N10) is connected to ground (VSSm), and the gate is connected to the zero (ZERO); the source of the eleventh NMOS tube (N11) is connected to ground (VSSm), the drain is connected to the highest bit (PP2) of the partial product [2:0], and the gate is connected to the shift complement (SHIFTB); the source of the twelfth NMOS tube (N12) is connected to ground (VSSm), the drain is connected to the lowest bit (PP0) of the partial product [2:0], and the gate is connected to the shift (SHIFT); the input end of the first inverter (INV1) is connected to the local bit line (LBL); and the input end of the second inverter (INV2) is connected to the complementary local bit line (LBLB), and the output end is connected to the source of the eighth NMOS tube (N8).The output end of the first transfer gate (TG1) is connected with the highest bit (PP2) of the partial product [2:0], the control end is connected with the shift (SHIFT), and the complementary control end is connected with the shift complement (SHIFTB); the output end of the second transfer gate (TG2) is connected with the middle bit (PP1) of the partial product [2:0], the control end is connected with the shift (SHIFT), and the complementary control end is connected with the shift complement (SHIFTB); the output end of the third transfer gate (TG3) is connected with the middle bit (PP1) of the partial product [2:0], the control end is connected with the shift complement (SHIFTB), and the complementary control end is connected with the shift (SHIFT); the output end of the fourth transfer gate (TG4) is connected with the lowest bit (PP0) of the partial product [2:0], the control end is connected with the shift complement (SHIFTB), and the complementary control end is connected with the shift (SHIFT).

4. The digital in-memory computing circuit based on the Potts encoding scheme according to claim 1, wherein, The multi-channel addition tree unit comprises seven adders, which realize the addition of 128 3-bit data; the first adder inputs 128 3-bit input data PP[2:0] to realize the addition of 3-bit data, and obtains 64 4-bit output data PP[3:0] of the first adder; the second adder inputs 64 4-bit data PP[3:0] to realize the addition of 4-bit data, and obtains 32 5-bit output data PP[4:0] of the second adder; and in this way, finally, one 10-bit data output PP[9:0] is obtained.

5. The digital in-memory computing circuit based on the Potts encoding scheme according to claim 1, wherein, The external shift adder unit includes two-stage shift adder structure, and the 4 addition trees of each memory and calculation unit are shifted and added to finally obtain an 18-bit data output calculation result, which represents the result of multiplication and addition of 128 channels of 3-bit input and 8-bit weight.

6. A method of computing for a digital in-memory computing circuit based on a polar encoding scheme according to any one of claims 1 to 5, characterized in that, When the calculation period of the memory and calculation unit starts, the horizontal word line HWL is first set to low level, and the word line WL<2m> and the read word line RWL<2m+1> are opened, the high and low bit data stored in the split word line SRAM memory unit are read to the local word line LBL and the complementary local bit line LBLB respectively, the Booth encoding signal shift SHIFTB, inversion, zero ZERO are input from the Booth encoding input unit to the Booth multiplication module in the memory and calculation unit, and the 3-bit output results PP0, PP1 and PP2 of the Booth multiplication unit are output, a total of 3-bit Booth multiplication results, and the 3-bit output results PP0, PP1 and PP2 of the 128 Booth multiplication units arranged in rows horizontally are input to the multi-channel addition tree unit, and the output results reflect the cumulative sum of the 128 memory and calculation units.

7. The method of claim 6, wherein the method further comprises: Each of the in-memory computing circuits is capable of calculating 2-bit weight multiplied by 3-bit input signal, each in-memory computing circuit includes 1 Booth-coded input unit; the output signal of the in-memory computing circuit is Pout of the external shift-addition unit <n>The digital domain result.< / n>

Images