Power management method and power management apparatus

Abstract

The present application provides a power management method and a power management device. The method includes reading a specific memory, wherein the specific memory includes a plurality of failure data records; selecting a specific data record based on a usage status indicator of each failure data record; sequentially sending an enabling signal to each hardware device; in response to determining that no enabling success response corresponding to the enabling signal is received from the specific hardware device, or a boot-up warning is received, obtaining at least a low bit value and a power management state; recording the low bit value and the power management state in the specific data record, and updating the usage status indicator of the specific data record accordingly. In this way, relevant maintenance personnel can know what kind of failure state may occur on the electronic device by checking the content of the specific memory, thereby improving the efficiency of subsequent debugging / maintenance.

Description

Technical Field

[0001] This invention relates to a power management mechanism, and more particularly to a power management method and power management device suitable for a central processing unit (CPU). Background Technology

[0002] Generally, during the computer boot-up process, the CPU needs to undergo a startup / enabling procedure. Since the CPU contains various hardware devices / components, these hardware devices / components must be enabled sequentially according to the specifications in the relevant CPU circuit datasheet when the CPU is booted up.

[0003] However, if a hardware device / component malfunctions during the power-on process, it often causes repair personnel to encounter difficulties in repair because they cannot determine the cause of the malfunction. Summary of the Invention

[0004] In view of this, the present invention provides a power management method and a power management device, which can be used to solve the above-mentioned technical problems.

[0005] This invention provides a power management method suitable for controlling a power management device with multiple hardware devices, comprising: reading a specific memory in the power management device, wherein the specific memory includes multiple fault data records, each fault data record having a usage status indicator; selecting a specific data record from the multiple fault data records based on the usage status indicator of each fault data record; sequentially sending an enable signal to each hardware device; in response to determining that a successful enable response corresponding to the enable signal has not been received from a specific hardware device among the multiple hardware devices, or receiving a power-on alarm, acquiring at least a low pin value and a power management status; recording the low pin value and the power management status in the specific data record, and updating the usage status indicator of the specific data record accordingly.

[0006] This invention provides a power management device that controls multiple hardware devices. The power management device includes a specific memory and a power management circuit. The specific memory includes multiple fault data records, and each fault data record has a usage status indicator. The power management circuit is coupled to the specific memory and configured to: read the specific memory in the power management device; select a specific data record from the multiple fault data records based on the usage status indicator of each fault data record; sequentially send a co-enabled signal to each hardware device; in response to determining that a co-enabled success response corresponding to the enable signal has not been received from a specific hardware device among the multiple hardware devices, or receiving a power-on alarm, obtain at least a low pin value and a power management status; record the low pin value and the power management status in the specific data record, and update the usage status indicator of the specific data record accordingly. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 This is a schematic diagram of a power management device illustrated according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram illustrating multiple fault data records according to an embodiment of the present invention.

[0010] Figure 3 This is a flowchart illustrating a power management method according to an embodiment of the present invention. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0012] Please refer to Figure 1 This is a schematic diagram of a power management device according to an embodiment of the present invention. In an embodiment of the present invention, the power management device 100 may include, for example, a power management circuit 101 and a specific memory 102, wherein the power management circuit 101 is coupled to the specific memory 102, and the specific memory 102 may be implemented as a non-volatile memory, for example.

[0013] In some embodiments, the power management device 100 may be located in the same electronic device (e.g., various smart devices and / or computer devices) as a processor (e.g., CPU) for power management of a plurality of hardware devices 111 to 11K (K being the number of hardware devices) in the processor.

[0014] In some embodiments, the power management device 100 may further include a low pin count (LPC) interface 103, a state machine 104, and an alarm interface 105, each individually connected to the power management circuit 101. In one embodiment, the LPC interface 103 can be used to obtain relevant LPC values / data from port 80 on the LPC bus of the electronic device. Additionally, the alarm interface 105 can be used to receive various alarms that occur when the electronic device is powered on and can provide these alarms to the power management circuit 101.

[0015] In one embodiment, a specific memory 102 may include a plurality of fault data records, wherein each fault data record may have a usage status indicator. Please refer to... Figure 2 This is a schematic diagram illustrating multiple fault data records according to an embodiment of the present invention.

[0016] like Figure 2 As shown, a specific memory 102 may include N fault data records 21 to 2N, and each of them may have a similar / identical data structure. For ease of understanding, fault data record 21 is used as an example below, while those skilled in the art should be able to understand the details of the other fault data records 22 to 2N accordingly.

[0017] In one embodiment, the fault data record 21 may include a usage status indicator 211, an address field 212, and a fault data field 213, wherein the usage status indicator 211 can be used to indicate a used or unused state. In some embodiments, when the usage status indicator 211 indicates a used state (which can be represented by a first logical value (e.g., 0)), it may indicate that the fault data record 21 has been used. Additionally, the address field 212 can be used to record the address of the fault data record 21, but is not limited thereto.

[0018] In one embodiment, if the fault data field 213 of the fault data record 21 has been used to record fault data corresponding to a certain processor fault, then the fault data record 21 can be defined as used, but is not limited to this. On the other hand, when the usage status indicator 211 indicates an unused state (which can be represented by a second logical value (e.g., 1)), it can represent that the fault data record 21 is not used. In one embodiment, if the fault data field 213 of the fault data record 21 has not yet been used to record fault data corresponding to a certain processor fault, then the fault data record 21 can be defined as unused, but is not limited to this.

[0019] For example, in Figure 2 In this scenario, since the usage status indicators of fault data records 21-23 all indicate the first logical value (i.e., 0), it can be concluded that the fault data fields of fault data records 21-23 have been individually used to record fault data corresponding to a certain processor fault. Furthermore, since the usage status indicators of fault data records 24-2N all indicate the second logical value (i.e., 1), it can be concluded that the fault data fields of fault data records 24-2N have not yet been used to record any fault data, but this is not necessarily the case.

[0020] In different embodiments, the designer can set the memory space occupied by fault data records 21 to 2N as needed. In one embodiment, assuming N is 128 and the length of each fault data record 21 to 2N is 32 bits, then the fault data records 21 to 2N can occupy a total of 128 x 32 bits of space, but it is not limited to this.

[0021] In different embodiments, the designer may adjust the length of the usage status indicator, address field, and fault data field corresponding to each fault data record 21-2N as needed. In one embodiment, the length of the usage status indicator, address field, and fault data field corresponding to each fault data record 21-2N may be set to, for example, 1 bit, 7 bits, and 24 bits, respectively, but is not limited to these.

[0022] In an embodiment of the present invention, the power management circuit 101 can access relevant modules and program code to implement the power management method proposed in the present invention, the details of which are described below.

[0023] Please refer to Figure 3 This is a flowchart illustrating a power management method according to an embodiment of the present invention. The method of this embodiment can be derived from... Figure 1 The power management device 100 is executed, and the following is the configuration. Figure 1 The components shown and Figure 2 Explanation of the examples Figure 3 Details of each step.

[0024] First, in step S310, the power management circuit 101 reads a specific memory 102 in the power management device 100. In one embodiment, the power management circuit 101 may obtain the contents of fault data records 21 to 2N by reading the specific memory 102, but it is not limited to this.

[0025] In step S320, the power management circuit 101 selects a specific data record from the plurality of fault data records 21 to 2N based on the usage status indicators of each fault data record 21 to 2N.

[0026] In the first embodiment, the power management circuit 101 can select at least one candidate data record from the fault data records 21 to 2N, wherein the usage status indicator of each candidate data record indicates an unused state. That is, the power management circuit 101 can select one or more of the fault data records 21 to 2N that have not yet been used to record any fault data as the aforementioned candidate data record. For example, the power management circuit 101 can select one or more of the fault data records 21 to 2N whose usage status indicator indicates an unused state (e.g., 1) as the aforementioned candidate data record. Then, the power management circuit 101 can select one of the aforementioned candidate data records as a specific data record.

[0027] For example, in Figure 2 In this scenario, the power management circuit 101 can select fault data records 24 to 2N as candidate data records and choose one of them as a specific data record, but it is not limited to this.

[0028] In one embodiment, if the power management circuit 101 cannot find any candidate data record from the fault data records 21-2N, this means that each of the fault data records 21-2N has been used to store the corresponding fault data. In this case, the power management circuit 101 can change the usage status indicator of each fault data record 21-2N to indicate an unused state, and select at least one candidate data record from the fault data records 21-2N again. For example, the power management circuit 101 can change the usage status indicator of each fault data record 21-2N to indicate a second logic value (e.g., 1), and select candidate data records and specific data records based on the above teaching, but it is not limited to this.

[0029] In the second embodiment, during the process of the power management circuit 101 selecting a specific data record from the plurality of fault data records 21 to 2N, the power management circuit 101 may also perform the following steps: (a1) obtaining the i-th fault data record from the fault data records 21 to 2N and the usage status indicator of the i-th fault data record, wherein the initial value of i is 1; (a2) in response to the determination that the usage status indicator of the i-th fault data record indicates that the i-th fault data record is not used, determining that the i-th fault data record is a specific data record; (a3) ​​in response to the determination that the usage status indicator of the i-th fault data record indicates that the i-th fault data record has been used, incrementing i, and performing step (a1) again.

[0030] In short, the power management circuit 101 can sequentially search down from the fault data record 21 until it finds an unused fault data record as a specific data record. Therefore, in Figure 2 In this scenario, the power management circuit 101 will identify the fault data record 24 as a specific data record.

[0031] Furthermore, in the second embodiment, the power management circuit 101 determines that the usage status indicator of fault data record 2N indicates that fault data record 2N has been used, which means that individual fault data records 21 to 2N have been used to store corresponding fault data. In this case, the power management circuit 101 can reset the usage status indicators of each fault data record 21 to 2N and return to step (a1). In one embodiment, the power management circuit 101 can reset the usage status indicators of each fault data record 21 to 2N, for example, by changing the usage status indicators of each fault data record 21 to 2N to indicate a second logic value (e.g., 1), but is not limited to this. In this case, after executing steps (a1) and (a2), the power management circuit 101 can select fault data record 21 as a specific data record.

[0032] After determining the specific data record, in step S330, the power management circuit 101 sequentially sends enable signals ES to each hardware device 111 to 11K, wherein the enable signal ES is used to enable (e.g., power on / start) each hardware device 111 to 11K. As previously mentioned, in order for the processor to power on successfully, the hardware devices 111 to 11K must be enabled / started in the order specified in the relevant specifications.

[0033] In one embodiment, during the execution of step S330 by the power management circuit 101, it may be configured to perform: (b1) send an enable signal ES to the i-th hardware device among the hardware devices 111 to 11K, where the initial value of i is 1; (b2) in response to determining that an enable success response ER corresponding to the enable signal ES has been received from the i-th hardware device, increment i, and execute step (b1) again.

[0034] In addition, in response to the power management circuit 101 determining that it has not received an enable success response ER corresponding to the enable signal ES from the i-th hardware device within a specified time, the power management circuit 101 may determine that the i-th hardware device is a specific hardware device.

[0035] In some embodiments, the power management circuit 101 may be controlled by the state machine 104 to execute step S330. For example, the state machine 104 may be used to control the power management circuit 101 to send an enable signal ES to the i-th hardware device and monitor whether a successful enable response ER is received from the i-th hardware device. If so, the state machine 104 may then control the power management circuit 101 to send the enable signal ES to the next hardware device, but is not limited to this.

[0036] In one embodiment, the i-th hardware device may execute its own power-on / boot procedure in response to the enable signal ES, and may send back an enable success response ER to the power management circuit 101 after the power-on / boot procedure is completed, to notify the power management circuit 101 that it has completed the power-on / boot procedure. Therefore, if the power management circuit 101 receives the enable success response ER from the i-th hardware device within a specified time, the power management circuit 101 can know that the i-th hardware device has completed the power-on / boot procedure, and then send the enable signal ES to the next hardware device to repeat the above mechanism.

[0037] In other words, if the power management circuit 101 does not receive a successful enable response ER from the i-th hardware device within the specified time, it means that the i-th hardware device may have failed to successfully complete the power-on / startup procedure. At this time, the power management circuit 101 can determine the i-th hardware device as a specific hardware device and continue to execute steps S340 to S350.

[0038] In step S350, in response to the power management circuit 101 determining that it has not received an enable success response ER corresponding to the enable signal ES from a specific hardware device among the plurality of hardware devices 111 to 11K, or has received an alarm associated with a specific hardware device, the power management circuit 101 at least obtains the LPC value and power management status.

[0039] In one embodiment, the power management state may, for example, record the currently booted i-th hardware device, i.e., the specific hardware device. For instance, assuming that after the power management circuit 101 sends an enable signal ES to the hardware device 112, it fails to receive a successful enable response ER from the hardware device 112 within a specified time, then the hardware device 112 is the specific hardware device under consideration, and the power management state may accordingly record that the processor's boot process stops when it reaches the hardware device 112, but it is not limited to this.

[0040] In one embodiment, the power management circuit 101 may obtain the required LPC value from the LPC bus via the LPC interface 103, for example. In some embodiments, the LPC interface 103 may obtain the LPC value by decoding data at address 0x80 on the LPC bus, where the LPC value may correspond to the type / content of an error currently occurring on a particular hardware device. For example, if the particular hardware device is a faulty hard drive, its corresponding LPC value may correspond to a hard drive failure; if the particular hardware device is a faulty memory, its corresponding LPC value may correspond to a memory failure; if the particular hardware device is a faulty motherboard, its corresponding LPC value may correspond to a motherboard failure, but this is not the only possibility.

[0041] Next, in step S350, the power management circuit 101 records the LPC value and power management status in a specific data record and updates the usage status indicator of the specific data record accordingly.

[0042] by Figure 2 For example, assuming that the power management circuit 101 selects the fault data record 24 as the specific data record to be considered according to the previous instruction, the power management circuit 101 can record the obtained LPC value and power management status in the fault data field of the fault data record 24 accordingly.

[0043] In one embodiment, the fault data field of the fault data record 24 can be divided into at least a first part, a second part and a third part, wherein the first part can be used, for example, to store the LPC value, and the second part can be used, for example, to store the power management state.

[0044] In one embodiment, if the power management circuit 101 determines that one of the power-on alarms ALM1 to ALM3 has been received, the power-on alarm can be recorded in a specific data record. In this case, the aforementioned third part can be used, for example, to store the power-on alarm, but is not limited thereto.

[0045] In different embodiments, the individual lengths of the first, second, and third portions can be set according to the designer's needs. For example, when the length of the fault data field of fault data record 24 is 24 bits, the lengths of the first, second, and third portions can be set to 16 bits, 5 bits, and 3 bits, respectively, but are not limited to this.

[0046] In this way, when the user of the aforementioned electronic device sends it for repair, the relevant repair personnel can check the contents of the fault data records 21 to 2N of the specific memory 102 to find out what kind of fault may have occurred on the electronic device, thereby improving the efficiency of subsequent troubleshooting / repair.

[0047] In summary, the method proposed in this invention can record relevant information (such as LPC values, power management status, and power-on alarms) of hardware devices that malfunction in the processor's boot process within a specially designed memory in the power management device. This allows maintenance personnel to determine the nature of the fault in the electronic device by examining the contents of this specific memory, thereby improving the efficiency of subsequent troubleshooting / repair.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power management method, suitable for a power management device controlling multiple hardware devices, characterized in that, include: Read a specific memory in the power management device, wherein the specific memory includes a plurality of fault data records, wherein each fault data record has a usage status indicator, wherein each fault data record includes at least a first part, a second part and a third part, wherein the first part stores low pin values, the second part stores power management status, and the third part stores power-on alarms, wherein the length of each of the first part, the second part and the third part is set as required; Selecting a specific data record from the plurality of fault data records based on the usage status indicator of each fault data record, wherein the usage status indicator of each fault data record indicates a used or unused state, wherein the used state indicates that the corresponding fault data record has been used, and the unused state indicates that the corresponding fault data record has not been used, wherein the step of selecting the specific data record from the plurality of fault data records based on the usage status indicator of each fault data record includes: At least one candidate data record is selected from the plurality of fault data records, wherein the usage status indicator of each candidate data record indicates the unused status; Select at least one candidate data record as the specific data record; A power signal is sent sequentially to each of the hardware devices, wherein the power signal is used to enable each of the hardware devices. In response to determining that a successful enable response corresponding to the enable signal has not been received from a specific hardware device among the plurality of hardware devices, or receiving the power-on alarm, at least the low pin value and the power management status are obtained; The low pin value and the power management status are recorded in the specific data record, and the usage status indicator of the specific data record is updated accordingly.

2. The method according to claim 1, further comprising: In response to the inability to find any candidate data record from the plurality of fault data records, the usage status indicator of each of the fault data records is changed to indicate the unused status, and at least one candidate data record is selected again from the plurality of fault data records.

3. The method according to claim 1, further comprising: In response to the determination that the power-on alarm has been received, the power-on alarm is also recorded in the specific data record.

4. The method of claim 1, wherein the step of selecting the specific data record from the plurality of fault data records based on the usage status indicator of each of the fault data records comprises: (a1) Obtain the i-th fault data record and the usage status indicator of the i-th fault data record from the plurality of fault data records, wherein the initial value of i is 1; (a2) In response to the determination that the i-th fault data record is not in use, the i-th fault data record is determined to be the specific data record.

5. The method according to claim 4, further comprising: (a3) In response to the determination that the usage status indicator of the i-th fault data record indicates that the i-th fault data record has been used, increment i, and execute step (a1) again.

6. The method according to claim 4, further comprising: In response to the determination that the usage status indicator of the Nth fault data record among the plurality of fault data records indicates that the Nth fault data record has been used, the usage status indicator of each of the fault data records is reset, and the process returns to step (a1), where N is the number of the plurality of fault data records.

7. The method of claim 1, wherein the step of sequentially sending the enable signal to each of the hardware devices comprises: (b1) Send the enable signal to the i-th hardware device among the plurality of hardware devices, wherein the initial value of i is 1; (b2) In response to the determination that the enable success response corresponding to the enable signal is received from the i-th hardware device, increment i and execute step (b1) again.

8. The method according to claim 7, further comprising: If the enable success response corresponding to the enable signal is not received from the i-th hardware device within the specified time, the i-th hardware device is determined to be the specific hardware device.

9. A power management device that controls multiple hardware devices, characterized in that, The power management device includes: A specific memory, wherein the specific memory includes a plurality of fault data records, and each of the fault data records has a usage status indicator, wherein each of the fault data records includes at least a first part, a second part and a third part, wherein the first part stores low pin values, the second part stores power management status, and the third part stores power-on alarms, wherein the length of each of the first part, the second part and the third part is set as required; A power management circuit, coupled to the specific memory, and configured to: Read the specific memory in the power management device; Based on the usage status indicator of each of the fault data records, a specific data record is selected from the plurality of fault data records, wherein the usage status indicator of each of the fault data records indicates a used state or an unused state, wherein the used state indicates that the corresponding fault data record has been used, and the unused state indicates that the corresponding fault data record has not been used; At least one candidate data record is selected from the plurality of fault data records, wherein the usage status indicator of each candidate data record indicates the unused status; Select at least one candidate data record as the specific data record; A power signal is sent sequentially to each of the hardware devices, wherein the power signal is used to enable each of the hardware devices. In response to determining that a successful enable response corresponding to the enable signal has not been received from a specific hardware device among the plurality of hardware devices, or receiving the power-on alarm, at least the low pin value and the power management status are obtained; The low pin value and the power management status are recorded in the specific data record, and the usage status indicator of the specific data record is updated accordingly.

10. The power management device of claim 9, wherein the power management circuit is further configured to: In response to the inability to find any candidate data record from the plurality of fault data records, the usage status indicator of each of the fault data records is changed to indicate the unused status, and at least one candidate data record is selected again from the plurality of fault data records.

11. The power management device according to claim 9, wherein the power management circuit is further configured to: In response to the determination that the power-on alarm has been received, the power-on alarm is also recorded in the specific data record.

12. The power management device of claim 9, wherein the power management circuit is configured to: (a1) Obtain the i-th fault data record and the usage status indicator of the i-th fault data record from the plurality of fault data records, wherein the initial value of i is 1; (a2) In response to the determination that the i-th fault data record is not in use, the i-th fault data record is determined to be the specific data record.

13. The power management device of claim 12, wherein the power management circuit is further configured to: (a3) In response to the determination that the usage status indicator of the i-th fault data record indicates that the i-th fault data record has been used, increment i, and execute step (a1) again.

14. The power management device of claim 12, wherein the power management circuit is further configured to: In response to the determination that the usage status indicator of the Nth fault data record among the plurality of fault data records indicates that the Nth fault data record has been used, the usage status indicator of each of the fault data records is reset, and the process returns to step (a1), where N is the number of the plurality of fault data records.

15. The power management device according to claim 9, wherein the step of sequentially sending enable signals to each hardware device includes: (b1) Send the enable signal to the i-th hardware device among the plurality of hardware devices, wherein the initial value of i is 1; (b2) In response to the determination that the enable success response corresponding to the enable signal is received from the i-th hardware device, increment i and execute step (b1) again.

16. The power management device of claim 15, wherein the power management circuit is further configured to: If the enable success response corresponding to the enable signal is not received from the i-th hardware device within the specified time, the i-th hardware device is determined to be the specific hardware device.

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