A method for mapping a network-on-chip high-speed data acquisition system

Abstract

The application discloses a kind of network-on-chip high-speed data acquisition system mapping method, this mapping method is composed of two parts of network-on-chip mapping model and mapping effect evaluation model.Network-on-chip mapping model is composed of encoder and decoder, encoder will be classified into four categories of acquisition node, storage node, transmission node, control node according to function in data acquisition system node, using graph convolutional neural network according to the node class and the connection between nodes in task graph carries out graph coding and obtains the encoder vector of each node in task graph, key as Query vector, with unmapped node coding vector does single-head attention operation, the attention value of unmapped node is as the probability that this node becomes the next mapping node, in the form of beam search obtains the solution sequence of multiple groups of the same problem, calculates each group of solution sequence as the actual communication delay of mapping result, selects the solution sequence with minimum communication delay as final solution sequence.Mapping effect evaluation model is introduced as baseline to carry out unsupervised training to network-on-chip mapping model in the way of reinforcement learning.The network-on-chip high-speed data acquisition system mapping method constructed by the application can realize fast and efficient solution of similar problems to be mapped for the same NoC architecture by model training.

Description

Technical Field

[0001] This invention relates to the field of high-speed data acquisition systems for on-chip networks, and specifically to an on-chip network system mapping method based on node classification of the data acquisition system. Background Technology

[0002] Data acquisition technology is an indispensable means of condition monitoring for electronic equipment. With the development of the national economy, the requirements for data acquisition speed and other indicators are becoming increasingly stringent. However, data acquisition and the measurement and control systems and related high-end instruments based on it are limited by the manufacturing process of the core component—the analog-to-digital converter (ADC). The speed of a single ADC device cannot be increased indefinitely. Therefore, using multiple converter devices with time-interleaved ADC (TIADC) sampling technology is one of the most feasible methods to improve the sampling rate and ensure system sampling performance. It can effectively overcome the limitation of the conversion rate of a single ADC chip on the system sampling rate and achieve higher-speed data acquisition. Currently, TIADCs are all based on traditional bus architecture designs. With the rapid development of electronic design and manufacturing processes, on-chip systems based on bus architectures face bottlenecks such as low communication bandwidth, difficulty in clock synchronization, and poor scalability, which affect the improvement of performance indicators and limit the expansion of the number of ADC chips.

[0003] Network on Chip (NoC) introduces computer network technology into chip design. It is a brand-new integrated circuit architecture that uses packet and routing switching technology to replace traditional bus technology for communication. It completely breaks the limitations of traditional bus communication from an architectural perspective, solves the bottleneck and clock problem of on-chip communication, and greatly increases the communication bandwidth of the on-chip system. The on-chip network structure also makes the address space of the on-chip system unrestricted, improving the scalability of the circuit.

[0004] The resource nodes of the on-chip network are designed as functional nodes for data acquisition, storage, and transmission. The alternating sampling principle is used to realize an on-chip network data acquisition system that is easy to expand, has a high sampling rate, low latency, and high throughput. This solves the problems of synchronization difficulties, limited communication bandwidth, and poor scalability that exist in the current time-alternating sampling method based on traditional buses.

[0005] The on-chip network mapping scheme determines the location of each resource node in the NoC topology. Therefore, optimizing the mapping algorithm is crucial for achieving low power consumption and low latency in NoC. For smaller on-chip networks, exhaustive search or swarm intelligence evolution can find a relatively optimal solution in a short time. However, in high-speed data acquisition systems, the more similar acquisition nodes there are and the higher the acquisition rate, the more time-consuming exhaustive search or swarm intelligence evolution becomes when dealing with a large number of nodes. In recent years, with the development of artificial intelligence technology, the "offline training, online decision-making" characteristics of deep reinforcement learning have provided a new method for quickly solving the mapping problem in high-speed on-chip network data acquisition systems. Therefore, using deep reinforcement learning to solve the NoC mapping problem is a good choice. Summary of the Invention

[0006] To address the mapping problem in high-speed data acquisition systems using on-chip networks, this invention proposes a mapping method for such systems. The method involves classifying nodes in the task graph of the high-speed data acquisition system according to their functions, encoding these nodes using a graph convolutional neural network, and incorporating global, local, and dynamic key node information from the task graph into the mapping model decoder as query vectors to calculate similarity between mapping nodes. A beam search approach is used to obtain multiple mapping solutions for the same task graph, and the solution that minimizes the latency of the high-speed data acquisition system is selected as the final solution. This method has the advantage of fully leveraging the functional characteristics of the nodes in the high-speed data acquisition system during the mapping process. This invention includes:

[0007] Step 1: Obtain the task graph of the high-speed data acquisition system to be mapped. Divide the nodes in the task graph into four categories according to their functions: acquisition nodes, storage nodes, transmission nodes, and control nodes. Perform one-hot encoding on each node. The encoding results are: acquisition node [1, 0, 0, 0], transmission node [0, 1, 0, 0], transmission node [0, 0, 1, 0], and control node [0, 0, 0, 1].

[0008] Step 2: The node category vector and the task graph to be mapped are used as input to the graph convolutional neural network (Graph Convolutional Neural Network). The Graph Convolutional Neural Network extracts node information and inter-node structural information from the task graph to encode the node information. The encoder output is {e0, e1, ..., e...} n-1 e n The coding formula is as follows:

[0009]

[0010] in A is the adjacency matrix of the graph, and I is the identity matrix. It is the degree matrix of the graph, where degree refers to the number of edges connected to a specified node in the graph. H is the feature of each node in each layer. For the input layer, H is the initial input X, and σ is the non-linear activation function.

[0011] Step 3: The decoder encodes the node vectors {e0, e1, ..., e...} in the task graph. n-1 e n The task graph takes the node classification vector as input, calculates the mean of the node encoding vectors as global information, and takes the encoding vectors of the three most recently mapped nodes as local information. The decoder dynamically selects the encoding vectors of two storage nodes from all storage nodes as key information of the task graph based on the global and local information. The selection of dynamic key nodes is obtained by a masked single-head attention mechanism.

[0012] Step 4: The decoder fuses global information, local information, and dynamic key node information of the task graph as the Query vector of the attention mechanism to calculate the matching degree with the encoding vector of the unmapped node, and selects the node with the high matching degree as the next mapping node to complete the mapping.

[0013] Step 5: Using the beam search method, repeat steps 3 and 4 to obtain multiple sets of mapping solutions M{M1, M2, ..., M... n The solution that minimizes the latency of the data acquisition system is selected as the final mapping solution. That is, a number arrangement from 1 to n, where the index represents a routing node in the architecture and the element represents an IP core in the task graph.

[0014] Step 6: The mapping effect evaluation model is composed of a fully connected neural network, which estimates the communication latency of the input task graph to be mapped.

[0015] Step 7: Using the actual system latency of the on-chip network mapping model as L(π) and the system communication latency estimated by the mapping effect evaluation model as the baseline b(s), optimize the on-chip network mapping model through gradient descent, as shown in the following formula:

[0016]

[0017] Where L(θ|s)=E pθ(π|s) [L(π)], where L((θ|s) is the expected communication delay of the task graph to be mapped.

[0018] Step 8: Use the system communication delay L(π) calculated by the solution sequence of the on-chip network mapping model as the actual value, and the system communication delay b(s) estimated by the mapping effect evaluation model as the predicted value. Optimize the mapping effect evaluation model using the mean squared error (MSE) as the loss function, as shown in the following formula:

[0019] MSE(L(π),b(s))=(L(π)-b(s)) 2 Attached Figure Description

[0020] Figure 1 This is a system block diagram of a mapping method for a high-speed data acquisition system using an on-chip network according to the present invention;

[0021] Figure 2 It is a model of an on-chip network high-speed data acquisition system;

[0022] Figure 3 This is a schematic diagram of the task graph input and mapping sequence output of the on-chip network high-speed data acquisition system of the present invention;

[0023] Figure 4 This is a schematic diagram of the encoder portion of the mapping model in the on-chip network high-speed data acquisition system of the present invention;

[0024] Figure 5 This is a schematic diagram of the deencoder part of the mapping model of the on-chip network high-speed data acquisition system of the present invention;

[0025] Figure 6 It is the training result of the mapping model of the on-chip network high-speed data acquisition system. Detailed Implementation

[0026] The technical solutions in specific embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings:

[0027] like Figure 1 The diagram shows the system block diagram of the mapping method for a high-speed data acquisition system on a network-on-chip. The system block diagram consists of two parts: a mapping model and a mapping effect evaluation model. The mapping model solves the task mapping solution sequence of the high-speed data acquisition system and calculates the actual communication latency of the data acquisition system based on the mapping solution sequence. The mapping effect evaluation model evaluates the communication latency of a specific task graph and updates the mapping model with gradients based on the actual latency and the evaluated latency.

[0028] The high-speed data acquisition system is functionally divided into four main parts: the data acquisition ADC, memory, transmission interface, and the main controller. The data acquisition ADC is controlled by the data acquisition controller to acquire data. The memory is used for data storage and forwarding. The transmission interface is responsible for uploading acquired data and receiving commands from the host computer. The data acquisition controller is responsible for clock correction and system coordination control. Based on the high-speed data acquisition system model, all IP cores in the system are abstracted as task nodes, and the data communication relationships between IP cores are mapped to the connection relationships between task nodes. A task graph for on-chip network data acquisition is established as follows: Figure 2 As shown.

[0029] like Figure 3As shown, a high-speed data acquisition system task graph to be mapped is mapped to a 2×2×2 3D Mesh architecture. The solution sequence of the mapping model is m={C1, C3, C2, C4, C5, C6, C7, C8}, where the index represents the routing node on the architecture and the element represents the IP core in the task graph. The specific meaning of this solution sequence is to mount IP core C1 to router R1, IP core C3 to router R2, and so on.

[0030] The mapping model consists of two parts: an encoder and a decoder. The encoder process of the mapping model is as follows: Figure 4 As shown, the nodes in the task graph to be mapped are first classified into four categories according to their functions: acquisition nodes [1, 0, 0, 0], transmission nodes [0, 1, 0, 0], transmission nodes [0, 0, 1, 0], and control nodes [0, 0, 0, 1]. The feature matrix of the classified nodes and the adjacency matrix of the task graph are used as the input of the encoder. The encoder uses a graph convolutional neural network to extract the node information and the structural information between nodes in the task graph to encode the node information in the task graph. The encoder output is {e0, e1, ..., e...} n-1 e n}, where e0 is the encoding of IP core c1 in the task graph, and so on, the encoding formula is as follows:

[0031]

[0032] in A is the adjacency matrix of the graph, and I is the identity matrix. It is the degree matrix of the graph, where degree refers to the number of edges connected to a specified node in the graph. H is the feature of each node in each layer. For the input layer, H is the initial input X, and σ is the non-linear activation function.

[0033] The high-speed data acquisition system mapping model decoder process is as follows: Figure 5 As shown, in a high-speed data acquisition system, the storage node plays a crucial role, receiving data from the acquisition node and forwarding the stored data to the transmission node. Therefore, the storage node is a key node in the data acquisition task diagram.

[0034] First, the decoder encodes the vectors {e0, e1, ..., e} of each node in the task graph. n-1 e n The node category matrix is ​​used as input, and the mean of the node encoding vectors is used as the global information e of the task graph. gobalThe encoded vectors of the three most recently mapped nodes are used as local information of the task graph {e1, e3, e2}. If the number of mapped nodes is less than three, a placeholder vector h0, which can be learned by the mapping model, is introduced. The decoder dynamically selects the encoded vectors of two storage nodes from all storage nodes as key information of the task graph based on the global and local information of the task graph. The probability value of each storage node as a dynamic key node is obtained by masked single-head attention operation. The encoded vectors of the two storage nodes with the highest probability values, i.e., {e5, e6}, are selected as the dynamic key nodes for this decoding. The formula for masked single-head attention operation is as follows:

[0035] a i =f(Q, K) i Mask, i∈{1…n}

[0036]

[0037] Decoder fusion task graph global information e gobal Local information {e1, e3, e2} and dynamic key node information {e5, e6} are used This indicates that l represents the number of decoder iterations. The query vector of the attention mechanism is used as the key, and the encoding vector of the unmapped node is used as the key for single-head attention operation. The value of the attention operation is used as the probability value {p1, p2, p3, p4} of each unmapped node as the next mapped node. The unmapped node with the highest probability value is selected as the next mapped node.

[0038] The decoder uses a beam search method and runs in a loop as follows: Figure 5 The decoding process yields multiple mapping solutions, and the solution that minimizes the latency of the data acquisition system is selected as the final mapping solution. That is, M = {1, 3, 2, 4, 5, 6, 7, 8}, where the index represents the routing node in the architecture, and the element represents the IP core in the task graph. The latency calculation formula for the data acquisition system is as follows:

[0039]

[0040] Among them, w i，j hop represents the communication volume between node i and node j. i，j c represents the number of communication hops from node i to node j after mapping. For different task graphs, c... i node to c j Node traffic w i，j Because they are different, standardization is performed, namely, the task graph communication delay and T. norm Positively correlated, T norm ≥1, T normThis represents the average number of communication hops between any two nodes in a NoC architecture, with an ideal value of 1.

[0041] The mapping performance evaluation model consists of a fully connected neural network. The communication delay calculated by the solution sequence of the on-chip network mapping model is used as the actual system communication delay L(π), and the system communication delay estimated by the mapping performance evaluation model is used as the baseline b(s). The on-chip network mapping model is optimized through gradient descent, as shown in the following formula:

[0042]

[0043] Where L(θ|s)=F pθ(π|s) [L(π)], where L((θ|s) is the expected communication delay of the task graph to be mapped.

[0044] The system communication delay L(π) calculated by the solution sequence of the on-chip network mapping model is used as the actual value, and the system communication delay b(s) estimated by the mapping effect evaluation model is used as the predicted value. The mean squared error (MSE) is used as the loss function to optimize the mapping effect evaluation model, as shown in the following formula:

[0045] MSE(L(π),b(s))=(L(π)-b(s)) 2

[0046] Figure 6 Using the method of this invention to Figure 3 The high-speed data acquisition system task diagram shown is used as a test set. The minimum normalized latency of the high-speed data acquisition system is 1.024T. norm The ideal value is 1T norm This demonstrates the effectiveness of the on-chip network high-speed data acquisition system mapping method proposed in this invention.

[0047] The present invention and its embodiments have been described above illustratively. This description is not restrictive, and the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. The accompanying drawings are only one embodiment of the invention; the actual structure is not limited thereto, and any reference numerals in the claims should not limit the scope of the claims. Therefore, if a person skilled in the art, inspired by this description, designs a similar structure and embodiment without departing from the spirit of the invention, such design should fall within the scope of protection of this patent.

Claims

1. A mapping method for a high-speed data acquisition system using an on-chip network, characterized in that, Includes the following steps: Step 1: Input the task diagram of the high-speed data acquisition system to be mapped. Divide the nodes in the task diagram into four categories according to their functions: acquisition nodes, storage nodes, transmission nodes, and control nodes. Then perform one-hot encoding. The encoding results are acquisition node [1,0,0,0], transmission node [0,1,0,0], transmission node [0,0,1,0], and control node [0,0,0,1]. Step 2: The node category vector and the adjacency matrix of the task graph to be mapped are used as input to the graph convolutional neural network. The graph convolutional neural network extracts node information and inter-node structural information from the task graph to encode each node. The encoder output is {e0, e1, ..., e...} n-1 ,e n The encoding formula is as follows: in A is the adjacency matrix of the graph, and I is the identity matrix. It is the degree matrix of the graph, where degree refers to the number of edges connected to a specified node in the graph, H is the feature of each node in each layer, and for the input layer, H is the initial input X, and σ is the non-linear activation function. Step 3: The decoder encodes the vectors {e0, e1, ..., e} of each node in the task graph. n-1 ,e n The task graph is processed by taking the node classification vector as input, averaging the node encoding vectors as global information, and taking the encoding vectors of the three most recently mapped nodes as local information. The decoder dynamically selects the encoding vectors of two storage nodes from all storage nodes as key information of the task graph based on the global and local information. The selection of dynamic key nodes is obtained by a masked single-head attention mechanism. Step 4: The decoder fuses global information, local information and dynamic key node information of the task graph as the Query vector of the attention mechanism to calculate the matching degree with the encoding vector of the unmapped node, and selects the node with the high matching degree as the next mapping node to complete the mapping. Step 5: Using the beam search method, repeat steps 3 and 4 to obtain multiple sets of mapping solutions M{M1,M2,…,M…} n The solution that minimizes the latency of the data acquisition system is selected as the final mapping solution. That is, a number arrangement from 1 to n, where the index represents a routing node in the architecture and the element represents an IP core in the task graph; Step 6: The mapping effect evaluation model is composed of a fully connected neural network, which estimates the communication latency of the input task graph to be mapped. Step 7: Using the actual system communication latency of the on-chip network mapping model as L(π) and the system communication latency estimated by the mapping effect evaluation model as the baseline b(s), optimize the on-chip network mapping model through gradient descent, as shown in the following formula: Where L(θ|s)=E pθ(π|s) [L(π)], L((θ|s) represents the expected communication delay of the task graph to be mapped; Step 8: Use the system communication delay L(π) calculated by the solution sequence of the on-chip network mapping model as the actual value, and the system communication delay b(s) estimated by the mapping effect evaluation model as the predicted value. Optimize the mapping effect evaluation model using the mean squared error (MSE) as the loss function, as shown in the following formula: MSE(L(π),b(s))=(L(π)-b(s)) 2 。 2. The mapping method for a high-speed data acquisition system using an on-chip network according to claim 1, characterized in that, In steps 1 and 2, the nodes in the high-speed data acquisition system task graph are classified according to their functions as the initial feature vectors of the nodes, and then encoded by a graph convolutional neural network.

3. The mapping method for a high-speed data acquisition system for on-chip networks according to claim 1, characterized in that, In steps 3-4, task graph global information, task graph local information, and dynamic key node information are introduced into the mapping model decoder as query vectors to perform similarity calculations on the mapping nodes.

4. The mapping method for a high-speed data acquisition system for on-chip networks according to claim 1, characterized in that, In step 5, multiple mapping solutions for the same task to be mapped are obtained using beam search, and the mapping solution that minimizes the latency of the high-speed data acquisition system is selected as the final solution.

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