UVM-based Verification Platform for PCIe to RapidIO Bridge Chip

Abstract

The present invention is a verification platform for a PCIe-to-RapidIO bridge chip based on UVM, including a RapidIO verification encapsulation environment, a design under test, and a PCIe verification encapsulation environment; the RapidIO verification encapsulation environment is used to generate test cases for the RapidIO protocol, the PCIe verification encapsulation environment is used to generate test cases for the PCIe protocol, the test cases for the RapidIO protocol and the test cases for the PCIe protocol serve as the excitation sources for the design under test. After the test cases for the RapidIO protocol are converted into data packets of the PCIe protocol in the design under test, they are sent to the PCIe verification encapsulation environment; after the test cases for the PCIe protocol are protocol-converted into data packets of the RapidIO protocol in the design under test, they are sent to the RapidIO verification encapsulation environment. This platform provides a standard protocol excitation source, simulates the data flow path of the real chip front-end design, and at the same time solves the problems of difficult construction and poor scalability of the protocol conversion chip verification platform.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit verification, and particularly relates to a PCIe-to-RapidIO bridge chip verification platform based on UVM. Background Art

[0002] With the continuous development of integrated circuit process technology, the design of integrated circuits has developed towards ultra-large scale, the complexity of chip design has become higher and higher, and the functions have been continuously enhanced. Nevertheless, the prediction of Moore's Law has not failed. The number of transistors that can be accommodated on an integrated circuit doubles every 18 to 24 months, and the processor performance is doubled compared with the previous generation. Although the chip is updated so fast, its tolerance for defects is quite low, and the cost of producing chips is expensive, which poses a very great challenge to the completeness of verification. During the entire R & D cycle of the chip, the work of chip verification occupies about two-thirds or even more. The market launch cycle of a product is of great significance for the promotion of the product. The shorter the market update cycle, the more proactive it will be. Therefore, shortening the chip verification cycle and improving the verification quality are crucial.

[0003] Hardware circuit design languages Verilog and VHDL are limited by static instantiation, not suitable for simulation dynamic switching during verification, and also unable to perform object-oriented encapsulation and modeling. Therefore, the System Verilog3.0 standard was first released by Accellera in 2002. System Verilog has excellent features such as object orientation, random constraints, and inter-thread communication management, and integrates some functions and type libraries for verification, providing many conveniences for the construction of the verification environment.

[0004] UVM, the Universal Verification Methodology, is the current mainstream chip verification method, facing digital designs from module level to chip level, with a wide range of applications. Since the release of the first UVM1.0 version in 2010, it has been continuously updated and was announced as an official standard by IEEE in 2017. The customizable verification framework of UVM can effectively save the time of verification engineers spent on building the verification environment, enabling them to focus more on formulating verification plans and creating test scenarios, and still maintains very good vitality in application so far.

[0005] All existing domestic CPUs do not support the RapidIO interface. Only through a PCIe-to-RapidIO bridge chip can they be connected to the switching network. However, due to the large variety of packet types and high redundancy between protocols, there are very high requirements for system stability and data correctness while maintaining high-speed transmission. This leads to great difficulty in building a chip verification platform and poor scalability, and the data inspection passing standards for the core data processing module are even more stringent. Therefore, it is of great significance to build a highly reusable verification platform that can be used to convert from the PCIe protocol to the RapidIO protocol for chips. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the technical problem to be solved by the present invention is to provide a UVM-based verification platform for PCIe-to-RapidIO bridge chips.

[0007] The technical solution adopted by the present invention to solve the above technical problem is as follows:

[0008] A UVM-based verification platform for PCIe-to-RapidIO bridge chips is used to verify the protocol conversion performance of PCIe-to-RapidIO bridge chips. It is characterized in that the verification platform includes a RapdiIO verification encapsulation environment, a design under test, and a PCIe verification encapsulation environment. The RapdiIO verification encapsulation environment is used to generate test cases for the RapdiIO protocol, and the PCIe verification encapsulation environment is used to generate test cases for the PCIe protocol. The test cases for the RapdiIO protocol and the test cases for the PCIe protocol serve as the excitation sources for the design under test. After the test cases for the RapdiIO protocol are converted into PCIe protocol data packets in the design under test, they are sent to the PCIe verification encapsulation environment, and test cases for the PCIe protocol are generated in the PCIe verification encapsulation environment. After the test cases for the PCIe protocol are protocol-converted into RapdiIO protocol data packets in the design under test, they are sent to the RapdiIO verification encapsulation environment, and test cases for the RapdiIO protocol are generated in the RapdiIO verification encapsulation environment.

[0009] Further, the RapidIO verification encapsulation environment includes a physical layer encapsulation, a transport layer encapsulation, a logical layer encapsulation, and a RapidIO comparator; the physical layer encapsulation is used to generate physical layer data packets of the RapidIO protocol. The physical layer encapsulation performs data transmission with the transport layer encapsulation in the transmission direction through the physical layer encapsulation transmission interface, and performs data transmission with the transport layer encapsulation in the reception direction through the physical layer encapsulation reception interface; the transport layer encapsulation is used to generate transport layer data packets of the RapidIO protocol. The transport layer encapsulation receives the data sent by the physical layer encapsulation through the transport layer encapsulation reception interface, sends data to the logical layer encapsulation through the transport layer encapsulation transmission interface, receives the data sent by the logical layer encapsulation through the transport layer encapsulation reception direction external interface, and sends data to the physical layer encapsulation through the transport layer encapsulation transmission direction external interface; the logical layer encapsulation is used to generate logical layer data packets of the RapidIO protocol, that is, test cases of the RapidIO protocol; the logical layer encapsulation receives the data sent by the transport layer encapsulation through the logical layer encapsulation reception interface, and sends data to the transport layer encapsulation through the logical layer encapsulation transmission direction external interface; the RapidIO comparator is used to determine whether the generated test cases of the RapidIO protocol are correct.

[0010] Further, the physical layer encapsulation includes a physical layer sequencer, a physical layer driver, a physical layer monitor, and a physical layer encapsulation transmission buffer module; the transport layer encapsulation includes a transport layer sequencer, a transport layer functional bus model, a transport layer monitor, a transport layer encapsulation transmission buffer module, and a transport layer encapsulation reception buffer module; the logical layer encapsulation includes a logical layer sequencer, a logical layer functional bus model, a logical layer monitor, a logical layer encapsulation reception buffer module, and a logical layer encapsulation transmission buffer module; wherein, the physical layer sequencer performs data transmission with the physical layer driver, the physical layer monitor performs data transmission with the transport layer monitor, and the physical layer encapsulation transmission buffer module is used to store the data sent by the transport layer encapsulation; the transport layer sequencer performs data transmission with the transport layer functional bus model, the transport layer monitor performs data transmission with the logical layer monitor, the transport layer encapsulation transmission buffer module is used to store the data sent by the physical layer encapsulation, and the transport layer encapsulation reception buffer module is used to store the data sent by the logical layer encapsulation; the logical layer sequencer performs data transmission with the logical layer functional bus model, the logical layer encapsulation reception buffer module is used to store the data sent by the transport layer encapsulation, and the logical layer encapsulation transmission buffer module is used to store the logical layer data packets.

[0011] Further, the PCIe verification encapsulation environment includes a PCIe application layer data module, a PCIe transport layer data module, a PCIe link layer data module, and a PCIe physical layer data module; the PCIe application layer data module is used for the initialization configuration and request packet processing of the PCIe verification encapsulation environment, the PCIe transport layer data module is used for generating and processing the transport layer data packets of the PCIe protocol, the PCIe link layer data module is used for generating and processing the link layer data packets of the PCIe protocol, and the PCIe physical layer data module is used for generating and processing the physical layer data packets of the PCIe protocol, that is, the test cases of the PCIe protocol.

[0012] Further, the PCIe application layer data module includes a PCIe configuration module, a PCIe conversion request module, and a PCIe conversion response module; the PCIe transport layer data module includes a PCIe transport layer sequencer, a PCIe transport layer driver, and a PCIe transport layer monitor; the PCIe link layer data module includes a PCIe link layer sequencer, a PCIe link layer driver, and a PCIe link layer monitor; the PCIe physical layer data module includes a PCIe physical layer sequencer, a PCIe physical layer driver, and a PCIe physical layer monitor. The PCIe configuration module is used for the initialization configuration of the PCIe verification encapsulation environment; the PCIe conversion request module and the conversion response module are used for processing the request packets and response packets in the sending direction. The PCIe transport layer driver transfers data to / from the PCIe transport layer sequencer and the PCIe link layer driver respectively, and at the same time transfers data to the PCIe transport layer monitor through the PCIe transport layer virtual interface. The PCIe transport layer monitor transfers data to the PCIe link layer monitor. The PCIe link layer sequencer transfers data to the PCIe link layer driver, and the PCIe link layer driver transfers data to the PCIe physical layer driver for output, and at the same time transfers data to the PCIe link layer monitor through the PCIe link layer virtual interface. The PCIe link layer monitor transfers data to the PCIe physical layer monitor at the same time. The PCIe physical layer sequencer transfers data to the PCIe physical layer driver, and the PCIe physical layer driver transfers data to the PCIe physical layer monitor through the PCIe physical layer virtual interface.

[0013] Further, the design to be tested includes an Srio controller, a PCIe controller, and a processing engine. After the test case of the RapidIO protocol completes the logical function through the Srio controller, the processing engine converts the RapidIO protocol into the PCIe protocol and sends it to the PCIe controller. After the output signal of the PCIe controller is set to 1, it is considered that the RapidIO protocol has been successfully converted into the PCIe protocol and then sent to the PCIe verification encapsulation environment. After the test case of the PCIe protocol completes the logical function through the PCIe controller, the processing engine converts the PCIe protocol into the RapidIO protocol and sends it to the Srio controller. After the output signal of the Srio controller is set to 1, it is considered that the PCIe protocol has been successfully converted into the RapidIO protocol and then sent to the RapdiIO verification encapsulation environment.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] The present invention uses System Verilog and the UVM general verification methodology to build a verification platform for the chip that can be used for the conversion between the PCIe protocol and the RapidIO protocol. Test cases for the RapidIO protocol and the PCIe protocol are generated through the RapdiIO verification encapsulation environment and the PCIe verification encapsulation environment respectively, providing a standard protocol excitation source and simulating the data flow path of the real chip front-end design. At the same time, it solves the problems of difficult construction and poor scalability of the protocol conversion chip verification platform.

[0016] The RapdiIO verification encapsulation environment and the PCIe verification encapsulation environment of the present invention can be directly reused for the independent data sources of the corresponding protocols, have good reusability, reduce the time spent on the verification platform, and greatly improve the verification efficiency. Even users who are not very familiar with UVM can directly use them. Description of the Drawings

[0017] Figure 1 is the overall structure diagram of the verification platform;

[0018] Figure 2 is the structure diagram of the RapidIO verification encapsulation environment;

[0019] Figure 3 is the structure diagram of the PCIe verification encapsulation environment. Detailed Embodiments

[0020] The technical solutions of the present invention will be described in detail below in conjunction with the drawings and specific embodiments, but this does not limit the protection scope of this application.

[0021] The present invention is a UVM-based verification platform for PCIe to RapidIO bridging chips, as Figure 1As shown in the figure, the verification platform includes a RapdiIO verification encapsulation environment (Srio Env), a design under test, and a PCIe verification encapsulation environment (PCIe Env); the RapidIO verification encapsulation environment is used to generate test cases for the RapdiIO protocol, the PCIe verification encapsulation environment is used to generate test cases for the PCIe protocol, the test cases for the RapdiIO protocol and the test cases for the PCIe protocol serve as the excitation sources for the design under test. The test cases for the RapdiIO protocol are sent to the PCIe verification encapsulation environment after completing the logical functions and protocol conversion in the design under test, and test cases for the PCIe protocol are generated in the PCIe verification encapsulation environment; the test cases for the PCIe protocol are sent to the RapdiIO verification encapsulation environment after completing the logical functions and protocol conversion in the design under test, and test cases for the RapdiIO protocol are generated in the RapdiIO verification encapsulation environment.

[0022] See Figure 2, The RapidIO verification encapsulation environment includes a physical layer encapsulation (Pl_agent), a transport layer encapsulation (Tl_agent), a logical layer encapsulation (L1_agent), and a RapidIO comparator (SRIO_Scoreboard); the physical layer encapsulation is used to generate and process physical layer data packets of the RapidIO protocol, including a physical layer sequencer (Pl_sequencer), a physical layer driver (Pl_driver), a physical layer monitor (Pl_monitor), a physical layer encapsulation transmit interface (Pl_agent_tx_put), a physical layer encapsulation receive interface (Pl_agent_rx_export), a physical layer driver interaction transmit interface (Pl_put), a physical layer driver interaction receive interface (Pl_get), and a physical layer encapsulation transmit buffer module (Pl_tx_fifo); the physical layer driver includes a physical layer driver transmit interface (Pl_put_port), a physical layer driver receive interface (Pl_get_port), and a physical layer transmit data queue interface (Seq_item_port); the physical layer monitor includes a physical layer monitor transmit analysis interface (Tx_monitor Analysis_port) and a physical layer monitor receive analysis interface (Rx_monitor Analysis_port). Among them, the physical layer driver transmit interface is connected to the physical layer encapsulation transmit interface for data transmission in the physical layer encapsulation transmit direction; the physical layer driver receive interface is connected to the physical layer encapsulation receive interface for data transmission in the physical layer encapsulation receive direction; data transmission between the physical layer driver and the physical layer sequencer is achieved through the physical layer transmit data queue interface, and the data is transmitted in a queue manner to ensure the reliability of transmission; the physical layer monitor transmit analysis interface is connected to the transport layer transmit direction buffer interface (Tl_tx_imp) to enable the physical layer monitor to send data to the transport layer monitor; the physical layer monitor receive analysis interface is connected to the transport layer receive direction buffer interface (Tl_rx_imp) to enable the physical layer monitor to receive data sent by the transport layer monitor; the physical layer driver interaction receive interface is connected to the physical layer driver receive interface and is responsible for transmitting the data in the physical layer encapsulation transmit buffer module to the physical layer driver; the physical layer driver interaction transmit interface is connected to the physical layer encapsulation receive interface for data transmission between the physical layer encapsulation and the physical layer encapsulation transmit buffer module in the receive direction.After the physical layer sequencer receives the application of the RapidIO protocol request packet, it submits a transaction application to the physical layer driver, that is, the physical layer driver obtains the transaction application through the physical layer driver receive interface. The physical layer driver returns a transaction application response to the physical layer sequencer through the physical layer send data queue interface. When the physical layer sequencer receives this response, it indicates that the transaction has been completed. At this time, the physical layer driver sends a sequence (Sequence), that is, a physical layer data packet, to the physical layer sequencer through the physical layer driver send interface. This physical layer data packet adds the field segments of the physical layer protocol, including the response ID and priority. The response ID indicates the data packet to which the currently transmitted data belongs. The response ID corresponds to the request ID, and the sequence number of the response ID is unique. The priority is to enhance the controllability of sending messages. It supports the configuration of 8 priorities and is selected according to the field segment (CRF) of the priority configuration in the sequence. The priorities from 0 to 7 can be selected as needed. The larger the number, the higher the priority. Sequences with higher priorities will be processed preferentially when processing data packets. The physical layer monitor is responsible for data collection and monitoring in the sending direction and receiving direction, that is, monitoring whether the physical layer data packets sent by the physical layer driver to the physical layer sequencer conform to the physical layer specifications of the RapidIO protocol. The physical layer monitor does not involve data exchange with the RapidIO comparator. After summarizing the collected and monitored data, the physical layer monitor sends it to the transport layer monitor through the physical layer send monitor analysis interface, and then transmits the physical layer data packet to the transport layer encapsulation.

[0023] The transport layer encapsulation is used to generate and process transport layer packets of the RapidIO protocol, including a transport layer sequencer (Tl_sequencer), a transport layer monitor (Tl_monitor), a transport layer transmit data queue interface (Seq_item_port), a transport layer encapsulation receive interface (Tl_agent_rx_put), a transport layer encapsulation transmit interface (Tl_agent_tx_put), a transport layer encapsulation receive direction external interface (Tl_agent_rx_export), a transport layer encapsulation transmit direction external interface (Tl_agent_tx_export), a transport layer function bus model interaction transmit interface (Tl_put), a transport layer function bus model interaction receive interface (Tl_get), a transport layer function bus model transmit interface (Tl_put_port), a transport layer function bus model receive interface (Tl_drv_Put_port), a transport layer encapsulation transmit buffer module (Tl_tx_fifo), and a transport layer encapsulation receive buffer module (Tl_rx_fifo); the transport layer monitor (Tl_monitor) includes a transport layer transmit monitor analysis interface (Tx monitor Analysis port), a transport layer receive monitor analysis interface (Rx monitor Analysis port), a transport layer transmit direction buffer interface (Tl_tx_imp), and a transport layer receive direction buffer interface (Tl_rx_imp). Among them, the transport layer transmit data queue interface is responsible for data exchange with the transport layer sequencer; the transport layer encapsulation receive interface is connected to the physical layer encapsulation transmit interface to implement the connection between the physical layer encapsulation and the transport layer encapsulation; the transport layer encapsulation transmit interface is connected to the transport layer function bus model transmit interface for data transmission in the transport layer encapsulation transmit direction; the transport layer encapsulation receive direction external interface is connected to the transport layer function bus model interaction transmit interface and is responsible for storing the received logical layer packets into the transport layer encapsulation receive buffer module; the transport layer encapsulation transmit direction external interface is connected to the transport layer function bus model interaction receive interface for sending the data in the transport layer encapsulation transmit buffer module to the physical layer encapsulation; the transport layer transmit monitor analysis interface is connected to the logical layer transmit direction buffer interface for data analysis of the transport layer packets stored in the transport layer monitor and for sending data to the logical layer monitor; the transport layer receive monitor analysis interface is connected to the logical layer receive direction buffer interface for receiving data from the logical layer monitor.Different from the physical layer encapsulation, the drivers for the transport layer encapsulation and the logical layer encapsulation do not use the traditional driver encapsulation method, but adopt the Bus Function Model (BFM). There are three reasons for adopting the BFM: (1) The sequencer of each layer protocol in this verification platform is packet-based, and each packet is collected at the rising edge of a clock. The biggest feature of the BFM is that it is a module with timing. In the sending direction, it can send data to the DUT clock by clock; (2) The BFM is conducive to data analysis and management. In the receiving direction, the data from the DUT is first stored in a large Memory or register, and when a certain condition is met, an event is triggered to perform assertions or interrupt reporting of events to control and analyze the data stream; (3) The BFM is a bus interface model provided for specific design units. It encapsulates the timing at the lowest layer and only leaves a call interface for the higher layer to use. This design makes the outer interface not need to understand the underlying design, and only needs to be called in the correct way. It can also improve the simulation speed. Especially when multiple layers of the same protocol are involved in transmission, it can effectively reduce the complexity of the communication interface, make the modeling level more concise and convenient to use. When the transport layer function bus model receives the sequence request from the physical layer encapsulation, it establishes a connection with the transport layer sequencer through the transport layer send data queue interface to receive the physical layer data packet. After the transport layer function bus model completes the transaction with the transport layer sequencer, it will add the domain segments of the transport layer protocol to the physical layer data packet, including the transport layer type, destination address, source address, 16-bit cyclic redundancy check, next data packet request, generate the transport layer data packet of the RapidIO protocol, and send it to the logical layer encapsulation.

[0024] The logic layer encapsulation is used to generate and process logic layer data packets of the RapidIO protocol, and can complete direct memory access (DMA) and message passing transactions, including a logic layer sequencer (Ll_sequencer), a logic layer monitor (Ll_monitor), a logic layer transmit data queue interface (Seq_item_port), a logic layer encapsulation receive interface (Ll_agent_rx_put), a logic layer encapsulation transmit interface (Ll_agent_tx_put), a logic layer encapsulation receive direction external interface (Ll_agent_rx_export), a logic layer encapsulation transmit direction external interface (Ll_agent_tx_export), a logic layer function bus model interaction transmit interface (Ll_put), a logic layer function bus model interaction receive interface (Ll_get), a logic layer function bus model transmit interface (Ll_put_port), a logic layer function bus model receive interface (Ll_drv_Put_port), a logic layer encapsulation receive buffer module (Ll_rx_fifo), and a logic layer encapsulation transmit buffer module (Ll_tx_fifo); the logic layer monitor (Ll_monitor) includes a logic layer monitor transmit analysis interface (Tx monitor Analysisport), a logic layer monitor receive analysis interface (Rx monitor Analysis port), a logic layer transmit direction buffer interface (Ll_tx_imp), a logic layer receive direction buffer interface (Ll_rx_imp), a comparator transmit direction interface (uvmblocking get_port), and a comparator receive direction buffer interface (uvm blocking get_imp). Among them, the logic layer transmit data queue interface is responsible for data exchange with the logic layer sequencer; the logic layer encapsulation receive interface is connected to the transport layer encapsulation transmit interface and is used to connect the transport layer encapsulation and the logic layer encapsulation; the logic layer encapsulation transmit interface is connected to the logic layer function bus model transmit interface and is used for data transmission in the logic layer encapsulation transmit direction; the logic layer encapsulation transmit direction external interface is connected to the transport layer encapsulation receive direction external interface and is used for data exchange with the transport layer encapsulation in the receive direction.The external interface in the receiving direction of the logic layer encapsulation is connected to the sending interface that interacts with the logic layer functional bus model, and is responsible for storing the data received in the receiving direction into the logic layer encapsulation sending buffer module; the external interface in the sending direction of the logic layer encapsulation is connected to the receiving interface of the logic layer functional bus model, and is used to send the data in the logic layer encapsulation sending buffer module to the transport layer encapsulation; the logic layer monitor sending analysis interface and the logic layer monitor receiving analysis interface are respectively connected to the RapidIO comparator through the comparator sending direction interface and the comparator receiving direction interface. The logic layer monitor sends the test cases of the RapidIO protocol generated to the RapidIO comparator for data comparison. After receiving the transport layer data packet, the logic layer encapsulation unpacks and parses the transport layer data packet and adds the field segments of the logic layer protocol, including format type, data size, device offset address, optional hidden data, etc., to generate the logic layer data packet, that is, the test case of the RapidIO protocol.

[0025] The RapidIO comparator is used to judge whether the test cases of the generated RapidIO protocol are correct; the RapidIO comparator introduces the data type of the queue. The queue combines the advantages of the linked list and the array, and elements can be added or deleted anywhere in the queue; using the queue can minimize the performance loss as much as possible, and any element can be accessed through the index without traversing all elements like a linked list; the RapidIO comparator can monitor the correctness of the generated RapidIO protocol, and there are 8 common RapidIO protocols.

[0026] The design under test includes an Srio controller, a PCIe controller, and a processing engine. Among them, the Srio controller is used to complete the logical functions of the test cases for the RapidIO protocol. The processing engine is used for the mutual conversion between the RapidIO protocol and the PCIe protocol, including a Mapping mapping engine, a BDMA mapping engine, and a message passing engine. Each engine includes a transmitter and a receiver. The Mapping mapping engine implements the protocol conversion interaction between operations initiated actively by the PCIe controller or the Srio controller. At the same time, the Mapping mapping engine serves as a data path traffic hub in the architecture, directly docking with the Srio controller and the PCIe controller to complete the sending, receiving, and distribution scheduling in both directions. The BDMA mapping engine realizes the data transfer operation function in the chip according to the descriptors configured by the software. The BDMA mapping engine adopts a linked list descriptor structure and performs data transfer operations according to data transfer descriptors and immediate descriptors, supporting dynamic descriptor linking and a maximum data transfer of 64MB. The message passing engine realizes the message passing interconnection between the Srio controller and the PCIe controller. Based on the descriptors, it obtains data from the PCIe controller to form the message packets of the Srio controller and sends them to the Srio controller, and writes the received message packets into the PCIe controller. The PCIe controller is used to complete the logical functions, that is, the signals on the differential link are subjected to digital-to-analog conversion, clock recovery, clock compensation, and channel bonding in the physical layer encapsulation. The test cases for the RapidIO protocol and the test cases for the PCIe protocol serve as the excitation sources for the design under test. After the test cases for the RapidIO protocol complete the logical functions through the Srio controller, the processing engine converts the RapidIO protocol into the PCIe protocol and then sends it to the PCIe controller. After the output signal pcie_change_done of the PCIe controller is set to 1, it is considered that the RapidIO protocol has been successfully converted into the PCIe protocol and then sent to the PCIe verification encapsulation environment. After the test cases for the PCIe protocol complete the logical functions through the PCIe controller, the processing engine converts the PCIe protocol into the RapidIO protocol and then sends it to the Srio controller. After the output signal srio_change_done of the Srio controller is set to 1, it is considered that the PCIe protocol has been successfully converted into the RapidIO protocol and then sent to the RapdiIO verification encapsulation environment.

[0027] Such as Figure 3As shown, the PCIe verification encapsulation environment includes a PCIe application layer data module (PCIe_app_goal_packet), a PCIe transport layer data module (PCIe_transaction_packet), a PCIe link layer data module (PCIe_dl_packet), and a PCIe physical layer data module (PCIe_phy_packet); the PCIe application layer data module is used for the initialization configuration and request packet processing of the PCIe verification encapsulation environment, the PCIe transport layer data module is used for generating and processing the transport layer data packets of the PCIe protocol, the PCIe link layer data module is used for generating and processing the link layer data packets of the PCIe protocol, and the PCIe physical layer data module is used for generating and processing the physical layer data packets of the PCIe protocol.

[0028] Among them, the PCIe application layer data module includes a PCIe configuration module (PCIe_goal_config), a PCIe conversion request module (PCIe_trans_req), a PCIe conversion response module (PCIe_trans_ack), a PCIe receiver interface (PCIe_rx_port), and a PCIe transmitter interface (PCIe_tx_port); the PCIe configuration module is used for the initialization configuration of the memory, IO pins, and window function, etc. of the PCIe verification encapsulation environment, the PCIe conversion request module and the conversion response module are used for processing the request packets and response packets in the transmission direction, and the PCIe transmitter interface and the PCIe receiver interface are used as the data transmission interfaces in the transmission direction and the reception direction respectively, facilitating data processing.

[0029] The PCIe transport layer data module includes a PCIe transport layer sequencer (PCIe_trans_sequencer), a PCIe transport layer driver (PCIe_trans_driver), a PCIe transport layer virtual interface (Virtual_interface), and a PCIe transport layer monitor (PCIe_trans_monitor); the PCIe transport layer driver includes a PCIe transport layer transmit data interface (Trans_tx_port) and a PCIe transport layer receive data interface (Trans_rx_port). The PCIe transport layer receive data interface is connected to the PCIe link layer transmit data interface, enabling the PCIe transport layer driver to send a link layer packet request application to the transmitting PCIe link layer driver; the PCIe transport layer transmit data interface is connected to the PCIe link layer transmit data interface, and transmits the link layer packets of the PCIe protocol generated by the PCIe link layer driver to the PCIe transport layer driver. The PCIe transport layer monitor includes a transport layer transmit data module (Trans_tx_data), a transport layer receive data module (Trans_rx_data), and a transport layer data analysis interface (Trans_analysis_port). The transport layer transmit data module is responsible for data caching in the transmit direction of the PCIe transport layer, the transport layer receive data module is responsible for data caching in the receive direction of the PCIe transport layer, and the transport layer data analysis interface is connected to the link layer data analysis interface, responsible for packing and sending the transport layer packets to the PCIe link layer data module. The PCIe transport layer data module receives request transactions from the PCIe application layer data module in the receive direction; the PCIe transport layer driver receives the sequence passed by the PCIe transport layer sequencer, generates transport layer packets (Transport Layer Packets, TLP), backs up the generated transport layer packets, and then sends them to the PCIe transport layer monitor through the PCIe transport layer virtual interface. The PCIe transport layer monitor performs data acquisition, monitoring, and caching, monitors whether the transport layer packets conform to the transport layer specifications of the PCIe protocol, and then sends the transport layer packets to the link layer data analysis interface through the transport layer data analysis interface, and further sends the transport layer packets to the PCIe link layer data module.

[0030] The PCIe link layer data module includes a PCIe link layer sequencer (PCIe_dl_sequencer), a PCIe link layer driver (PCIe_dl_driver), a PCIe link layer virtual interface (Virtual_interface), and a PCIe link layer monitor (PCIe_dl_monitor). The PCIe link layer driver includes a PCIe link layer transmit data interface (D1_tx_port) and a PCIe link layer receive data interface (D1_rx_port). The PCIe link layer receive data interface (D1_rx_port) is bidirectionally connected to the PCIe physical layer transmit data interface. While sending a request for a physical layer data packet to the PCIe physical layer driver, the PCIe link layer driver receives the physical layer data packet generated by the PCIe physical layer driver. The PCIe link layer monitor includes a link layer transmit data module (Dl_tx_data), a link layer receive data module (Dl_rx_data), and a link layer data analysis interface (Dl_analysis_port). The link layer transmit data module is responsible for data caching in the link layer transmit direction, and the link layer receive data module is responsible for data caching in the link layer receive direction. The link layer data analysis interface is connected to the physical layer data analysis interface and is responsible for packing and sending the link layer data packet to the PCIe physical layer data module. The PCIe link layer data module is used to generate and process the link layer data packets (Data Link Layer Packet, DLLP) of the PCIe protocol. The PCIe link layer driver receives the sequence passed by the PCIe link layer sequencer, adds fields unique to the link layer data packet to the transport layer data packet, including the DLLP type start flag, end flag, and 16-bit cyclic redundancy check, generates the link layer data packet, backs up the link layer data packet, and then sends it to the PCIe link layer monitor through the PCIe link layer virtual interface. The PCIe link layer monitor performs data acquisition, monitoring, and caching, and then sends the link layer data packet to the physical layer data analysis interface through the link layer data analysis interface, and further sends the link layer data packet to the PCIe physical layer data module.

[0031] The PCIe physical layer data module includes a PCIe physical layer sequencer (PCIe_phy_sequencer), a PCIe physical layer driver (PCIe_phy_driver), a PCIe physical layer virtual interface (Virtual_interface), and a PCIe physical layer monitor (PCIe_phy_monitor). The PCIe physical layer driver includes a PCIe physical layer transmit data interface (Phy_tx_port) and a PCIe physical layer receive data interface (Phy_rx_port). The PCIe physical layer transmit data interface is connected to the PCIe link layer receive data interface, and the PCIe physical layer receive data interface is connected to the PCIe physical layer virtual interface. The PCIe physical layer monitor includes a physical layer transmit data module (Phy_tx_data), a physical layer receive data module (Phy_rx_data), and a physical layer data analysis interface (Phy_analysis_port). The physical layer transmit data module is responsible for data caching in the physical layer transmit direction, and the physical layer receive data module is responsible for data caching in the physical layer receive direction. The physical layer data analysis interface is connected to the link layer data analysis interface to receive link layer data packets. The PCIe physical layer data module is used to generate and process physical layer data packets of the PCIe protocol. The PCIe physical layer driver receives the sequence passed by the PCIe physical layer sequencer, performs 8 / 10b encoding and decoding on the link layer data packets to generate physical layer data packets, which are the test cases of the PCIe protocol, and backs up the physical layer data packets, and then sends them to the PCIe physical layer monitor through the PCIe physical layer virtual interface. The PCIe physical layer monitor performs data acquisition, monitoring, and caching.

[0032] In the verification platform of the present invention, since there are many types of data packets of the chip under test, the redundancy between protocols is large, and a part of the collected output signals are high-speed channel lines, it is very difficult to convert them into transaction-level transaction types and it is not conducive to data comparison. Therefore, the RapidIO comparator is optimized and improved. First, instead of collecting data from the output interface of the DUT and bypassing the high-speed channel lines with complex signal structures, data is collected from the PCIe link layer data module in the receive direction of the PCIe verification encapsulation environment and the collected data is put into a queue cache. Then, instead of waiting for the entire data chain to complete before performing data comparison, when a single descriptor return information write is received, the data packet format, header, etc. are checked and the cache space is released at the same time. Finally, a descriptor-based real-time comparison is adopted, and as long as a single descriptor write-back information is received, a check is performed in the Check, which can greatly reduce the cache pressure of the path and speed up the simulation speed.

[0033] The process of the above verification platform is as follows:

[0034] 1) Configure the reference clock and verify the environment reset; After the system is powered on, configure the reference clock. When the reference clock is 100 / 125 MHZ, the RapidIO SerDes rate supports 2.5G / 5G / 7.5GM, and the PCIe SerDes rate can be configured as 5G / 7.5G. Select the clock frequency before establishing the link by configuring the Global Clk_sel register; The reset of the Srio controller is controlled by four Link request device descriptors. When the self-reset signal Self rst is 1, all logic and registers of the entire chip (including sticky and non-sticky) can be reset; The PCIe link reset is controlled by the indication signal Dl_down of the PCIe link layer data module, which can reset and initialize all registers except the sticky registers to ensure the normal link state;

[0035] 2) Initialize the configuration of the verification environment; First, load the test case and start the verification platform; The selection of the test case loaded each time the verification platform is started is selected through run_test() in the global function, and the name of the test case is in the parentheses; However, in actual applications, there may be hundreds or thousands of test cases, and it is too cumbersome to modify the name in the parentheses each time. Add +UVM_TESTNAME= in the Makefile <test>To specify the test cases called during simulation; each time a test case is run, simply enter make test_name=test_demo1 in the Terminal under the Linux system environment to complete the selection of the test case, and this method allows for flexible selection of the test case called by run_test() without modifying the test case name and recompiling repeatedly; use make run_vcs test_name=test_demo command to complete the operation of the verification platform and the selection of the test case. As long as the written test case is loaded in the corresponding list, the search and execution can be automatically completed according to the test case name; all test cases run inherit from base_test, and base_test inherits from the UVM test case library (uvm_test);

[0036] Taking the base test case (base_test) as an example, the verification process is started according to the phase in base_test. In the build_phase, 8 interface sequences are mainly created, the instantiation of the i2c and jtag peripheral access registers is completed, and the creation of the register model is also included, etc.; only build_phase, connect_phase, run_phase, main_phase, and report_phase are used in this base_test. Not all phases need to be used, but the running order generally cannot be changed. In all phases, the channel start command phase.raise_objection and the channel close command phase.drop_objection are used to control the opening and closing of the phase, which is convenient for management;

[0037] 3) After completing the initialization configuration of the verification environment, send the test case; taking the Nread data packet of the RapidIO protocol as an example, the physical layer encapsulation of the RapidIO verification encapsulation environment first sends a request transaction, generates a physical layer data packet with a response ID and priority, and then sends the physical layer data packet to the transport layer encapsulation; the transport layer encapsulation adds fields such as the transport layer type, destination address, and source address to the physical layer data packet, generates a transport layer data packet and packs it for sending to the logical layer encapsulation; the logical layer encapsulation adds fields such as the format type, data size, source transport layer ID, address offset address, and data cache to the transport layer data packet, generating a logical layer data packet; after the logical layer data packet passes the comparison by the RapidIO comparator, it is sent to the transport layer module of the Srio controller of the design under test;

[0038] 4) The Srio controller completes 16-bit cyclic redundancy check, destination sequence number check, packet filtering, data width transformation, etc. After completing the processing logic such as control character parsing, control character generation, link initialization state machine, input error retransmission, etc. in the RapidIO specification, it completes the parsing of the Nread data packet of the RapidIO protocol; sends the parsed data packet to the processing engine, the processing engine converts the Nread data packet from the RapidIO protocol to the PCIe protocol, and then sends it to the PCIe controller. The PCIe controller sends it to the PCIe verification and encapsulation environment through the SerDes to complete the high-speed serial communication interface.

[0039] 5) The PCIe verification and encapsulation environment receives the Non-Posted bus request transaction from the PCIe controller. The PCIe application layer data module completes the initialization configuration of memory, IO pins, and window functions. The PCIe transport layer data module splits and packs the data into the header, packet information, and cyclic redundancy check code (CRC) of the TLP, and puts these into the cache. The PCIe link layer data module will check the CRC and the requested sequence number. If the check is correct, it will be sent to the PCIe link layer data module, otherwise, the transaction will be returned for retransmission. After the PCIe link layer data module receives the transport layer data packet from the PCIe transport layer data module, it adds a sequence number at the header position and adds an LCRC check at the end of the packet. If the CRC check has no error, it will generate a link layer data packet with an ACK response flag and send it to the PCIe physical layer data module; the PCIe physical layer data module adds start and end flags on the basis of the link layer data packet header and packet tail, and then performs encoding, decoding, serial-to-parallel conversion, etc. and sends it to the link, waiting for the LTSSM state machine to complete the initialization.

[0040] 6) When the LTSSM state machine initialization is completed, the PCIe verification and encapsulation environment sends the converted PCIe protocol (Mrd data packet) to the BDMA mapping engine; the BDMA engine and the message passing engine unpack and parse the Mrd data packet. If an abnormality is found, an interrupt event will be triggered for reporting and processing. Some abnormal errors, such as detecting 1-bit error in error checking and correction (ECC) of memory, will trigger interrupt reporting. After correct repair, the data packet will continue to be sent; if there is a 2-bit error detected by ECC and it cannot be repaired, an interrupt will be triggered, then the data packet will be destroyed and a retransmission will be requested.

[0041] 7) After the RapidIO controller receives the Mrd data packet, it splits the data packet into layers after passing various levels of inspection. The physical layer has a 5-bit response sequence number, a 1-bit configuration bit, a 2-bit priority, and a 16-bit CRC. The transport layer has a 2-bit transport layer type, an 8-bit destination sequence number, and an 8-bit source sequence number. The logical layer has a 2-bit packet type format, a 4-bit transport type format, an 8-bit source type sequence number, and a 1-bit pointer. The data packet is then sent to the RapidIO verification encapsulation environment.

[0042] 8) After receiving the data packet, RapidIO Verification Encapsulation sends it to the RapidIO comparator and compares it with the data packet backed up before sending. If the mapping of each field passes, the data packet is received and the data packet information is printed in the result file. If the comparison fails, the retransmission or discarding of the data packet information will be printed in the result file. If the comparison passes, it will be printed in the result file. At this point, the transmission of the request data packet initiated by the RapidIO side is completed. The above process can be used in self-loop or loopback testing.

[0043] Any matters not described in the present invention are applicable to the prior art.< / test>

Claims

1. A verification device for a PCIe-to-RapidIO bridge chip based on UVM, which is used to verify the protocol conversion performance of the PCIe-to-RapidIO bridge chip; It is characterized in that, the verification device includes a RapdiIO verification encapsulation environment, a design under test, and a PCIe verification encapsulation environment; the RapdiIO verification encapsulation environment is used to generate test cases for the RapdiIO protocol, the PCIe verification encapsulation environment is used to generate test cases for the PCIe protocol, the test cases for the RapdiIO protocol and the test cases for the PCIe protocol are used as the excitation sources for the design under test. After the test cases for the RapdiIO protocol are converted into PCIe protocol data packets in the design under test, they are sent to the PCIe verification encapsulation environment, and test cases for the PCIe protocol are generated in the PCIe verification encapsulation environment; After the test cases for the PCIe protocol are protocol-converted into RapdiIO protocol data packets in the design under test, they are sent to the RapdiIO verification encapsulation environment, and test cases for the RapdiIO protocol are generated in the RapdiIO verification encapsulation environment.

2. The verification device for a PCIe-to-RapidIO bridge chip based on UVM according to claim 1, It is characterized in that, the RapdiIO verification encapsulation environment includes a physical layer encapsulation, a transport layer encapsulation, a logical layer encapsulation, and a RapdiIO comparator; the physical layer encapsulation is used to generate physical layer data packets for the RapdiIO protocol. The physical layer encapsulation performs data transmission with the transport layer encapsulation in the transmission direction through the physical layer encapsulation transmission interface, and performs data transmission with the transport layer encapsulation in the reception direction through the physical layer encapsulation reception interface; the transport layer encapsulation is used to generate transport layer data packets for the RapdiIO protocol. The transport layer encapsulation receives the data sent by the physical layer encapsulation through the transport layer encapsulation reception interface, sends data to the logical layer encapsulation through the transport layer encapsulation transmission interface, receives the data sent by the logical layer encapsulation through the transport layer encapsulation reception direction external interface, and sends data to the physical layer encapsulation through the transport layer encapsulation transmission direction external interface; the logical layer encapsulation is used to generate logical layer data packets for the RapdiIO protocol, that is, test cases for the RapdiIO protocol; the logical layer encapsulation receives the data sent by the transport layer encapsulation through the logical layer encapsulation reception interface, and sends data to the transport layer encapsulation through the logical layer encapsulation transmission direction external interface; the RapdiIO comparator is used to determine whether the generated test cases for the RapdiIO protocol are correct.

3. The verification device for a PCIe-to-RapidIO bridge chip based on UVM according to claim 2, It is characterized in that, The physical layer encapsulation includes a physical layer sequencer, a physical layer driver, a physical layer monitor, and a physical layer encapsulation transmit buffer module; the transport layer encapsulation includes a transport layer sequencer, a transport layer functional bus model, a transport layer monitor, a transport layer encapsulation transmit buffer module, and a transport layer encapsulation receive buffer module; the logical layer encapsulation includes a logical layer sequencer, a logical layer functional bus model, a logical layer monitor, a logical layer encapsulation receive buffer module, and a logical layer encapsulation transmit buffer module; wherein, the physical layer sequencer transfers data with the physical layer driver, the physical layer monitor transfers data with the transport layer monitor, and the physical layer encapsulation transmit buffer module is used to store the data transmitted by the transport layer encapsulation; the transport layer sequencer transfers data with the transport layer functional bus model, the transport layer monitor transfers data with the logical layer monitor, the transport layer encapsulation transmit buffer module is used to store the data transmitted by the physical layer encapsulation, and the transport layer encapsulation receive buffer module is used to store the data transmitted by the logical layer encapsulation; the logical layer sequencer transfers data with the logical layer functional bus model, the logical layer encapsulation receive buffer module is used to store the data transmitted by the transport layer encapsulation, and the logical layer encapsulation transmit buffer module is used to store the logical layer data packets.

4. The UVM-based PCIe-to-RapidIO bridge chip verification device according to claim 1, characterized in that the PCIe verification encapsulation environment includes a PCIe application layer data module, a PCIe transport layer data module, a PCIe link layer data module, and a PCIe physical layer data module; The PCIe application layer data module is used for the initialization configuration and request packet processing of the PCIe verification encapsulation environment. The PCIe transport layer data module is used for generating and processing the transport layer data packets of the PCIe protocol. The PCIe link layer data module is used for generating and processing the link layer data packets of the PCIe protocol. The PCIe physical layer data module is used for generating and processing the physical layer data packets of the PCIe protocol, that is, the test cases of the PCIe protocol.

5. The UVM-based PCIe-to-RapidIO bridge chip verification device according to claim 4, characterized in that the PCIe application layer data module includes a PCIe configuration module, a PCIe conversion request module, and a PCIe conversion response module. The PCIe transport layer data module includes a PCIe transport layer sequencer, a PCIe transport layer driver, and a PCIe transport layer monitor. The PCIe link layer data module includes a PCIe link layer sequencer, a PCIe link layer driver, and a PCIe link layer monitor. The PCIe physical layer data module includes a PCIe physical layer sequencer, a PCIe physical layer driver, and a PCIe physical layer monitor; the PCIe configuration module is used for the initialization configuration of the PCIe verification encapsulation environment, and the PCIe conversion request module and the conversion response module are used for processing the request packets and response packets in the sending direction; The PCIe transport layer driver transfers data to the PCIe transport layer sequencer and the PCIe link layer driver respectively. Meanwhile, the PCIe transport layer driver transfers data to the PCIe transport layer monitor through the PCIe transport layer virtual interface, and the PCIe transport layer monitor transfers data to the PCIe link layer monitor. The PCIe link layer sequencer transfers data to the PCIe link layer driver. The PCIe link layer driver transfers data to the PCIe physical layer driver, and transfers data to the PCIe link layer monitor through the PCIe link layer virtual interface at the same time. The PCIe link layer monitor transfers data to the PCIe physical layer monitor at the same time. The PCIe physical layer sequencer transfers data to the PCIe physical layer driver, and the PCIe physical layer driver transfers data to the PCIe physical layer monitor through the PCIe physical layer virtual interface.

6. The UVM-based PCIe-to-RapidIO bridge chip verification device according to claim 1, characterized in that the device under test includes an Srio controller, a PCIe controller and a processing engine; after the test case of the RapidIO protocol completes the logical function through the Srio controller, the processing engine converts the RapidIO protocol into the PCIe protocol and then sends it to the PCIe controller. After the output signal of the PCIe controller is set to 1, it is considered that the RapidIO protocol is successfully converted into the PCIe protocol and then sent to the PCIe verification encapsulation environment; after the test case of the PCIe protocol completes the logical function through the PCIe controller, the processing engine converts the PCIe protocol into the RapidIO protocol and then sends it to the Srio controller. After the output signal of the Srio controller is set to 1, it is considered that the PCIe protocol is successfully converted into the RapidIO protocol and then sent to the RapdiIO verification encapsulation environment.

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