Server signal point measurement position optimization method, system, terminal and storage medium

Abstract

The application relates to the technical field of server testing, and specifically provides a server signal point measurement position optimization method, a system, a terminal and a storage medium, which comprises the following steps: using tool software to screen out signal lines with reserved test points from a PCB diagram, and screening out target signal lines with surface layer test points being blocked or test points being in an inner layer from the signal lines with the reserved test points; generating a substitute test point for the target signal line based on a test point position of the target signal line and a preset processing rule, and marking the substitute test point to the PCB diagram, wherein the processing rule comprises generating a surface layer test point or an inner layer test point needing to be punched for the reserved test point. According to the application, the surface layer and the inner layer signal can be measured by points, the coverage of signal testing is greatly increased, and the workload of finding different types of screws to fix iron pieces or cutting iron pieces for different CPUs is avoided, so that the input of manpower and material resources is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of server testing, and particularly relates to a server signal point measurement position optimization method, system, terminal and storage medium. BACKGROUND

[0002] With the rapid development of the server industry, international competition is becoming increasingly fierce, and the requirements for server performance and quality are also becoming higher and higher. In server quality evaluation, signal testing is an effective means to test server quality. In order to cover a wider range of signals, the point measurement method is usually used to measure signals without test fixtures. Server point measurement can only be performed on the surface layer of the server. In the actual point measurement process, the ideal test point is often covered by the CPU back iron, the iron cannot be removed, or the ideal test point of the signal to be measured is located on the inner layer of the PCB, which leads to the failure of point measurement on the surface layer. This will result in the failure of signal quality testing.

[0003] Currently, when performing server signal point measurement, the ideal test point is covered by the CPU back iron mainly because the design of some CPUs causes the CPU to be unable to be fixed on the mainboard when the iron is removed, thereby causing the server to be unable to be normally used and the signal point measurement to be unable to be performed. In order to solve this problem, there are mainly two solutions: the first method is to find a via on the surface layer of the signal line to be measured, and to scrape a point for measurement at the via. The second method is to remove the back iron, and to find a screw of a suitable size or to cut the iron to obtain a screw that can match the screw hole on the front surface, so as to fix the CPU on the mainboard and normally perform signal testing. When the ideal test point is located on the inner layer, the method one mentioned above is usually used as a solution: finding a via on the surface layer of the signal line, scraping a point at the via, and then performing point measurement.

[0004] Among them, the surface via selected by the first method is usually far away from the expected optimal test point, and the signal may be affected by reflection, link loss, etc., so that the measurement effect is poor, and the accuracy of the measurement data obtained is affected. The second method is relatively complex to operate and consumes manpower and material resources. Because the fixed screw size required by CPUs of different manufacturers may be different, it is time-consuming and laborious to find a suitable screw. Cutting the iron requires professional machine tool operation and cutting, and different CPUs need to be cut multiple times, which requires high operating conditions. SUMMARY

[0005] In view of the above shortcomings of the prior art, the application provides a server signal point measurement position optimization method, system, terminal and storage medium to solve the above technical problems.

[0006] In a first aspect, the application provides a server signal point measurement position optimization method, comprising:

[0007] The tool software screens signal lines with reserved test points from the PCB diagram, and screens target signal lines with occluded surface layer test points or test points in inner layers from the signal lines with reserved test points;

[0008] The tool software generates a substitute test point for the target signal line based on the test point position of the target signal line and a preset processing rule, and marks the substitute test point to the PCB diagram, wherein the processing rule includes generating a surface layer test point or an inner layer test point requiring punching for the reserved test point.

[0009] Further, the tool software screens target signal lines with occluded surface layer test points or test points in inner layers from the signal lines with reserved test points in the PCB diagram, including:

[0010] Importing a schematic diagram of the PCB into the tool software, and calling a screening function of the tool software to screen all candidate signal lines with reserved test points;

[0011] Importing a complete file of the PCB layout into the tool software, screening a first type of signal lines with reserved test points in inner layers from the candidate signal lines, and screening a second type of signal lines with surface layer reserved test points covered by surface layer cover marks from the remaining candidate signal lines based on the surface layer cover marks in the complete file;

[0012] The first type of signal lines and the second type of signal lines are summarized as a target signal line set.

[0013] Further, the processing rule includes:

[0014] If the reserved test point of the signal line is in the inner layer of the PCB, the coordinates of the substitute test point are set to be consistent with the coordinates of the reserved test point;

[0015] If the coordinates of the reserved test point of the signal line are in the coordinate area range of the surface layer cover mark, candidate nodes satisfying a preset distance from the reserved test point are screened from all nodes of the signal line not in the coordinate area range of the surface layer cover mark, and the distance refers to the length of the signal line between the candidate node and the reserved test point;

[0016] A node with the shortest signal line between the coordinates of the node and the coordinates of the reserved test point and located on the surface layer of the PCB is screened from the candidate nodes as the substitute test point of the reserved test point;

[0017] If there is no node located on the surface layer of the PCB in the candidate nodes, a node with the shortest signal line between the coordinates of the node and the coordinates of the reserved test point is screened from the candidate nodes as the substitute test point of the reserved test point.

[0018] Further, the position optimization unit generates a substitute test point for the target signal line based on the test point position of the target signal line and a preset processing rule, and marks the substitute test point to the PCB diagram, the processing rule including generating a surface test point or a via test point for the reserved test point in proximity.

[0019] determining whether the test point is on the surface of the PCB diagram:

[0020] If not, a via mark is generated at a corresponding position on the surface of the PCB diagram based on the coordinates of the test point.

[0021] Further, the method further includes:

[0022] previously setting a reserved test point scheme corresponding to a plurality of types of PCB schematic diagrams;

[0023] importing a schematic diagram of a target PCB diagram, and screening a matching reserved test point scheme for the schematic diagram of the PCB diagram;

[0024] marking a reserved test point at a corresponding position of the schematic diagram of the target PCB diagram based on the matching reserved test point scheme.

[0025] Further, the target signal line where the reserved test point in the matching reserved test point scheme is located and the relative position of the target signal line are extracted;

[0026] finding the target signal line from the schematic diagram of the target PCB diagram, and marking the reserved test point at a corresponding position of the target signal line.

[0027] Further, after the substitute test point of the reserved test point is produced, the method further includes:

[0028] deleting the reserved test point with the corresponding substitute test point from the PCB diagram.

[0029] In a second aspect, the present application provides a server signal point position optimization system, comprising:

[0030] a target screening unit configured to screen a signal line with a reserved test point from a PCB diagram by using tool software, and screen a target signal line with a surface test point blocked or a test point in an inner layer from the signal line with the reserved test point;

[0031] a position optimization unit configured to generate a substitute test point for the target signal line based on the test point position of the target signal line and a preset processing rule, and mark the substitute test point to the PCB diagram, the processing rule including generating a surface test point or a via test point for the reserved test point in proximity.

[0032] Further, the target screening unit includes:

[0033] The first screening module is configured to import a schematic diagram of the PCB into tool software, and call a screening function of the tool software to screen all candidate signal lines having reserved test points;

[0034] The second screening module is configured to import a complete file of a layout of the PCB into the tool software, screen a first type of signal line having a reserved test point on an inner layer of the PCB from the candidate signal lines, and screen a second type of signal line having a reserved test point on a surface layer covered by a surface layer cover identifier from the remaining candidate signal lines based on the surface layer cover identifier in the complete file.

[0035] The result summarizing module is configured to summarize the first type of signal line and the second type of signal line into a target signal line set.

[0036] Further, the processing rule comprises:

[0037] If the reserved test point of the signal line is on the inner layer of the PCB, the coordinates of the substitute test point are consistent with the coordinates of the reserved test point.

[0038] If the coordinates of the reserved test point of the signal line are within the coordinate area range of the surface layer cover identifier, a candidate node satisfying a preset distance from the reserved test point is screened from all nodes of the signal line not within the coordinate area range of the surface layer cover identifier, and the distance refers to a signal line length between the candidate node and the reserved test point.

[0039] A node having the shortest signal line between the coordinates of the node and the coordinates of the reserved test point is screened from the candidate node as the substitute test point of the reserved test point.

[0040] If there is no node on the surface layer of the PCB in the candidate node, a node having the shortest signal line between the coordinates of the node and the coordinates of the reserved test point is screened from the candidate node as the substitute test point of the reserved test point.

[0041] Further, the position optimization unit comprises:

[0042] The position judgment module is configured to judge whether the test point is on the surface layer of the PCB layout.

[0043] The punching mark module is configured to, if the substitute test point is not on the surface layer of the PCB layout, generate a punching identifier based on a corresponding position of the test point on a side of the surface layer of the PCB layout without occlusion.

[0044] Further, the system further performs:

[0045] A reserved test point scheme corresponding to a plurality of types of PCB schematic diagrams is preset.

[0046] A schematic diagram of a target PCB layout is imported, and a matching reserved test point scheme is screened for the schematic diagram of the PCB layout.

[0047] Based on the matching reserved test point scheme, a reserved test point is marked at a corresponding position of a schematic diagram of the target PCB diagram.

[0048] Further, based on the matching reserved test point scheme, a reserved test point is marked at a corresponding position of a schematic diagram of the PCB diagram, comprising:

[0049] Extracting a target signal line where the reserved test point in the matching reserved test point scheme is located and a relative position of the target signal line;

[0050] Finding the target signal line from the schematic diagram of the target PCB diagram, and marking the reserved test point at a corresponding position of the target signal line.

[0051] Further, after the production of the substitute test point of the reserved test point, the system further comprises:

[0052] Deleting the reserved test point with the corresponding substitute test point from the PCB diagram.

[0053] In a third aspect, a terminal is provided, comprising:

[0054] A processor and a memory, wherein,

[0055] The memory is used to store a computer program,

[0056] The processor is used to call and run the computer program from the memory, so that the terminal executes the method of the terminal described above.

[0057] In a fourth aspect, a computer storage medium is provided, and the computer readable storage medium stores instructions, when the instructions are run on a computer, the computer executes the method described in the above aspects.

[0058] The server signal point measurement position optimization method, system, terminal and storage medium provided by the application have the beneficial effects that the signal lines that cannot be directly measured on the surface are screened, the test points are regenerated based on the reserved test points of the screened signal lines, and it is evaluated whether the regenerated test points need to be set through holes and the through hole planning is performed. The application makes the surface layer and the inner layer signal can be measured, greatly increases the coverage of signal testing, avoids the work of finding different types of screws to fix the iron parts or cutting the iron parts for different CPUs, reduces the investment of manpower and material resources. The application has strong practicability, wide application range, more accurate test results, and greatly reduces the labor cost and time cost.

[0059] In addition, the application has reliable design principles, simple structure, and very wide application prospects. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings can also provide the basis for the person of ordinary skill in the art to obtain other drawings without creative effort.

[0061] Figure 1 is a schematic flow chart of a method of an embodiment of the present application.

[0062] Figure 2 is a schematic block diagram of a system of an embodiment of the present application.

[0063] Figure 3 is a structural schematic diagram of a terminal provided by an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the person of ordinary skill in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described in the embodiments of the present application in combination with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person of ordinary skill in the art without creative effort should belong to the protection scope of the present application.

[0065] The key terms appearing in the present application will be explained as follows.

[0066] PCB (Printed Circuit Board), Chinese name is printed circuit board, also known as printed wiring board, is an important electronic component, is the support of electronic components, is the carrier of electrical interconnection of electronic components. Since it is made by electronic printing, it is called 'printed' circuit board. PCB is one of the important components of electronic industry. Almost every kind of electronic equipment, small to electronic watch, calculator, large to computer, communication electronic equipment, military weapon system, as long as there are integrated circuits and other electronic components, in order to realize the electrical interconnection between various components, printed board must be used. Printed wiring board is composed of insulating substrate, connecting wire and pad for assembling and welding electronic components, has the dual role of conductive circuit and insulating substrate. It can replace the complex wiring to realize the electrical connection between various components in the circuit, not only simplifies the assembly and welding work of electronic products, reduces the wiring workload under the traditional way, greatly reduces the labor intensity of workers; and reduces the volume of the whole machine, reduces the cost of products, improves the quality and reliability of electronic equipment. Printed wiring board has good product consistency, it can be designed with standardization, which is conducive to the realization of mechanization and automation in the production process. At the same time, the whole printed wiring board after assembly and debugging can be used as an independent spare part, which is convenient for the interchange and maintenance of the whole machine product. At present, printed wiring board has been widely used in the production and manufacturing of electronic products.

[0067] CPU (central processing unit, CPU for short) as the operation and control core of computer system, is the final execution unit of information processing and program running.

[0068] Figure 1 is the schematic flow chart of the method of one embodiment of the present application. Wherein, Figure 1 The execution subject can be a server signal point measurement position optimization system.

[0069] As Figure 1 shown, the method comprises:

[0070] Step 110, using tool software to screen out signal lines with reserved test points from the PCB diagram, and screen out target signal lines whose surface test points are blocked or test points are in the inner layer from the signal lines with reserved test points;

[0071] Step 120, generating a substitute test point for the target signal line based on the test point position of the target signal line and the preset processing rule, and marking the substitute test point to the PCB diagram, the processing rule includes generating a surface test point or a hole required inner layer test point for the reserved test point.

[0072] For the convenience of understanding the present application, the principle of the server signal point measurement position optimization method of the present application is described below in combination with the process of optimizing the server signal point measurement position in the embodiment to further describe the server signal point measurement position optimization method provided by the present application.

[0073] Specifically, the server signal point measurement position optimization method comprises:

[0074] S 1, using tool software to screen out signal lines with reserved test points from the PCB diagram, and screen out target signal lines with surface layer test points blocked or test points in the inner layer from the signal lines with reserved test points.

[0075] First, add reserved test points in the PCB diagram, and the specific method comprises: setting a plurality of types of PCB schematic diagram corresponding reserved test point scheme in advance, wherein the plurality of types of PCB are, for example, server hard disk backplane, motherboard, network management part, etc.; importing the schematic diagram of the target PCB diagram, and screening and matching the reserved test point scheme for the schematic diagram of the PCB diagram; based on the matching reserved test point scheme, marking the reserved test point at the corresponding position of the schematic diagram of the target PCB diagram, specifically, extracting the target signal line where the reserved test point in the matching reserved test point scheme is located and the relative position of the target signal line; finding the target signal line from the schematic diagram of the target PCB diagram, and marking the reserved test point at the corresponding position of the target signal line.

[0076] Import the schematic diagram of the PCB into the tool software, call the screening function of the tool software to screen out all candidate signal lines with reserved test points; import the complete file of the PCB layout into the tool software, screen out a type of signal lines with reserved test points in the inner layer from the candidate signal lines, and screen out a type of signal lines with surface layer reserved test points covered by surface layer cover marks from the remaining candidate signal lines based on the surface layer cover marks in the complete file; and the first type of signal lines and the second type of signal lines are summarized as a target signal line set.

[0077] Mark the reserved test points on the signal lines in the ideal position when designing the PCB diagram. In this embodiment, the tool software selects all e gro, and the information of the signal lines with reserved test points in the schematic diagram is exported through all e gro to obtain candidate signal lines. First, screen out a type of signal lines with reserved test points in the inner layer from all candidate signal lines, then call the comparison function of all e gro, and based on the pre-imported complete file of the PCB layout (BRD format file), compare the coordinates of the reserved test points with the coordinate region of the surface layer cover marks in the complete file to screen out a type of signal lines with surface layer reserved test points covered by surface layer cover marks.

[0078] Since the number of various signal lines and related information in the PCB diagram is large, the calculation amount is large when the target is investigated, and in the embodiment, the screening features are set and screened in batches to quickly and accurately screen the point measurement signal lines that need to be optimized.

[0079] S 2, generate a substitute test point for the target signal line based on the test point position of the target signal line and a preset processing rule, and mark the substitute test point to the PCB diagram, the processing rule includes generating a surface test point or a hole-need inner layer test point for the reserved test point.

[0080] First, set the processing rule, the specific content of the processing rule includes: if the reserved test point of the signal line is in the inner layer of the PCB, set the coordinates of the substitute test point and the reserved test point to be consistent; if the coordinates of the reserved test point of the signal line are within the coordinate area range of the surface layer cover mark, select a candidate node from all nodes of the signal line that are not within the coordinate area range of the surface layer cover mark, the distance between the candidate node and the reserved test point satisfies the preset distance, the distance refers to the length of the signal line between the candidate node and the reserved test point; select the node with the shortest signal line between the candidate node and the reserved test point as the substitute test point of the reserved test point; if there is no node on the surface layer of the PCB in the candidate node, select the node with the shortest signal line between the candidate node and the reserved test point as the substitute test point of the reserved test point.

[0081] In actual processing, if the reserved test point is in the inner layer, since there is basically no case of relative arrangement of iron and other coverings on both surfaces of the PCB in actual PCB design, it is not necessary to move the position of the reserved test point, and it is only necessary to punch on the side convenient for punching. If the reserved test point is in the surface layer and is covered, the coordinate area (x1-x2, y1-y2) of the surface layer covering is obtained, the horizontal parameter k and the vertical parameter b (k and b are both positive numbers) are set based on the conventional size of the iron and other coverings, it is assumed that the coordinates of the reserved test point are (x0, y0), obviously x1

[0082] Based on the above four kinds of test points, different processing needs to be carried out, and the specific processing method is:

[0083] Determine whether the test point is in the surface layer of the PCB diagram: if yes, no processing is needed; if no, generate a punch mark based on the corresponding position of the unobstructed side of the test point in the surface layer of the PCB diagram. In this way, it is possible to punch from the surface layer to the inner layer reserved test point as close as possible to the ideal test point position on the signal line, so that the surface layer point of the to-be-tested board can be tested.

[0084] Based on the above PCB diagram, a PCB board is prepared, and signal testing can be carried out at the surface layer test point or the inner layer test point with a via. The test instrument is composed of an oscilloscope and a probe that meet the bandwidth requirements of the test. In testing, the probe is connected to the test channel of the oscilloscope, the oscilloscope parameter setting is adjusted, the test data is obtained, and the oscilloscope is turned off. End of test.

[0085] The method can make the surface layer signal and the inner layer signal can be tested, greatly increase the coverage of the signal test, and avoid the work of searching different types of screws to fix the iron piece or cutting the iron piece for different CPUs, thereby reducing the labor and material investment.

[0086] As shown in Figure 2 The system 200 comprises:

[0087] A target screening unit 210 is configured to screen, by using tool software, signal lines with reserved test points from a PCB diagram, and screen target signal lines with surface layer test points being blocked or test points being in an inner layer from the signal lines with the reserved test points.

[0088] A position optimization unit 220 is configured to generate a substitute test point for the target signal line based on a test point position of the target signal line and a preset processing rule, and mark the substitute test point to the PCB diagram, wherein the processing rule comprises generating a surface layer test point or a hole-requiring inner layer test point for the reserved test point.

[0089] Optionally, as an embodiment of the present application, the target screening unit comprises:

[0090] A first screening module is configured to import a schematic diagram of a PCB to tool software, and call a screening function of the tool software to screen all candidate signal lines with reserved test points.

[0091] A second screening module is configured to import a complete file of a PCB layout to the tool software, screen a first type of signal lines with the reserved test points in an inner layer of the PCB from the candidate signal lines, and screen a second type of signal lines with surface layer reserved test points being covered by surface layer cover marks from remaining candidate signal lines based on the surface layer cover marks in the complete file.

[0092] A result summarizing module is configured to summarize the first type of signal lines and the second type of signal lines as a target signal line set.

[0093] Optionally, as an embodiment of the present application, the processing rule comprises:

[0094] If the reserved test point of the signal line is in the inner layer of the PCB, the coordinate of the substitute test point is set to be consistent with the coordinate of the reserved test point.

[0095] If the coordinate of the reserved test point of the signal line is in a coordinate area range of the surface layer cover mark, a candidate node satisfying a preset distance from the reserved test point is screened from all nodes of the signal line not in the coordinate area range of the surface layer cover mark, and the distance refers to a signal line length between the candidate node and the reserved test point.

[0096] Screening a node with the shortest signal line between the reserved test point from the candidate nodes as the substitute test point of the reserved test point if the node is located on the surface layer of the PCB;

[0097] Screening a node with the shortest signal line between the reserved test point from the candidate nodes as the substitute test point of the reserved test point if there is no node located on the surface layer of the PCB in the candidate nodes.

[0098] Optionally, as an embodiment of the present application, the position optimization unit comprises:

[0099] A position judging module for judging whether the test point is on the surface layer of the PCB diagram;

[0100] A drilling marking module for generating a drilling mark based on the corresponding position of the test point on the unobstructed side of the surface layer of the PCB diagram if the substitute test point is not on the surface layer of the PCB diagram.

[0101] Optionally, as an embodiment of the present application, the system further performs:

[0102] Pre-setting a reserved test point scheme corresponding to a plurality of types of PCB schematic diagrams;

[0103] Importing a schematic diagram of a target PCB diagram and screening a matching reserved test point scheme for the schematic diagram of the PCB diagram;

[0104] Marking a reserved test point at the corresponding position of the schematic diagram of the target PCB diagram based on the matching reserved test point scheme.

[0105] Optionally, as an embodiment of the present application, marking a reserved test point at the corresponding position of the schematic diagram of the PCB diagram based on the matching reserved test point scheme comprises:

[0106] Extracting a target signal line where the reserved test point in the matching reserved test point scheme is located and a relative position of the target signal line;

[0107] Finding the target signal line from the schematic diagram of the target PCB diagram and marking the reserved test point at the corresponding position of the target signal line.

[0108] Optionally, as an embodiment of the present application, after the position optimization unit produces the substitute test point of the reserved test point, the system further comprises:

[0109] Deleting the reserved test point with the corresponding substitute test point from the PCB diagram.

[0110] Figure 3 A structure schematic diagram of a terminal 300 is provided for an embodiment of the present application, which can be used to execute the server signal point position optimization method provided by an embodiment of the present application.

[0111] The terminal 300 can include a processor 310, a memory 320 and a communication unit 330. These components communicate via one or more buses, and those skilled in the art can understand that the structure of the server shown in the figure does not constitute a limitation on the present application, which can be a bus structure or a star structure, and can include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0112] The memory 320 can be used to store the execution instructions of the processor 310, and the memory 320 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the terminal 300 can execute some or all of the steps in the following method embodiments.

[0113] The processor 310 is the control center of the storage terminal, which connects all parts of the electronic terminal through various interfaces and lines, executes or runs the software programs and / or modules stored in the memory 320, and calls the data stored in the memory, to perform various functions of the electronic terminal and / or process data. The processor can be composed of integrated circuits (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs connected together. For example, the processor 310 can only include a central processing unit (CPU). In the embodiments of the present application, the CPU can be a single operation core or can include multiple operation cores.

[0114] The communication unit 330 is used to establish a communication channel, so that the storage terminal can communicate with other terminals. Receive user data sent by other terminals or send user data to other terminals.

[0115] The present application also provides a computer storage medium, wherein the computer storage medium can store a program, and the program can include some or all steps in the embodiments provided by the present application when executed. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0116] Therefore, the application can screen the signal lines which cannot be directly measured on the surface, and re-generate test points for the screened signal lines based on the reserved test points, and evaluate whether the re-generated test points need to be provided with vias and plan the vias. The application can make the surface layer and the inner layer signal be measured, greatly increase the coverage of signal testing, and avoid the workload of finding different types of screws to fix the iron pieces or cutting the iron pieces for different CPUs, and reduce the labor and material inputs. The application has strong practicability, wide application range, and more accurate test results, and greatly reduces the labor cost and time cost. The technical effects achieved by the embodiment can be referred to the description in the foregoing, and will not be described herein.

[0117] Those skilled in the art can clearly understand that the technologies in the embodiments of the application can be realized by means of software and necessary general hardware platforms. Based on such understanding, the technical solutions in the embodiments of the application can be embodied in the form of a software product, which is stored in a storage medium such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes, and includes a plurality of instructions for causing a computer terminal (which can be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in the embodiments of the application.

[0118] In the present specification, the same or similar parts among various embodiments can be referred to each other. Especially, for the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the description in the method embodiments.

[0119] In the several embodiments provided in the present application, it should be understood that the disclosed system and method can be implemented in other ways. For example, the system embodiments described above are only schematic. The division of the units is only a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, access layers, or intermediate units. The indirect couplings or communication connections between the units, or the display of the mutual couplings between the units can be in electrical, mechanical or other forms.

[0120] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment of the present application according to actual needs.

[0121] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0122] Although the present application is described in detail with reference to the preferred embodiments, the present application is not limited thereto. Various equivalent modifications or replacements can be made to the embodiments of the present application by those skilled in the art without departing from the spirit and essence of the present application, and these modifications or replacements shall be within the scope of the present application. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or replacements, which shall be within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for optimizing the location of server signal point measurement, characterized in that, The method comprises the following steps: screening signal lines with reserved test points from a PCB diagram by using tool software, and screening target signal lines with occluded surface test points or test points in inner layers from the signal lines with the reserved test points; generating substitute test points for the target signal lines based on the test point positions of the target signal lines and preset processing rules, and marking the substitute test points to the PCB diagram, wherein the processing rules comprise generating surface test points or inner layer test points requiring punching for the reserved test points as close as possible; the processing rules comprise: if the reserved test point of a signal line is in the inner layer of a PCB, setting the coordinates of the substitute test point to be consistent with those of the reserved test point; if the coordinates of the reserved test point of a signal line are within the coordinate area range of a surface cover identifier, screening candidate nodes from all nodes of the signal line that are not within the coordinate area range of the surface cover identifier, wherein the distance refers to the length of the signal line between the candidate nodes and the reserved test point; screening a node with the shortest signal line between the reserved test point and the surface of the PCB from the candidate nodes as the substitute test point of the reserved test point; if there is no node on the surface of the PCB in the candidate nodes, screening a node with the shortest signal line between the reserved test point as the substitute test point of the reserved test point.

2. The method of claim 1, wherein, The method for screening target signal lines with occluded surface test points or test points in inner layers from signal lines with reserved test points in a PCB diagram by using tool software comprises the following steps: importing a schematic diagram of a PCB into tool software, and calling a screening function of the tool software to screen all candidate signal lines with reserved test points; importing a complete file of a PCB layout into the tool software, screening a first type of signal lines with reserved test points in inner layers from the candidate signal lines, and screening a second type of signal lines with surface reserved test points covered by a surface cover identifier from the remaining candidate signal lines based on the surface cover identifier in the complete file; combining the first type of signal lines and the second type of signal lines into a target signal line set.

3. The method of claim 1, wherein, The method for generating substitute test points for target signal lines based on the test point positions of the target signal lines and preset processing rules, and marking the substitute test points to a PCB diagram, wherein the processing rules comprise generating surface test points or inner layer test points requiring punching for the reserved test points as close as possible, comprises the following steps: determining whether the test point is on the surface of the PCB diagram: if not, generating a punching identifier based on the corresponding position of the coordinates of the test point on the unoccluded side of the surface of the PCB diagram.

4. The method of claim 1, wherein, The method further comprises the following steps: pre-setting a plurality of types of PCB schematic diagrams corresponding to reserved test point schemes; importing a schematic diagram of a target PCB diagram, and screening a matching reserved test point scheme for the schematic diagram of the PCB diagram; marking a reserved test point at a corresponding position of the schematic diagram of the PCB diagram based on the matching reserved test point scheme.

5. The method of claim 4, wherein, The method for marking a reserved test point at a corresponding position of a schematic diagram of a PCB diagram based on a matching reserved test point scheme comprises the following steps: extracting a target signal line where a reserved test point in the matching reserved test point scheme is located and a relative position of the target signal line; Finding the target signal line from the schematic diagram of the target PCB diagram, and marking the reserved test point at the corresponding position of the target signal line.

6. The method of claim 1, wherein, After producing the substitute test point of the reserved test point, the method further comprises: Deleting the reserved test point with the corresponding substitute test point from the PCB diagram.

7. A server signal point location optimization system, comprising: Comprise: A target screening unit for screening the signal line with the reserved test point from the PCB diagram by using the tool software, and screening the target signal line with the surface test point being blocked or the test point being in the inner layer from the signal line with the reserved test point; A position optimization unit for generating the substitute test point for the target signal line based on the test point position of the target signal line and the preset processing rule, and marking the substitute test point to the PCB diagram, the processing rule comprising generating the surface test point or the inner layer test point needing to be punched for the reserved test point as close as possible; The processing rule comprises: If the reserved test point of the signal line is in the inner layer of the PCB, setting the coordinate of the substitute test point consistent with the coordinate of the reserved test point; If the coordinate of the reserved test point of the signal line is in the coordinate area range of the surface layer cover mark, screening the candidate node satisfying the preset distance from the reserved test point from all the nodes of the signal line not in the coordinate area range of the surface layer cover mark, the distance referring to the signal line length between the candidate node and the reserved test point; Screening the node with the shortest signal line between the coordinate located in the surface layer of the PCB and the reserved test point from the candidate node as the substitute test point of the reserved test point; If there is no node located in the surface layer of the PCB in the candidate node, screening the node with the shortest signal line between the candidate node and the reserved test point as the substitute test point of the reserved test point.

8. A terminal, characterized by comprising: Comprise: A processor; A memory for storing the execution instruction of the processor; Wherein, the processor is configured to execute the method of any one of claims 1-6.

9. A computer readable storage medium storing a computer program, characterized in that, The program is executed by the processor to realize the method of any one of claims 1-6. The program is executed by the processor to realize the method of any one of claims 1-6.

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