Gate driving circuit, driving method thereof and display panel

Abstract

The application provides a gate driving circuit and a driving method thereof and a display panel, relates to the technical field of display, and improves the use yield of a transistor, thereby prolonging the service life of the gate driving circuit. The gate driving circuit comprises n row shift register units, a frame start signal line, k clock signal lines, and x control sub-circuits; the mth control sub-circuit is coupled with the input end of the mth row shift register unit, the frame start signal line, and the mth clock signal line; the mth clock signal line is coupled with the mth row shift register unit; the rising edge of the frame start signal transmitted by the frame start signal line is in the same period as the starting rising edge of the clock signal transmitted by the first clock signal line; and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the kth clock signal line.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and its driving method, and a display panel. Background Technology

[0002] Gate-on-Array (GONA) technology has become mainstream in the LCD industry. It not only improves bezel utilization but also reduces costs. Display products using this technology have a large number of thin-film transistors (TFTs) in the gate drive circuit area. These TFTs perform different functions, and these functions are interdependent. If one or more TFTs malfunction, the output signal will be abnormal, reducing the lifespan of the gate drive circuit, leading to abnormal image display and affecting customer satisfaction.

[0003] Therefore, improving the yield of transistors and extending the lifespan of gate drive circuits has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a gate driving circuit and its driving method, as well as a display panel, for improving the yield of transistors and thus extending the service life of the gate driving circuit.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A first aspect of the present invention provides a gate driving circuit, comprising: n rows of shift register units, n > 4; a frame start signal line, k clock signal lines, k satisfying 4 ≤ k < n, and k being an even number; and x control sub-circuits, x = k / 2;

[0007] The m-th control sub-circuit is coupled to the input terminal of the m-th row shift register unit, the frame start signal line, and the m-th clock signal line, respectively, and is used to: control the electrical connection between the input terminal of the m-th row shift register unit and the m-th clock signal line under the control of the frame start signal line; and / or, control the electrical connection between the input terminal of the m-th row shift register unit and the frame start signal line under the control of the m-th clock signal line; 1≤m≤x;

[0008] The m-th clock signal line is coupled to the m-th row shift register unit. The rising edge of the frame start signal transmitted by the frame start signal line is in the same time period as the rising edge of the clock signal transmitted by the first clock signal line. The falling edge of the frame start signal is in the same time period as the falling edge of the first pulse of the clock signal transmitted by the k-th clock signal line.

[0009] Optionally, the mth control sub-circuit comprises a first control unit and / or a second control unit.

[0010] The control end of the first control unit is coupled with the frame start signal line, the input end of the first control unit is coupled with the mth clock signal line, and the output end of the first control unit is coupled with the input end of the mth row of shift register units; and the first control unit is configured to control the electrical connection between the input end of the mth row of shift register units and the mth clock signal line to be turned on or turned off under the control of the frame start signal line.

[0011] The control end of the second control unit is coupled with the mth clock signal line, the input end of the second control unit is coupled with the frame start signal line, and the output end of the second control unit is coupled with the input end of the mth row of shift register units; and the second control unit is configured to control the electrical connection between the input end of the mth row of shift register units and the frame start signal line to be turned on or turned off under the control of the mth clock signal line.

[0012] Optionally, the first control unit comprises a first transistor, the gate of the first transistor is coupled with the frame start signal line, the first pole of the first transistor is coupled with the mth clock signal line, and the second pole of the first transistor is coupled with the input end of the mth row of shift register units.

[0013] Optionally, the second control unit comprises a second transistor, the gate of the second transistor is coupled with the mth clock signal line, the first pole of the second transistor is coupled with the frame start signal line, and the second pole of the second transistor is coupled with the input end of the mth row of shift register units.

[0014] Optionally, the mth row of shift register units comprises an input transistor, a pull-up node, an output transistor, a bootstrap capacitor, a first reset transistor and a second reset transistor.

[0015] The gate of the input transistor is coupled with the first pole of the input transistor, the first pole of the input transistor serves as the input end of the mth row of shift register units, and the second pole of the input transistor is coupled with the pull-up node.

[0016] The gate of the output transistor is coupled with the pull-up node, the first pole of the output transistor is coupled with the mth clock signal line, and the second pole of the output transistor is coupled with the output end of the mth row of shift register units.

[0017] The first end of the bootstrap capacitor is coupled with the pull-up node, and the second end of the bootstrap capacitor is coupled with the output end of the mth row of shift register units.

[0018] The gate of the first reset transistor is coupled with a reset signal input end, the first pole of the first reset transistor is coupled with the pull-up node, and the second pole of the first reset transistor is coupled with a first level signal input end.

[0019] The gate of the second reset transistor is coupled with the reset signal input end, the first pole of the second reset transistor is coupled with the output end of the mth row of shift register units, and the second pole of the second reset transistor is coupled with the first level signal input end.

[0020] Based on the technical scheme of the above-described gate driving circuit, a second aspect of the present application provides a display panel comprising the above-described gate driving circuit.

[0021] Optionally, the display panel comprises a display area and a peripheral area, the peripheral area comprises a first bezel area and a second bezel area arranged oppositely, and a third bezel area located on the same side of the first bezel area and the second bezel area; the display area is located between the first bezel area and the second bezel area.

[0022] In the first bezel area and / or the second bezel area, a first part of a frame start signal line, k clock signal lines and a shift register unit are arranged in a first direction in sequence, and the shift register unit is closest to the display area.

[0023] A second part of the frame start signal line is located in the third bezel area, and the second part comprises at least part extending in the first direction.

[0024] Optionally, the control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the clock signal line on the substrate and a projection of the shift register unit on the substrate.

[0025] Optionally, the control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the second part on the substrate and a projection of the shift register unit on the substrate.

[0026] Optionally, the display panel further comprises a signal line group, and the signal line group comprises a clock signal line, a reset signal line, a first level signal line and a second level signal line.

[0027] The control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the second part on the substrate and a projection of the signal line group on the substrate.

[0028] Based on the technical scheme of the above-described gate driving circuit, a third aspect of the present application provides a driving method of a gate driving circuit, used for driving the above-described gate driving circuit, and the driving method comprises:

[0029] In the output period of the mth row of the shift register unit: the mth control sub-circuit controls the electrical connection between the input end of the mth row of the shift register unit and the mth clock signal line under the control of the frame start signal line; and / or, the mth control sub-circuit controls the electrical connection between the input end of the mth row of the shift register unit and the frame start signal line under the control of the mth clock signal line.

[0030] Optionally, the mth control sub-circuit comprises: a first control unit and / or a second control unit.

[0031] In the output period of the mth row of the shift register unit:

[0032] The first control unit controls the electrical connection between the input end of the mth row of the shift register unit and the mth clock signal line under the control of the frame start signal line; and / or, the second control unit controls the electrical connection between the input end of the mth row of the shift register unit and the frame start signal line under the control of the mth clock signal line.

[0033] Optionally, the first control unit comprises a first transistor, and the second control unit comprises a second transistor.

[0034] In the output period of the mth row of the shift register unit: the first transistor is turned on, and / or the second transistor is turned on.

[0035] In the technical scheme provided by the present application, the rising edge of the frame start signal transmitted by the frame start signal line is in the same period as the starting rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the k / 2th clock signal line; so that the starting pulses included by the first clock signal line to the k / 2th clock signal line can all be in the valid level period of the frame start signal.

[0036] The mth control sub-circuit is coupled with the input end of the mth row of shift register units, the frame start signal line and the mth clock signal line; the mth row of shift register units can write the frame start signal and output the gate drive signal only during the frame start signal is at the active level and the clock signal transmitted by the mth clock signal line is active. Thus, the mth row of shift register units will not have the problem of the pull-up node being high for a long time due to long-time writing of the frame start signal, avoiding the electrode of the transistor coupled with the pull-up node being in the high-voltage state for a long time, thereby improving the use yield of the transistor and prolonging the service life of the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0038] Figure 1 A circuit structure diagram of the shift register unit provided for the embodiment of the application;

[0039] Figure 2 A layout position schematic diagram of the control sub-circuit provided for the embodiment of the application;

[0040] Figure 3 A drive timing diagram of the gate drive circuit corresponding to the single-side four clock signal lines in the related art;

[0041] Figure 4 A drive timing diagram of the gate drive circuit corresponding to the single-side ten clock signal lines in the related art;

[0042] Figure 5 A circuit structure schematic diagram of the control sub-circuit provided for the embodiment of the application;

[0043] Figure 6 A connection schematic diagram of the five rows of shift register units corresponding to the single-side four clock signal lines provided for the embodiment of the application;

[0044] Figure 7 A drive timing diagram of the gate drive circuit corresponding to the single-side four clock signal lines provided for the embodiment of the application;

[0045] Figure 8 A drive timing diagram of the gate drive circuit corresponding to the single-side ten clock signal lines provided for the embodiment of the application;

[0046] Figure 9 A comparison diagram of the transfer curve of the first reset transistor in the normal shift register unit and the transfer curve of the first reset transistor in the abnormal shift register unit provided for the embodiment of the application. Detailed Implementation

[0047] To further illustrate the gate driving circuit and its driving method, as well as the display panel provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0048] Based on the technical problems existing in the background technology, research has found that:

[0049] In display products using Gate on Array technology, the frame start signal line is directly electrically connected to the input of the first few rows of shift register units.

[0050] like Figure 1 and Figure 3 As shown, taking a single-sided four clock signal line as an example, the input terminals of the first and second row shift register units are both coupled to the frame start signal line. In the shift register unit, the second terminal of the input transistor M1 is coupled to the pull-up node PU. Simultaneously, the pull-up node PU is coupled not only to the first terminal of the first reset transistor M2 but also to the gate of the output transistor M3, providing the turn-on voltage for the output transistor M3. The output terminal of the first row shift register unit, i.e., the second terminal of the output transistor, is coupled to the input terminal of the third row shift register unit, and the output terminal of the second row shift register unit is coupled to the input terminal of the fourth row shift register unit. When the first row shift register unit stops outputting, the first reset transistor M2 in the first row shift register unit discharges the pull-up node PU, and the second reset transistor M4 in the first row shift register unit discharges the output terminal of the first row shift register unit. This process continues, ensuring that each cascaded shift register unit functions normally and guarantees proper image display.

[0051] like Figure 3 As shown, when the pull-up node PU in the first row shift register unit is at a high level, the pull-up node PU in the second row shift register unit is also at a high level. However, when the first row shift register unit is closed, the pull-up node PU in the second row shift register unit remains at a high level. The pull-up node PU in the second row shift register unit remains high for a longer time than the pull-up node PU in the first row shift register unit. Since the drain of the first reset transistor M2 in the second row shift register unit is coupled to the pull-up node PU, the first reset transistor M2 in the second row shift register unit is under the high voltage signal of the pull-up node PU for a longer period of time, making the device more susceptible to damage, greatly reducing the lifespan of the first reset transistor M2, and easily causing related abnormal display. At the same time, as the number of single-sided clock signal lines in the display product increases, the pull-up node PU of the first few rows of shift register units connected to the direct frame start signal line STV remains high for an even longer period of time, making related problems more likely to occur.

[0052] likeFigure 3 As shown, the high voltage of the frame start signal transmitted by the frame start signal line STV keeps for a total time of 3H, and the high voltage of the clock signals transmitted by the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 keeps for a total time of 2H in one period, and the duty cycle is 50%, and the high voltage level of the frame start signal is 2H ahead of the first clock signal. The frame start signal line STV is directly connected to the input end of the first row of shift register units and the input end of the second row of shift register units. Before the high voltage level of the clock signal received by the first row of shift register units arrives, the high voltage of the pull-up node PU1 of the first row of shift register units is lifted for a first time of 2H, and after the high voltage level of the clock signal received by the first row of shift register units arrives, the high voltage of the pull-up node PU1 is lifted for a second time due to the bootstrap capacitor C1, and the duration is also 2H (the high voltage duration of the clock signal), that is, the total high voltage duration of the pull-up node PU1 of the first row of shift register units is 4H.

[0053] Before the high voltage level of the clock signal received by the second row of shift register units arrives, the high voltage of the pull-up node PU2 of the second row of shift register units is lifted for a first time of 3H, and after the high voltage level of the clock signal received by the second row of shift register units arrives, the high voltage of the pull-up node PU is lifted for a second time due to the bootstrap capacitor C1, and the duration is also 2H (the high voltage duration of the clock signal), that is, the total high voltage duration of the pull-up node PU2 of the second row of shift register units is 5H.

[0054] The first row of shift register units and the second row of shift register units only have outputs when the clock signals inputted thereto are high, and thus the output signals (such as Gout1 and Gout2) are the same as the received clock signals, and the total high voltage duration is 2H. The outputs of the first row of shift register units and the second row of shift register units are respectively used as the inputs of the input transistors M1 in the third row of shift register units and the fourth row of shift register units, and when the outputs of the two rows of shift register units are high, the pull-up nodes (such as PU3 and PU4) in the third row of shift register units and the fourth row of shift register units maintain the high voltage for a total time of 2H, and when the clock signals inputted thereto are high, the pull-up nodes maintain the high voltage for a second time of 2H, that is, the total high voltage time of the pull-up node PU3 in the third row of shift register units and the pull-up node PU4 in the fourth row of shift register units is 4H, and the output signals (such as Gout3 and Gout4) of the third row of shift register units and the fourth row of shift register units are the same as those of the previous two rows, and only have a high voltage output for 2H.

[0055] As shown in FIG. 4, the frame start signal line STV is directly connected to the input end of the first row of shift register units and the input end of the second row of shift register units. The high voltage of the clock signals transmitted by the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 keeps for a total time of 2H in one period, and the duty cycle is 50%, and the high voltage level of the frame start signal is 2H ahead of the first clock signal. The frame start signal line STV is directly connected to the input end of the first row of shift register units and the input end of the second row of shift register units. Figure 3As shown, when the clock signal transmitted by the first clock signal line CLK1 coupled to the first row of shift register units is at high level, the clock signal transmitted by the second clock signal line CLK2 coupled to the second row of shift register units is at low level, however, at this time, the pull-up node PU2 in the second row of shift register units is at high level, and until the clock signal transmitted by the second clock signal line CLK2 is at high level, the second row of shift register units starts to work, and during this period of time, the pull-up node PU2 in the second row of shift register units is always at high voltage, that is, the drain of the first reset transistor M2 in the second row of shift register units is at high voltage for 5H, and actually, the time when it is really needed to work is 4H. Similarly, as the number of single-sided clock signal lines increases, the high voltage time of the pull-up node PU in the last row of shift register units directly connected to the start signal line STV is longer than that of the pull-up node PU1 in the first row of shift register units.

[0056] If six clock signal lines are set unilaterally, the pull-up node in the second row of shift register units is at high level for 1H more than that in the first row of shift register units. The pull-up node in the third row of shift register units is at high level for 2H more than that in the first row of shift register units.

[0057] If eight clock signal lines are set unilaterally, the pull-up node in the second row of shift register units is at high level for 1H more than that in the first row of shift register units. The pull-up node in the third row of shift register units is at high level for 2H more than that in the first row of shift register units. The pull-up node in the fourth row of shift register units is at high level for 3H more than that in the first row of shift register units.

[0058] As shown in FIG. 1, the shift register unit 100 includes a start signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a first reset transistor M1, a second reset transistor M2, a first pull-up node PU1, a second pull-up node PU2, a third pull-up node PU3, a fourth pull-up node PU4, a fifth pull-up node PU5, a sixth pull-up node PU6, a seventh pull-up node PU7, an eighth pull-up node PU8, a first shift register unit 101, a second shift register unit 102, a third shift register unit 103, a fourth shift register unit 104, a fifth shift register unit 105, a sixth shift register unit 106, a seventh shift register unit 107, and an eighth shift register unit 108. Figure 4As shown, in the case of setting 10 clock signal lines on one side, the total length of the high level of the frame start signal is 9H, which is 5H earlier than the high level of the first clock signal line CLK1. The first row of the shift register unit includes the pull-up node PU1, which maintains a high level for a total of 10H (5H first high voltage lifting and 5H second high voltage lifting). The pull-up node PU2 in the second row of the shift register unit maintains a high level for a total of 11H. The pull-up node PU3 in the third row of the shift register unit maintains a high level for a total of 12H. The pull-up node PU4 in the fourth row of the shift register unit maintains a high level for a total of 13H. The pull-up node PU5 in the fifth row of the shift register unit maintains a high level for a total of 14H. That is, the high voltage maintenance time of the pull-up node PU of the later rows of the shift register unit directly connected to the frame start signal line STV is 1H, 2H, 3H, and 4H longer than the pull-up node PU1, respectively, and the extra time is in the first high voltage lifting stage of the pull-up node. However, there is no difference in the high voltage time of the output signals of the later rows and the earlier rows, only the difference appears on the frame start signal. It is worth noting that Figure 4 The timing of the clock signal transmitted by the second clock signal line CLK2, the timing of the clock signal transmitted by the third clock signal line CLK3, the timing of the clock signal transmitted by the fourth clock signal line CLK4, and the timing of the clock signal transmitted by the fifth clock signal line CLK5 are also shown in the middle.

[0059] Since the pull-up node PU is coupled to the drain of the first reset transistor M2, the drain of the first reset transistor M2 in the last few rows of the shift register unit directly connected to the frame start signal line STV will maintain a high voltage signal for a longer time. However, the other shift register units of the corresponding row have not been turned on at this stage. Under the condition that the drain maintains a high voltage signal for a long time, the service life of the shift register unit to which the first reset transistor M2 belongs will be reduced, which will cause abnormal display or horizontal lines during the module or reliability test, resulting in yield loss or an increase in new product evaluation period, and seriously affecting the product quality and customer satisfaction.

[0060] Taking a 17.3QHD Oxide display product as an example, the display product has 10 clock signal lines on one side. The display product has a regular horizontal line (NG row: fifth row / tenth row / fifteenth row…) visible at a gray scale. The starting behavior is the fifth row, and the input of the tenth row is the output of the fifth row. The same applies to the fifth row / tenth row / fifteenth row…, which are all caused by the abnormal output of the fifth row. The waveform confirms that the pull-up node PU and the output signal of the fifth row are both multiple outputs (wrong charging), and it is suspected that the abnormal characteristics of the first reset transistor M2 in the shift register unit discharging the pull-up node PU cause the multiple output of the pull-up node PU.

[0061] As Figure 9As shown, in the same display product, the same side OK line shift register unit (L1 curve in the figure) / NG line, i.e. the fifth line shift register unit (L2 curve in the figure), the transfer curve of the first reset transistor M2 is compared, it can be seen that the NG line curve is normal when Vg=-30~2.6V, but during Vg=2.6~30V, the curve is abnormal and there is a mutation and Drop, the Ion of the first reset transistor M2 is far less than that of the OK line, so that the first reset transistor M2 of the NG line (the fifth line) cannot normally open when discharging the pull-up node PU, so that the pull-up node and the output signal appear multiple outputs, and horizontal lines appear. It is worth noting that Vg represents the gate voltage of the first reset transistor M2, and Id represents the current of the first reset transistor M2.

[0062] For a display product with 10 clock signal lines on one side, the input ends of the first line shift register unit, the second line shift register unit, the third line shift register unit, the fourth line shift register unit and the fifth line shift register unit are directly connected to the frame start signal line STV, and the pull-up node PU point of the fifth line shift register unit maintains the highest voltage for the longest time, so the risk is also the highest. At the same time, with the continuous upgrading of product specifications, more and more products with higher resolution and higher refresh rate will appear, and the number of clock signal lines on one side of the product will also increase. The pull-up node PU of the first few line shift register units directly connected to the frame start signal line STV maintains a high voltage for a longer and longer time, and the risk of horizontal lines also increases.

[0063] The above problems are mainly solved from two aspects: 1. Improve the high voltage or large voltage resistance of the shift register unit; 2. Optimize the problem of the frame start signal line STV directly connected to the input end of multiple shift register units from the product design. However, improving the high voltage or large voltage resistance of the shift register unit mainly adjusts the process, improves the interface between the film layers and the film layer defects, but often improves the large voltage resistance of the shift register unit, which is prone to other problems, such as yield or reliability problems, such as film layer breakdown voltage weakening and characteristic curve left shift. With a large number of oxide products about to be mass-produced, optimization from the product design has become the best choice, which optimizes the design level and requires less process margin.

[0064] Please refer to Figure 5 to Figure 8 The embodiment of the present application provides a gate drive circuit, which comprises: n line shift register units, n>4; a frame start signal line, k clock signal lines, k satisfies 4≤k

[0065] The mth control sub-circuit 10 is coupled with the input end IN of the mth row of shift register units, a frame start signal line and the mth clock signal line, for controlling the electrical connection between the input end IN of the mth row of shift register units and the mth clock signal line under the control of the frame start signal line, and / or controlling the electrical connection between the input end IN of the mth row of shift register units and the frame start signal line under the control of the mth clock signal line, 1≤m≤x.

[0066] The mth clock signal line is coupled with the mth row of shift register units, the rising edge of the frame start signal transmitted by the frame start signal line is in the same period as the starting rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the k / 2th clock signal line.

[0067] Illustratively, the gate drive circuit is applied to a display panel, and the display panel comprises a plurality of rows of sub-pixels, and each row of shift register units is coupled with corresponding at least one row of sub-pixels.

[0068] Illustratively, k=4, x=2, and m takes values 1 and 2.

[0069] Illustratively, k=10, x=5, and m takes values 1, 2, 3, 4 and 5.

[0070] It is worth noting that n, k, x and m are positive integers.

[0071] During the output period of the mth row of shift register units, the mth control sub-circuit 10 controls the electrical connection between the input end IN of the mth row of shift register units and the mth clock signal line under the control of the frame start signal line, and / or the mth control sub-circuit 10 controls the electrical connection between the input end IN of the mth row of shift register units and the frame start signal line under the control of the mth clock signal line.

[0072] In one way, during the non-output period of the mth row of shift register units, the mth control sub-circuit 10 controls the electrical connection between the input end IN of the mth row of shift register units and the mth clock signal line under the control of the frame start signal line, and / or the mth control sub-circuit 10 controls the electrical connection between the input end IN of the mth row of shift register units and the frame start signal line under the control of the mth clock signal line.

[0073] In another manner, during the non-output period of the m-th row shift register unit: the m-th control sub-circuit 10, under the control of the frame start signal line, controls the electrical connection between the input terminal IN of the m-th row shift register unit and the m-th clock signal line, but at this time the signal transmitted by the m-th clock signal line is at an inactive level, such as a low level; or, the m-th control sub-circuit 10, under the control of the m-th clock signal line, controls the electrical connection between the input terminal IN of the m-th row shift register unit and the frame start signal line, but at this time the signal transmitted by the frame start signal line is at an inactive level, such as a low level.

[0074] Taking k=4 as an example, the first clock signal line is coupled to the first row of shift register cells, the second clock signal line is coupled to the second row of shift register cells, the third clock signal line is coupled to the third row of shift register cells, and the fourth clock signal line is coupled to the fourth row of shift register cells. The first clock signal line is coupled to the fifth row of shift register cells, the second clock signal line is coupled to the sixth row of shift register cells, and so on.

[0075] For example, the m-th row shift register unit is a shift register unit directly connected to the start-of-frame signal line. The inputs of the (x+1)-th to n-th row shift register units are provided by the outputs of the preceding shift register units.

[0076] For example, the high voltage of both the frame start signal and the clock signal is Vgh, and the low voltage is Vgl.

[0077] It is worth noting that the side of the display panel where the data lines are coupled to the chip is called the DP side, and the side opposite to the DP side is called the DPO side. The m-th row shift register units can be distributed on the DPO side.

[0078] It needs to be explained, such as Figure 5 and Figure 6 As shown in the figure, the frame start signal transmitted by the frame start signal line STV is provided by the driver chip in the display panel. The control sub-circuit 10 finally outputs a new frame start signal STV' to the input terminal IN of the shift register unit.

[0079] As can be seen from the specific structure of the gate driving circuit described above, in the gate driving circuit provided in this embodiment of the invention, by setting the rising edge of the frame start signal transmitted by the frame start signal line to be in the same time period as the rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal to be in the same time period as the falling edge of the first pulse of the clock signal transmitted by the k / 2th clock signal line, the starting pulses included by the first clock signal line to the k / 2th clock signal line can all be in the effective level period of the frame start signal.

[0080] The mth control sub-circuit 10 is coupled with the input end IN of the mth row of shift register units, the frame start signal line and the mth clock signal line respectively; the mth row of shift register units can write the frame start signal and output the gate drive signal only during the period when the frame start signal is at the active level and the clock signal transmitted by the mth clock signal line is active. Thus, the mth row of shift register units will not have the problem of the pull-up node being high for a long time due to the long-time writing of the frame start signal, avoiding the electrodes of the transistors coupled with the pull-up node being in the high-voltage state for a long time, thereby improving the use yield of the transistors and prolonging the service life of the gate drive circuit.

[0081] As shown in Figure 5 and Figure 6 In some embodiments, the mth control sub-circuit 10 includes a first control unit 101 and / or a second control unit 102.

[0082] The control end of the first control unit 101 is coupled with the frame start signal line STV, the input end of the first control unit 101 is coupled with the mth clock signal line CLK, and the output end of the first control unit 101 is coupled with the input end IN of the mth row of shift register units; for controlling the electrical connection between the input end IN of the mth row of shift register units and the mth clock signal line under the control of the frame start signal line.

[0083] The control end of the second control unit 102 is coupled with the mth clock signal line CLK, the input end of the second control unit 102 is coupled with the frame start signal line STV, and the output end of the second control unit 102 is coupled with the input end IN of the mth row of shift register units; for controlling the electrical connection between the input end IN of the mth row of shift register units and the frame start signal line under the control of the mth clock signal line.

[0084] During the output period of the mth row of shift register units:

[0085] The first control unit 101 controls the electrical connection between the input end IN of the mth row of shift register units and the mth clock signal line to be conductive under the control of the frame start signal line; and / or, the second control unit 102 controls the electrical connection between the input end IN of the mth row of shift register units and the frame start signal line to be conductive under the control of the mth clock signal line.

[0086] As shown in Figure 5 and Figure 6As shown, in some embodiments, the first control unit 101 includes a first transistor T1, the gate of the first transistor T1 is coupled to the frame start signal line STV, the first terminal of the first transistor T1 is coupled to the m-th clock signal line CLK, and the second terminal of the first transistor T1 is coupled to the input terminal IN of the m-th row shift register unit.

[0087] In some embodiments, the second control unit 102 includes a second transistor T2, the gate of which is coupled to the m-th clock signal line CLK, the first terminal of which is coupled to the frame start signal line STV, and the second terminal of which is coupled to the input terminal IN of the m-th row shift register unit.

[0088] During the output period of the shift register unit in the m-th row: the first transistor T1 is turned on, and the second transistor T2 is turned on.

[0089] like Figure 1 As shown, in some embodiments, the m-th row shift register unit includes: an input transistor M1, a pull-up node, an output transistor M3, a bootstrap capacitor C1, a first reset transistor M2, and a second reset transistor M4.

[0090] The gate of the input transistor M1 is coupled to the first terminal of the input transistor M1, the first terminal of the input transistor M1 serves as the input terminal IN of the m-th row shift register unit, and the second terminal of the input transistor M1 is coupled to the pull-up node.

[0091] The gate of the output transistor M3 is coupled to the pull-up node PU, the first terminal of the output transistor M3 is coupled to the m-th clock signal line CLK, and the second terminal of the output transistor M3 is coupled to the output terminal Out of the m-th row shift register unit.

[0092] The first end of the bootstrap capacitor C1 is coupled to the pull-up node, and the second end of the bootstrap capacitor C1 is coupled to the output terminal Out of the m-th row shift register unit.

[0093] The gate of the first reset transistor M2 is coupled to the reset signal input terminal Reset, the first terminal of the first reset transistor M2 is coupled to the pull-up node, and the second terminal of the first reset transistor M2 is coupled to the first level signal input terminal Vss.

[0094] The gate of the second reset transistor M4 is coupled to the reset signal input terminal Reset, the first terminal of the second reset transistor M4 is coupled to the output terminal Out of the m-th row shift register unit, and the second terminal of the second reset transistor M4 is coupled to the first level signal input terminal Vss.

[0095] It is worth noting that the shift register unit is not limited to the above structure, but can also include a pull-up unit, a pull-down unit, and a plurality of reset units in the related art.

[0096] In more detail, as shown in Figure 5 and Figure 6 , the gate of the first transistor T1 receives a frame start signal, and the drain receives a clock signal. The gate of the second transistor T2 receives a clock signal, and the drain receives a frame start signal. The source of the first transistor T1 and the second transistor T2 provides an input signal for the input end IN of the shift register unit. For example, when the frame start signal is high and the clock signal is low, the first transistor T1 is open and the second transistor T2 is closed, but the clock signal received by the drain of the first transistor T1 is low, and the first transistor T1 and the second transistor T2 both output low. When the frame start signal and the clock signal are both high, the first transistor T1 and the second transistor T2 are both open, and the first transistor T1 and the second transistor T2 both output high. When the frame start signal is low and the clock signal is high, the first transistor T1 is closed and the second transistor T2 is open, but the drain of the second transistor T2 is low, and the first transistor T1 and the second transistor T2 output low. When the frame start signal and the clock signal are both low, the first transistor T1 and the second transistor T2 are both closed.

[0097] As shown in Figure 5 and Figure 6 , Figure 6 The black dot in the middle indicates that the wire is electrically connected. Figure 6 Taking a product with four clock signal lines on one side as an example, for the first row of shift register units and the second row of shift register units, the frame start signal and the clock signal pass through the first transistor T1 and the second transistor T2 to output a new frame start signal STV' as the input of the input transistor M1, and the clock signal as the drain of the output transistor M3 to ensure the output of the shift register unit. The output of the first row of shift register units and the second row of shift register units can be used as the input of the third row of shift register units and the fourth row of shift register units, respectively, so that the display panel can display normally.

[0098] It is worth noting that the shift register unit is not limited to the above structure, but can also include a pull-up unit, a pull-down unit, and a plurality of reset units in the related art. Figure 6 The cascade mode of five rows of shift register units GOA is shown in , the reset signal input end Reset of the third row of GOA is coupled with the output end of the sixth row of shift register units, and receives the output signal Gout of the sixth row of shift register units. The reset signal input end Reset of the fourth row of GOA receives the output signal Gout of the seventh row of shift register units. The reset signal input end Reset of the fifth row of GOA receives the output signal Gout of the eighth row of shift register units.

[0099] As Figure 7 shown, the frame start signal in the related art is designed as a high level of 3H (such as the related art STV), and the high level of the frame start signal is opened by 2H of the time of the high level of the clock signal transmitted by the first clock signal line CLK1; in the present application, the high level time of the frame start signal remains unchanged compared with the related art, and is 3H (such as the present application STV), but the high level opening timing thereof lags behind the related art by 2H, that is, the high level of the frame start signal is opened at the same time as the high level of the clock signal transmitted by the first clock signal line CLK1; because the high level time of the clock signal transmitted by the first clock signal line CLK1 and the clock signal transmitted by the second clock signal line CLK2 is 2H, and there is an overlap of 1H of the high voltage signal, the high voltage of the clock signal transmitted by the second clock signal line CLK2 ends at the same time as the high voltage of the frame start signal.

[0100] As Figure 7 shown, the signal (such as the present application STV1) received by the input end IN of the first row shift register unit is at a high level only when the first clock signal line CLK1 transmits the clock signal in the first cycle, and is at a low level at other times; the signal (such as the present application STV2) received by the input end IN of the second row shift register unit is at a high level only when the second clock signal line CLK2 transmits the clock signal in the first cycle, and is at a low level at other times. The waveform of the signal received by the input end IN of the first row shift register unit and the waveform of the signal received by the input end IN of the second row shift register unit are at a high voltage only for 2H, that is, the high voltage time of the pull-up node is only 2H (such as the present application PU1 and the present application PU2), which is far lower than the high voltage time of the pull-up node in the first row shift register unit and the second row shift register unit in the related art (such as the related art PU1 and the related art PU2), and the present application embodiment has a pull-up node high voltage time ratio of 50% in the first row shift register unit and a pull-up node high voltage time ratio of 40% in the second row shift register unit, which greatly reduces the load pressure of the first reset transistor M2 and greatly improves the service life thereof.

[0101] Meanwhile, the actual gate drive signal output waveform of the first row shift register unit and the second row shift register unit has no obvious difference from the related art, in addition, the transistor of the input transistor M1 is relatively small, and the Ion level is relatively high, Ion normalization > 10 microamperes, the threshold voltage of the input transistor M1 and the output transistor M3 is very small, only 1V-3V, that is, a very small voltage is needed to open, and the opening and full time is very short, and there is no problem of abnormal waveform output of the gate drive signal caused by insufficient pre-charge time, and the picture can be normally displayed.

[0102] As Figure 8As shown, the frame start signal in the related art is designed as a high level of 9H (such as the related art STV), and the high level of the frame start signal is opened 5H time earlier than the high level of the clock signal provided by the first clock signal line CLK1; in the embodiment of the application, the high level time of the frame start signal is the same as that in the related art, both being 9H (such as the STV of the application), but the high level opening timing thereof lags behind that in the related art by 5H, that is, the high level of the frame start signal is opened at the same time as the high level of the clock signal transmitted by the first clock signal line CLK1; because the timing of the clock signal transmitted by the second clock signal line CLK2 lags behind that of the clock signal transmitted by the first clock signal line by 1H, the timing of the clock signal transmitted by the third clock signal line CLK3 lags behind that of the clock signal transmitted by the second clock signal line CLK2 by 1H, the timing of the clock signal transmitted by the fourth clock signal line CLK4 lags behind that of the clock signal transmitted by the third clock signal line CLK3 by 1H, and the timing of the clock signal transmitted by the fifth clock signal line CLK5 lags behind that of the clock signal transmitted by the first clock signal line CLK1 by 4H, the total high voltage time of the frame start signal (such as the STV of the application) is 9H, so the high voltage of the clock signal transmitted by the fifth clock signal line CLK5 ends at the same time as the high voltage of the frame start signal (such as the STV of the application).

[0103] The waveforms of the input signals received by the first five row shift register units all maintain a high voltage signal for 5H (such as the STV1 to the STV5 of the application), that is, the high voltage signal time of the pull-up node in the first five row shift register units is all 5H (such as the PU1 to the PU5 of the application), which is far lower than the high voltage signal time of the pull-up node in the shift register units in the related art, 10H / 11H / 12H / 13H / 14H, the high voltage time of the pull-up node in the first row shift register unit is only half of the previous one, the high voltage time of the pull-up node in the fifth row shift register unit is only 36% of the previous one, and the high voltage time of the pull-up node in the shift register units of other rows accounts for between 36% and 50%, which greatly reduces the load pressure of the first reset transistor M2 and greatly improves the service life thereof. At the same time, as the number of single-sided clock signal lines increases, the high voltage time of the pull-up node in the embodiment of the application is lower, and the load capacity of the first reset transistor M2 unit is smaller, which reduces the risk of the service life of the shift register unit, improves the product quality and yield, and also enhances the market competitiveness of the product.

[0104] It is worth noting that in the technical solutions provided by the present application, by increasing the control sub-circuit 10, the frame start signal and the clock signal are ingeniously used to control the output of the control sub-circuit 10, and the timing of the frame start signal is adjusted, so that when each row of shift register units starts to work, only the input signal and the pull-up node of the row of shift register units are high, and the input signal and the pull-up node of other rows of shift register units are low, and the high level time of the pull-up node in each row of shift register units in the present application is significantly shortened (36% to 50% before and after) compared with related art, thereby improving the device service life reduction caused by the long high level of the pull-up node, improving product yield and market customer satisfaction, and improving product quality and market competitiveness.

[0105] It should be noted that in the gate drive circuit provided by the embodiment of the present application, the number of the first control unit 101 and the second control unit 102 is not limited, and can be one or more.

[0106] In addition, in the gate drive circuit provided by the embodiment of the present application, the long high voltage of the pull-up node reduces the service life of the first reset transistor M2, but for different product shift register unit architecture models, the pull-up node also serves as the drain of other noise reduction units, so it is not limited to improving the service life of a certain transistor (such as the first reset transistor M2), and the essence is to reduce the high voltage time of the pull-up node, thereby reducing the loss of the shift register unit.

[0107] The embodiment of the present application also provides a display panel comprising the gate drive circuit provided by the above embodiment.

[0108] The display panel can be applied to a display device, and the display device can be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further comprises a flexible circuit board, a printed circuit board, a back plate, etc.

[0109] The gate drive circuit provided by the above embodiment has the following advantages: the rising edge of the frame start signal transmitted by the frame start signal line is in the same period as the initial rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the k / 2th clock signal line; therefore, the initial pulses of the first clock signal line to the k / 2th clock signal line can all be in the active level period of the frame start signal. The input end IN of the mth row of shift register units, the frame start signal line and the mth clock signal line are coupled to the mth control sub-circuit 10; the mth row of shift register units can write the frame start signal and output the gate drive signal only during the period when the frame start signal is in the active level and the clock signal transmitted by the mth clock signal line is active; therefore, the mth row of shift register units will not have the problem of the pull-up node being in the high level for a long time due to the long-time writing of the frame start signal, the electrode of the transistor coupled to the pull-up node is not in the high voltage state for a long time, the yield of the transistor is improved, and the service life of the gate drive circuit is prolonged.

[0110] The display panel provided by the embodiment of the application has the above advantages when the gate drive circuit is included, and details are not repeated here.

[0111] As shown in FIG. 1, Figure 2 In some embodiments, the display panel includes a display area and a peripheral area, the peripheral area includes a first bezel area 21 and a second bezel area arranged oppositely, and a third bezel area 23 located on the same side of the first bezel area 21 and the second bezel area; the display area is located between the first bezel area 21 and the second bezel area.

[0112] In the first bezel area 21 and / or the second bezel area, a first part 31 of the frame start signal line, k clock signal lines and a shift register unit are arranged in a first direction in sequence, and the shift register unit is closest to the display area.

[0113] A second part 32 of the frame start signal line is located in the third bezel area 23, and the second part 32 includes at least part extending in the first direction.

[0114] For example, the peripheral area surrounds the display area, and the peripheral area includes the first bezel area 21, the second bezel area, the third bezel area 23 and a fourth bezel area; the first bezel area 21 includes the left bezel of the display panel, the second bezel area includes the right bezel of the display panel, the third bezel area 23 includes the upper bezel of the display panel, and the fourth bezel includes the lower bezel of the display panel.

[0115] For example, the display panel is provided with a single-sided gate driving circuit or a double-sided gate driving circuit. When a double-sided gate driving circuit is provided, gate driving circuits are provided on both the left and right sides of the display substrate.

[0116] For example, the frame start signal line includes a first portion 31 and a second portion 32 coupled together, at least a portion of the first portion 31 extending along a second direction, and at least a portion of the second portion 32 extending along a first direction, the first direction intersecting the second direction. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction, but is not limited thereto.

[0117] For example, the first portion 31 and the second portion 32 are configured in different layers.

[0118] The above layout method can occupy the least amount of layout space and reduce the difficulty of layout.

[0119] like Figure 2 As shown, in some embodiments, the orthographic projection of the control sub-circuit 10 included in the gate drive circuit on the substrate of the display panel is located between the orthographic projection of the clock signal line on the substrate and the orthographic projection of the shift register unit GOA on the substrate (e.g., region A2).

[0120] There is ample layout space between the clock signal line and the shift register unit GOA, which reduces the layout difficulty of the control sub-circuit 10. Furthermore, the control sub-circuit 10 needs to be coupled to the frame start signal line, the clock signal line, and the shift register unit GOA; the above arrangement facilitates better electrical connection.

[0121] like Figure 2 As shown, in some embodiments, the orthographic projection of the control sub-circuit 10 included in the gate drive circuit on the substrate of the display panel is located between the orthographic projection of the second portion 32 on the substrate and the orthographic projection of the shift register unit GOA on the substrate (e.g., region A3).

[0122] The second part 32 has a large layout space between itself and the shift register unit GOA, and the above arrangement can reduce the layout difficulty of the control sub-circuit 10. Moreover, the control sub-circuit 10 needs to be coupled to the frame start signal line, the clock signal line and the shift register unit GOA, and the above arrangement is conducive to better implementation of electrical connections.

[0123] like Figure 2 As shown, in some embodiments, the display panel further includes a signal line group 40, which includes: a clock signal line, a reset signal line, a first level signal line, and a second level signal line;

[0124] The control sub-circuit 10 included in the gate driving circuit has a normal projection on a substrate of the display panel, which is located between a normal projection of the second part 32 on the substrate and a normal projection of the signal line group 40 on the substrate (such as an A1 region).

[0125] Exemplarily, the first level signal line includes a VGH line, and the second level signal line includes a VGL line, but is not limited thereto.

[0126] The second part 32 and the signal line group 40 have a large layout space, and the above arrangement can reduce the layout difficulty of the control sub-circuit 10. Moreover, the control sub-circuit 10 needs to be coupled with a frame start signal line, a clock signal line and a shift register unit, and the above arrangement is conducive to better electrical connection.

[0127] In the above display panel, the layout of the control sub-circuit 10 utilizes the existing layout space and does not affect the frame of the display panel.

[0128] The embodiment of the present application also provides a driving method of a gate driving circuit, which is used for driving the above-mentioned gate driving circuit, and the driving method comprises the following steps:

[0129] In the output period of the mth row of shift register units: the mth control sub-circuit controls the electrical connection between the input end of the mth row of shift register units and the mth clock signal line under the control of the frame start signal line; and / or the mth control sub-circuit controls the electrical connection between the input end of the mth row of shift register units and the frame start signal line under the control of the mth clock signal line.

[0130] The driving method provided by the embodiment of the present application is used for driving the above-mentioned gate driving circuit, and the mth row of shift register units can write the frame start signal and output the gate driving signal only during the period when the frame start signal is at an effective level and the clock signal transmitted by the mth clock signal line is effective. In this way, the mth row of shift register units does not have the problem of the pull-up node being at a high level for a long time due to long-time writing of the frame start signal, the electrode of the transistor coupled with the pull-up node is at a high voltage state for a long time, and thus the use yield of the transistor is improved, and the service life of the gate driving circuit is prolonged.

[0131] In some embodiments, the mth control sub-circuit comprises a first control unit and / or a second control unit.

[0132] In the output period of the mth row of shift register units:

[0133] The first control unit controls, under the control of the frame start signal line, to turn on the electrical connection between the input end of the mth row of shift register units and the mth clock signal line; and / or, the second control unit controls, under the control of the mth clock signal line, to turn on the electrical connection between the input end of the mth row of shift register units and the frame start signal line.

[0134] In some embodiments, the first control unit comprises a first transistor, and the second control unit comprises a second transistor.

[0135] In the output period of the mth row of shift register units: the first transistor is turned on, and / or the second transistor is turned on.

[0136] It should be noted that the signal line extending in a certain direction refers to that the signal line comprises a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0137] In the method embodiments of the present application, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative efforts are within the protection scope of the present application.

[0138] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the differences from other embodiments. Especially, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the product embodiments.

[0139] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect", "couple", or "link" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0140] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be directly on or under the other element, or intervening elements can also be present.

[0141] In the description above, specific features, structures, materials or characteristics can be combined in any one or more examples or embodiments in a suitable manner.

[0142] The above description is merely illustrative of the application and not restrictive. Since the application can be modified in various ways, it should be understood that the application should be construed in accordance with the scope of the claims rather than the scope of the specification.

Claims

1. A gate driving circuit, characterized in that, The application relates to a shift register unit, and comprises the following: n rows of shift register units, n>4; a frame start signal line; k clock signal lines, k satisfying 4<=k<n, and k being an even number; and x control sub-circuits, x=k / 2; the mth control sub-circuit is coupled with the input end of the mth row of shift register units, the frame start signal line and the mth clock signal line, and is used for controlling the electrical connection between the input end of the mth row of shift register units and the mth clock signal line to be turned on or turned off under the control of the frame start signal line; the electrical connection between the input end of the mth row of shift register units and the frame start signal line is controlled to be turned on or turned off under the control of the mth clock signal line; 1<=m<=x; the mth clock signal line is coupled with the mth row of shift register units; the rising edge of the frame start signal transmitted by the frame start signal line is in the same period as the starting rising edge of the clock signal transmitted by the first clock signal line; and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the k / 2th clock signal line. The mth control sub-circuit comprises a first control unit and a second control unit; the control end of the first control unit is coupled with the frame start signal line; the input end of the first control unit is coupled with the mth clock signal line; the output end of the first control unit is coupled with the input end of the mth row of shift register units; and the electrical connection between the input end of the mth row of shift register units and the mth clock signal line is controlled to be turned on or turned off under the control of the frame start signal line; the control end of the second control unit is coupled with the mth clock signal line; the input end of the second control unit is coupled with the frame start signal line; the output end of the second control unit is coupled with the input end of the mth row of shift register units; and the electrical connection between the input end of the mth row of shift register units and the frame start signal line is controlled to be turned on or turned off under the control of the mth clock signal line. The first control unit comprises a first transistor; the gate of the first transistor is coupled with the frame start signal line; the first pole of the first transistor is coupled with the mth clock signal line; and the second pole of the first transistor is coupled with the input end of the mth row of shift register units. The second control unit comprises a second transistor; the gate of the second transistor is coupled with the mth clock signal line; the first pole of the second transistor is coupled with the frame start signal line; and the second pole of the second transistor is coupled with the input end of the mth row of shift register units. The mth row of shift register units comprises an input transistor, a pull-up node, an output transistor, a bootstrap capacitor, a first reset transistor and a second reset transistor; the gate of the input transistor is coupled with the first pole of the input transistor; the first pole of the input transistor serves as the input end of the mth row of shift register units; and the second pole of the input transistor is coupled with the pull-up node. ​ 2. The gate drive circuit according to claim 1, characterized by ​ ​ ​ 3. The gate drive circuit according to claim 2, characterized by ​ 4. The gate drive circuit according to claim 2, characterized by ​ 5. The gate drive circuit according to any one of claims 1 to 4, characterized by ​ ​ A gate of the output transistor is coupled with the pull-up node, a first pole of the output transistor is coupled with the mth clock signal line, and a second pole of the output transistor is coupled with an output end of the mth shift register unit; A first end of the bootstrap capacitor is coupled with the pull-up node, and a second end of the bootstrap capacitor is coupled with the output end of the mth shift register unit; A gate of the first reset transistor is coupled with a reset signal input end, a first pole of the first reset transistor is coupled with the pull-up node, and a second pole of the first reset transistor is coupled with a first level signal input end; A gate of the second reset transistor is coupled with the reset signal input end, a first pole of the second reset transistor is coupled with the output end of the mth shift register unit, and a second pole of the second reset transistor is coupled with the first level signal input end.

6. A display panel, characterized by, The gate driving circuit comprises the gate driving circuit according to any one of claims 1 to 5.

7. The display panel of claim 6, wherein, The display panel comprises a display area and a peripheral area, the peripheral area comprises a first frame area and a second frame area arranged oppositely, and a third frame area located on the same side of the first frame area and the second frame area; the display area is located between the first frame area and the second frame area; In the first frame area and / or the second frame area, a first part of a frame start signal line, k clock signal lines and a shift register unit are arranged in a first direction in sequence, and the shift register unit is closest to the display area; A second part of the frame start signal line is located in the third frame area, and the second part comprises at least part extending in the first direction.

8. The display panel of claim 7, wherein, The control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the clock signal line on the substrate and a projection of the shift register unit on the substrate.

9. The display panel of claim 7, wherein, The control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the second part on the substrate and a projection of the shift register unit on the substrate.

10. The display panel of claim 7, wherein, The display panel further comprises a signal line group, and the signal line group comprises clock signal lines, reset signal lines, first level signal lines and second level signal lines. The control sub-circuit included in the gate driving circuit has a projection on a substrate of the display panel, and the projection is located between a projection of the second part on the substrate and a projection of the signal line group on the substrate.

11. A driving method of a gate driving circuit, characterized by, The driving method is used for driving the gate driving circuit according to any one of claims 1 to 5, and the driving method comprises: In an output period of the mth shift register unit: the mth control sub-circuit controls to turn on an electrical connection between an input end of the mth shift register unit and the mth clock signal line under control of a frame start signal line; and the mth control sub-circuit controls to turn on an electrical connection between the input end of the mth shift register unit and the frame start signal line under control of the mth clock signal line.

12. The driving method of the gate driving circuit according to claim 11, wherein The mth control sub-circuit comprises a first control unit and a second control unit; In the output period of the mth row of shift register units: The first control unit controls the electrical connection between the input end of the mth row of shift register units and the mth clock signal line to be conducted under the control of the frame start signal line; the second control unit controls the electrical connection between the input end of the mth row of shift register units and the frame start signal line to be conducted under the control of the mth clock signal line.

13. The driving method of the gate driving circuit according to claim 12, wherein The first control unit comprises a first transistor, and the second control unit comprises a second transistor; In the output period of the mth row of shift register units: the first transistor is conducted, and the second transistor is conducted.

Images