Memory detection method

Abstract

The present application provides a memory detection method, which relates to the field of semiconductor technology. The memory detection method includes writing first storage data into a memory cell connected to a first word line and writing second storage data into a memory cell connected to a second word line, wherein the first storage data is different from the second storage data; activating the first word line and keeping it on for a first preset time period before shutting it off, wherein the first preset time period is greater than a first time threshold. The present application increases the on-time of the first word line to increase the time and amount of charge leaked from the first word line to the second word line. Subsequently, by comparing actual storage data with the first storage data, it is accurately determined whether there is leakage between the first and second word lines, thereby ensuring the accuracy of leakage detection between adjacent word lines and thereby improving the yield of the memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for detecting a memory. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory (DRAM) consists of multiple repetitive memory cells. Each memory cell typically includes a capacitor structure and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to the capacitor structure. A voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor structure through the bit line or write data to the capacitor structure for storage.

[0004] As dynamic random access memory (DRAM) develops toward miniaturization and integration, the distance between adjacent storage cells decreases, which in turn causes leakage between adjacent word lines. However, there is currently no detection method to accurately detect whether there is leakage between adjacent word lines, resulting in a low yield of dynamic random access memory. Summary of the Invention

[0005] In view of the above problems, an embodiment of the present application provides a memory detection method for testing whether adjacent word lines have leakage, thereby improving the yield of the memory.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] An embodiment of the present application provides a memory detection method. Among any two adjacent word lines, one of the word lines is a first word line and the other word line is a second word line. The detection method includes:

[0008] Writing first storage data into a memory cell connected to the first word line, and writing second storage data into a memory cell connected to the second word line, wherein the first storage data is different from the second storage data;

[0009] activating the first word line to turn on a transistor of a memory cell connected to the first word line, and keeping the transistor on for a first preset time period before turning it off, where the first preset time period is greater than a first time threshold;

[0010] Acquire actual storage data of a memory cell connected to the second word line, and determine whether the actual storage data is the same as the first storage data.

[0011] In some embodiments, the step of starting the first word line includes: applying a first voltage to the first word line to start the transistor connected to the first word line, wherein the first voltage is greater than a turn-on voltage of the first word line.

[0012] In some embodiments, turning on the second word line and starting the first word line further includes applying a second voltage to the first word line to turn off the transistor connected to the first word line, wherein the second voltage is greater than a turn-off voltage of the first word line.

[0013] In some embodiments, the memory further includes a plurality of reference bit lines, the plurality of reference bit lines being arranged in a one-to-one correspondence with the plurality of bit lines, and after the step of activating the first word line and before the step of activating the second word line, the detection method further includes:

[0014] One of the bit lines corresponding to the first word line and the reference bit line corresponding to the bit line are precharged so that a potential of the precharged bit line is not equal to a potential of the reference bit line.

[0015] In some embodiments, the equalization circuit of the memory is started, and the bit line and the reference bit line corresponding to the bit line are in a precharge state within a second preset time period, and the second preset time period is less than a second time threshold.

[0016] In some embodiments, the equalization circuit includes a first transistor, a second transistor, and a third transistor disposed between the bit line and the reference bit line;

[0017] The gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are connected;

[0018] The source of the first transistor is connected to the bit line, and the drain of the first transistor is connected to the reference bit line;

[0019] The source of the second transistor is connected to the bit line, and the drain of the second transistor is connected to the source of the third transistor;

[0020] A drain of the third transistor is connected to the reference bit line.

[0021] In some embodiments, the balancing circuit further includes a first signal line, which is respectively connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor, and the first signal line is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit.

[0022] In some embodiments, the drain of the second transistor and the source of the third transistor are further connected to a second signal line, and the second signal line is used to provide a reset voltage to the bit line and the reference bit line.

[0023] In some embodiments, the first stored data is "1" and the second stored data is "0";

[0024] If actual storage data of a memory cell on one of the bit lines connected to the second word line is "1", it is proved that leakage occurs between the first word line and the second word line.

[0025] In some embodiments, the step of obtaining actual storage data of a memory cell connected to the second word line includes:

[0026] The memory includes a read circuit and a peripheral circuit. The read circuit is connected to the bit line. The read circuit is activated to transfer storage data connected to the first word line to the peripheral circuit.

[0027] In some embodiments, the read circuit includes: a read transistor, a gate of the read transistor being connected to a third signal line, the third signal line being used to control the opening or closing of the read transistor;

[0028] A source of the read transistor is connected to the bit line, and a drain of the read transistor is connected to the peripheral circuit.

[0029] In some embodiments, a fourth signal line is provided between the drain of the read transistor and the peripheral circuit.

[0030] In some embodiments, the memory further includes a sensitive amplifier, which is arranged between the bit line and the reference bit line corresponding to the bit line, and is used to amplify the voltage difference between the bit line and the reference bit line corresponding to the bit line.

[0031] In some embodiments, the sense amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0032] A gate of the fourth transistor is connected to the reference bit line, and a source of the fourth transistor is connected to the bit line;

[0033] The gate of the fifth transistor is connected to the bit line, the source of the fifth transistor is connected to the reference bit line, the drain of the fifth transistor is connected to the drain of the fourth transistor, and is connected to a first power line, wherein the first power line is used to provide a low potential voltage;

[0034] The gate of the sixth transistor is connected to the reference bit line, and the source of the sixth transistor is connected to the bit line;

[0035] The gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor and to a second power line, and the second power line is used to provide a high potential voltage.

[0036] In some embodiments, the fourth transistor and the fifth transistor are both N-type transistors, and the sixth transistor and the seventh transistor are both P-type transistors.

[0037] In the memory detection method provided in the embodiment of the present application, the turn-on time of the first word line is increased to increase the time during which the current leaks from the first word line to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and allowing the charge to change the actual storage data of the memory cell connected to the second word line. Subsequently, by comparing the actual storage data with the first storage data, it is accurately determined whether there is leakage between the first word line and the second word line, thereby ensuring the accuracy of leakage detection between adjacent word lines and thereby improving the yield of the memory.

[0038] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the memory detection method provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 A schematic diagram of the memory layout provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of a storage unit of a memory provided in an embodiment of the present application;

[0042] Figure 3 A process flow chart of a memory detection method provided in an embodiment of the present application;

[0043] Figure 4A schematic diagram of writing first stored data and second stored data in a memory detection method provided in an embodiment of the present application;

[0044] Figure 5 This is a timing diagram of the operation of the first word line in the memory provided by an embodiment of the present application;

[0045] Figure 6 A circuit diagram of a memory provided in an embodiment of the present application;

[0046] Figure 7 This is a timing diagram of the operation of the second word line of the memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] As described in the background art, there is a problem of leakage current between adjacent word lines of a dynamic random access memory, but the detection method in the related art cannot accurately detect whether there is leakage between adjacent word lines. The inventors have found that the reason for this problem is that, among two adjacent word lines, if the current leaked from one word line to the other word line is not sufficient to change the storage data of the memory cell connected to the other word line, then when the data of the memory cell connected to the other word line is subsequently read, the data will be the same as the theoretical storage data, making it difficult to determine whether there is leakage between adjacent word lines.

[0048] In response to the above-mentioned technical problems, in an embodiment of the present application, the turn-on time of the first word line is increased to increase the time for the current to leak from the first word line to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and allowing the charge to change the actual storage data of the storage unit connected to the second word line. Afterwards, by comparing the actual storage data with the first storage data, it is accurately determined whether there is leakage between the first word line and the second word line, thereby ensuring the accuracy of leakage detection between adjacent word lines, and thereby improving the yield of the memory.

[0049] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0050] Figure 1 A schematic diagram of the memory layout provided in an embodiment of the present application; Figure 2 A schematic diagram of a storage unit of a memory provided in an embodiment of the present application; Figure 3A process flow chart of a memory detection method provided in an embodiment of the present application; Figure 4 A schematic diagram of writing first stored data and second stored data in a memory detection method provided in an embodiment of the present application; Figure 5 This is a timing diagram of the operation of the first word line in the memory provided by an embodiment of the present application; Figure 6 A circuit diagram of a memory provided in an embodiment of the present application; Figure 7 This is a timing diagram of the operation of the second word line of the memory provided in an embodiment of the present application.

[0051] The following will be combined Figures 1 to 7 The memory detection method is described in detail.

[0052] The memory detection method provided in an embodiment of the present application is used to detect whether there is leakage between adjacent word lines of the memory, wherein the memory includes multiple bit lines (BL), multiple word lines (WL), and multiple memory cells 10, wherein each memory cell 10 is connected to a corresponding word line WL and a bit line BL.

[0053] like Figure 1 As shown, the plurality of bit lines BL are distributed in rows, and the plurality of bit lines are divided into 128 bit line groups, each of which has 8 bit lines BL. For the convenience of the following description, the bit lines in each bit line group may be denoted as BL0, BL1, BL2...BL7.

[0054] The multiple word lines WL are distributed in columns and divided into 128 word line groups. Each word line group has 8 word lines WL. For the convenience of the following description, the bit lines in each bit line group may be recorded as WL0, WL1, WL2...WL7.

[0055] Multiple memory cells 10 are distributed in a matrix, wherein the memory cells 10 in the first column are all connected to the word line WL0, the memory cells 10 in the second column are all connected to the word line WL1, and so on, the memory cells 10 in the eighth column are all connected to the word line WL7; the memory cells 10 in the first row are all connected to the bit line BL0, the memory cells 10 in the second row are all connected to the bit line BL1, and so on, the memory cells 10 in the eighth row are all connected to the bit line BL7, so that each memory cell 10 is connected to a word line WL and a bit line BL.

[0056] Among them, such as Figure 2As shown, each memory cell 10 includes a transistor 12 and a capacitor 11, the gate of the transistor 12 is connected to the word line WL, the source of the transistor 12 is connected to the bit line BL, and the drain of the transistor 12 is connected to the capacitor 11. It should be noted that the source of the transistor 12 can also be connected to the capacitor 11, and accordingly, the drain of the transistor 12 is connected to the bit line BL.

[0057] In order to facilitate the description of the memory detection method, it is recommended to define one of the two adjacent word lines as the first word line and the other word line as the second word line. For example, Figure 1 As shown, from left to right, the first word line WL0 can be defined as a first word line, and the second word line WL1 can be defined as a second word line.

[0058] like Figure 3 As shown, the memory detection method includes the following steps:

[0059] Step S100 : writing first storage data into a memory cell connected to a first word line, and writing second storage data into a memory cell connected to a second word line, wherein the first storage data is different from the second storage data.

[0060] For example, Figure 4 As shown, the memory cell 10 is first initialized to activate the memory cell 10, and then a write operation is performed, so that each memory cell 10 connected to the first word line WL0 is written with the first storage data, and each memory cell 10 connected to the second word line WL1 is written with the second storage data. The first storage data is different from the second storage data. For example, when the first storage data is "1", the second storage data is "0"; for another example, when the first storage data is "0", the second storage data is "1".

[0061] In order to facilitate the description of the technical solution of the present application, the following description is given as an example in which the first stored data is "1", the second stored data is "0", and the first bit line BL0 is used to read the data of the storage unit 10 connected thereto.

[0062] Step S200: Start the first word line to turn on the transistor of the memory cell connected to the first word line, and keep it on for a first preset time period and then turn it off. The first preset time period is greater than a first time threshold. The first time threshold is the timing parameter tRAS (Row Address Strobe Time, tRAS for short). The timing parameter tRAS refers to the row activity time, which is actually the entire time from the activation of addressing (ACT for short) to the completion of reading after a row address precharge command (Precharge, PRE for short).

[0063] Exemplarily, in this step, a high level is first written to the first word line WL0, so that the first word line WL0 is in an on state and is kept turned off after a first preset time period. When the first word line WL0 is in an on state, the first word line WL0 applies a high level to the gate of the transistor 12 of the memory cell 10 connected thereto, so that the source and drain of the transistor 12 are connected, thereby enabling the data in the capacitor 11 in the memory cell 10 to be transferred to the bit line BL0.

[0064] It should be noted that when the first word line WL0 is turned on, no read operation is performed on the memory cell 10 connected to the first word line WL0 , and the first word line WL0 is simply turned on for the first preset time period.

[0065] Step S300: Turn on the second word line.

[0066] For example, after the first word line WL0 is turned off, a high level is written to the second word line WL1 so that the second word line WL1 is turned on. At this time, the data on the storage unit 10 connected to the second word line WL1 is transferred to BL0.

[0067] Step S400: obtaining actual storage data of a memory cell connected to the second word line. If the actual storage data is the same as the first storage data, it indicates that leakage occurs between the first word line and the second word line.

[0068] For example, if the first storage data is "1" and the second storage data is "0", if the actual storage data of the memory cell 10 connected to the second word line WL1 is "1", it is proved that leakage occurs between the first word line WL0 and the second word line WL1.

[0069] When leakage occurs on the first word line WL0, the charge on the memory cell 10 connected to the first word line WL0 is transferred to the bit line corresponding to the memory cell. For example, the charge on the memory cell 10 connected to the first word line WL0 is transferred to the bit line BL0, so that a certain amount of charge exists on the bit line. Since the first word line WL0 and the second word line WL1 share the same bit line BL0, after the first word line WL0 is closed, the second word line WL1 is opened, and the actual storage data of the memory cell 10 connected to the second word line WL1 is read through the bit line BL0, the potential of the bit line BL0 is high. Compared with the reference bit line / BL, the potential of the bit line BL0 increases by ΔV. After amplification by the sense amplifier, the actual storage data read is "1", which is opposite to the second storage data. That is, it proves that leakage occurs between the first word line WL0 and the second word line WL1.

[0070] This embodiment increases the turn-on time of the first word line to increase the time for leakage current from the first word line to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and allowing this charge to change the actual storage data of the memory cell connected to the second word line. Subsequently, by comparing the actual storage data with the first storage data, it is accurately determined whether there is leakage between the first word line and the second word line, thereby ensuring the accuracy of leakage detection between adjacent word lines and thereby improving the yield of the memory.

[0071] In the present application, the time during which the current leaks from the first word line WL0 to the second word line WL1 can be increased by the following two implementation methods.

[0072] In an optional embodiment, the step of starting the first word line includes: applying a first voltage to the first word line to start a transistor connected to the first word line, wherein the first voltage is greater than a turn-on voltage of the first word line.

[0073] The transistor 11 generally has a threshold voltage. For example, the threshold voltage of an NMOS transistor is 0.7V. When the voltage applied to the gate of the NMOS transistor is greater than the threshold voltage of the NMOS transistor, the NMOS transistor is turned on.

[0074] The word line WL also usually has peak voltages Vpp and Vkk. When the voltage applied to the word line WL is greater than Vpp, the word line WL will be selected and turned on. Therefore, the voltage Vpp can be called the turn-on voltage of the word line WL, where the value of Vpp is around 3V; when the voltage applied to the word line is less than Vkk, the word line WL will be turned off. Therefore, the voltage Vkk can be called the turn-off voltage of the word line WL.

[0075] like Figure 5 As shown, when the first voltage applied to the first word line WL0 is greater than the turn-on voltage of the first word line WL0, the voltage applied to the gate of the transistor 12 by the first word line WL0 is greater than the threshold voltage of the transistor 12, thereby increasing the degree of opening of the transistor 12, so as to increase the amount of charge leaked from the capacitor 11 to the bit line BL connected to the memory cell 10, so that the potential of the bit line BL is greater than the potential on the reference bit line / BL.

[0076] When the second word line WL1 is to be opened, since the second word line WL1 and the first word line W1 share a set of bit lines and reference bit lines, when reading the data of the memory cell connected to the second word line WL1, the potential of the bit line BL is still greater than the potential on the reference bit line / BL. Therefore, after the potential difference between the bit line BL and the reference bit line / BL is amplified by the sense amplifier, the actual storage data of the memory cell 10 connected to the second word line WL1 that is read is "1", which is opposite to the second storage data "0" of the memory cell 10, thereby proving that leakage occurs between the first word line WL0 and the second word line WL1.

[0077] In another optional embodiment, the step of starting the first word line WL0 further includes applying a second voltage to the first word line WL0 to turn off the transistor 12 connected to the first word line WL0, wherein the second voltage is greater than the turn-off voltage of the first word line WL0.

[0078] When the second voltage applied to the first word line WL0 is greater than the shutdown voltage, the degree of shutdown of the transistor 12 is weakened, causing the capacitor 11 to leak current to the bit line BL connected to the memory cell 10, thereby causing the charge of the memory cell connected to the first word line WL0 to still be transferred to the bit line BL, so that the potential of the bit line BL is greater than the potential on the reference bit line / BL.

[0079] When the second word line WL1 is to be opened, since the second word line WL1 and the first word line WL0 share a set of bit lines and reference bit lines, when reading the data of the memory cell connected to the second word line WL1, the potential of the bit line BL is still greater than the potential on the reference bit line / BL. Therefore, after the potential difference between the bit line BL and the reference bit line / BL is amplified by the sense amplifier, the actual storage data of the memory cell 10 connected to the second word line WL1 that is read is "1", which is opposite to the second storage data "0" of the memory cell 10, thereby proving that leakage occurs between the first word line WL0 and the second word line WL1.

[0080] It should be noted that after the memory structure is prepared, the feasibility of the memory needs to be tested (Design for Test, abbreviated as DFT). Therefore, a test circuit will be set up in the peripheral circuit area of ​​the memory. During the actual test process, the test circuit can be started and used to apply the first voltage and the second voltage to the first word line WL0 and the second word line WL1 respectively.

[0081] In some embodiments, the memory further includes a plurality of reference bit lines, and the plurality of reference bit lines are arranged in a one-to-one correspondence with the bit lines, that is, one bit line corresponds to one reference bit line. For example, referring to Figure 1The memory has multiple bit line groups, each of which has 8 bit lines BL. When reading the data stored on one of the bit lines BL, the bit line BL adjacent to the bit line BL can be used as a reference bit line / BL, and the voltage difference between the bit line BL and the reference bit line / BL can be used to obtain the data stored on one of the bit lines BL.

[0082] For example, when data in the first row of memory cells 10 need to be read, the first bit line BL0 can be used to read data in the memory cells 10 connected thereto. At this time, the second bit line BL1 can be used as a reference bit line / BL.

[0083] For another example, when data in the second row of memory cells 10 is needed, the second bit line BL1 can be used to read the data of the memory cells 10 connected thereto. At this time, the first bit line BL0 or the third bit line BL2 can be used as a reference bit line.

[0084] During a normal read operation, after the storage data of the memory cell 10 connected to the first word line WL0 is read, the potentials on the bit line BL and the reference bit line / BL corresponding to the first word line WL0 need to be precharged so that the potentials on the bit line BL and the reference bit line / BL are restored to the same value, so that when the second word line WL1 is turned on, the storage data of the memory cell 10 connected to the second word line WL1 can be continued to be read using the bit line BL and the reference bit line / BL.

[0085] Based on the above theory, in this embodiment, after the step of starting the first word line and before the step of opening the second word line, the memory detection method further includes:

[0086] One of the bit lines corresponding to the first word line and a reference bit line corresponding to the bit line are precharged so that a potential of the precharged bit line is not equal to a potential of the reference bit line.

[0087] For example, Figure 1 and Figure 4 As shown, there are 8 bit lines BL corresponding to the first word line WL0, namely BL0 to BL7. One of the bit lines BL corresponding to the first word line WL0 can be understood as any one of the 8 bit lines, for example, the first bit line BL0. At the same time, the reference bit line corresponding to the bit line can be understood as the second bit line BL1.

[0088] After the first word line WL0 is turned on, since the first storage data on the memory cell 10 connected to the first word line WL0 is "1", at this time, the first storage data "1" is transmitted to the bit line BL, so that the data on the memory cell 10 and the bit line BL enter a charge sharing stage, making the potential on the bit line BL greater than the potential on the reference bit line / BL.

[0089] Continue to refer Figure 5 After the first word line WL0 is turned off, in order to ensure the accuracy of reading the data of the memory cell 10 connected to the second word line WL1, it is usually necessary to precharge the bit line BL and the reference bit line / BL so that the potentials of the bit line BL and the reference bit line / BL are restored to the same value. However, in this embodiment, by making the potential of the precharged bit line BL unequal to the potential of the reference bit line / BL, the potential on the bit line BL is greater than the potential on the reference bit line / BL. When the second word line WL1 is turned on, although the second storage data "0" of the memory cell 10 connected to the second word line WL1 lowers the potential of the bit line BL, the potential on the bit line BL is still greater than the potential on the reference bit line / BL, causing the potential on the bit line BL to increase by ΔV. In this way, after the sense amplifier is subsequently used to amplify ΔV, the read data is "1", ensuring that the current leakage problem between the first word line WL0 and the second word line WL1 can be accurately detected.

[0090] In some embodiments, as Figure 6 As shown, the memory includes an equalization circuit BLEQ. When the bit line BL and the reference bit line / BL need to be reset, the equalization circuit BLEQ of the memory can be started, and the bit line BL and the reference bit line / BL corresponding to the bit line BL are in a precharge state for a second preset time period, where the second preset time period is less than a second time threshold. The second time threshold is the time taken for the potential of the bit line and the potential of the reference bit line to reach equal potential after precharging. That is, the second time threshold is the timing parameter tRP (full name: Row Precharge Time, abbreviated as tRP). tRP is the time between the precharge command (PRE) and the activate command (ACT) of the next word line in the DRAM, and is used to characterize the speed at which the DRAM array recovers to the precharge state, especially the time required for the bit lines in the array to charge from a high level or a low level to an intermediate potential.

[0091] If the tRP time is shortened, the potential on the bit line BL will not be restored to the intermediate potential V when the second bit line WL1 starts the activation command. BLE , so that the potential on the bit line BL is still greater than the reference bit line / BL, resulting in the sense amplifier SA giving an erroneous data result when reading data of the memory cell 10 connected to the second bit line WL1.

[0092] For example, Figure 6 As shown, the equalizer circuit BLEQ includes a first transistor P1, a second transistor P2, and a third transistor P3 disposed between the bit line BL and the reference bit line / BL.

[0093] The gates of the first transistor P1, the second transistor P2, and the third transistor P3 are connected and connected to the first signal line 20. The first signal line 20 is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit. In other words, the first signal line 20 is used to provide a high level or a low level to the gates of the first transistor P1, the second transistor P2, and the third transistor P3 to turn on or off the above-mentioned transistors.

[0094] A source of the first transistor P1 is connected to the bit line BL, and a drain of the first transistor P1 is connected to the reference bit line / BL.

[0095] A source of the second transistor P2 is connected to the bit line BL, and a drain of the second transistor P2 is connected to a source of the third transistor P3.

[0096] The drain of the third transistor P3 is connected to the reference bit line / BL. The drain of the second transistor P2 and the source of the third transistor P3 are also connected to the second signal line 30. The second signal line 30 is used to provide a reset voltage to the bit line BL and the reference bit line / BL. The second signal line 30 is connected to the peripheral circuit and is used to provide an intermediate voltage V to the bit line BL and the reference bit line / BL. BLE .

[0097] In some embodiments, the step of obtaining actual storage data of a memory cell connected to the second word line further includes:

[0098] like Figure 6 As shown, the memory includes a read circuit and a peripheral circuit (not shown in the figure), the read circuit is connected to the bit line, the read circuit is started to transfer the storage data of the memory cell connected to the first word line to the peripheral circuit, and the storage data of the memory cell is obtained using the peripheral circuit.

[0099] Exemplarily, the reading circuit includes: a reading transistor YSW, the gate of the reading transistor YSW is connected to the third signal line 40, and the third signal line 40 is used to control the opening or closing of the reading transistor YSW; the source of the reading transistor YSW is connected to the bit line BL, and the drain of the reading transistor YSW is connected to the peripheral circuit, wherein a fourth signal line 50 is arranged between the drain of the reading transistor YSW and the peripheral circuit.

[0100] When the potential of the third signal line 40 is at a high level, the read transistor YSW is turned on, and the source and drain of the read transistor YSW are connected, so that the potential on the bit line BL is transmitted to the peripheral circuit through the fourth signal line 50, and then the potential on the bit line BL is read using the peripheral circuit.

[0101] In some embodiments, in order to improve the accuracy of reading data from the memory, a sensitive amplifier SA is usually provided in the memory, wherein the sensitive amplifier SA is provided between the bit line BL and the reference bit line / BL corresponding to the bit line BL, one end of the sensitive amplifier SA is connected to the bit line BL, and the other end is connected to the reference bit line / BL, and is used to amplify the voltage difference between the bit line BL and the reference bit line / BL corresponding to the bit line BL.

[0102] Exemplarily, the sense amplifier SA includes a fourth transistor P4 , a fifth transistor P5 , a sixth transistor P6 , and a seventh transistor P7 .

[0103] A gate of the fourth transistor P4 is connected to the reference bit line / BL, and a source of the fourth transistor P4 is connected to the bit line BL.

[0104] The gate of the fifth transistor P5 is connected to the bit line BL, the source of the fifth transistor P5 is connected to the reference bit line / BL, the drain of the fifth transistor P5 is connected to the drain of the fourth transistor P4 and to the first power line NCS, which is used to provide a low potential voltage.

[0105] A gate of the sixth transistor P6 is connected to the reference bit line / BL, and a source of the sixth transistor P6 is connected to the bit line BL.

[0106] The gate of the seventh transistor P7 is connected to the bit line BL, the source of the seventh transistor P7 is connected to the reference bit line / BL, the drain of the seventh transistor P7 is connected to the drain of the sixth transistor P6, and is connected to the second power line PCS, which is used to provide a high potential voltage.

[0107] In this embodiment, the fourth transistor P4 and the fifth transistor P5 are both N-type transistors, and the sixth transistor P6 and the seventh transistor P7 are both P-type transistors.

[0108] In this embodiment, when the bit line BL is used to read data "1", the sensitive amplifier SA can pull the potential on the bit line BL up to the highest potential Vary, and at the same time pull the potential on the reference bit line / BL down to the lowest potential Vss, so as to amplify the voltage difference between the bit line BL and the reference bit line / BL corresponding to the bit line BL, thereby facilitating reading by the reading circuit.

[0109] When reading the stored data in the memory cell connected to the second word line, the following processes are mainly included: Figure 7As shown, after the first word line WL0 is closed and reset is completed, the equalization circuit BLEQ is turned off and the second word line WL1 is turned on to open the memory cell 10 connected to the second word line WL1, so that the data in the memory cell 10 is shared with the potential on the bit line BL. Since the potential on the bit line BL and the reference bit line / BL are not reset to the intermediate potential V when the first word line is turned on, the data in the memory cell 10 is shared with the potential on the bit line BL. BLE , the potential of the bit line BL is still higher than the potential on the reference bit line / BL. After waiting for the second word line WL1 to be turned on, the sense amplifier SA is turned on and the potential on the bit line BL is quickly pulled up to the highest potential Vary by using the sense amplifier SA, and the potential on the reference bit line / BL is quickly pulled down to the lowest potential Vss to amplify the potential difference between the bit line BL and the reference bit line / BL. Then, the read circuit is turned on and the data in the memory cell 10 is transmitted to the peripheral circuit by using the fourth signal line 50 to obtain the data of the memory cell 10 connected to the second word line WL1. After that, the reference bit line / BL and the bit line BL are precharged, and the second word line WL1 and the sense amplifier are turned off, so that the potentials of the bit line BL and the reference bit line / BL are restored to the intermediate potential V BLE , so as to read the data in the storage cells connected to the remaining word lines.

[0110] In this embodiment, on the one hand, by increasing the opening time of the first word line WL0, the opening time of the first word line WL0 is made greater than the timing parameter tRAS, thereby increasing the leakage current time of the first word line. On the other hand, by shortening the timing parameter tRP, the precharge time of the bit line and the reference bit line is reduced, making it difficult for the potential of the bit line and the reference bit line to return to the intermediate value V BLE , to affect the type of storage data read from the storage unit connected to the second word line. Based on this, this embodiment can timely detect whether adjacent word lines have leakage through the above two improvements, providing a guarantee for improving the yield of the memory.

[0111] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0112] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.

[0113] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory detection method, characterized in that: Among any two adjacent word lines, one of the word lines is a first word line and the other word line is a second word line, the detection method includes: Writing first storage data into a memory cell connected to the first word line, and writing second storage data into a memory cell connected to the second word line, wherein the first storage data is different from the second storage data; activating the first word line to turn on a transistor of a memory cell connected to the first word line, and keeping the transistor on for a first preset time period before turning it off, where the first preset time period is greater than a first time threshold; turning on the second word line; Acquire actual storage data of a memory cell connected to the second word line, and determine whether the actual storage data is the same as the first storage data; If actual storage data of a memory cell on one of the bit lines connected to the second word line is the same as the first storage data, leakage occurs between the first word line and the second word line.

2. The memory detection method according to claim 1, wherein: The step of starting the first word line includes: applying a first voltage to the first word line to start the transistor connected to the first word line, wherein the first voltage is greater than a turn-on voltage of the first word line.

3. The memory detection method according to claim 1 or 2, characterized in that: The step of starting the first word line further includes applying a second voltage to the first word line to turn off the transistor connected to the first word line, wherein the second voltage is greater than a turn-off voltage of the first word line.

4. The memory detection method according to claim 3, wherein: The memory further includes a plurality of reference bit lines, the plurality of reference bit lines being arranged in a one-to-one correspondence with the plurality of bit lines. After the step of activating the first word line and before the step of activating the second word line, the detection method further includes: One of the bit lines corresponding to the first word line and the reference bit line corresponding to the bit line are precharged so that a potential of the precharged bit line is not equal to a potential of the reference bit line.

5. The memory detection method according to claim 4, characterized in that: An equalization circuit of the memory is started, and the bit line and the reference bit line corresponding to the bit line are placed in a precharge state within a second preset time period, where the second preset time period is less than a second time threshold.

6. The memory detection method according to claim 5, characterized in that: The equalization circuit includes a first transistor, a second transistor, and a third transistor disposed between the bit line and the reference bit line; The gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are connected; The source of the first transistor is connected to the bit line, and the drain of the first transistor is connected to the reference bit line; The source of the second transistor is connected to the bit line, and the drain of the second transistor is connected to the source of the third transistor; A drain of the third transistor is connected to the reference bit line.

7. The memory detection method according to claim 6, characterized in that: The balancing circuit further includes a first signal line, which is respectively connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor. The first signal line is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit.

8. The memory detection method according to claim 7, characterized in that: The drain of the second transistor and the source of the third transistor are further connected to a second signal line, and the second signal line is used to provide a reset voltage to the bit line and the reference bit line.

9. The memory detection method according to claim 1, wherein: The step of obtaining actual storage data of a memory cell connected to the second word line includes: The memory includes a read circuit and a peripheral circuit. The read circuit is connected to the bit line. The read circuit is activated to transfer storage data connected to the first word line to the peripheral circuit.

10. The memory detection method according to claim 9, characterized in that: The read circuit includes: a read transistor, wherein a gate of the read transistor is connected to a third signal line, and the third signal line is used to control the opening or closing of the read transistor; A source of the read transistor is connected to the bit line, and a drain of the read transistor is connected to the peripheral circuit.

11. The memory detection method according to claim 10, wherein: A fourth signal line is provided between the drain of the read transistor and the peripheral circuit.

12. The memory detection method according to claim 4, characterized in that: The memory further includes a sensitive amplifier, which is arranged between the bit line and the reference bit line corresponding to the bit line, and is used to amplify the voltage difference between the bit line and the reference bit line corresponding to the bit line.

13. The memory detection method according to claim 12, wherein: The sense amplifier includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; A gate of the fourth transistor is connected to the reference bit line, and a source of the fourth transistor is connected to the bit line; The gate of the fifth transistor is connected to the bit line, the source of the fifth transistor is connected to the reference bit line, the drain of the fifth transistor is connected to the drain of the fourth transistor, and is connected to a first power line, wherein the first power line is used to provide a low potential voltage; The gate of the sixth transistor is connected to the reference bit line, and the source of the sixth transistor is connected to the bit line; The gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor and to a second power line, and the second power line is used to provide a high potential voltage.

14. The memory detection method according to claim 13, wherein: The fourth transistor and the fifth transistor are both N-type transistors, and the sixth transistor and the seventh transistor are both P-type transistors.

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