Content addressable memory device

Abstract

A content addressable memory device includes first through third content addressable memory circuits and first and second peripheral circuits. The first content addressable memory circuit stores first bits of a first word group. The second content addressable memory circuit is disposed adjacent to the first content addressable memory circuit and stores the first bits of a second word group. The third content addressable memory circuit is disposed adjacent to the second content addressable memory circuit and stores second bits of the second word group, wherein the first through third content addressable memory circuits are disposed in a memory column. The first peripheral circuit accesses the first bits of the first and second word groups. The second peripheral circuit accesses the second bits of the second word group.

Description

TECHNICAL FIELD

[0001] The present invention relates to memory devices, and more particularly, to content addressable memory devices with row-multiplexed and shared peripheral element arrangements. BACKGROUND

[0002] Content addressable memories can quickly compare stored data with data to be searched and output a comparison result. In a conventional content addressable memory, multiple memory circuits storing different bits of the same byte are arranged in the same column, and multiple memory circuits storing the same bit in different bytes are arranged in the same row. A corresponding peripheral circuit is provided for each memory row to read the bits. This results in an excessive number of peripheral circuits and inefficient use of memory area. In addition, some old row-multiplexed arrangements of memory arrays are no longer suitable for implementation using current processes due to layout restrictions or changes in component locations. If these arrangements are implemented using current processes, more circuit area can be consumed. SUMMARY

[0003] In some embodiments, a content addressable memory device includes a first content addressable memory circuit, a second content addressable memory circuit, a third content addressable memory circuit, a first peripheral circuit, and a second peripheral circuit. The first content addressable memory circuit is configured to store first bits of a first byte. The second content addressable memory circuit is arranged adjacent to the first content addressable memory circuit and is configured to store first bits of a second byte. The third content addressable memory circuit is arranged adjacent to the second content addressable memory circuit and is configured to store second bits of the second byte, wherein the first content addressable memory circuit, the second content addressable memory circuit, and the third content addressable memory circuit are arranged in a memory column. The first peripheral circuit is configured to access the first bits of the first byte and the first bits of the second byte. The second peripheral circuit is configured to access the second bits of the second byte.

[0004] In some embodiments, a content addressable memory device includes a first memory row, a second memory row, and a match line. The first memory row includes a first content addressable memory circuit. The second memory row is arranged adjacent to the first memory row and includes a second content addressable memory circuit, and the first content addressable memory circuit and the second content addressable memory circuit are arranged in a same memory column. The first content addressable memory circuit and the second content addressable memory circuit are configured to store different bits of a byte and are connected to the match line via a same via.

[0005] The present application will be described with reference to the attached drawings, which are provided solely for purposes of illustration and wherein like elements denote the same throughout the various figures and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 schematic diagram of a content addressable memory device according to some embodiments of the present application;

[0007] Figure 2A circuit schematic of a content addressable memory circuit in Figure 1 according to some embodiments of the present application;

[0008] Figure 2B top view of a content addressable memory circuit in Figure 2A according to some embodiments of the present application;

[0009] Figure 2C schematic diagram of two content addressable memory circuits in Figure 1 according to some embodiments of the present application;

[0010] Figure 2D top view of two content addressable memory circuits in Figure 2C according to some embodiments of the present application; and

[0011] Figure 3 top view of two content addressable memory circuits in Figure 1 according to some embodiments of the present application.

[0012] REFERENCE NUMERALS

[0013] DETAILED DESCRIPTION

[0014] All words used herein are to be interpreted in their normal and customary way. The definitions of the above words in common, generally used dictionaries, and the usage examples of any of the words discussed herein included in the summary of the application, are all to be used only as examples and should not be used to limit the scope and meaning of the present application. Likewise, the present application is not to be limited only to the various embodiments shown in this specification.

[0015] As used herein, "coupled" or "connected" can mean either a direct electrical or physical contact between two or more elements, or an indirect electrical or physical contact between two or more elements, or that the two or more elements are operatively or functionally associated with each other. As used herein, the term "circuit" can be a device that has at least one transistor and / or at least one active or passive element connected in a certain manner to process a signal.

[0016] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the terms first, second, third, etc. are used only to describe different elements and do not imply a particular order or ranking. Thus, a first element herein can be termed a second element without departing from the spirit of the application. For ease of understanding, the same reference numbers will be used to designate similar elements in the various figures.

[0017] Figure 1 A schematic diagram of a content addressable memory (CAM) device 100 according to some embodiments of the present application is shown. The CAM device 100 includes a plurality of content addressable memory circuits (CAM circuits) 110

[11] ~110

[14] , 110

[21] ~110

[24] , 110

[31] ~110

[34] , a plurality of precharge circuits 120[1]~120[3], a plurality of peripheral circuits 130[1]~130[2], a plurality of match lines ML0~ML5, and a plurality of search bit lines SBLP1~SBLP4 and SBLN1~SBLN4.

[0018] The plurality of CAM circuits 110

[11] ~110

[14] , 110

[21] ~110

[24] , 110

[31] ~110

[34] are arranged as a memory array having a plurality of memory rows (e.g., consecutive rows 1~4) and a plurality of memory columns (e.g., consecutive columns 1~3). For example, the plurality of CAM circuits 110

[11] ~110

[14] are disposed in column 1, the plurality of CAM circuits 110

[21] ~110

[24] are disposed in column 2, and the plurality of CAM circuits 110

[31] ~110

[34] are disposed in column 3. The plurality of CAM circuits 110

[11] , 110

[21] , and 110

[31] are disposed in row 1, the plurality of CAM circuits 110

[12] , 110

[22] , and 110

[32] are disposed in row 2, and the plurality of CAM circuits 110

[13] , 110

[23] , and 110

[33] Set in row 3, and multiple CAM circuits 110

[14] 110

[24] and 110

[34] Set it on line 4.

[0019] In column 1, CAM circuit 110

[11] With CAM circuit 110

[14] Coupled to matching line ML0, CAM circuit 110

[11] The first bit in the stored word W0, and CAM circuit 110

[14] The second bit in the storage word group W0. Similarly, CAM circuit 110

[12] With CAM circuit 110

[13] Coupled to matching line ML1, CAM circuit 110

[12] The first bit in the storage word group W1, and CAM circuit 110

[13] The second bit in the storage word group W1. In the second column, CAM circuit 110

[21] and CAM circuit 110

[24] Coupled to the matching line ML2, CAM circuit 110

[21] stores the first bit in word group W2, and CAM circuit 110

[24] The second bit in storage word group W2. Similarly, CAM circuit 110

[22] With CAM circuit 110

[23] Coupled to matching line ML3, CAM circuit 110

[22] The first bit in the storage word group W3, and CAM circuit 110

[23] The second bit in storage word group W3. In column 3, CAM circuit 110.

[31] With CAM circuit 110

[34] Coupled to matching line ML4, CAM circuit 110

[31] The first bit in the storage word group W4, and CAM circuit 110

[34] The second bit in storage word group W4. Similarly, CAM circuit 110

[32] With CAM circuit 110

[33] Coupled to matching line ML5, CAM circuit 110

[32] The first bit in the storage word group W5, and CAM circuit 110

[33] The second bit in the storage word W5.

[0020] In line 1, CAM circuit 110

[11] CAM circuit 110

[21] and CAM circuit 110

[31] It is coupled to peripheral circuit 130 via search bit line SBLP1 and search bit line SBLN1 [1]. In the second row, CAM circuit 110

[12] CAM circuit 110

[22] and CAM circuit 110

[32] The peripheral circuit 130[1] is coupled to search bit line SBLP2 and search bit line SBLN2. In this way, the peripheral circuit 130[1] can access (including read and / or write) the first bit in each word group W0 to W5. In some embodiments, the peripheral circuit 130[1] may include (but is not limited to) a multiplexer circuit (not shown) and a sensing circuit (not shown). The multiplexer circuit can be used to implement column muxing to selectively access data (i.e., the first bit in each word group W0 to W5) from the first or second row. The sensing circuit receives the data from the multiplexer circuit and amplifies the data to a logic level suitable for subsequent circuit recognition. Alternatively, in some embodiments, the peripheral circuit 130[1] may transmit the first bit of the data to be searched to multiple CAM circuits in the first and second rows.

[0021] Similarly, in line 3, CAM circuit 110

[13] CAM circuit 110

[23] and CAM circuit 110

[33] It is coupled to peripheral circuit 130 via search bit line SBLP3 and search bit line SBLN3 [2]. In line 4, CAM circuit 110

[14] CAM circuit 110

[24] and CAM circuit 110

[34] The peripheral circuit 130[2] is coupled to search bit line SBLP4 and search bit line SBLN4. In this way, the peripheral circuit 130[2] can access the second bit of each word group W0 to W5. The implementation of the peripheral circuit 130[2] can be referred to the peripheral circuit 130[1], so it will not be repeated here.

[0022] Taking column 1 as an example, CAM circuit 110

[11] CAM circuit 110

[12] CAM circuit 110

[13] and CAM circuit 110

[14] They are sequentially arranged in column 1. Specifically, CAM circuit 110

[12] Set in CAM circuit 110

[11] With CAM circuit 110

[13] Between. CAM circuit 110

[13] Set with CAM circuit 110

[12] Adjacent to each other, and CAM circuit 110

[14] Set with CAM circuit 110

[13] They are adjacent. Therefore, CAM circuit 110

[12] The CAM circuit 110

[13] (which stores the first and second bits of the same word group W1 respectively) will be located in the CAM circuit 110

[11] With CAM circuit 110

[14] (They store the first and second bits of the same word group W0 respectively) and CAM circuit 110

[12] With CAM circuit 110

[13] They are respectively set in the second and third rows adjacent to each other. Through the above arrangement, the CAM circuit 110...

[12] With CAM circuit 110

[13] It can be connected to the mating line ML1 via the same via. Similarly, in column 2, CAM circuit 110...

[22] With CAM circuit 110

[23] It can be connected to the mating line ML3 via the same through-hole. In column 3, CAM circuit 110

[32] With CAM circuit 110

[33] It can be connected to the mating line ML5 via the same through-hole. This saves circuit space while performing line multiplexing operations. The setup discussed here will be explained later. Figure 3 Please provide an explanation.

[0023] Figure 2A As illustrated in some embodiments of the present invention Figure 1 CAM circuit 110 in

[12] The circuit diagram is shown below. In this example, CAM circuit 110...

[12] The system includes storage circuits 210 and 220, and a comparator circuit 230. Storage circuit 210 stores the first bit of word group W1. Storage circuit 220 stores a mask bit, which can be used to indicate an additional state (e.g., a care state or a don't care state). Comparator circuit 230 receives the first bit of the data to be searched and determines whether to adjust the level of the matching line W1 based on the first bit of word group W1, the mask bit, and the first bit of the data to be searched. The above operation is similar to the function of a typical CAM circuit and will not be elaborated further here.

[0024] In this example, each of storage circuits 210 and 220 can be a bit cell implemented by six transistors. Specifically, storage circuit 210 includes multiple transistors T1 to T6, and comparator circuit 230 includes multiple transistors T7 to T8. The first terminals of transistors T1 and T3 receive voltage VDD. The second terminal of transistor T1 is coupled to the first terminals of transistors T2 and T5. The control terminals of transistors T1, T2, and T7, the second terminal of transistor T3, the first terminal of transistor T4, and the first terminal of transistor T6 are coupled to node N1. The control terminals of transistors T3 and T4, the second terminal of transistor T1, the first terminal of transistor T2, and the first terminal of transistor T5 are coupled to node N2. The control terminals of transistors T5 and T6 are coupled to the corresponding CAM circuit 110.

[12] The word line WL1. The second terminal of transistor T5 is coupled to the corresponding CAM circuit 110.

[12] The bit line BLN, and the second terminal of transistor T6 is coupled to the corresponding CAM circuit 110.

[12] The first terminal of transistor T7 is coupled to the second terminal of transistor T8, and the second terminal of transistor T7 is coupled to the matching line ML1. The first terminal of transistor T8 receives the ground voltage GND, and the control terminal of transistor T8 is coupled to the search bit line SBLN2.

[0025] Similar to storage circuit 210, storage circuit 220 includes multiple transistors T1' to T6', and comparator circuit 230 also includes multiple transistors T7' to T8'. Nodes N1' and N2' in storage circuit 220 correspond to nodes N1 and N2 in storage circuit 210, respectively, and the connection relationships between the multiple transistors T1' to T8' are roughly the same as those between the multiple transistors T1 to T8 in storage circuit 210, so they will not be repeated. In storage circuit 220, the control terminals of transistors T5' and T6' are coupled to the corresponding CAM circuit 110.

[12] The word line WL2. Furthermore, compared to transistor T8, the control terminal of transistor T8' is coupled to the search bit line SBLP2.

[0026] Figure 2B As illustrated in some embodiments of the present invention Figure 2A CAM circuit 110 in

[12] A top view. In some embodiments, Figure 2B It can be regarded as CAM circuit 110

[12] In the actual structure, the top view can be regarded as CAM circuit 110.

[12] The layout design diagram.

[0027] Refer to together Figure 2A and Figure 2B The control terminal of each of the multiple transistors T1 to T8 and T1' to T8' can be a gate (drawn as diagonal stripes). In this example, the multiple gates are arranged along a horizontal direction (e.g., direction X). For ease of understanding, Figure 2B The labels indicate the corresponding gate locations of transistors T1 to T8 and T1' to T8'. Since node N1 is coupled to the control terminals of multiple transistors T1, T2, and T7, the control terminals of these transistors can be implemented using the same gate structure (e.g., polysilicon). Similarly, since node N1' is coupled to the control terminals of multiple transistors T1', T2', and T7', the control terminals of these transistors can also be implemented using the same gate structure. Likewise, the control terminals of multiple transistors T3 and T4 can be implemented using the same gate structure, and the control terminals of multiple transistors T3' and T4' can also be implemented using the same gate structure.

[0028] Each of the multiple transistors T1-T8 and T1'-T8' can have its first and second terminals serving as drain (or source) and source (or drain), respectively, which can be the gate terminals on the left and right sides of the active region (drawn in white). The multiple transistors T1, T3, T1', and T3' are P-type transistors and are therefore disposed in an N-type well. Contacts couple the terminals or gates on the active region to the corresponding metal layers (drawn with dots) to connect to specific components (e.g., bit line BLN, bit line BLP, search bit line SBLN2, search bit line SBLP2, word line WL1, or word line WL2) or to receive specific voltages (e.g., voltage VDD or ground GND). Vias couple metal to specific components (e.g., matching line ML1) or to receive specific voltages (e.g., voltage VDD or ground GND). (See reference...) Figure 2A and Figure 2B The CAM circuit 110 should be understandable.

[12] The specific configuration relationships between multiple components.

[0029] Figure 2C As illustrated in some embodiments of the present invention Figure 1 CAM circuit 110 in

[11] With CAM circuit 110

[12] Schematic diagram. CAM circuit 110

[12] Structure and Figure 2A The same applies, so I will not repeat it here. Figure 2C As shown, CAM circuit 110

[11] The structure is roughly the same as CAM circuit 110

[12] The structure. Compared to CAM circuit 110

[12] In CAM circuit 110

[11] The comparator circuit 230 is coupled to the matching line ML0, the search bit line SBLP1, and the search bit line SBLN1.

[0030] Figure 2D As illustrated in some embodiments of the present invention Figure 2C CAM circuit 110 in

[11] With CAM circuit 110

[12] A top view. In some embodiments, Figure 2D It can be regarded as CAM circuit 110

[11] With CAM circuit 110

[12] In the actual structure, the top view can be regarded as CAM circuit 110.

[11] With CAM circuit 110

[12] The layout design diagram. Figure 2D The configuration of each component can be found in the following reference. Figure 2B Therefore, I will not repeat the details here.

[0031] As mentioned earlier, CAM circuit 110

[11] With CAM circuit 110

[12] They have the same structure. For example... Figure 2D As shown, CAM circuit 110

[11] Structure and CAM circuit 110

[12] The structure is essentially a mirror image of the reference line AA. In this example, CAM circuit 110

[11] With CAM circuit 110

[12] Shared contacts, metal layers, and / or gates can be coupled to word lines WL1 and WL2. This further reduces the circuit area. Additionally, search bit line SBLN1 and search bit line SBLP1 are set... Figure 2D On the left side, search bit line SBLN2 and search bit line SBLP2 are set... Figure 2D On the right side, and search bit lines SBLN1 and SBLP1 are independent of search bit lines SBLN2 and SBLP2. CAM circuit 110

[11] With CAM circuit 110

[12] The same data (e.g., the first bit of the data to be searched) is received from the peripheral circuit 130[1]. The same data is transmitted to the CAM circuit 110 via multiple independent search bit lines.

[11] With CAM circuit 110

[12] This reduces the load on each search bit line (compared to using a single search bit line to transmit data to the CAM circuitry in two memory rows). This configuration improves operating speed.

[0032] Figure 3As illustrated in some embodiments of the present invention Figure 1 CAM circuit 110 in

[12] With CAM circuit 110

[13] A top view. In some embodiments, Figure 3 It can be regarded as CAM circuit 110

[12] With CAM circuit 110

[13] In the actual structure, the top view can be regarded as CAM circuit 110.

[12] With CAM circuit 110

[13] The layout design diagram. Figure 3 The configuration of each component can be found in the following reference. Figure 2B Therefore, I will not repeat the details here.

[0033] As mentioned earlier, CAM circuit 110

[12] With CAM circuit 110

[13] They have the same structure. For example... Figure 3 As shown, relative to the reference line BB, CAM circuit 110

[12] Structure and CAM circuit 110

[13] The structure is essentially mirror-symmetric. This is due to the CAM circuit 110.

[12] With CAM circuit 110

[13] All are coupled to the matching line ML1, CAM circuit 110

[12] With CAM circuit 110

[13] A shared via and / or metal layer can be used to couple to the mating line ML1. This can further reduce the circuit area.

[0034] The number of elements and / or connection relationships shown in the above figures are for illustrative purposes only, and the invention is not limited thereto. For example, Figure 1 The CAM device 100 may include more rows and / or more columns. Alternatively, for practical winding designs, Figure 2B , Figure 2D or Figure 3 It may include more metal layers, contacts and / or vias for connection.

[0035] In summary, the content-addressable memory device provided in some embodiments of the present invention achieves multiplexing and shared components by changing the arrangement of memory circuits in the memory array. This reduces the number of circuit elements and saves circuit area, while also reducing the load on the wires to improve operating speed.

[0036] Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the content explicitly or implicitly shown in the present application, and these changes can all belong to the patent protection scope required by the present application. In other words, the patent protection scope of the present application should be defined according to the claims of the present application.

Claims

1. A content-addressable memory device, characterized in that, include: A first content-addressable memory circuit is used to store the first bit of a first word group; A second content-addressable memory circuit is configured to be adjacent to the first content-addressable memory circuit and is used to store the first bit of a second word group; A third content-addressable memory circuit is configured to be adjacent to the second content-addressable memory circuit and used to store the second bit of the second word group, wherein the first content-addressable memory circuit, the second content-addressable memory circuit and the third content-addressable memory circuit are arranged in a memory column; A first peripheral circuit is used to access the first bit of the first word group and the first bit of the second word group; and A second peripheral circuit is used to access the second bit of the second word group.

2. The content-addressable memory device according to claim 1, characterized in that, The structure of the second content-addressable memory circuit is a mirror image of the structure of the third content-addressable memory circuit.

3. The content-addressable memory device according to claim 1, characterized in that, Also includes: A first matching line is coupled to the first content-addressable memory circuit; as well as A second matching line is coupled to the second content-addressable memory circuit and the third content-addressable memory circuit.

4. The content-addressable memory device according to claim 3, characterized in that, The second content-addressable memory circuit and the third content-addressable memory circuit are coupled to the second matching line via the same via.

5. The content-addressable memory device according to claim 1, characterized in that, The second content-addressable memory circuit and the third content-addressable memory circuit are located in two adjacent memory rows.

6. The content-addressable memory device according to claim 1, characterized in that, The second content-addressable memory circuit is disposed between the first content-addressable memory circuit and the third content-addressable memory circuit.

7. The content-addressable memory device according to claim 1, characterized in that, Also includes: A fourth content-addressable memory circuit is disposed in the memory column and configured to be adjacent to the third content-addressable memory circuit, and is used to store the second bit of the first word group. The second peripheral circuit is also used to access the second bit of the first word group.

8. The content-addressable memory device according to claim 7, characterized in that, The second content-addressable memory circuit and the third content-addressable memory circuit are located between the first content-addressable memory circuit and the fourth content-addressable memory circuit.

9. The content-addressable memory device according to claim 7, characterized in that, The first content-addressable memory circuit, the second content-addressable memory circuit, the third content-addressable memory circuit, and the fourth content-addressable memory circuit are sequentially arranged in different memory rows.

10. A content-addressable memory device, characterized in that, include: A first memory row includes a first content-addressable memory circuit; A second memory row, configured to be adjacent to the first memory row, wherein the second memory row includes a second content-addressable memory circuit, and the first content-addressable memory circuit and the second content-addressable memory circuit are disposed in the same memory column; and A matching line, wherein the first content-addressable memory circuit and the second content-addressable memory circuit are used to store different bits of a word group and are connected to the matching line via the same via.

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