Base chip, memory system, and semiconductor structure

Abstract

Embodiments of the present disclosure provide a basic chip, a storage system, and a semiconductor structure. The basic chip includes: The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data and the first encoded data to generate second encoded data. During the write phase, the basic chip transmits second data to a storage chip. The second data includes the first data, the first encoded data, and the second encoded data. The basic chip is further configured to receive the second data from the storage chip during a read phase and perform first error detection and correction processing, and transmit third data during the read phase. The third data is the first data after performing the first error detection and correction processing and the first encoded data after performing the first error detection and correction processing. Embodiments of the present disclosure are beneficial to improving the storage performance of the storage system.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As volatile storage, Dynamic Random Access Memory (DRAM) has advantages such as high storage density and fast read / write speed, and is widely used in various electronic systems.

[0003] As the manufacturing process of DRAM becomes more and more advanced and the storage density becomes higher and higher, the stored data in DRAM may be incorrect, seriously affecting the performance of DRAM. Therefore, Error Checking and Correction (ECC) technology is usually adopted in DRAM to detect or correct errors in the stored data. Summary of the Invention

[0004] Embodiments of the present disclosure provide a basic chip, a storage system, and a semiconductor structure, which are at least helpful to solve the problem of tight area of the controller or the storage chip.

[0005] According to some embodiments of the present disclosure, on the one hand, a basic chip is provided, which is applied to a storage system and includes: the basic chip is configured to receive first data and first encoded data in a write stage, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data and the first encoded data to generate second encoded data, and transmit second data to a storage chip in the write stage, the second data includes the first data, the first encoded data, and the second encoded data; the basic chip is further configured to receive the second data from the storage chip and perform first error detection and correction processing in a read stage, and transmit third data in the read stage, the third data is the first data after the first error detection and correction processing and the first encoded data after the first error detection and correction processing.

[0006] In addition, the basic chip includes: a second encoding module, the second encoding module is configured to receive the first data and the first encoded data in the write stage and perform the second error correction code encoding processing to generate the second encoded data; a first error detection and correction module, the first error detection and correction module is configured to receive the second data and perform the first error detection and correction processing in the read stage.

[0007] In addition, the base chip further includes: a first serial-parallel conversion module configured to receive the first data and the first encoded data during the writing stage, perform a first serial-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-parallel conversion process to the second encoding module; a first parallel-serial conversion module configured to receive the third data during the reading stage, perform a first parallel-serial conversion process on the third data, and transmit the third data after the first parallel-serial conversion process to the controller.

[0008] In addition, the base chip further includes: a second parallel-serial conversion module configured to receive the second data from the second encoding module during the writing stage, perform a second parallel-serial conversion process on the second data, and transmit the second data after the second parallel-serial conversion process to the storage chip; a second serial-parallel conversion module configured to receive the second data from the storage chip during the reading stage, perform a second serial-parallel conversion process on the second data, and transmit the second data after the second serial-parallel conversion process to the first error detection and correction module.

[0009] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data, the first encoded data, and the second encoded data during the transmission process based on the first error detection flag signal.

[0010] In addition, the base chip further includes: a first storage buffer module configured to store the error conditions of the first data, the first encoded data, and the second encoded data during the transmission process; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, where the first characterization signal characterizes the error conditions of the first data, the first encoded data, or the second encoded data during the transmission process.

[0011] In addition, the encoding algorithms used for the first error correction code encoding process and the second error correction code encoding process are different.

[0012] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a storage system, including a controller, a base chip, and a storage chip; the controller is configured to perform a first error correction code encoding process on first data in a write stage to generate first encoded data, and transmit the first data and the first encoded data to the base chip; the base chip is configured to receive the first data and the first encoded data in the write stage and perform a second error correction code encoding process to generate second encoded data, transmit second data to the storage chip in the write stage, the second data including the first data, the first encoded data, and the second encoded data, receive the second data from the storage chip in a read stage and perform a first error detection and correction process, and transmit third data to the controller in the read stage, the third data being the first data after the first error detection and correction process and the first encoded data after the first error detection and correction process; the storage chip is configured to receive the second data from the base chip in the write stage and store the second data, and transmit the second data to the base chip in the read stage; the controller is further configured to receive the third data from the base chip in the read stage, perform a second error detection and correction process on the third data, and transmit the first data after the second error detection and correction process.

[0013] In addition, the controller includes: a first encoding module configured to receive the first data in the write stage and perform the first error correction code encoding process to generate the first encoded data; a second error detection and correction module configured to receive the third data in the read stage and perform the second error detection and correction process.

[0014] In addition, the base chip includes: a second encoding module configured to receive the first data and the first encoded data in the write stage and perform the second error correction code encoding process to generate the second encoded data; a first error detection and correction module, the second error detection and correction module being configured to receive the second data in the read stage and perform the first error detection and correction process.

[0015] In addition, the base chip further includes: a first serial-to-parallel conversion module configured to receive the first data and the first encoded data during the write phase, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the second encoding module; a first parallel-to-serial conversion module configured to receive the third data during the read phase, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0016] In addition, the base chip further includes: a second parallel-to-serial conversion module configured to receive the second data from the second encoding module during the write phase, perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module configured to receive the second data from the storage chip during the read phase, perform a second serial-to-parallel conversion process, and transmit the second data after the second serial-to-parallel conversion process to the first error detection and correction module.

[0017] In addition, the storage chip includes: a first storage module for storing the first data and the first encoded data; a second storage module for storing the second encoded data.

[0018] In addition, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

[0019] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record the error conditions of the first data, the first encoded data, and the second encoded data during the transmission process; the storage system further includes: a first register configured to store the error conditions of the first data, the first encoded data, and the second encoded data during the transmission process.

[0020] In addition, the base chip includes: a first storage buffer module configured to store error conditions during transmission of the first data, the first encoded data, and the second encoded data; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, the first characterization signal characterizing an error condition during transmission of the first data, the first encoded data, or the second encoded data.

[0021] In addition, the controller is further configured to issue the first polling instruction to the first command module.

[0022] In addition, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and record error conditions during transmission of the first data and the first encoded data after the first error detection and correction process based on the second error detection flag signal; the storage system further includes: a second register configured to store error conditions during transmission of the first data and the first encoded data after the first error detection and correction process.

[0023] In addition, the controller includes: a second storage buffer module configured to store error conditions during transmission of the first data and the first encoded data after the first error detection and correction process; a second command module that receives a second polling instruction and generates a second command signal and a second clock signal; the second storage buffer module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, the second characterization signal characterizing an error condition during transmission of the first data or the first data or the first encoded data after the first error detection and correction process.

[0024] According to some embodiments of the present disclosure, yet another aspect of the embodiments of the present disclosure further provides a semiconductor structure, including: a carrier substrate; the above storage system, and the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

[0025] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0026] In the technical solution of the basic chip provided by the embodiments of the present disclosure, the basic chip performs first error correction code encoding processing on the first data and the first encoded data in the writing stage to obtain the second encoded data, and transmits the first data, the first encoded data, and the second encoded data to the storage chip in the writing stage; and the basic chip receives the first data, the first encoded data, and the second encoded data from the storage chip in the reading stage and performs second error detection and correction processing, and transmits the first data and the first encoded data after the first error detection and correction processing. Therefore, the basic chip has an encoding processing function and an error detection and correction function, so that the storage chip does not need to have an encoding processing function and an error detection and correction function, and can share the encoding processing function and the error detection and correction function that the controller needs to have, which is beneficial to improving the performance of the controller and the storage chip, and reasonably utilizing the chip area of the basic chip, thereby being beneficial to improving the storage performance of the storage system.

[0027] Moreover, the basic chip performs error correction code encoding processing and first error detection and correction processing on the first data and the first encoded data, so as to perform error detection and correction on the first encoded data, thereby ensuring the accuracy of the first encoded data, which is beneficial to further ensuring the accuracy of the first data during transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a scale limitation.

[0029] Figure 1 It is a schematic structural diagram of a semiconductor structure;

[0030] Figure 2 is Figure 1 a schematic diagram of data transmission in the provided semiconductor structure;

[0031] Figures 3 to 6 It is a schematic structural diagram of the basic chip provided by the embodiments of the present disclosure;

[0032] Figures 7 to 10 It is a schematic structural diagram of the storage system provided by the embodiments of the present disclosure;

[0033] Figure 11 It is a schematic cross-sectional structural diagram of the semiconductor structure provided by the embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Figure 1 It is a schematic structural diagram of a semiconductor structure, Figure 2 is Figure 1 a schematic diagram of data transmission in the provided semiconductor structure.

[0035] Reference Figure 1 Figure 1 , a semiconductor structure may include: a substrate 11; a base die 12 and a processor 13 respectively located on the surface of the substrate 11; a plurality of core dies 14 are stacked on the base die 12, and the core die 14 may be a DRAM chip. Reference Figure 2 Figure 2 , during the data transmission process in the semiconductor structure, in the writing stage, the controller 13 transmits data to the base die 12, and the base die 12 transmits the data into the core die 14. The controller 13 may perform error correction code encoding processing on the data before transmitting the data; in the reading stage, the core die 14 transmits the data to the base die 12, and then, the base die 12 transmits the data to the controller 13. The controller 13 receives the data and performs error correction code decoding processing to detect and correct errors in the data.

[0036] It is not difficult to find that in the above semiconductor structure, the base die 12 does not participate in the error detection and correction process, that is, there is no error correction code encoding function and corresponding error detection and correction function in the base die 12. The controller 13 or the core die 14 needs to complete the error detection and correction, which results in the chip area of the controller 13 and the core die 14, where the chip area is already tight, becoming even more tense. Therefore, the performance of the controller 13 and the core die 14 is affected, and further the storage performance of the entire semiconductor structure needs to be improved.

[0037] The present disclosure provides a base die, a storage system, and a semiconductor structure, and the base die has an error detection and correction function. Figure 3 It is the first structural schematic diagram of the base die provided by the embodiment of the present disclosure. Figure 4 It is the second structural schematic diagram of the base die provided by the embodiment of the present disclosure. Figure 5 It is the third structural schematic diagram of the base die provided by the embodiment of the present disclosure. Figure 6 It is the fourth structural schematic diagram of the base die provided by the embodiment of the present disclosure.

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present disclosure can still be implemented.

[0039] Reference Figure 3, the basic chip 100 is applied to a storage system. Among them, the basic chip is configured to receive a first data data1 and a first encoded data ecc1 during a write stage. The first encoded data ecc1 is obtained by performing a first error correction code encoding process on the first data data1, and perform a second error correction code encoding process on the first data data1 and the first encoded data ecc1 to generate a second encoded data ecc2. During the write stage, the second data data2 is transmitted to the storage chip. The second data data2 includes the first data data1, the first encoded data ecc1, and the second encoded data ecc2; the basic chip 100 is further configured to receive the second data data2 from the storage chip and perform a first error detection and correction process during the read stage, and transmit a third data data3 during the read stage. The third data data3 is the first data data1 after the first error detection and correction process and the first encoded data ecc1 after the first error detection and correction process.

[0040] In the embodiments of the present disclosure, the basic chip 100 participates in error correction code encoding processing and error detection and correction processing during data transmission. Specifically, the basic chip 100 can perform a second error correction code encoding process on the first data data1 and the first encoded data ecc1, and can perform a first error detection and correction process on the first data data1 and the first encoded data ecc1 transmitted via the storage chip to detect whether the first data data1 and the first encoded data ecc1 are in error during the write and read stages, and correct the in-error first data data1 or first encoded data ecc1, which is beneficial to improving the error detection and correction ability of the storage system and reasonably utilizing the chip area of the basic chip 100. In addition, since the basic chip 100 can perform error detection and correction on the first encoded data ecc1, the accuracy of the first encoded data ecc1 is guaranteed. Subsequently, during the transmission process of the first data data1, the highly accurate first encoded data ecc1 will also be used as the basis for error detection and correction, which is beneficial to further improving the accuracy during the transmission process of the first data data1.

[0041] In some embodiments, the basic chip 100 can be connected between a first port A and a second port B. Among them, the first port A is connected to the data transmission port of the controller of the storage system, and the second port B is connected to the data transmission port of the storage chip of the storage system. It can be understood that the first port A and the second port B are general terms. The first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. Among them, the number of data transmission ports is related to the number of data to be transmitted by the basic chip 100. For example, the number of data transmission ports can be the same as the number of data to be transmitted by the basic chip 100, and one data can be transmitted via one data transmission port.

[0042] Both the error correction code encoding process and the error detection and correction process are used to implement ECC error detection and correction, so as to detect and locate the errors occurring in the first data transmission process and correct the errors. In some embodiments, the ECC error detection and correction can adopt the error correction mechanism of Reed Solomon Code (RS). Correspondingly, the error correction code encoding process can adopt the RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the RS decoding algorithm. In other embodiments, the ECC error detection and correction can adopt the error correction mechanism of Hamming Code. Correspondingly, the error correction code encoding process can adopt the Hamming code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the Hamming code decoding algorithm.

[0043] In some embodiments, the first data data1 can be data of 256 bits (bit). Correspondingly, the first encoded data ecc1 can be data of 16 bits. It can be understood that in other embodiments, due to the difference in the specific algorithm adopted by the first error correction code encoding process, the number of bits of the first encoded data can also be correspondingly different. In addition, the number of bits of the first data data1 can also be other quantities, such as 128, 512, etc.

[0044] In some embodiments, the encoding algorithms adopted by the first error correction code encoding process and the second error correction code encoding process are different. Correspondingly, the decoding algorithms adopted by the first error detection and correction process and the second error detection and correction process performed by the controller are also different. In this way, using different encoding and decoding algorithms for error detection and correction is beneficial to further improve the correct rate of data error correction and the data error detection and correction ability, and reduce the difficulty for the basic chip 100 to identify different encoded data. For example, the first encoded data ecc1 is 16-bit data, and the second encoded data ecc2 can be 32-bit data. It should be noted that in other embodiments, the first error correction code encoding process and the second error correction code encoding process can also adopt the same encoding algorithm. In addition, the encoding algorithm adopted by the second error correction code encoding process corresponds to the decoding algorithm adopted by the first error detection and correction process.

[0045] Figure 4 This is the second structural schematic diagram of the basic chip provided by the embodiments of the present disclosure. Refer to Figure 4 , in some embodiments, the basic chip 100 may include: a second encoding module 110, which is configured to receive the first data data1 and the first encoded data ecc1 during the writing stage and perform a second error correction code encoding process to generate the second encoded data ecc2; a first error detection and correction module 120, which is configured to receive the second data data2 during the reading stage and perform the first error detection and correction process.

[0046] The second encoding module 110 is connected between the data transmission port of the controller and the data transmission port of the storage chip. The first data data1 and the first encoded data ecc1 are transmitted to the second encoding module 110 as a whole. The first data data1 transmitted to the second encoding module 120 is data that has not been error detection and correction processed; the whole of the first data data1 and the first encoded data ecc1 corresponds to the second encoded data ecc2 generated by the second encoding module 120.

[0047] The first error detection and correction module 120 is connected between the data transmission port of the controller and the data transmission port of the storage chip. The first error detection and correction module 120 performs error detection and correction on the first data data1 and the first encoded data ecc1 using the second encoded data ecc2. Specifically, the paths where data errors can be detected by the first error detection and correction module 120 include: the transmission path from the second encoding module 110 to the storage chip, and the transmission path from the storage chip to the first error detection and correction module 120.

[0048] Through the second error correction code encoding process and the first error detection and correction process, it is possible to perform error detection and correction on the data transmission path between the base chip 100 and the storage chip, which is beneficial to improving the data error detection and correction ability. It should be noted that the "first", "second", and "third" in the embodiments of the present disclosure are only for descriptive distinction, and there is no special limitation on the order in which the corresponding features appear.

[0049] The following will be combined with Figure 4 to elaborate on the working principle of the base chip 100 in detail:

[0050] In the writing stage, the first data data1 and the first encoded data ecc1 from the controller are transmitted to the second encoding module 110. The second encoding module 110 performs second error correction code encoding processing on the first data data1 and the first encoded data ecc1 to generate the second encoded data ecc2; then the first data data1, the first encoded data ecc1, and the second encoded data ecc2 are written into the storage chip. For example, the first data data1 is 256bit, the first encoded data ecc1 is 16bit, 272bit of data is transmitted to the second encoding module 110 and the generated second encoded data ecc2 is 32bit. Therefore, 272bit + 32bit of data is stored in the storage chip.

[0051] In the reading stage, the first data data1, the first encoded data ecc1, and the second encoded data ecc2 from the storage chip are read out and transmitted to the first error detection and correction module 120. The first error detection and correction module 120 performs the first error detection and correction process to obtain the first data data1 after the first error detection and correction process and the first encoded data ecc1 after the first error detection and correction process. The first data data1 after the first error detection and correction process and the first encoded data ecc1 after the first error detection and correction process can be transmitted to the controller. For example, 272bit + 32bit of data is read out from the storage chip and 272bit of data is output after the first error detection and correction process by the first error detection and correction module 120. Among them, 256bit is the first data data1 after the first error detection and correction process, and 16bit is the first encoded data ecc1 after the first error detection and correction process. Then, the 272bit of data can be transmitted into the controller, enabling the controller to perform the second error detection and correction process.

[0052] In this way, in the reading stage, the basic chip 100 can perform the first error detection and correction process on the first data data1 and the first encoded data ecc1, so that both the first data data1 and the first encoded data ecc1 transmitted back to the controller are the data after the error detection and correction process. That is to say, the accuracy rates of the first data data1 and the first encoded data ecc1 transmitted back to the controller are both improved. The high accuracy rate of the first encoded data ecc1 is beneficial to further improving the accuracy rate of error detection and correction of the first data data1 in the subsequent transmission process. Then, the controller performs the second error detection and correction process on the first data data1 and the first encoded data ecc1 with high accuracy rates to obtain the first data data1 after the second error detection and correction process, and the first data data1 after the second error detection and correction process will also have a high accuracy rate accordingly.

[0053] In summary, the basic chip 100 is beneficial to improving the overall data error detection and correction accuracy rate of the storage system. In addition, the storage chip in the storage system does not need to have the encoding processing function and the error detection and correction function, and the basic chip 100 can share the encoding processing function and the error detection and correction function required by the controller, which is beneficial to improving the performance of the controller and the storage chip, and reasonably utilizing the chip area of the basic chip 100 is beneficial to alleviating the chip area pressure of the controller and the storage chip, and further beneficial to improving the storage performance of the storage system.

[0054] Figure 5 This is the third structural schematic diagram of the basic chip provided in the embodiment of the present disclosure. Refer to Figure 5, in some embodiments, the base chip 100 may further include: a first serial-to-parallel (DES, DESerializer) conversion module 130, which is configured to receive a first data data1 and a first encoded data ecc1 during the write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the second encoding module 110; a first parallel-to-serial (SER, SERlializer) conversion module 140, which is configured to receive a third data data3 during the read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller.

[0055] The settings of the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140 can reduce the number of transmission channels between the base chip 100 and the controller and increase the number of bits transmitted per transmission channel. In addition, since the number of transmission channels is reduced, the number of data transmission ports required to be set on the base chip 100 and the controller can be saved, thereby saving the chip area of the base chip 100 and the chip area of the controller. The first data data1 and the first encoded data ecc1 are transmitted to the first serial-to-parallel conversion module 130 in a serial manner. The first serial-to-parallel conversion module 130 can also be referred to as a deserialization unit, that is, deserializing the serial first data data1 and the first encoded data ecc1. The first parallel-to-serial conversion module 140 performs a serial processing on the third data data3 and transmits the third data data3 after the serial processing. The first parallel-to-serial conversion module 140 can also be referred to as a serializer.

[0056] For example, if the first data data1 is 256 bits, the first data data1 is transmitted to the first serial-to-parallel conversion module 130 through 32 transmission channels. If the first encoded data ecc1 is 16 bits, the first encoded data ecc1 is transmitted to the first serial-to-parallel conversion module 130 through 2 transmission channels. After the first data data1 and the first encoded data ecc1 are deserialized by the first serial-to-parallel conversion module 130, the first data data1 is transmitted to the first error detection and correction module 110 in parallel through 256 transmission channels, and the first encoded data ecc1 is transmitted to the first error detection and correction module 110 through 16 transmission channels.

[0057] For example, 256 bits is the first data data1 after the first error detection and correction process, 16 bits is the first encoded data ecc1 after the first error detection and correction process. The third data dtat3 can be converted into 32 + 2 string data after being serially processed by the first serial-to-parallel conversion module 140, and the 32 + 2 string data can be transmitted through 32 + 2 transmission channels accordingly. Among them, 32 string data is the first data data1 after the first error detection and correction process, and 2 string data is the first encoded data ecc1 after the first error detection and correction process. Refer to Figure 5 , in some embodiments, in addition to the first parallel-to-serial conversion module 130 and the first serial-to-parallel conversion module 140, the base chip 100 may further include: a second serial-to-parallel conversion module 150, which is configured to receive the second data data2 from the second encoding module 110 and perform a second serial-to-parallel conversion process during the write stage, and transmit the second data data2 after the second serial-to-parallel conversion process to the storage chip; a second parallel-to-serial conversion module 160, which is configured to receive the second data data2 from the storage chip and perform a second parallel-to-serial conversion process during the read stage, and transmit the second data data2 after the second parallel-to-serial conversion process to the first error detection and correction module 120.

[0058] The second serial-to-parallel conversion module 150 performs serial processing on the second data data2, which is beneficial to reducing the transmission channels between the base chip 100 and the storage chip, thereby saving the number of data transmission ports required on the base chip 100 and the storage chip, and further saving the chip area of the base chip 100 and the chip area of the storage chip. For example, if the first data is 256 bits, the first encoded data ecc1 is 16 bits, and the second encoded data is 32 bits, after the parallel-to-serial conversion process by the second serial-to-parallel conversion module 150, 128 + 8 + 16 transmission channels can be used to transmit the second data data2. Among them, 128 transmission channels transmit the first data data1, 8 transmission channels transmit the first encoded data ecc1, and 16 transmission channels transmit the second encoded data ecc2.

[0059] In addition, in some embodiments, the base chip 100 may also be configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process based on the first error detection flag signal. Specifically, if an error occurs in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during the transmission process, a first error detection flag signal is generated; if no error occurs in the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process, the first error detection flag signal is not generated. In addition, in some embodiments, the first error detection flag signal may be defined as: if an error occurs in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1; if no error occurs in the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0. In other embodiments, the first error detection flag signal may also be defined as: if an error occurs in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0; if no error occurs in the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1.

[0060] Through the first error detection flag signal, it is possible to obtain whether an error occurs in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 in the data transmission path from the controller to the base chip 100 during the write phase, and it is also possible to obtain whether an error occurs in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 in the data transmission path from the storage chip to the base chip during the read phase.

[0061] As Figure 6 shown, Figure 6 For Figure 4Schematic structural diagram based on this. In some embodiments, the basic chip 100 may further include: a first storage cache module 101, which is configured to store the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during transmission; a first command module 102, which receives the first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage cache module 101 is further configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during transmission.

[0062] In addition, in the case where the first polling instruction PS1 is not received, the first storage cache module 101 only stores the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during transmission; after the first command module 102 receives the first polling instruction PS1, it controls the first storage cache module 101 to output the first characterization signal flag1 that characterizes the error conditions of the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during transmission. Based on this first characterization signal flag1, the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 can be obtained.

[0063] In some embodiments, the first characterization signal flag1 may be a binary string of numbers. For example, if an error is detected in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during transmission, 1 is recorded; if no error is detected in the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during transmission, 0 is recorded. Thus, after a period of time, the first characterization signal flag1 is a binary string composed of 0 and 1. In other embodiments, the first characterization signal flag1 may also be a decimal value. For example, the first storage cache module 101 may be a counter, and if an error is detected in the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during transmission, it is incremented by 1. Thus, after a period of time, the first characterization signal flag1 is a decimal value related to the number of errors.

[0064] In some embodiments, the first storage buffer module 101 may be a first-in, first-out (FIFO) register. Using a first-in, first-out register as the first storage buffer module 101 can cache continuous data streams to prevent data loss during storage operations. In addition, error conditions during the transmission of the first data data1 are aggregated for stacking and storage, which can avoid frequent bus operations and is beneficial to improving the data transmission speed.

[0065] In addition, in some embodiments, the first clock signal CLK1 may be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 may also be externally provided, such as being generated by the controller that generates the first polling instruction PS1.

[0066] The basic chip 100 provided in the above embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. In this way, the chip area of the basic chip 100 can be effectively utilized, reducing the chip area pressure on the controller and the storage chip, and saving the chip area of the controller and the storage chip.

[0067] Moreover, since the basic chip 100 can perform second error correction code encoding processing on the first data data1 and the first encoded data ecc1 to obtain the second encoded data ecc2, and can transmit the second encoded data ecc2, the first encoded data ecc1, and the first data data1 to the storage chip, facilitating the first error detection and correction processing based on the second encoded data during the reading stage. Therefore, it is possible to detect whether errors occur in the first data data1 and the first encoded data ecc1 during the writing stage or the reading stage and correct the errors, and the first data data1 and the first encoded data ecc1 after the first error detection and correction processing can be transmitted to the controller for the controller to perform error detection and correction processing again, thereby improving the error detection and correction ability of the storage system and enhancing the data error detection and correction accuracy rate. In addition, compared with the solution where the basic chip does not perform error detection and correction on the first encoded data, the basic chip 100 of the present disclosure embodiment performs error detection and correction on the first encoded data ecc1, so the accuracy rate of the first encoded data ecc1 transmitted to the storage chip is improved, further ensuring the accuracy rate of error detection and correction of the first data data1.

[0068] In addition, the basic chip 100 may also have the functions of data serial processing and deserialization processing, which is beneficial to reducing the transmission channels between the controller and the basic chip 100, and reducing the transmission channels between the storage chip and the basic chip 100, thereby saving the number of data transmission ports required on the controller, the basic chip 100, and the storage chip, and further saving the chip areas of the controller, the basic chip 100, and the storage chip.

[0069] Another embodiment of the present disclosure also provides a storage system, which includes a controller, a storage chip, and a basic chip as provided in the foregoing embodiment. The storage system provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiment, reference may be made to the detailed description of the foregoing embodiment, and details will not be repeated below.

[0070] Figure 7 It is a schematic diagram of the first structure of the storage system provided in the embodiment of the present disclosure.

[0071] Reference Figure 7 As shown in [figure reference], the storage system includes: a basic chip 200, a controller 300, and a storage chip 400; the controller 300 is configured to perform a first error correction code encoding process on the first data data1 in the write stage to generate a first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 to the basic chip 200; the basic chip 200 is configured to receive the first data data1 and the first encoded data ecc1 in the write stage and perform a second error correction code encoding process to generate a second encoded data ecc2, transmit a second data data2 to the storage chip 400 in the write stage, the second data data2 includes the first data data1, the first encoded data ecc1, and the second encoded data ecc2, receive the second data data2 from the storage chip 400 in the read stage and perform a first error detection and correction process, and transmit a third data data3 to the controller 300 in the read stage, the third data data3 is the first data data1 after the first error detection and correction process and the first encoded data ecc1 after the first error detection and correction process; the storage chip 400 is configured to receive the second data data2 from the basic chip 200 in the write stage and store the second data data2, and transmit the second data data2 to the basic chip 200 in the read stage; the controller 300 is further configured to receive the third data data3 from the basic chip 200 in the read stage, perform a second error detection and correction process on the third data data3, and transmit the first data data1 after the second error detection and correction process.

[0072] In the above storage system, the error correction code encoding process and error detection and correction process performed on data can both be implemented by the base chip 200. Thus, the storage chip 400 does not need to perform the encoding process and error detection and correction process, and the base chip 200 can share the encoding process and error detection and correction process required by the controller 300, so that the functions required by the controller 300 and the storage chip 400 are relatively reduced. Therefore, the pressure of the tight chip area of the controller 300 and the storage chip 400 can be alleviated, so as to better improve the performance of the controller 300 and the storage chip 400. For example, the reliability of the storage chip 400 can be improved, thereby enhancing the storage performance of the storage system. Moreover, both the base chip 200 and the controller 300 can perform error detection and correction processing on the first data, which is beneficial to improving the data error detection and correction ability of the storage system.

[0073] In some embodiments, the storage system may be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system may also be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0074] The controller 300 may include: a first encoding module 301 configured to perform a first error correction code encoding process on the first data data1 in the write stage to generate first encoded data ecc1; a second error detection and correction module 302 configured to receive the third data data3 and perform a second error detection and correction process in the read stage.

[0075] The base chip 200 can provide a high-speed interface for data transmission in the storage system. In addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform a Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used to perform error detection and correction on the transmitted data.

[0076] Figure 8 This is the second structural schematic diagram of the storage system provided by the embodiments of the present disclosure. Refer to Figure 8, in some embodiments, the base chip 200 may include: a second encoding module 210 configured to receive a first data data1 and a first encoded data ecc1 during a write phase and perform a second error correction code encoding process to generate a second encoded data ecc2; a first error detection and correction module 220 configured to receive a second data data2 and perform a first error detection and correction process during a read phase.

[0077] Regarding the working principle of the storage system, reference may be made to the corresponding description of the foregoing embodiments, which will not be elaborated herein. It can be understood that the controller 300 can perform a second error detection and correction process on the first data data1 after the first error detection and correction process.

[0078] In some embodiments, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, and the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm. Using different compilation algorithms for error detection and correction of data is beneficial to further improving the accuracy rate of error detection and correction of data.

[0079] Specifically, the encoding algorithms used by the second encoding module 210 and the first encoding module 301 may be different, and the decoding algorithms used by the first error detection and correction module 220 and the second error detection and correction module 302 may be different.

[0080] It should be noted that in some other embodiments, the first compilation algorithm and the second compilation algorithm may also be the same.

[0081] Reference Figure 8 , the storage chip 400 may include: a first storage module 410 for storing the first data data1 and the first encoded data ecc1; a second storage module 420 for storing the second encoded data ecc2. For example, the first storage module 410 may store 272-bit data, and the second storage module 420 may store 32-bit data.

[0082] Figure 9 This is the third structural schematic diagram of the storage system provided by the embodiments of the present disclosure. Reference Figure 9, in some embodiments, the base chip 200 may further include: a first serial-to-parallel conversion module 230, which is configured to receive a first data data1 and a first encoded data ecc1 during the write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the second encoding module 210; a first parallel-to-serial conversion module 240, which is configured to receive a third data data3 during the read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller 300.

[0083] Specifically, the first serial-to-parallel conversion module 230 is connected between the data transmission port of the controller 300 and the data transmission port of the second encoding module 210. In this way, the number of transmission channels between the controller 300 and the base chip 200 can be less than the sum of the bit numbers of the first data data1 and the first encoded data ecc1, thereby saving the number of transmission channels between the controller 300 and the base chip 200, saving the number of data transmission ports required to be set on the base chip 200 and the controller 300, facilitating reducing the complexity of the electrical connection structure between the controller 300 and the base chip 200, and saving the chip areas of the controller 300 and the base chip 200.

[0084] Reference Figure 9 , the base chip 200 may further include: a second parallel-to-serial conversion module 250, which is configured to receive a second data data2 from the second encoding module 210 during the write phase, perform a second parallel-to-serial conversion process on the second data data2, and transmit the second data data2 after the second parallel-to-serial conversion process to the storage chip 400; a second serial-to-parallel conversion module 260, which is configured to receive the second data data2 from the storage chip 400 during the read phase, perform a second serial-to-parallel conversion process on the second data data2, and transmit the second data data2 after the second serial-to-parallel conversion process to the first error detection and correction module 220.

[0085] In this way, the number of transmission channels between the storage chip 400 and the base chip 200 can be less than the sum of the bit numbers of the first data data1, the first encoded data ecc1, and the second encoded data ecc2, thereby saving the number of transmission channels between the storage chip 400 and the base chip 200, facilitating reducing the number of data transmission ports required to be set on the base chip 200 and the storage chip 400, facilitating reducing the complexity of the electrical connection structure between the storage chip 400 and the base chip 200, and saving the chip areas of the storage chip 400 and the base chip 200.

[0086] It is understandable that the number of data transmission channels between the controller 300 and the base chip 200 is M, and the number of data transmission channels between the base chip 200 and the storage chip 400 is N. Both M and N are positive integers greater than 1, and N is greater than M. This is because, in addition to transmitting the first data data1 and the first encoded data ecc1 between the base chip 200 and the storage chip 400, the second encoded data ecc2 also needs to be transmitted.

[0087] Reference Figure 10 , Figure 10 For Figure 8 a basic structural schematic diagram, in some embodiments, the base chip 200 is further configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process; the storage system further includes: a first register 501, and the first register 501 is configured to store the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process.

[0088] Specifically, referring to Figure 10 , the base chip 200 may include: a first storage buffer module 201, and the first storage buffer module 201 is configured to store the error conditions of the first data data1, the first encoded data ecc1, and the second encoded data ecc2 during the transmission process; a first command module 202, and the first command module 202 receives the first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 201 is further configured to output a first characterization signal flag1 to the first register 500 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1, the first encoded data ecc1, or the second encoded data ecc2 during the transmission process.

[0089] In some embodiments, the controller 300 may also be configured to issue the first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues an inquiry to control the first storage buffer module 201 to output the first characterization signal flag1 to the first register 501. It is understandable that in other embodiments, the first polling instruction may also be provided by an external circuit.

[0090] Reference Figure 10, in some embodiments, the controller 300 may also be configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record the first data data1 after the first error detection and correction process and the error situation of the first encoded data during the ecc1 transmission; the storage system may further include: a second register 502, which is configured to store the first data data1 after the first error detection and correction process and the error situation of the first encoded data ecc1 after the first error detection and correction process during the transmission.

[0091] Reference Figure 10 , in some embodiments, the controller 300 may further include: a second storage buffer module 271, which is configured to store the first data data1 after the first error detection and correction process and the error situation of the first encoded data ecc1 during the transmission; a second command module 281, which receives the second polling instruction PS2 and generates a second command signal CMD2 and a second clock signal CLK2; the second storage buffer module 271 is further configured to output a second characterization signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, and the second characterization signal flag2 characterizes the error situation of the first data data1 or the first encoded data after the first error detection and correction process during the transmission.

[0092] It can be understood that the first register 501 and the second register 502 may be the same register.

[0093] For the storage system provided in the above embodiments, the base chip 200 can implement the error detection and correction function. Correspondingly, the storage chip 400 does not need to have the error detection and correction function, and the base chip 200 can share the error detection and correction function originally borne by the controller 300. Therefore, it is beneficial to save the space area of the controller 300 and the storage chip 400, improve the storage performance of the storage chip 400, and thus improve the storage performance of the storage system. At the same time, both the base chip 200 and the controller 300 can perform error detection and correction processing on the first data. Therefore, the data error detection and correction accuracy rate of the storage system is high, and it is beneficial to improve the RAS performance of the storage system, that is, to improve the reliability, availability, and serviceability of the storage system.

[0094] In addition, the settings of the first error detection and correction module 220 and the second error detection and correction module 302 enable error detection and correction to be performed on different data transmission paths, improve the error detection and correction ability of the storage system, and are beneficial to locating the specific data transmission path where the error occurs.

[0095] Correspondingly, an embodiment of the present disclosure further provides a semiconductor structure, which may include the storage system provided in the foregoing embodiment. The semiconductor structure provided in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated hereinafter.

[0096] Figure 11 It is a schematic cross-sectional structure diagram of the semiconductor structure provided in the embodiments of the present disclosure.

[0097] Referring to Figure 11 , the semiconductor structure includes: a carrier substrate 600; the storage system provided in the foregoing embodiment, and both the controller 300 and the base chip 200 are located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the carrier substrate 600.

[0098] Among them, the semiconductor structure may include a plurality of storage chips 400 stacked in sequence. The semiconductor structure may be a memory such as a DRAM device or an SRAM device.

[0099] In some embodiments, the carrier substrate 600 may be a PCB (Printed Circuit Board) circuit board. For a detailed description of the storage system, reference may be made to the foregoing embodiments, which will not be repeated here.

[0100] The semiconductor structure may be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving the size in the horizontal direction, and using the base chip 200 in the semiconductor structure to implement the ECC error detection and correction function is beneficial to improving the performance of the semiconductor structure.

[0101] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A basic chip is applied to a storage system. It is characterized in that it includes: The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data and the first encoded data to generate second encoded data. During the write phase, transmit second data to a storage chip. The second data includes the first data, the first encoded data, and the second encoded data; The basic chip is further configured to receive the second data from the storage chip and perform first error detection and correction processing during a read phase, and transmit third data during the read phase. The third data is the first data after the first error detection and correction processing and the first encoded data after the first error detection and correction processing; The basic chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record the error conditions of the first data, the first encoded data, and the second encoded data during the transmission process based on the first error detection flag signal.

2. The basic chip according to claim 1, it is characterized in that the basic chip includes: A second encoding module, which is configured to receive the first data and the first encoded data during the write phase and perform the second error correction code encoding processing to generate the second encoded data; A first error detection and correction module, which is configured to receive the second data and perform the first error detection and correction processing during the read phase.

3. The basic chip according to claim 2, it is characterized in that the basic chip further includes: A first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data during the write phase, perform first serial-to-parallel conversion processing on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion processing to the second encoding module; A first parallel-to-serial conversion module, which is configured to receive the third data during the read phase, perform first parallel-to-serial conversion processing on the third data, and transmit the third data after the first parallel-to-serial conversion processing to a controller.

4. The basic chip according to claim 3, it is characterized in that the basic chip further includes: A second parallel-to-serial conversion module, which is configured to receive the second data from the second encoding module during the write phase, perform second parallel-to-serial conversion processing on the second data, and transmit the second data after the second parallel-to-serial conversion processing to the storage chip; A second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip during the read phase, perform second serial-to-parallel conversion processing on the second data, and transmit the second data after the second serial-to-parallel conversion processing to the first error detection and correction module.

5. The base chip according to claim 1, wherein, the base chip further includes: a first storage buffer module configured to store the error conditions during the transmission of the first data, the first encoded data, and the second encoded data; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, where the first characterization signal characterizes the error conditions during the transmission of the first data, the first encoded data, or the second encoded data.

6. The base chip according to claim 1, wherein, the encoding algorithms used for the first error correction code encoding process and the second error correction code encoding process are different.

7. A storage system, wherein, it includes a controller, a base chip, and a storage chip, and further includes: the controller is configured to perform a first error correction code encoding process on the first data during the write phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; the base chip is configured to receive the first data and the first encoded data during the write phase and perform a second error correction code encoding process to generate second encoded data, transmit second data to the storage chip during the write phase, where the second data includes the first data, the first encoded data, and the second encoded data, receive the second data from the storage chip during the read phase and perform a first error detection and correction process, and transmit third data to the controller during the read phase, where the third data is the first data after the first error detection and correction process and the first encoded data after the first error detection and correction process; the storage chip is configured to receive the second data from the base chip during the write phase and store the second data, and transmit the second data to the base chip during the read phase; the controller is further configured to receive the third data from the base chip during the read phase, perform a second error detection and correction process on the third data, and transmit the first data after the second error detection and correction process; the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions during the transmission of the first data, the first encoded data, and the second encoded data based on the first error detection flag signal; the storage system further includes: a first register configured to store the error conditions during the transmission of the first data, the first encoded data, and the second encoded data.

8. The storage system according to claim 7, wherein, the controller includes: A first encoding module, which is configured to receive the first data and perform the first error correction code encoding process during the writing stage to generate the first encoded data; A second error detection and correction module, which is configured to receive the third data and perform the second error detection and correction process during the reading stage.

9. The storage system according to claim 7, wherein, the base chip includes: A second encoding module, which is configured to receive the first data and the first encoded data and perform the second error correction code encoding process during the writing stage to generate the second encoded data; A first error detection and correction module, which is configured to receive the second data and perform the first error detection and correction process during the reading stage.

10. The storage system according to claim 9, wherein, the base chip further includes: A first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data during the writing stage, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion process to the second encoding module; A first parallel-to-serial conversion module, which is configured to receive the third data and perform a first parallel-to-serial conversion process on the third data during the reading stage, and transmit the third data after the first parallel-to-serial conversion process to the controller.

11. The storage system according to claim 10, wherein, the base chip further includes: A second parallel-to-serial conversion module, which is configured to receive the second data from the second encoding module and perform a second parallel-to-serial conversion process during the writing stage, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; A second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip and perform a second serial-to-parallel conversion process during the reading stage, and transmit the second data after the second serial-to-parallel conversion process to the first error detection and correction module.

12. The storage system according to claim 7, wherein, the storage chip includes: A first storage module, which is used to store the first data and the first encoded data; A second storage module, which is used to store the second encoded data.

13. The storage system according to claim 7, wherein, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

14. The storage system according to claim 7, wherein, the base chip includes: A first storage buffer module, which is configured to store the error conditions of the first data, the first encoded data, and the second encoded data during transmission; A first command module, which receives a first polling instruction and generates a first command signal and a first clock signal; The first storage buffer module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, where the first characterization signal characterizes the error conditions of the first data, the first encoded data, or the second encoded data during transmission.

15. The storage system according to claim 14, wherein, the controller is further configured to issue the first polling instruction to the first command module.

16. The storage system according to claim 7, wherein, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record the error conditions of the first data and the first encoded data after the first error detection and correction process during transmission; The storage system further includes: A second register, which is configured to store the error conditions of the first data and the first encoded data after the first error detection and correction process during transmission.

17. The storage system according to claim 16, wherein, the controller includes: A second storage buffer module, which is configured to store the error conditions of the first data and the first encoded data after the first error detection and correction process during transmission; A second command module, which receives a second polling instruction and generates a second command signal and a second clock signal; The second storage buffer module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, where the second characterization signal characterizes the error conditions of the first data or the first data or the first encoded data during transmission after the first error detection and correction process.

18. A semiconductor structure, wherein, it includes: A carrier substrate; The storage system according to any one of claims 7-17, and the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

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