Semiconductor structure and method of fabricating the same
By forming mask layers with different etching rates on the substrate and adjusting the trench spacing, the problem of uneven key dimensions of trenches in the doubling process was solved, resulting in more uniform trench formation and reduced equipment costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-11-05
- Publication Date
- 2026-05-19
AI Technical Summary
In the doubling process, the key dimensions of the trenches are uneven due to process errors such as photolithography, etching, and thin film.
A first patterned mask layer and a second patterned mask layer with different etching rates are formed on the substrate. By adjusting the spacing between adjacent mask pattern structures, the critical dimension uniformity of the trench is controlled.
This achieves uniformity in key dimensions of the trenches, reducing the need for lithography equipment and the cost of purchasing the equipment.
Smart Images
Figure CN116092920B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] The pitch doubling process flow is a known technique for miniaturizing critical dimensions. In this process, a mask material layer and a patterned photoresist are first formed on a substrate, and then sidewalls are formed on both sides of the patterned photoresist. The patterned photoresist is then removed, and the mask material layer is etched using the sidewalls as a mask to form a patterned mask layer. Subsequently, trenches are formed by etching the substrate based on this patterned mask layer.
[0003] The above method can effectively reduce the demand for photolithography equipment and lower the cost of purchasing the equipment. However, in this process, due to the overlapping errors of photolithography, etching, and thin film processing, the critical dimensions of the final trenches will be uneven. Summary of the Invention
[0004] Based on this, embodiments of this application provide a semiconductor structure and a method for fabricating the same.
[0005] A method for fabricating a semiconductor structure, comprising:
[0006] Provide a base;
[0007] A first patterned mask layer and a second patterned mask layer are formed on the substrate at intervals, wherein the first patterned mask layer and the second patterned mask layer have different etching rates under the same etching conditions;
[0008] The substrate is etched based on the first patterned mask layer and the second patterned mask layer.
[0009] In one embodiment, forming a first patterned mask layer and a second patterned mask layer spaced apart on the substrate includes:
[0010] A patterned intermediate mask layer is formed on the substrate;
[0011] The first patterned mask layer is formed on the sidewall of the intermediate mask layer;
[0012] The intermediate mask layer is patterned to form the second patterned mask layer.
[0013] In one embodiment, forming a patterned intermediate mask layer on the substrate includes:
[0014] An intermediate mask material layer is formed on the substrate;
[0015] The intermediate mask material layer is patterned to form the intermediate mask layer.
[0016] In one embodiment, the step of patterning the intermediate mask material layer to form the intermediate mask layer includes:
[0017] A first patterned photoresist is formed on the intermediate mask material layer;
[0018] Based on the first patterned photoresist, the intermediate mask material layer is etched, and the remaining intermediate mask material layer constitutes the intermediate mask layer.
[0019] In one embodiment, prior to forming the first patterned photoresist on the intermediate mask material layer, the method further includes:
[0020] Clean the surface of the intermediate mask material layer.
[0021] In one embodiment, after etching the intermediate mask material layer based on the first patterned photoresist, the method further includes:
[0022] Remove the first patterned photoresist.
[0023] In one embodiment,
[0024] Before performing patterning processing on the intermediate mask layer to form the second patterned mask layer, the process includes:
[0025] A patterned sacrificial mask layer is formed on the intermediate mask layer;
[0026] The step of patterning the intermediate mask layer to form the second patterned mask layer includes:
[0027] Based on the sacrificial mask layer, the intermediate mask layer is etched, and the remaining intermediate mask layer constitutes the second patterned mask layer.
[0028] In one embodiment,
[0029] The process of forming the first patterned mask layer on the sidewall of the intermediate mask layer includes:
[0030] A second patterned photoresist is formed on the intermediate mask layer;
[0031] A first mask material layer is formed, which covers the second patterned photoresist, the intermediate mask layer, and the substrate;
[0032] The first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate is removed. The remaining first mask material layer located on the sidewall of the intermediate mask layer constitutes the first patterned mask layer, and the remaining first mask material layer located on the sidewall of the second patterned photoresist constitutes the sacrificial mask layer.
[0033] In one embodiment, prior to forming the second patterned photoresist on the intermediate mask layer, the method further includes:
[0034] Clean the surface of the intermediate mask layer.
[0035] In one embodiment, after removing the first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate, the method further includes:
[0036] The cleaning process removes the residual first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate.
[0037] Remove the second patterned photoresist.
[0038] In one embodiment, the second patterned mask layer includes a plurality of second mask structures, and the first patterned mask layer includes a first mask structure located on both sides of the plurality of second mask structures;
[0039] Before etching the substrate based on the second patterned mask layer and the first patterned mask layer, the method further includes:
[0040] The distance between adjacent first mask structures and second mask structures is measured as a first dimension, and the distance between adjacent second mask structures is measured as a second dimension;
[0041] Based on the relationship between the first dimension and the second dimension, the etching conditions for etching the substrate are determined.
[0042] In one embodiment,
[0043] When the first size is larger than the second size, under the etching conditions of etching the substrate, the etching rate of the first patterned mask layer is less than the etching rate of the second patterned mask layer.
[0044] In one embodiment,
[0045] When the first size is smaller than the second size, under the etching conditions of etching the substrate, the etching rate of the first patterned mask layer is greater than the etching rate of the second patterned mask layer.
[0046] In one embodiment, after etching the substrate based on the first patterned mask layer and the second patterned mask layer, the method further includes:
[0047] Remove the first patterned mask layer and the second patterned mask layer.
[0048] A semiconductor structure prepared by any of the methods described above.
[0049] The aforementioned semiconductor structure and its fabrication method, by forming a first patterned mask layer and a second patterned mask layer with different etching rates on the substrate, allows the first and second patterned structures to have different shrinkage rates during etching, thereby adjusting the spacing between adjacent mask patterned structures. Therefore, this application enables the trenches ultimately formed on the substrate to have more uniform critical dimensions. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 A flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0052] Figures 2-11 This is a schematic diagram of the fabrication process of the semiconductor structure provided in one embodiment;
[0053] Figures 12-13 This is a schematic diagram of the fabrication process of the semiconductor structure provided in another embodiment.
[0054] Explanation of reference numerals in the attached figures: 100 - substrate, 200 - first patterned mask layer, 201 - first mask material layer, 300 - second patterned mask layer, 301 - intermediate mask layer, 3011 - intermediate mask material layer, 400 - first patterned photoresist, 401 - first photoresist layer, 500 - sacrificial mask layer, 600 - second patterned photoresist, 601 - second photoresist layer. Detailed Implementation
[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0060] As stated in the background section, pitch doubling process flow is a known technique for miniaturizing critical dimensions. This process method specifically includes:
[0061] Step S10: Form a mask material layer and a photoresist layer on the substrate;
[0062] Step S20: The photoresist layer is patterned to form a patterned photoresist.
[0063] Step S30: Deposit an oxide material layer or a nitride material layer on the substrate and the patterned photoresist.
[0064] Step S40: Remove the oxide material layer or nitride material layer from the substrate surface and the top surface of the patterned photoresist, and retain the oxide material layer or nitride material layer on the sidewalls to form the sidewalls of the patterned photoresist.
[0065] Step S50: Remove the patterned photoresist;
[0066] Step S60: Using the sidewalls as a mask, the mask material layer is etched to form a patterned mask layer;
[0067] Step S70: Remove the sidewall mask;
[0068] Step S80: Based on the patterned mask layer, the substrate is etched to form trenches.
[0069] When forming trenches in a substrate using this method, the critical dimensions of the final trenches will be uneven due to the overlapping errors in photolithography, etching, and thin film processes.
[0070] Based on this, embodiments of this application propose a semiconductor structure and its fabrication method that can improve the uniformity of critical dimensions of each trench.
[0071] In one embodiment, see Figure 1 A method for fabricating a semiconductor structure includes the following steps:
[0072] Step S100: Provide a substrate, the substrate including substrate 100;
[0073] In step S200, a first patterned mask layer 200 and a second patterned mask layer 300 are formed on the substrate 100 at intervals. The first patterned mask layer 200 and the second patterned mask layer 300 have different etching rates under the same etching conditions. Please refer to [link to relevant documentation]. Figure 10 ;
[0074] Step S300: Based on the first patterned mask layer 200 and the second patterned mask layer 300, the substrate 100 is etched. Please refer to [link to relevant documentation]. Figure 11 .
[0075] In step S100, the substrate may include a semiconductor substrate, such as a silicon substrate. The semiconductor substrate itself may serve as substrate 100. Alternatively, the substrate may include a semiconductor substrate (not shown) and a functional film layer formed on the semiconductor substrate.
[0076] In step S200, both the first patterned mask layer 200 and the second patterned mask layer 300 are formed on the substrate 100, thereby jointly serving as masks for etching the substrate 100. Specifically, the first patterned mask layer 200 may include a plurality of first patterned structures 210, and the second patterned mask layer 300 may include a plurality of second patterned structures 310. The plurality of first patterned structures 210 and the plurality of second patterned structures 310 all serve as mask pattern structures for etching the substrate 100.
[0077] The first patterned mask layer 200 and the second patterned mask layer 300 can be formed in different processes or simultaneously; there is no limitation on this.
[0078] In step S200, during the actual process of etching the substrate 100, the first patterned structure 210 of the first patterned mask layer 200 and the second patterned structure 310 of the second patterned mask layer 300 are simultaneously partially etched and shrink inward. Since the first patterned mask layer 200 and the second patterned mask layer 300 have different etching rates under the same etching conditions, the shrinkage rates of the first patterned structure 210 and the second patterned structure 310 are different.
[0079] Meanwhile, the trenches formed within the substrate 100 are formed by etching based on the first patterned structure 210 and the second patterned structure 310. Both the first patterned structure 210 and the second patterned structure 310 serve as mask pattern structures for etching the substrate 100.
[0080] Therefore, the dimensions of the first patterned structure 210 and the second patterned structure 310 will affect the spacing between adjacent mask patterned structures, and thus affect the dimensions of the trenches formed in the substrate 100.
[0081] Therefore, in this embodiment, the spacing between adjacent mask pattern structures can be adjusted by the different shrinkage rates of the first patterned structure 210 and the second patterned structure 310, so that the trenches finally formed on the substrate 100 have relatively uniform key dimensions.
[0082] In one embodiment, see Figure 10 or Figure 12 The second patterned mask layer 300 includes a plurality of second mask structures 310, and the first patterned mask layer 200 includes a first mask structure 210 located on both sides of the plurality of second mask structures 310.
[0083] The word "multiple" here can refer to two or more.
[0084] Before step S300, the following are also included:
[0085] Step S310: Measure the distance between adjacent first mask structure 210 and second mask structure 310 as the first dimension CD1, and the distance between adjacent second mask structure 310 as the second dimension CD2.
[0086] Step S320: Determine the etching conditions for etching the substrate 100 based on the relationship between CD1 and CD2.
[0087] In step S310, the distance between one of the first mask structures 210 and its adjacent second mask structure 310 can be measured using a measuring instrument to obtain CD1. Alternatively, the distances between each adjacent first mask structure 210 and its adjacent second mask structure 310 can be measured, and their average value can be taken as CD1.
[0088] Simultaneously, the distance between two adjacent second mask structures 310 is measured using a measuring machine to serve as CD2. Alternatively, the distance between each pair of adjacent second mask structures 310 can be measured, and their average value can be taken as CD2.
[0089] In step S320, the etching conditions for etching the substrate 100 can be determined by comparing the size relationship between CD1 and CD2.
[0090] As an example, dry etching can be performed on substrate 100. Etching conditions may include the composition of the etching gas. Additionally, etching conditions may also include chamber pressure, etching power, gas flow rate, temperature, etc.
[0091] In one embodiment, see Figure 12 as well as Figure 13When CD1 is greater than CD2, under the etching conditions of etching substrate 100, the etching rate of the first patterned mask layer 200 is less than the etching rate of the second patterned mask layer 300.
[0092] At this time, the shrinkage rate of the second mask structure 310 is greater than that of the first mask structure 210, which makes the expansion rate of CD2 greater than that of CD1, so that the final CD1 and CD2 are equal.
[0093] Therefore, this embodiment can make the trenches ultimately formed on the substrate 100 have more uniform critical dimensions.
[0094] In one embodiment, see Figure 10 as well as Figure 11 When CD1 is less than CD2, under the etching conditions of etching substrate 100, the etching rate of the first patterned mask layer 200 is greater than the etching rate of the second patterned mask layer 300.
[0095] At this time, during the etching process, the shrinkage rate of the first mask structure 210 is greater than that of the second mask structure 310, which makes the expansion rate of CD1 greater than that of CD2, so that the final CD1 and CD2 are equal.
[0096] Therefore, this embodiment can make the trenches ultimately formed on the substrate 100 have more uniform critical dimensions.
[0097] In one embodiment, step S200 includes:
[0098] Step S210: A patterned intermediate mask layer 301 is formed on the substrate 100. Please refer to [link to relevant documentation]. Figure 3 ;
[0099] Step S220: A first patterned mask layer 200 is formed on the sidewall of the intermediate mask layer 301. Please refer to [link to relevant documentation]. Figure 8 ;
[0100] Step S230: The intermediate mask layer 301 is patterned to form the second patterned mask layer 300. Please refer to [link to relevant documentation]. Figure 10 .
[0101] In step S210, the intermediate mask layer 301 is a patterned film layer. The material of the intermediate mask layer 301 can be a hard mask material such as SiBN or SiCON.
[0102] In step S220, the material of the first patterned mask layer 200 can be an oxide or a nitride, etc. The material of the first patterned mask layer 200 is different from the material of the intermediate mask layer 301, so that the material of the first patterned mask layer 200 is different from the material of the second patterned mask layer 300 formed by the intermediate mask layer 301, thereby allowing the two to have different etching rates under the same etching conditions.
[0103] In step S230, the second patterned mask layer 300 is a patterned film layer formed after patterning the intermediate mask layer 301, and has finer dimensions than the intermediate mask layer 301.
[0104] As an example, the dimensions of the second patterned mask layer 300 may be equal to or comparable to those of the first patterned mask layer 200.
[0105] In this embodiment, the fabrication of the patterned intermediate mask layer 301 facilitates the formation of the first patterned mask layer 200 and the second patterned mask layer 300.
[0106] In one embodiment, step S210 includes:
[0107] Step S211: An intermediate mask material layer 3011 is formed on the substrate 100. Please refer to [link / reference]. Figure 2 ;
[0108] Step S212: The intermediate mask material layer 3011 is patterned to form the intermediate mask layer 301. Please refer to [link to relevant documentation]. Figure 4 .
[0109] In step S211, an intermediate mask material layer 3011 may be deposited on the surface of the substrate 100 to cover the substrate 100.
[0110] In step S212, as an example, the intermediate mask material layer 3011 can be patterned using a photolithography process. Specifically, this can include:
[0111] Step S2121: A first patterned photoresist 400 is formed on the intermediate mask material layer 3011. Please refer to [link to relevant documentation]. Figure 3 ;
[0112] Step S2122: Based on the first patterned photoresist 400, the intermediate mask material layer 3011 is etched. The remaining intermediate mask material layer 3011 constitutes the intermediate mask layer 301. Please refer to [link to relevant documentation]. Figure 4 .
[0113] In step S2121, a first photoresist layer 401 can be coated onto the surface of the mask material layer 3011 using spin coating, followed by soft baking. Then, exposure is performed at a predetermined location, and development is performed after exposure to remove a portion of the first photoresist layer 401. The remaining photoresist material constitutes the first patterned photoresist 400.
[0114] To ensure proper adhesive application, the surface of the intermediate mask material layer 3011 can be cleaned before this step.
[0115] In step S2122, the intermediate mask material layer 3011 is etched using the first patterned photoresist 400 as a mask, thereby forming the patterned intermediate mask layer 301.
[0116] As an example, after the intermediate mask layer 301 is formed, the first patterned photoresist 400 can be removed to facilitate subsequent process steps.
[0117] In one embodiment, prior to step S230, the method further includes:
[0118] A patterned sacrificial mask layer 500 is formed on the intermediate mask layer 301. (See also...) Figure 9 .
[0119] Step S230 includes: etching the intermediate mask layer 301 based on the sacrificial mask layer 500, the remaining intermediate mask layer 301 forming the second patterned mask layer 300. (See also...) Figure 10 .
[0120] In this embodiment, a sacrificial mask layer 500 is formed as an etching mask for the intermediate mask layer 301, thereby enabling effective etching of the intermediate mask layer 301.
[0121] In one embodiment, step S220 includes:
[0122] Step S221: A second patterned photoresist 600 is formed on the intermediate mask layer 301. Please refer to [link / reference]. Figure 6 ;
[0123] Step S222: A first mask material layer 201 is formed, which covers the second patterned photoresist 600, the intermediate mask layer 301, and the substrate 100. (See also...) Figure 7 ;
[0124] Step S223: Remove the first mask material layer 201 located on the top surface of the second patterned photoresist 600, the top surface of the intermediate mask layer 301, and the top surface of the substrate 100. The remaining first mask material layer 201 located on the sidewall of the intermediate mask layer constitutes the first patterned mask layer 200. The remaining first mask material layer 201 located on the sidewall of the second patterned photoresist 600 constitutes the sacrificial mask layer 500. Please refer to [link to relevant documentation]. Figure 8 .
[0125] In step S221, a second photoresist layer 601 can be coated onto the substrate and the intermediate mask layer 301 using spin coating. Then, the second photoresist layer 601 is exposed and developed to form a second patterned photoresist 600.
[0126] To ensure good spin coating quality, the surface of the intermediate mask layer 301 can be cleaned and dried before this step.
[0127] In step S222, oxides or nitrides can be deposited on the surface of the second patterned photoresist 600, the surface of the intermediate mask layer 301, and the surface of the substrate 100 as the first mask material layer 201.
[0128] In step S223, the first mask material layer 201 located on the top surface of the second patterned photoresist 600, the top surface of the intermediate mask layer 301, and the top surface of the substrate 100 can be removed by anisotropic dry etching, while retaining the first mask material layer 201 located on the sidewall of the intermediate mask layer and the sidewall of the second patterned photoresist 600.
[0129] The thicknesses of the first patterned mask layer 200 located on the sidewall of the intermediate mask layer and the sacrificial mask layer 500 located on the sidewall of the second patterned photoresist 600 can be monitored using a linewidth measurement machine.
[0130] In this embodiment, the formation of the second patterned photoresist 600 allows the sacrificial mask layer 500 and the first patterned mask layer 200 to be formed synchronously, thereby facilitating the control of the spacing between the first patterned mask layer 200 and the second patterned mask layer 300.
[0131] In one embodiment, after step S222, the method further includes:
[0132] Step S223: Clean and remove the residual first mask material layer 201 located on the top surface of the second patterned photoresist 600, the top surface of the intermediate mask layer 301, and the top surface of the substrate 100.
[0133] Step S224, remove the second patterned photoresist 600, please refer to [link / reference]. Figure 9 .
[0134] At this point, based on the sacrificial mask layer 500 formed by the first mask material layer 201, the intermediate mask layer 301 can be well patterned to form the second patterned mask layer 300.
[0135] Of course, in other embodiments, the sacrificial mask layer 500 and the first patterned mask layer 200 may also be formed separately in different process steps. There is no limitation on this.
[0136] For example, a first patterned mask layer 200 can be formed first, followed by the formation of a sacrificial mask layer 500. Specifically, step S220 may also include:
[0137] First, a first mask material layer 201 is deposited on the surface of the intermediate mask layer 301 and the surface of the substrate 100. Then, the first mask material layer 201 located on the top surface of the intermediate mask layer 301 and the top surface of the substrate 100 is removed by anisotropic dry etching, thereby forming a first patterned mask layer 200 on the sidewall of the intermediate mask layer 301.
[0138] Next, a second patterned photoresist 600 can be formed on the intermediate mask layer 301. Then, by masking with a mask, sacrificial mask material layers are deposited on the surfaces of the intermediate mask layer 301 and the second patterned photoresist 600. Subsequently, the sacrificial mask material layers located on the top surfaces of the intermediate mask layer 301 and the second patterned photoresist 600 are removed by anisotropic dry etching. The remaining sacrificial mask material layers on the sidewalls of the second patterned photoresist 600 constitute the sacrificial mask layer 500.
[0139] Alternatively, in other embodiments, the intermediate mask layer 301 may not be formed.
[0140] For example, a first patterned photoresist 400 can be formed directly on the substrate 100. Then, a first mask material layer 201 is formed on the surface of the first patterned photoresist 400 and the surface of the substrate 100. Then, the first mask material layer 201 located on the top surface of the first patterned photoresist 400 and the top surface of the substrate 100 is removed by anisotropic dry etching, thereby forming the first patterned mask layer 200 on the sidewall of the first patterned photoresist 400.
[0141] The first patterned photoresist 400 is then removed. A second patterned photoresist 600 is then formed between the two first mask structures 210 of the first patterned mask layer 200. A second mask material layer is then formed on the surface of the second patterned photoresist 600 and a portion of the substrate 100 surface (or on the surface of the second patterned photoresist 600) by masking.
[0142] Then, anisotropic dry etching is used to remove the second mask material layer located on the top surface of the second patterned photoresist 600 and the top surface of the substrate 100, as well as the top surface of the second patterned photoresist 600 (or remove the second mask material layer located on the top surface of the second patterned photoresist 600). The remaining second mask material layer on the sidewall of the second patterned photoresist 600 constitutes the second patterned mask layer 300.
[0143] In one embodiment, after step S300, the method further includes:
[0144] Remove the first patterned mask layer 200 and the second patterned mask layer 300.
[0145] After removing the first patterned mask layer 200 and the second patterned mask layer 300, other process steps can be performed on the substrate 300 with the grooves formed.
[0146] In one embodiment, a semiconductor structure is also provided, which is prepared by any of the methods described above.
[0147] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0148] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A first patterned mask layer and a second patterned mask layer are formed on the substrate at intervals. The first patterned mask layer and the second patterned mask layer have different etching rates under the same etching conditions. The second patterned mask layer includes a plurality of second mask structures. The first patterned mask layer includes a first mask structure located on both sides of the plurality of second mask structures. The distance between adjacent first mask structures and second mask structures is measured as a first dimension, and the distance between adjacent second mask structures is measured as a second dimension; Based on the relationship between the first dimension and the second dimension, the etching conditions for etching the substrate are determined; When the first size is larger than the second size, under the etching conditions of etching the substrate, the etching rate of the first patterned mask layer is less than the etching rate of the second patterned mask layer. When the first size is smaller than the second size, under the etching conditions of etching the substrate, the etching rate of the first patterned mask layer is greater than the etching rate of the second patterned mask layer. The substrate is etched based on the first patterned mask layer and the second patterned mask layer.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a first patterned mask layer and a second patterned mask layer spaced apart on the substrate includes: A patterned intermediate mask layer is formed on the substrate; The first patterned mask layer is formed on the sidewall of the intermediate mask layer; The intermediate mask layer is patterned to form the second patterned mask layer.
3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The formation of a patterned intermediate mask layer on the substrate includes: An intermediate mask material layer is formed on the substrate; The intermediate mask material layer is patterned to form the intermediate mask layer.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The step of patterning the intermediate mask material layer to form the intermediate mask layer includes: A first patterned photoresist is formed on the intermediate mask material layer; Based on the first patterned photoresist, the intermediate mask material layer is etched, and the remaining intermediate mask material layer constitutes the intermediate mask layer.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, Before forming the first patterned photoresist on the intermediate mask material layer, the method further includes: Clean the surface of the intermediate mask material layer.
6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, After etching the intermediate mask material layer based on the first patterned photoresist, the process further includes: Remove the first patterned photoresist.
7. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Before performing patterning processing on the intermediate mask layer to form the second patterned mask layer, the process includes: A patterned sacrificial mask layer is formed on the intermediate mask layer; The step of patterning the intermediate mask layer to form the second patterned mask layer includes: Based on the sacrificial mask layer, the intermediate mask layer is etched, and the remaining intermediate mask layer constitutes the second patterned mask layer.
8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The process of forming the first patterned mask layer on the sidewall of the intermediate mask layer includes: A second patterned photoresist is formed on the intermediate mask layer; A first mask material layer is formed, which covers the second patterned photoresist, the intermediate mask layer, and the substrate; The first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate is removed. The remaining first mask material layer located on the sidewall of the intermediate mask layer constitutes the first patterned mask layer, and the remaining first mask material layer located on the sidewall of the second patterned photoresist constitutes the sacrificial mask layer.
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Before forming the second patterned photoresist on the intermediate mask layer, the method further includes: Clean the surface of the intermediate mask layer.
10. The method for fabricating a semiconductor structure according to claim 8, characterized in that, After removing the first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate, the process further includes: The cleaning process removes the residual first mask material layer located on the top surface of the second patterned photoresist, the top surface of the intermediate mask layer, and the top surface of the substrate. Remove the second patterned photoresist.
11. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After etching the substrate based on the first patterned mask layer and the second patterned mask layer, the method further includes: Remove the first patterned mask layer and the second patterned mask layer.
12. A semiconductor structure, characterized in that, Prepared by the method of fabricating the semiconductor structure according to any one of claims 1-11.