Chip packaging method
By embedding the solder metal layer with a barrier structure during the soldering process, the problems of solder metal layer loss and bridging are solved, improving the reliability and heat dissipation capability of chip packaging, and reducing solder metal layer spatter and voids.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANTONG FUJITSU MICROELECTRONICS
- Filing Date
- 2022-11-08
- Publication Date
- 2026-07-24
Smart Images
Figure CN116092951B_ABST
Abstract
Description
Technical Field
[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging method. Background Technology
[0002] However, with the increase in package size and the number of chips, the soldering of metal layers has also become more challenging. Using conventional gold-plated heat sinks for soldering often results in abnormal phenomena such as missing solder metal layers and bridging of solder metal layers after reflow. This can lead to reliability issues and cause quality damage to electronic components other than the chip.
[0003] To address the aforementioned problems, it is necessary to propose a chip packaging method that is rationally designed and can effectively improve these issues. Summary of the Invention
[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a chip packaging method.
[0005] This disclosure provides a chip packaging method, the method comprising:
[0006] Forming a barrier structure;
[0007] Fix the chip to the substrate;
[0008] A solder metal layer is disposed on the side of the chip opposite to the substrate;
[0009] The blocking structure is disposed on the side of the welding metal layer opposite to the chip;
[0010] A heat sink is disposed on the side of the barrier structure away from the welded metal layer, and the edge region of the heat sink is fixed to the substrate.
[0011] The solder metal layer is reflow soldered to fix the heat sink to the chip; wherein the barrier structure can be embedded in the solder metal layer during the reflow soldering process to prevent the solder metal layer from flowing in the molten state.
[0012] Optionally, the formation of the barrier structure includes:
[0013] Metal sheets are provided;
[0014] A first photoresist layer is formed on the surface of the metal plate;
[0015] A first mask is placed on the first photoresist layer, wherein the first mask is provided with a preset pattern that matches the blocking structure;
[0016] Using the first photomask as a mask, the first photoresist layer is exposed and developed to transfer the preset pattern on the first photoresist layer;
[0017] The metal plate is etched to transfer the preset pattern on the first photoresist layer to the metal plate, forming the barrier structure.
[0018] Optionally, the formation of the barrier structure further includes:
[0019] A second photoresist layer is formed on the surface of the heat sink facing the chip;
[0020] A second photomask is placed on the second photoresist layer, wherein the second photomask has a preset pattern that matches the blocking structure;
[0021] Using the second photomask as a mask, the second photoresist layer is exposed and developed to transfer the preset pattern on the second photomask onto the second photoresist layer;
[0022] A metal layer is deposited at the preset pattern on the second photoresist layer to form the barrier structure on the heat sink.
[0023] Optionally, the blocking structure includes multiple connectors and multiple first blocking elements;
[0024] The plurality of connectors are disposed on the surface of the welded metal layer and are spaced apart along a first direction of the welded metal layer. The plurality of first blocking members are spaced apart along the length direction of the connectors. The first end of the first blocking member is connected to the connector, and the second end of the first blocking member is inserted into the welded metal layer.
[0025] Optionally, the plurality of first blocking elements on two adjacent connectors are staggered.
[0026] Optionally, there is a gap between each of the first blocking members on two adjacent connectors and the opposite connector to form a flow channel.
[0027] Optionally, before fixing the chip to the substrate, the method further includes:
[0028] An insulating adhesive layer is formed in the edge region of the substrate, and the insulating adhesive layer is patterned to form a plurality of openings, wherein the openings correspond to the channel openings of the flow guiding channels.
[0029] Optionally, before depositing the solder metal layer on the side of the chip facing away from the substrate, the method further includes:
[0030] An indentation of the barrier structure is formed on the side of the welded metal layer facing the barrier structure, and the indentation matches the barrier structure.
[0031] Optionally, before placing the heat sink on the side of the blocking structure away from the welded metal layer, the method further includes:
[0032] An electroplated metal layer is formed on the side of the heat sink facing the chip.
[0033] Optionally, before placing the blocking structure on the side of the solder metal layer facing away from the chip, the method further includes:
[0034] Flux is applied to the side of the weld metal layer facing the barrier structure.
[0035] The chip packaging method of this disclosure forms a barrier structure that embeds a solder metal layer during reflow soldering to prevent the solder metal layer from flowing in a molten state. This barrier structure increases the flow resistance of the molten solder metal layer during reflow, reducing its loss; it also reduces solder metal spatter, preventing damage to electronic components outside the chip and increasing the reliability of the chip packaging structure. Furthermore, it increases the contact area between the solder metal layer and the heat sink after soldering, improving the heat dissipation interface from unidirectional vertical heat conduction to multidirectional efficient heat conduction, thus increasing heat diffusion capability. Additionally, it increases the flux coating area, reduces flux accumulation at single points, and minimizes voids in the solder metal layer at high temperatures. Attached Figure Description
[0036] Figure 1 This is a schematic flowchart of a chip packaging method according to an embodiment of this disclosure;
[0037] Figure 2 As described in this embodiment of the disclosure Figure 1 Step S110 corresponds to a flowchart of an embodiment;
[0038] Figures 3-7 As described in this embodiment of the disclosure Figure 1 A schematic diagram of the packaging process for forming a barrier structure in step S110 of an embodiment;
[0039] Figure 8 As described in this embodiment of the disclosure Figure 1 A flowchart of another embodiment corresponds to step S110;
[0040] Figures 9-11 As described in this embodiment of the disclosure Figure 1 A schematic diagram of the encapsulation process for forming a barrier structure, corresponding to step S110 in another embodiment;
[0041] Figures 12-15 This is a schematic diagram of the chip packaging process in an embodiment of this disclosure;
[0042] Figure 16 This is a top view of the blocking structure in another embodiment of this disclosure;
[0043] Figure 17 This is a top view of the flow channel and insulating adhesive layer in another embodiment of this disclosure. Detailed Implementation
[0044] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0045] like Figure 1 As shown, one aspect of this disclosure provides a chip packaging method S100, the packaging method S100 including:
[0046] S110, forming a barrier structure.
[0047] For example, such as Figure 2 As shown, a barrier structure is formed, comprising:
[0048] S101, Provide metal sheet.
[0049] Specifically, such as Figure 3 As shown, a metal plate 10 is provided. In this embodiment, the metal plate 10 can be a copper plate, that is, the material of the formed blocking structure 140 is copper. The metal plate 10 can also be other metal materials, and this embodiment does not make specific limitations.
[0050] S102, A first photoresist layer is formed on the surface of the metal plate.
[0051] Specifically, such as Figure 3 As shown, a first photoresist layer 20 is formed on the surface of the metal plate 10. The first photoresist layer 20 can be either a positive or negative photoresist; this embodiment does not impose a specific limitation. Positive photoresist is insoluble in the developer before exposure but soluble after exposure; negative photoresist is soluble in the developer before exposure but insoluble after exposure. In this embodiment, the first photoresist layer 20 is a positive photoresist.
[0052] S103. Place a first photomask on the first photoresist layer, wherein the first photomask has a preset pattern that matches the blocking structure.
[0053] Specifically, such as Figure 4As shown, a first photomask 30 is placed on the first photoresist layer 20, wherein the first photomask 30 is provided with a preset pattern 31 that matches the blocking structure 140.
[0054] S104. Using the first mask as a mask, expose and develop the first photoresist layer to transfer the preset pattern on the first mask onto the first photoresist layer.
[0055] Specifically, such as Figure 4 and Figure 5 As shown, using the first photomask 30 as a mask, the first photoresist layer 20 is first exposed and developed. Because the first photoresist layer 20 uses positive photoresist, the first photoresist layer 20 covered by the first photomask 30 is insoluble in the developer, while the first photoresist layer 20 not covered by the first photomask 30 is soluble in the developer, thus forming multiple openings 21 in the first photoresist layer 20. In this way, the preset pattern of the blocking structure 140 on the first photomask 30 is transferred onto the first photoresist layer 20.
[0056] S105. Etch the metal plate to transfer the preset pattern on the first photoresist layer to the metal plate to form the blocking structure.
[0057] Specifically, such as Figure 6 As shown, the metal plate 10 is etched along the opening 21 on the first photoresist layer 20 to transfer the preset pattern 31 of the barrier structure 140 on the first photoresist layer 20 onto the metal plate 10, as follows. Figure 7 As shown, the excess first photoresist layer 20 is removed to form a barrier structure 140. The etching process can be wet etching or dry etching; this embodiment does not impose a specific limitation.
[0058] In the above embodiments, the barrier structure 140 is formed separately, and the chip is packaged after the barrier structure 140 is formed.
[0059] For example, such as Figure 8 As shown, the barrier structure also includes:
[0060] S111, A second photoresist layer is formed on the surface of the heat sink facing the chip.
[0061] Specifically, such as Figure 9As shown, a first photoresist layer 40 is formed on the surface of the heat sink 150 facing the chip 120. The second photoresist layer 40 can be either a positive or negative photoresist; this embodiment does not specify a particular type. Positive photoresist is insoluble in the developer before exposure but soluble after exposure; negative photoresist is soluble in the developer before exposure but insoluble after exposure. In this embodiment, the second photoresist layer 40 uses a positive photoresist.
[0062] S112. A second photomask is placed on the second photoresist layer, wherein the second photomask has a preset pattern that matches the blocking structure.
[0063] Specifically, such as Figure 9 As shown, a second photomask 50 is placed on the second photoresist layer 40, wherein the second photomask 50 is provided with a preset pattern 51 that matches the blocking structure 140.
[0064] S113. Using the second mask as a mask, expose and develop the second photoresist layer to transfer the preset pattern on the second mask onto the second photoresist layer.
[0065] Specifically, such as Figure 10 As shown, using the second mask 50 as a mask, the second photoresist layer 40 is exposed and developed. Because the second photoresist layer 40 uses positive photoresist, the second photoresist layer 40 covered by the second mask 50 is insoluble in the developer, while the second photoresist layer 40 not covered by the first mask 30 is soluble in the developer, thus forming multiple openings 41 in the second photoresist layer 40. In this way, the preset pattern 51 of the blocking structure 140 on the second mask 50 is transferred onto the second photoresist layer 40.
[0066] S114. Deposit a metal layer at the preset pattern on the second photoresist layer to form the barrier structure on the heat sink.
[0067] Specifically, such as Figure 11 As shown, a metal layer is deposited at multiple openings in the predetermined pattern of the barrier structure 140 on the second photoresist layer 40. The metal layer can be formed using processes such as electroplating or sputtering to form the barrier structure 140 on the heat sink 150. In this embodiment, an electroplating process is used to form the barrier structure 140 at the multiple openings in the second photoresist layer 40. Then, the excess second photoresist layer 40 is removed.
[0068] In the above embodiments, the blocking structure 140 is formed directly on the side of the heat sink 150 facing the chip 120, and is integrally formed with the heat sink 150 for chip packaging, thereby improving the integration of the package.
[0069] For example, such as Figures 15 to 17 As shown, the blocking structure 140 includes a plurality of connectors 141 and a plurality of first blocking members 142. The plurality of connectors 141 are disposed on the surface of the welding metal layer 130, and the plurality of connectors 141 are spaced apart along a first direction of the welding metal layer 130. In this embodiment, the first direction is the width direction of the welding metal layer 130, but it can also be other directions, and this embodiment does not specifically limit it.
[0070] Multiple first blocking members 142 are spaced apart along the length of the connector 141. The first end of the first blocking member 142 is connected to the connector 141, and the second end of the first blocking member 142 is inserted into the welded metal layer 130. That is, the blocking structure 140 formed by the multiple connectors 141 and the multiple first blocking members 142 is in the shape of a dam or a fence.
[0071] Specifically, in this embodiment, a plurality of first blocking members 142 are spaced apart along the length direction of the connector 141. The plurality of first blocking members 142 may be equally spaced or not equally spaced, and this embodiment does not make a specific limitation. Further, in this embodiment, each connector 141 is provided with four first blocking members 142, wherein both ends of the connector 141 are provided with first blocking members 142.
[0072] It should be noted that the number of the first blocking member 142 is not specifically limited in this embodiment, and can be selected as needed.
[0073] In the above embodiments, the blocking structure includes multiple connectors and multiple first blocking components. The multiple first blocking components can block the flow of the solder metal layer in the molten state, increase the flow resistance of the molten solder metal layer during reflow, and reduce the loss of the solder metal layer during reflow; reduce solder metal layer spatter, prevent quality damage to electronic components outside the chip, and increase the reliability of the chip packaging structure; at the same time, it increases the contact area between the solder metal layer and the heat sink after soldering, improves the heat dissipation interface from unidirectional vertical heat conduction to multidirectional efficient heat conduction, and increases the heat diffusion capability; it can increase the flux coating area, reduce the amount of flux accumulation at a single point, and reduce the generation of voids in the solder metal layer at high temperatures.
[0074] For example, multiple first blocking members 142 on adjacent connectors 141 are staggered. That is, as... Figure 16 and Figure 17 As shown, the multiple first blocking members 142 on two adjacent connecting members 141 are not aligned, but staggered.
[0075] For example, such as Figure 17As shown, there is a gap between each first blocking member 142 on two adjacent connectors 141 and the opposite connector 141 to form a flow channel 160.
[0076] Specifically, such as Figure 16 and Figure 17 As shown, in two adjacent connectors 141, there is a gap between the upper connector 141 and the plurality of first blocking members 142 on the lower connector 141, and there is also a gap between the lower connector 141 and the plurality of first blocking members 142 on the upper connector 141, thus forming a flow channel 160.
[0077] In the above embodiments, a flow channel is formed between two adjacent first blocking members, which allows the gas generated by the flux at high temperature to be extracted along the path of the flow channel during vacuum reflow welding of the welding metal layer, thereby reducing the accumulation of welding voids on the welding metal layer.
[0078] For example, such as Figure 16 and Figure 17 As shown, the connector 141 located at the edge region of the weld metal layer 130 also includes a plurality of second blocking members 143. The plurality of second blocking members 143 are spaced apart on the outside of the corresponding connector 141. The first end of the second blocking member 143 is connected to the corresponding first blocking member 142, and the second end of the second blocking member 143 is inserted into the weld metal layer 130.
[0079] Specifically, such as Figure 16 and Figure 17 As shown, a second blocking member 142 is provided on the outside of the first blocking member 141 on the connector 141 located at the top and bottom. The first end of the second blocking member 143 is connected to the corresponding first blocking member 142. The second end of the second blocking member 143 is inserted into the solder metal layer 130, which can increase the flow resistance of the molten solder metal layer during the reflow process, reduce the spatter of the solder metal layer, and prevent quality damage to electronic components outside the chip.
[0080] After forming the barrier structure 140 according to the above steps, the chip packaging structure is packaged.
[0081] S120. Fix the chip to the substrate.
[0082] For example, before fixing the chip 120 to the substrate 110, the method further includes:
[0083] like Figure 17 As shown, an insulating adhesive layer 170 is formed in the edge region of the substrate 110. The insulating adhesive layer 170 is patterned to form a plurality of openings 171, wherein the openings 171 of the insulating adhesive layer 170 correspond to the channel openings 161 of the flow channel 160.
[0084] In the above embodiments, by optimizing the design of the insulating adhesive layer pattern, the opening of the insulating adhesive layer corresponds to the channel opening of the flow channel, thereby enhancing the vacuuming force at the channel opening position, reducing voids after welding the welding metal layer, and at the same time, due to the presence of the dam-like blocking structure, the spatter of the welding metal layer can be reduced.
[0085] The steps of fixing chip 120 to substrate 110 include:
[0086] Specifically, such as Figure 13 As shown, in this embodiment, the chip 120 is flip-chip fixed to the substrate 110 by a plurality of solder balls 121. An underfill layer 122 is disposed between the chip 120 and the substrate 110, which covers the plurality of solder balls 121, thus fixing the chip 120 and protecting the solder balls. It should be noted that the chip 120 can also be disposed on the substrate 110 in other ways, and this embodiment does not impose a specific limitation.
[0087] S130. A welding metal layer is disposed on the side of the chip away from the substrate.
[0088] Specifically, such as Figure 13 As shown, the solder metal layer 130 is fixed to the side of the chip 120 away from the substrate 110 by an adhesive layer.
[0089] It should be noted that in this embodiment, the solder metal layer 130 is a solder thermal interface material layer, that is, the solder metal layer 130 uses a solder thermal interface material. Solder thermal interface materials have high thermal conductivity, increasing heat dissipation capacity. More preferably, in this embodiment, the solder metal layer 130 uses indium foil. Indium foil is a solder thermal interface material with high thermal conductivity, which can increase the heat dissipation of the chip package structure.
[0090] For example, before depositing the solder metal layer on the side of the chip facing away from the substrate, the method further includes:
[0091] like Figure 14 As shown, an indentation of the barrier structure 140 is formed on the side of the weld metal layer 130 facing the barrier structure 140, and the indentation matches the barrier structure 140.
[0092] Specifically, in this embodiment, an indentation of the blocking structure 140 is formed on the side of the weld metal layer 130 facing the blocking structure 140, and the shape of the indentation matches the shape of the blocking structure 140. For example, if the second end of the first blocking member 142 is inserted into the weld metal layer 130, a concave indentation matching the first blocking member 142 is formed on the surface of the weld metal layer 130 corresponding to the first blocking member 142. This allows the blocking structure 140 to be more securely mounted on the weld metal layer 130.
[0093] S140. The blocking structure is disposed on the side of the welding metal layer away from the chip.
[0094] Specifically, on the one hand, such as Figure 14 As shown, the separately formed barrier structure 140 can be disposed on the side of the solder metal layer 130 away from the chip 120 via an adhesive layer. On the other hand, as Figure 15 As shown, the barrier structure 140, which is integrally formed on the heat sink 150 and is integrally molded with the heat sink 150, can be disposed on the side of the solder metal layer 130 away from the chip 120 by means of an adhesive layer.
[0095] Before placing the barrier structure 140 on the side of the solder metal layer 130 facing away from the chip 120, flux needs to be applied to the side of the solder metal layer 130 facing the barrier structure 140. The barrier structure 140 can increase the flux coating area, reduce the amount of flux accumulation at a single point, and reduce the generation of voids in the solder metal layer 130 under high temperature conditions.
[0096] S150. The heat sink is placed on the side of the blocking structure away from the welding metal layer, and the edge area of the heat sink is fixed to the substrate.
[0097] For example, such as Figure 15 As shown, before the heat sink 150 is positioned on the side of the barrier structure 140 facing away from the solder metal layer 130, an electroplated metal layer 191 can also be formed on the side of the heat sink 150 facing the chip 120. In this embodiment, the electroplated metal layer 191 is a gold plating layer, which can increase the thermal conductivity of the chip.
[0098] The steps of placing the heat sink 150 on the side of the barrier structure 140 away from the solder metal layer 130 include:
[0099] Specifically, such as Figure 14 and Figure 15 As shown, when the blocking structure 140 is formed alone, after the blocking structure 140 is disposed on the side of the solder metal layer 130 away from the chip 120, the heat sink 150 is disposed on the side of the blocking structure 140 away from the solder metal layer 130, and the edge area of the heat sink 150 is fixed to the substrate 110 by the adhesive layer 151.
[0100] In this embodiment, the heat sink 150 can be made of metals such as elemental indium, indium alloys, or silver alloys; no specific limitation is made in this embodiment. The heat sink 150 helps to dissipate heat from the entire package structure, thereby improving the heat dissipation performance of the package structure.
[0101] S160. The solder metal layer is reflow soldered to fix the heat sink to the chip; wherein the blocking structure can be embedded in the solder metal layer during the reflow soldering process to block the flow of the solder metal layer in the molten state.
[0102] Specifically, after the heat sink 150 is mounted, the solder metal layer 130 is vacuum reflow soldered to fix the heat sink 150 to the chip 120. During the high-temperature soldering process, the solder metal layer 130 is in a molten state, and the blocking structure 140 is embedded in the solder metal layer 130 under a preset pressure to prevent the solder metal layer 130 from flowing in the molten state.
[0103] like Figure 15 As shown, after vacuum reflow soldering is completed, multiple encapsulation solder balls 192 can be formed on the side of the substrate 110 away from the chip 120, and the encapsulation structure is electrically connected to the outside world through the encapsulation solder balls 192.
[0104] The chip packaging method of this disclosure forms a barrier structure that embeds a solder metal layer during reflow soldering to prevent the solder metal layer from flowing in a molten state. This barrier structure increases the flow resistance of the molten solder metal layer during reflow, reducing its loss; it also reduces solder metal spatter, preventing damage to electronic components outside the chip and increasing the reliability of the chip packaging structure. Furthermore, it increases the contact area between the solder metal layer and the heat sink after soldering, improving the heat dissipation interface from unidirectional vertical heat conduction to multidirectional efficient heat conduction, thus increasing heat diffusion capability. Additionally, it increases the flux coating area, reduces flux accumulation at single points, and minimizes voids in the solder metal layer at high temperatures.
[0105] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.
Claims
1. A chip packaging method, characterized in that, The method includes: Forming a barrier structure; Fix the chip to the substrate; A solder metal layer is disposed on the side of the chip opposite to the substrate; The blocking structure is disposed on the side of the welding metal layer opposite to the chip; A heat sink is disposed on the side of the barrier structure away from the welded metal layer, and the edge region of the heat sink is fixed to the substrate. The solder metal layer is reflow soldered to fix the heat sink to the chip; wherein the barrier structure can be embedded in the solder metal layer during the reflow soldering process to prevent the solder metal layer from flowing in the molten state.
2. The method according to claim 1, characterized in that, The formation of the barrier structure includes: Metal sheets are provided; A first photoresist layer is formed on the surface of the metal plate; A first mask is placed on the first photoresist layer, wherein the first mask is provided with a preset pattern that matches the blocking structure; Using the first photomask as a mask, the first photoresist layer is exposed and developed to transfer the preset pattern on the first photoresist layer; The metal plate is etched to transfer the preset pattern on the first photoresist layer to the metal plate, forming the barrier structure.
3. The method according to claim 1, characterized in that, The formation of the barrier structure also includes: A second photoresist layer is formed on the surface of the heat sink facing the chip; A second photomask is placed on the second photoresist layer, wherein the second photomask has a preset pattern that matches the blocking structure; Using the second photomask as a mask, the second photoresist layer is exposed and developed to transfer the preset pattern on the second photomask onto the second photoresist layer; A metal layer is deposited at the preset pattern on the second photoresist layer to form the barrier structure on the heat sink.
4. The method according to any one of claims 1 to 3, characterized in that, The blocking structure includes multiple connectors and multiple first blocking components; The plurality of connectors are disposed on the surface of the welded metal layer and are spaced apart along a first direction of the welded metal layer. The plurality of first blocking members are spaced apart along the length direction of the connectors. The first end of the first blocking member is connected to the connector, and the second end of the first blocking member is inserted into the welded metal layer.
5. The method according to claim 4, characterized in that, The plurality of first blocking elements on two adjacent connectors are staggered.
6. The method according to claim 5, characterized in that, There is a gap between each of the first blocking members on two adjacent connectors and the opposite connector to form a flow channel.
7. The method according to claim 6, characterized in that, Before fixing the chip to the substrate, the process further includes: An insulating adhesive layer is formed in the edge region of the substrate, and the insulating adhesive layer is patterned to form a plurality of openings, wherein the openings correspond to the channel openings of the flow guiding channels.
8. The method according to any one of claims 1 to 3, characterized in that, Before depositing the solder metal layer on the side of the chip facing away from the substrate, the method further includes: An indentation of the barrier structure is formed on the side of the welded metal layer facing the barrier structure, and the indentation matches the barrier structure.
9. The method according to any one of claims 1 to 3, characterized in that, Before placing the heat sink on the side of the blocking structure away from the welded metal layer, the method further includes: An electroplated metal layer is formed on the side of the heat sink facing the chip.
10. The method according to any one of claims 1 to 3, characterized in that, Before placing the blocking structure on the side of the solder metal layer facing away from the chip, the method further includes: Flux is applied to the side of the weld metal layer facing the barrier structure.