Three-dimensional flash memory module chip and method of manufacturing the same

Abstract

A three-dimensional flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of blocks, each block including a plurality of three-dimensional flash memory structures, and a plurality of heaters disposed around the plurality of three-dimensional flash memory structures of each block. The control chip is coupled to the memory chip to drive at least one of the plurality of heaters.

Description

Technical Field

[0001] This invention relates to a memory module and a method for manufacturing the same, and more particularly to a three-dimensional flash memory module and a method for manufacturing the same. Background Technology

[0002] Non-volatile memory (NDRAM) has the advantage of preserving stored data even after power loss, making it widely used in personal computers and other electronic devices. Currently, the most commonly used 3D memory types include NOR (Neuron OR) and NAND (Non-AND) memory. Another type of 3D memory is AND (AND) memory, which can be used in multi-dimensional memory arrays, offering high integration, high area utilization, and fast operation speeds. Therefore, the development of 3D memory devices has gradually become a current trend.

[0003] Public content

[0004] This invention provides a three-dimensional flash memory module chip and its manufacturing method, which can perform local repair (healing) processing on the flash memory.

[0005] In one embodiment of the present invention, a three-dimensional flash memory module chip includes a memory chip and a control chip. The memory chip includes multiple blocks, each block comprising multiple three-dimensional flash memory structures; and multiple heaters disposed around the multiple three-dimensional flash memory structures in each block. The control chip is coupled to the memory chip to drive at least one of the multiple heaters.

[0006] In one embodiment of the present invention, a method for manufacturing a three-dimensional flash memory module chip includes: forming a memory chip, including: forming a plurality of blocks on a first substrate, each block including a plurality of three-dimensional flash memory structures; forming a plurality of heaters around the plurality of three-dimensional flash memory structures on each block; forming a control chip; and bonding the control chip to the memory chip, wherein the control chip is used to drive the plurality of heaters.

[0007] Based on the above, the three-dimensional flash memory module chip and its manufacturing method of the present invention use an additional control chip to drive the heater to perform local repair processing on each block of the flash memory. The control chip can be manufactured separately to avoid the heater controller occupying the area of ​​the memory chip, and the control chip can be manufactured using a lower-level process to reduce process costs. Attached Figure Description

[0008] Figure 1A and Figure 1BThese are three-dimensional schematic diagrams of a three-dimensional flash memory module chip according to an embodiment of the present invention.

[0009] Figure 2A This is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention.

[0010] Figure 2B yes Figure 2A A cross-sectional view of line I-I'.

[0011] Figure 3A This is a partial top view of a memory chip with a heater according to another embodiment of the present invention.

[0012] Figure 3B yes Figure 3A A cross-sectional view of line I-I'.

[0013] Figure 4A This is a partial top view of a memory chip with a heater according to another embodiment of the present invention.

[0014] Figure 4B This is a partial top view of the heater and pad of a memory chip according to another embodiment of the present invention.

[0015] Figure 4C yes Figure 4B A cross-sectional view of line II-II'.

[0016] Figures 5A to 5E These are various three-dimensional schematic diagrams of a control chip according to embodiments of the present invention.

[0017] Figure 6A This is a three-dimensional schematic diagram of a memory chip and a control chip according to an embodiment of the present invention.

[0018] Figure 6B yes Figure 6A A partial circuit diagram.

[0019] Figures 7A to 7C A cross-sectional schematic diagram showing the manufacturing process of the three-dimensional flash memory module chip of the present invention is shown.

[0020] Figure 8 This is a perspective view of another control chip according to an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures

[0022] 14: Tunneling Layer

[0023] 16: Channel Column

[0024] 20: Storage unit

[0025] 24: Insulating filler layer

[0026] 28: Insulating Post

[0027] 32a: Conductor post / Source post

[0028] 32b: Conductor post / drain post

[0029] 34: Horizontal opening

[0030] 36: Barrier layer

[0031] 37, 1204: Barrier layer

[0032] 38, 2028: Gate layer

[0033] 40: Charge storage structure

[0034] 52: Gate stacking structure

[0035] 54, 1304, 2054: Insulation layer

[0036] 1000: Memory chip

[0037] 1010: First base

[0038] 1010W: Wafer

[0039] 1020: The First Transistor

[0040] 1020: Active components

[0041] 1030: First Intra-connection Structure

[0042] 1032: Lower internal connection structure

[0043] 1034: Upper internal connection structure

[0044] 1040, 2031: Dielectric layer

[0045] 1100, 11001, 11002: Three-dimensional flash memory structures

[0046] 1110: Dividing channel

[0047] 1112: Insulating Liner

[0048] 1200, 12001, 12002, 12003: Heaters

[0049] 1202: Metal layer

[0050] 1300, 2050: Bonding layer

[0051] 3000: Joint structure

[0052] 1302, 1302a, 1302b, 2052, 2052a, 2052b: Sealing pads

[0053] 2000: Control chip

[0054] 2000C, 2000C1, 2000C2: Line

[0055] 2000R: Drive Column

[0056] 2010: Second Base

[0057] 2012: Active Zone

[0058] 2020, 20201: Second transistor

[0059] 2022a: Source Region

[0060] 2022b: Drain Region

[0061] 2024: Gate Dielectric Layer

[0062] 2030: Second Intra-connection Structure

[0063] 2032, 2034, C1, C2, C3: Contact windows

[0064] 2036, 2040, 2040a, 2040b, 2040c: Conductors

[0065] 2038, 2042, 2042a, 2042b: Mesoscopic windows

[0066] 2100: Global Power Supply

[0067] 2200: Column Decoder

[0068] 2300: Line Decoder

[0069] 5000: 3D Flash Memory Module Chip

[0070] A0, A1, A2: Column address signals

[0071] A3, A4: Row address signals

[0072] AR: Array area

[0073] B, B1, B2, B3, B4: Blocks

[0074] BM1: Lower First Metal Layer

[0075] BM2: Lower second metal layer

[0076] BM3: Lower third metal layer

[0077] BV1, BV2, TV1: Interlayer Window

[0078] TM1: Upper First Metal Layer

[0079] TM2: Upper Second Metal Layer

[0080] E1: First end

[0081] E2: Second end

[0082] OP1: Ditch

[0083] OP2: Sealing pad opening

[0084] SC: Stepped structure

[0085] SL: Cutting Track

[0086] SLT: Separating Slit

[0087] SR: Staircase Area

[0088] T, T', T1, T1', T2, T2', T3, T3', T4, T4': blocks

[0089] W1, W2: Width

[0090] I-I', II-II': line

[0091] X, Y, Z: Direction Detailed Implementation

[0092] Flash memory performance degrades significantly after repeated operations, necessitating healing. Healing can be achieved by heating the flash memory with a heater to restore its charge storage structure (e.g., nitride layers). Current technologies often use word lines as heaters. However, the large number of word lines and their complex configuration with other components (e.g., word line decoders) makes flash memory layout design challenging.

[0093] This invention provides various three-dimensional flash memory module chips, in which heaters are placed above or around the sidewalls of the three-dimensional flash memory structure of the memory chip, and the memory chip is connected to a control chip, so that the control chip drives the heaters to perform local block repair processing of the memory chip.

[0094] Figure 1A and Figure 1B These are three-dimensional schematic diagrams of a three-dimensional flash memory module chip according to an embodiment of the present invention. Figure 2AThis is a partial top view of a three-dimensional flash memory structure of a memory chip according to an embodiment of the present invention. Figure 2B yes Figure 2A A cross-sectional view of line I-I'. Figure 3A This is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Figure 3B is... Figure 3A A cross-sectional view of line I-I'.

[0095] Please refer to Figure 1A and Figure 1B A three-dimensional flash memory module chip (also known as a three-dimensional integrated circuit, 3DIC) 5000 according to an embodiment of the present invention includes: a memory chip 1000 and a control chip 2000. The memory chip 1000 includes a plurality of three-dimensional flash memory structures 1100 and a plurality of heaters 1200. The plurality of heaters 1200 are disposed around the plurality of three-dimensional flash memory structures 1100. In some embodiments, the plurality of heaters 1200 are disposed above the plurality of three-dimensional flash memory structures 1100, such as... Figure 1A As shown. In other embodiments, a plurality of heaters 1200 are disposed in a partition channel 1110 between a plurality of three-dimensional flash memory structures 1100, as shown. Figure 1B As shown. The control chip 2000 is disposed above the memory chip 1000 and is used to drive the heater 1200 in the memory chip 1000. The control chip 2000 and the memory chip 1000 can be coupled to each other through the coupling structure 3000.

[0096] Please refer to Figure 1A and Figure 1B The three-dimensional flash memory structure 1100 of the memory chip 1000 can be a three-dimensional AND flash memory structure (such as...). Figure 2A and Figure 2B The three-dimensional flash memory structure 1100 of the present invention is illustrated below using a three-dimensional NAND flash memory structure (not shown) or a three-dimensional NOR flash memory structure (not shown). However, the embodiments of the present invention are not limited thereto.

[0097] Please refer to Figure 2A and Figure 2BThe memory chip 1000 may include multiple blocks T. These blocks T may be arranged in an array comprising multiple rows and multiple columns. In this embodiment, four blocks T (e.g., T1 to T4) are used. Of the four blocks T, blocks T1 and T2 are arranged in one column; blocks T3 and T4 are arranged in another column. Blocks T1 and T3 are arranged in one row; blocks T2 and T4 are arranged in another row. Each block T may include multiple regions B (e.g., B1 to B4). Each region B includes a three-dimensional flash memory structure 1100. The multiple three-dimensional flash memory structures 1100 extend in the X direction and are arranged in the Y direction. Adjacent three-dimensional flash memory structures 1100 are separated from each other by a separator channel 1110.

[0098] Please refer to Figure 2B Each three-dimensional flash memory structure 1100 may include at least one memory array formed by multiple memory cells. More specifically, the three-dimensional flash memory structure 1100 may be disposed above one or more active elements (e.g., first transistors 1020) on a first substrate (e.g., a semiconductor substrate) 1010. The first transistor 1020 is, for example, a complementary metal-oxide-semiconductor field-effect transistor (CMOS). Therefore, this architecture may also be referred to as a complementary metal-oxide-semiconductor field-effect transistor under array (CMOS under Array, CUA) architecture.

[0099] Please refer to Figure 2B The three-dimensional flash memory structure 1100 can be disposed in the backend of line (BEOL) process of a semiconductor die. For example, the three-dimensional flash memory structure 1100 can be embedded in a first interconnect structure 1030. The first interconnect structure 1030 includes, for example, a lower interconnect structure 1032 and an upper interconnect structure 1034. The lower interconnect structure 1032 is disposed above one or more active elements (e.g., a first transistor 1020) on a first substrate (e.g., a semiconductor substrate) 1010 and below the memory array of the three-dimensional flash memory structure 1100. The upper interconnect structure 1034 is disposed above the memory array of the three-dimensional flash memory structure 1100. The lower interconnect structure 1032 includes, for example, a lower first metal layer BM1, a lower second metal layer BM2, and a lower third metal layer BM3, and interlayer windows BV1 and BV2 between them. The upper interconnect structure 1034 may include, for example, an upper first metal layer TM1 and an upper second metal layer TM2, and a dielectric window TV1 between them. The number of metal layers and dielectric windows of the lower interconnect structure 1032 and the upper interconnect structure 1034 are not limited to the above.

[0100] Please refer to Figure 2BThe three-dimensional flash memory structure 1100 includes a plurality of gate stack structures 52. Each gate stack structure 52 is formed on a lower interconnect structure 1032. Each gate stack structure 52 extends in the X direction from the array region AR of the first substrate 1010 to the step region SR. The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 vertically stacked on the surface of the first substrate 1010 and multiple layers of insulating layers 54. In the Z direction, these gate layers 38 are electrically isolated from each other by insulating layers 54 disposed therebetween. The gate layers 38 include metal layers such as tungsten. In some embodiments, the gate layers 38 further include a barrier layer 37, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The insulating layer 54 is, for example, silicon oxide.

[0101] Gate layer 38 is adjacent to the first substrate 1010 (shown in Figure 2B The gate layer 38 of the stepped region SR extends in a direction parallel to the surface. The gate layer 38 of the stepped region SR may have a stepped structure SC (shown in...). Figure 2B The lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. The contact window C1 for connecting the gate layer 38 can land at the end of the gate layer 38 located in the stepped region SR, thereby connecting each gate layer 38 to the respective wires of the lower interconnect structure 1032 via the contact window C1 and the upper interconnect structure 1034, such as the wires of the lower third metal layer BM3.

[0102] Please refer to Figure 2B The three-dimensional flash memory structure 1100 also includes a plurality of channel pillars 16. The channel pillars 16 extend continuously through the gate stack structure 52 of the array region AR. In some embodiments, the channel pillars 16 may have a ring-shaped profile when viewed from a top angle. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon.

[0103] Please refer to Figure 2B The three-dimensional flash memory structure 1100 further includes an insulating fill layer 24, insulating pillars 28, a plurality of conductor pillars (e.g., as source pillars) 32a, and a plurality of conductor pillars (e.g., as drain pillars) 32b. The conductor pillars 32a and 32b, and the insulating pillars 28, are disposed within the channel pillar 16 and each extends in a direction perpendicular to the gate layer 38 (i.e., the Z direction). The conductor pillars 32a and 32b are separated from the insulating pillars 28 by the insulating fill layer 24 and are electrically coupled to the channel pillar 16. The conductor pillars 32a and 32b are, for example, doped polysilicon. The insulating fill layer 24 is, for example, silicon oxide; the insulating pillars 28 are, for example, silicon nitride.

[0104] Please refer to Figure 2BA charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38. The charge storage structure 40 may include a tunneling layer (or bandgap engineered tunneling oxide layer) 14, a charge storage layer 12, and a barrier layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the barrier layer 36. In some embodiments, the tunneling layer 14, the charge storage layer 12, and the barrier layer 36 are, for example, silicon oxide, silicon nitride, and silicon oxide. In some embodiments, a portion of the charge storage structure 40 (e.g., the tunneling layer 14) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (e.g., the charge storage layer 12 and the barrier layer 36) surrounds the gate layer 38, such as... Figure 2B As shown. In other embodiments, charge storage structures 40 (e.g., tunneling layer 14, charge storage layer 12, and barrier layer 36) surround the gate layer 38 (not shown). Each gate layer 38, together with the surrounding charge storage structure 40, channel pillar 16, and source pillar 32a and drain pillar 32b, defines a memory cell 20. Thus, each three-dimensional flash memory structure 1100 includes at least one memory array composed of a plurality of memory cells 20.

[0105] The three-dimensional flash memory architecture 1100 also includes local bit lines (LBLs). n With local source line LSL n and global bit line GBL n With Global Source Line (GSL) n Local bit line LBL n With local source line LSL n The upper first metal layer TM1 is located in the upper interconnect structure 1034 and is electrically connected to the source terminal 32a and the drain terminal 32b via contact window C2. Global bit line GBL n With Global Source Line (GSL) n Local bit lines LBL are electrically connected via the upper interlayer window (not shown) in the upper interconnect structure 1034. n With local source line LSL n .

[0106] Storage cell 20 can be operated in one-bit or two-bit modes using different methods. For example, when a voltage is applied to the source terminal 32a and the drain terminal 32b, since the source terminal 32a and the drain terminal 32b are connected to the channel terminal 16, electrons can be transported along the channel terminal 16 and stored in the entire charge storage structure 40, thus enabling one-bit operation of storage cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source terminal 32a and the drain terminal 32b. For source-side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 of one of the two adjacent source posts 32a and drain posts 32b, thus enabling single-cell (SLC, 1-bit) or multi-cell (MLC, greater than or equal to 2 bits) operations on the storage cell 20.

[0107] During operation, a voltage is applied to the selected word line (gate layer) 38, for example, applying a voltage higher than the corresponding start voltage (V) of the corresponding memory cell 20. th When the selected word line 38 is selected, the channel region of the channel post 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL. n It enters the drain terminal 32b, flows through the conductive channel region to the source terminal 32a, and finally flows to the source line SL. n .

[0108] Please refer to Figure 3A and Figure 3B The memory chip 1000 also includes a plurality of heaters 1200. The heaters 1200 may be disposed within a dielectric layer 1040 above the three-dimensional flash memory structure 1100. The dielectric layer 1040 is made of, for example, silicon oxide. The heaters 1200 include a metal layer 1202, such as copper or tungsten. In some embodiments, the heaters 1200 further include a barrier layer 1204, such as titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

[0109] Please refer to Figure 3A In some embodiments, a single heater 1200 is provided on each block B, and the two heaters 1200 of any two adjacent blocks B are separated from each other. The heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is provided in the array region AR and extends to the stepped region SR (e.g., Figure 3A and 3B(As shown). In one embodiment, the heater 1200 may be located in the array region AR, but not in the stepped region SR (not shown). That is, the length of the heater 1200 may be greater than, equal to or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

[0110] Furthermore, multiple heaters 1200 can be provided on each block B, for example, one heater 1200 each in the array region AR and the step region SR, and each heater can heat independently (not shown). However, the embodiments of the present invention are not limited thereto. In another embodiment, multiple heaters 1200 of two, three or more adjacent blocks B can be combined into a single heater (not shown) to simultaneously heat the three-dimensional flash memory structure 1100 of multiple blocks B.

[0111] Please refer to Figure 3A The top view shape of heater 1200 is, for example, rectangular or other shapes. Multiple heaters 1200 on multiple blocks B can have the same width or different widths. The width W1 of heater 1200 in array region AR is the same as the width W2 of heater 1200 in stepped region SR. However, the invention is not limited thereto. The shape of heater 1200 can be changed according to actual needs or design. The width W1 of heater 1200 in array region AR can be greater than, equal to, or less than the width W2 of heater 1200 in stepped region SR.

[0112] Please refer to Figure 1A , Figure 1B and Figure 3B The memory chip 1000 also includes a bonding layer 1300. The bonding layer 1300 includes pads 1302 and an insulating layer 1304. The insulating layer 1304 is disposed on the heater 1200. The material of the insulating layer 1304 is, for example, silicon oxide. Pads 1302 are disposed within the insulating layer 1304 on the surface of each heater 1200. The material of the pads 1302 is, for example, copper. The pads 1302 include pads 1302a and 1302b. Pads 1302a and 1302b are respectively connected to a first terminal E1 and a second terminal E2 of the heater 1200.

[0113] In the above embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are disposed above the three-dimensional AND flash memory structures (e.g., Figure 3A , Figure 3B as well as Figure 6A (As shown). In other embodiments, the plurality of three-dimensional flash memory structures 1100 are three-dimensional AND flash memory structures, and the plurality of heaters 1200 are disposed in the separating channels 1110 between the three-dimensional AND flash memory structures (e.g. Figures 4A to 4C (As shown).

[0114] Figure 4A This is a partial top view of a memory chip with a heater according to another embodiment of the present invention. Figure 4B This is a partial top view of the heater and pad of a memory chip according to another embodiment of the present invention. Figure 4C yes Figure 4B A cross-sectional view of line II-II'.

[0115] Please refer to Figure 4A and Figure 4C Multiple heaters 1200 are disposed in the partition channels 1110 between the three-dimensional flash memory structures 1100. The heaters 1200 are disposed around the multiple gate layers 38 and the multiple insulating layers 54 of the gate stack structure 52. The heaters 1200 are separated from the multiple gate layers 38 and the multiple insulating layers 54 by insulating liner 1112 (e.g., Figure 4C (As shown). The insulating liner 1112 includes an insulating material such as silicon oxide or silicon nitride. The heater 1200 includes a metal layer 1202 (e.g., Figure 4C (as shown), for example, copper or tungsten. In some embodiments, the heater 1200 further includes a barrier layer 1204 (such as... Figure 4C (As shown). Barrier layer 1204 is located between insulating liner 1112 and metal layer 1202. Barrier layer 1204 is, for example, titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

[0116] In some embodiments, a single heater 1200 is provided in each partition channel 1110. For example, the heater 1200 may extend in the X direction. In one embodiment, the heater 1200 is located in the array region AR and extends to the stepped region SR (e.g., Figure 4A and 4B (As shown). In one embodiment, the heater 1200 may be located in the array region AR, but not in the stepped region SR (not shown). That is, the length of the heater 1200 may be greater than, equal to or less than the length of the three-dimensional flash memory structure 1100 in the X direction.

[0117] Alternatively, multiple heaters 1200 may be provided in each dividing channel 1110, for example, one heater 1200 may be provided in the array region AR and the stepped region SR, and each heater may be heated separately (not shown). However, the embodiments of the present invention are not limited thereto.

[0118] Please refer to Figure 4AFurthermore, the top view shape of the heater 1200 may be rectangular or other shapes. The multiple heaters 1200 in the multiple dividing channels 1110 may have the same width or different widths. However, the invention is not limited thereto. The shape of the heater 1200 may be changed according to actual needs or design.

[0119] Please refer to Figure 4B and Figure 4C Each heater 1200 has a contact window C3 on its two ends (E1 and E2). The contact window C3 can be connected to the upper pads 1302a and 1302b via the upper interconnect structure 1034, so that the heater 1200 of the memory chip 1000 can be electrically connected to the control chip 2000 through the upper interconnect structure 1034 and the pads 1302a and 1302b. The material of the pads 1302a and 1302b is, for example, copper.

[0120] Figures 5A to 5E These are various three-dimensional schematic diagrams of a control chip according to embodiments of the present invention. Figure 6A This is a perspective view of a memory chip and a control chip according to an embodiment of the present invention. Figure 6B is... Figure 6A The circuit diagram.

[0121] Please refer to Figure 5A The control chip 2000 may include multiple blocks T'. These blocks T' can be arranged in an array. In this embodiment, four blocks T' (e.g., T1' to T4') are used as an example. Of the four blocks T', blocks T1' and T2' are arranged in one column; blocks T3' and T4' are arranged in another column. Blocks T1' and T3' are arranged in one row; blocks T2' and T4' are arranged in another row.

[0122] Please refer to Figure 5A and Figure 5E Each T' includes multiple drive columns 2000R and rows 2000C. Each drive column 2000R includes a second transistor 2020, a second interconnect structure 2030, and a pad 2052, such as... Figure 5E As shown. The second transistor 2020 is disposed on the active region 2012 of the second substrate 2010. The second substrate 2010 can be a semiconductor substrate, such as a silicon substrate. The second transistor 2020 can be a complementary metal-oxide-semiconductor (CMOS) transistor. The second transistor 2020 can be a planar transistor (e.g., Figures 5A to 5E (as shown) or finned transistors (such as) Figure 8 (As shown).

[0123] Please refer to Figure 5B and Figure 5E as well as Figure 8The second transistor 2020 includes a gate dielectric layer 2024, a gate layer 2028, a source region 2022a, and a drain region 2022b. The gate dielectric layer 2024 is, for example, silicon oxide or a high-dielectric-constant material. The gate layer 2028 is, for example, doped polysilicon or tungsten. The gate layer 2028 is located on the gate dielectric layer 2024. The gate layer 2028 is elongated, and its extension direction is, for example, the same as the extension direction of the heater 1200, for example, extending in the X direction. Figure 6A In some instances, the gate layers 2028 of the second transistors 2020 in two adjacent columns (e.g., blocks T1' and T2', or blocks T3' and T4') can be electrically connected, such as... Figure 5A As shown.

[0124] Please refer to Figure 5E The source region 2022a and drain region 2022b of the second transistor 2020 are disposed in the active regions 2012 on both sides of the gate layer 2028. The source region 2022a and drain region 2022b contain dopants, such as N-type or P-type dopants. In some embodiments, two adjacent second transistors 2020 share the source region 2022a.

[0125] Please refer to Figure 5B and Figure 5C The second interconnect structure 2030 is located on a plurality of second transistors 2020. The second interconnect structure 2030 includes a dielectric layer 2031 (e.g., Figure 5C (As shown) and multiple contact windows 2032, 2034, multiple wires 2036, 2040, and multiple dielectric windows 2038, 2042 located in dielectric layer 2031. Multiple contact windows 2032 land on and are electrically connected to source region 2022a and drain region 2022b, respectively. Contact window 2034 lands on and is electrically connected to gate layer 2028. Contact window 2032 is elongated, extending along the X direction and approximately parallel to gate layer 2028, as shown. Figure 5B and Figure 5D As shown. The shape of contact window 2034 is different from that of contact window 2032; its shape is, for example, columnar, as... Figure 5B As shown. Wires 2036 and 2040 (as shown) Figure 5C(As shown) Multiple contact windows 2032 and 2034 are respectively disposed on them. Conductors 2036 and 2040 are electrically insulated from each other by a dielectric window 2038. A dielectric window 2042 is disposed on conductor 2040 and electrically connects conductor 2040 to the upper bonding layer 2050. The dielectric layer 2031 is, for example, silicon oxide. The multiple contact windows 2032 and 2034, multiple conductors 2036 and 2040, and multiple dielectric windows 2038 and 2042 include a metal layer, for example, tungsten or copper. The multiple contact windows 2032 and 2034, multiple conductors 2036 and 2040, and multiple dielectric windows 2038 and 2042 may further include a barrier layer (not shown), for example, titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

[0126] Please refer to Figure 5C Each drive column 2000R has a pad 2052 that is part of the bonding layer 2050 of the control chip 2000. The bonding layer 2050 includes the pad 2052 and an insulating layer 2054. The insulating layer 2054 is located on the second interconnect structure 2030. The pad 2052 is located in the insulating layer 2054 and is electrically connected to the interlayer window 2042 of the second interconnect structure 2030. The material of the pad 2052 is, for example, copper. The material of the insulating layer 2054 is, for example, silicon oxide.

[0127] Please refer to Figure 5A and Figure 5E The pad 2052 includes pad 2052a and pad 2052b. More specifically, each drive column 2000R includes a pair of pads 2052a and 2052b disposed along the X direction. Pad 2052a is electrically connected to the first terminal E1 of the heater 1200; pad 2052b is electrically connected to the second terminal E2 of the heater 1200 to ground, as shown below. Figure 1A , 1B as well as Figure 6A As shown. Please refer to... Figure 5C and Figure 5D Each pad 2052a is electrically connected to its underlying conductor 2040a via a dielectric window 2042a. The conductors 2040a within the same T' are separate and electrically isolated from each other, each electrically connected to the drain region 2022b of the second transistor 2020, as shown below. Figure 5A and Figure 5C As shown. Each pad 2052b is electrically connected to the conductor 2040b below it via a window 2042b, as... Figure 5D As shown. Multiple pads 2052b of blocks T' in the same row (e.g., blocks T1' and T3', or blocks T2' and T4') are electrically connected to ground via the same conductor 2040b, as... Figure 5A As shown in Figure 5D.

[0128] Please refer to Figure 5C , Figure 1A and Figure 1B The bonding layer 2050 of the control chip 2000 and the bonding layer 1300 of the memory chip 1000 are bonded together to form a bonding structure 3000. More specifically, the insulating layer 2054 of the control chip 2000 corresponds to the insulating layer 1304 of the memory chip 1000 and is bonded to each other. The pads 2052a and 2052b of the control chip 2000 correspond to the pads 1302a and 1302b of the memory chip 1000 and are bonded to each other.

[0129] Please refer to Figure 5A , Figure 5C and Figure 5D The row 2000C of the control chip 2000 electrically couples the multiple common source regions 2022a of multiple second transistors 2020 in the same row (e.g., blocks T1' and T3', or blocks T2' and T4') to the global power supply 2100 via wire 2040c.

[0130] Please refer to Figure 5E The drain region 2022b of the second transistor 2020 of the control chip 2000 is connected to the second interconnect structure 2030 and the pad 2052a of the bonding layer 2050, as shown. Figure 5C As shown. This pad 2052a is electrically connected to the pad 1302a at the first end E1 of the heater 1200 of the memory chip 1000, as shown. Figure 6A As shown. In one embodiment, each drive column 2000R of the control chip 2000 can control a heater 1200 of a corresponding block B of the memory chip 1000, as shown. Figure 6A and Figure 6B As shown.

[0131] Please refer to Figure 5E In some embodiments, the control chip 2000 further includes a row decoder 2300 and a column decoder 2200. The row decoder 2300 is electrically connected to the global power supply 2100. After receiving row address signals A3 and A4, the row decoder 2300 selects one of the rows (e.g., ...). Figure 5A Multiple blocks (two in this example, such as line 2000C1) of line 2000C1) Figure 5A Blocks T1' and T3'). Thus, the global power supply 2100 is connected via conductor 2040c of the second interconnect structure 2030 (shown in...). Figure 5A Provided to the selected row (e.g.) Figure 5A Each block of line 2000C1 (e.g.) Figure 5AThe column decoder 2200 is electrically connected to the gate layers 2028 of the multiple second transistors 2020 of the multiple driving columns 2000R. After receiving the column address signals A0 to A2 (or control signals), the column decoder 2200 decodes the input column address signals to select one of the multiple second transistors 2020 (e.g., ...). Figure 5A The second transistor (20201) or more are turned on.

[0132] Generally, the memory chip 1000 includes a control logic unit for controlling the memory array, and the temporary register in the control logic unit stores the status signal of the number of erases of the memory array for each block B. When the number of erases reaches the predetermined number, this status signal is sent to the control chip 2000.

[0133] Please refer to Figure 6A and Figure 6B During the repair process, the control chip 2000 can generate the block T and block B (e.g., ...) that need to be repaired based on the received status signals. Figure 6A The corresponding column address signal and row address signal of block B1 of block T1 are received and transmitted to column decoder 2200 and row decoder 2300 respectively. Row decoder 2300 selects one row (e.g., ...) based on the received row address signal. Figure 6A Row 2000C1), thereby providing global power 2100 to the row located in that row (e.g., Figure 6A The block of line 2000C1 (e.g.) Figure 5AThe column decoder 2200 selects a second transistor 20201 driving column 2000R1 based on the received column address signal and turns it on. Therefore, current can flow from the global power supply 2100 through the wire 2040c into the source region 2022a of the second transistor 20201, and through the channel and drain region 2022b of the second transistor 20201, via the second interconnect structure 2030 and pad 2052a into the pad 1302a of the memory chip 1000, and then into the first terminal E1 of the heater 1200 (e.g., 12001). Afterwards, the current flows through the heater 12001, exits from the second terminal E2 of the heater 12001, and through the pad 1302b of the memory chip 1000, then into the pad 2052b of the control chip 2000, and is then electrically connected to ground via the wire 2040b. In this embodiment of the invention, the second transistor (driver) 2020 (e.g., 20201) of the control chip 2000 can provide a high drive current to a specific heater 1200 (e.g., 12001) to heat the conductor that serves as the heater 1200 (e.g., 12001), thereby repairing the charge storage layer in a specific block B (e.g., B1) of a specific block T (e.g., T1).

[0134] Please refer to Figure 1A and Figure 1B In some embodiments, during the repair process, a single heater 1200 (e.g., 12001) can be driven by a control chip 2000 to repair the charge storage layer in the three-dimensional flash memory structure 1100 (e.g., 11001) of a single block B (e.g., B1). Please refer to... Figure 1B In other embodiments, during repair, two heaters 1200 (e.g., 12002 and 12003) can be driven simultaneously by the control chip 2000 to repair the charge storage layer in the three-dimensional flash memory structure 1100 (e.g., 11002) of a single block B (e.g., B2).

[0135] Figures 7A to 7C A cross-sectional schematic diagram showing the manufacturing process of the three-dimensional flash memory module chip of the present invention is shown.

[0136] Please refer to Figure 7A A wafer 1010W is provided, and a plurality of memory chips 1000 are formed on the wafer 1010W. The plurality of memory chips 1000 have cleaving lines SL between them. The method for forming the memory chips 1000 is described below. Please refer to... Figure 3BFirst, one or more active elements (e.g., first transistors) 1020 are formed on wafer 1010W. Next, a lower interconnect structure 1032 is formed on the active elements 1020. The lower interconnect structure 1032 can be formed using any known method, such as damascene or dual damascene. Then, an insulating stack structure (not shown) is formed on the lower interconnect structure 1032, consisting of alternating layers of insulating layers (e.g., silicon oxide) 54 and another insulating layer (not shown, e.g., silicon nitride). Subsequently, a tunneling layer 14, channel pillars 16, and conductor pillars 32a and 32b of the charge storage structure 40 can be formed in the insulating stack structure using any known method. The material of the tunneling layer 14 can be a dielectric material, such as silicon oxide. The material of the channel pillars 16 can be a semiconductor, such as undoped polysilicon. The conductor pillars 32a and 32b are, for example, doped polysilicon.

[0137] Next, photolithography and etching processes are performed to form separation channels 1110 in the insulating stack structure and to divide the insulating stack structure into multiple blocks B.

[0138] Next, a gate replacement process is performed to form a gate stack structure 52. First, an etching process is performed to inject etchant into the separator channel 1110 to remove another insulating layer in the insulating stack structure, forming a plurality of horizontal openings 34, and then a gate layer 38 is formed in the horizontal openings 34. In some embodiments, a charge storage layer 12 and a barrier layer 36 are also formed in the horizontal openings 34 before forming the gate layer 38. The charge storage layer 12 is, for example, silicon nitride. The barrier layer 36 is, for example, a material with a high dielectric constant greater than or equal to 7, such as alumina (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. The gate layer 38 is, for example, tungsten. In some embodiments, a barrier layer 37 is also formed before forming the multilayer gate layer 38. The material of the barrier layer 37 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0139] Next, a partition slit SLT is formed in the partition channel 1110. The method for forming the partition slit SLT includes filling the gate stack structure 52 and the partition channel 1110 with an insulating filler material, and then removing excess insulating filler material from the gate stack structure 52 via an etch-back process or a planarization process. The insulating filler material is, for example, silicon oxide.

[0140] Subsequently, an upper interconnect structure 1034 (including local bit lines LBL) is formed on the gate stack structure 52. n Local source line LSL n and global bit line GBL nWith Global Source Line (GSL) n The upper internal interconnect structure 1034 can be formed using any known method, such as tessellation, double tessellation, etc., which will not be described in detail here.

[0141] Please refer to Figure 3A and Figure 3B In this embodiment, the upper internal interconnect structure 1034 (including the local bit line LBL) n Local source line LSL n and global bit line GBL n With Global Source Line (GSL) n After the formation of the upper interconnect structure 1034, a heater 1200 is formed above it. The heater 1200 is formed, for example, by first forming a dielectric layer 1040 above the upper interconnect structure 1034. The material of the dielectric layer 1040 is, for example, silicon oxide. In some embodiments, a planarization process, such as a chemical mechanical planarization process, is performed to give the dielectric layer 1040 a flat surface. Then, photolithography and etching processes are performed to form multiple channels OP1 in the dielectric layer 1040. Next, a barrier material layer and a metal material layer are sequentially formed on the dielectric layer 1040 and in the channels. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the dielectric layer 1040, and a barrier layer 1204 and a metal layer 1202 are formed in the channels. The metal material layer is, for example, copper or tungsten. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

[0142] Please refer to Figure 3B After the heater 1200 is formed, a bonding layer 1300 is formed. The bonding layer 1300 is formed as follows: First, an insulating layer 1304 is formed on the heater 1200 and the dielectric layer 1040. Then, a photolithography and etching process is performed to form a plurality of pad openings OP2 in the insulating layer 1304. The bottom of the pad openings OP2 exposes the heater 1200. Next, a conductor layer is formed on the insulating layer 1304 and in the pad openings OP2. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the conductor layer on the insulating layer 1304 and form pads 1302 in the pad openings OP2.

[0143] In the above embodiments, the heater 1200 of the memory chip 1000 is formed after the upper interconnect structure 1034 is formed. In other embodiments, the heater 1200 of the memory chip 1000 may be formed before the upper interconnect structure 1034 is formed.

[0144] Please refer to Figure 4CThe heater 1200 of the memory chip 1000 is formed after the gate stack structure 52 of the three-dimensional flash memory 1100 is formed, and the upper interconnect structure 1034 (including the local bit line LBL) is connected. n Local source line LSL n And global bit line GBLn and global source line GSL n Before formation, it is formed in the separation channel 1110 between the gate stack structure 52.

[0145] Please refer to Figure 4A and Figure 4C The heater 1200 is formed, for example, by first forming a substrate layer in the partition channel 1110. The substrate layer is, for example, silicon oxide or silicon nitride. Next, a barrier material layer and a metal material layer are sequentially formed on the gate stack structure 52 and in the partition channel 1110. Then, a planarization process, such as a chemical mechanical planarization process, is performed to remove the barrier material layer and the metal material layer on the surface of the gate stack structure 52, and an insulating substrate 1112, a barrier layer 1204, and a metal layer 1202 are formed in the partition channel 1110. The metal material layer is, for example, copper or tungsten. The barrier material layer is, for example, titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

[0146] Please refer to Figure 4B and Figure 4C After the heater 1200 is formed, the upper internal interconnect structure 1034 (including the local bit line LBL) is formed. n Local source line LSL n and global bit line GBL n With Global Source Line (GSL) n Subsequently, a bonding layer 1300 is formed on the upper internal interconnect structure 1034 according to the above method.

[0147] Please refer to Figure 7A Multiple control chips 2000 are provided. The method for forming the control chip 2000 is as follows. Please refer to... Figure 5C A second transistor 2020 is formed on a second substrate (wafer) 2010. Next, a second interconnect structure 2030 is formed on the second transistor 2020. The second interconnect structure 2030 can be formed using any known method, such as damascene or dual damascene. Subsequently, a bonding layer 2050 is formed on the second interconnect structure 2030 according to the above method. Afterwards, dicing is performed to form a plurality of control chips 2000.

[0148] Please refer to Figure 7BThe bonding layers 2050 of multiple control chips 2000 are bonded to the bonding layer 1300 of memory chip 1000 to form a bonding structure 3000. The bonding method is, for example, a hybrid bonding process. In some embodiments, after bonding the multiple control chips 2000 to the memory chip 1000 on wafer 1010W, an encapsulation layer (not shown) is also formed around the sidewalls of the multiple control chips 2000.

[0149] Please refer to Figure 7C The process involves cutting the chips to form multiple independent 3D flash memory module chips 5000.

[0150] In summary, this invention integrates a memory chip and a control chip to form a three-dimensional flash memory module chip. By providing a high drive current through the driver of the control chip to heat the heater in the memory chip, the charge storage structure of the flash memory can be repaired, resulting in faster erase speeds and improved flash memory durability. Furthermore, the control chip can locally heat corresponding blocks based on the status signals of the control logic units of the memory chip. Moreover, in this type of three-dimensional flash memory module chip formed through integration, the control chip can be fabricated separately, eliminating the need for a large-area heater controller within the memory chip. This avoids the heater controller occupying area of ​​the memory chip and allows the control chip to be manufactured using lower-level processes, reducing manufacturing costs.

Claims

1. A three-dimensional flash memory module chip, characterized in that, include: Memory chips, including: Multiple blocks, each comprising multiple three-dimensional flash memory structures; and Multiple heaters are disposed around the multiple three-dimensional flash memory structures of each block; A control chip, coupled to the memory chip, is used to drive at least one of the plurality of heaters; wherein the control chip includes: a plurality of drive columns, wherein each drive column includes: The second transistor is located on the second substrate, and the source region of the second transistor is electrically connected to the global power supply. A first pad is electrically connected to the drain region of the second transistor and electrically connected to a first terminal of one of the plurality of heaters; and The second pad is grounded and electrically connected to the second terminal of one of the plurality of heaters.

2. The three-dimensional flash memory module chip according to claim 1, characterized in that, The plurality of heaters are disposed above the plurality of three-dimensional flash memory structures and adjacent to the control chip.

3. The three-dimensional flash memory module chip according to claim 1, characterized in that, The plurality of heaters are disposed in multiple separating channels between the plurality of three-dimensional flash memory structures.

4. The three-dimensional flash memory module chip according to claim 1, characterized in that, The memory chip also includes: Multiple first transistors are located on a first substrate; The plurality of three-dimensional flash memory structures are located above the plurality of first transistors; and A first interconnect structure, wherein the plurality of three-dimensional flash memory structures are embedded in the first interconnect structure.

5. The three-dimensional flash memory module chip according to claim 4, characterized in that, The first interconnect structure includes: The lower interconnect structure is located between the plurality of three-dimensional flash memory structures and the plurality of first transistors, and electrically connects the plurality of three-dimensional flash memory structures and the plurality of first transistors; and The upper internal interconnect structure is located on the plurality of three-dimensional flash memory structures and is electrically connected to the plurality of three-dimensional flash memory structures.

6. The three-dimensional flash memory module chip according to claim 1, characterized in that, The control chip also includes: A column decoder, electrically coupled to multiple gate layers of multiple second transistors of the multiple drive columns; and The line decoder is electrically coupled to multiple source regions of the plurality of second transistors and the global power supply.

7. The three-dimensional flash memory module chip according to claim 1, characterized in that, The control chip includes multiple blocks arranged in an array, wherein multiple source regions of multiple second transistors in multiple blocks in the same row are electrically connected to each other.

8. The three-dimensional flash memory module chip according to claim 1, characterized in that, The control chip and the memory chip are bonded together via a bonding structure.

9. The three-dimensional flash memory module chip according to claim 1, characterized in that, The plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, a three-dimensional NAND flash memory structure, or a plurality of three-dimensional NOR flash memory structures.

10. A method for manufacturing a three-dimensional flash memory module chip, characterized in that, include: Forming a memory chip includes: Multiple blocks are formed on a first substrate, each block comprising multiple three-dimensional flash memory structures; and Multiple heaters are formed around each of the multiple three-dimensional flash memory structures; Forming a control chip; and The control chip and the memory chip are coupled together, wherein the control chip is used to drive the plurality of heaters; The formation of the control chip includes: forming a plurality of drive columns, wherein forming each drive column includes: A second transistor is formed on a second substrate; A second interconnect structure is formed on the second transistor, wherein the source region of the second transistor is electrically coupled to a global power supply via the second interconnect structure. A first pad is formed on the second interconnect structure, and the first pad is electrically connected to the drain region of the second transistor via the second interconnect structure. A second pad is formed on the second interconnect structure, and the second pad is electrically connected to ground via the second interconnect structure; Electrically connect the first pad to a first end of one of the plurality of heaters; and The second pad is electrically connected to the second end of one of the plurality of heaters.

11. The method for manufacturing a three-dimensional flash memory module chip according to claim 10, characterized in that, The plurality of heaters are formed above the plurality of three-dimensional flash memory structures.

12. The method for manufacturing a three-dimensional flash memory module chip according to claim 11, characterized in that, The plurality of heaters are formed in a plurality of partitioned channels around the plurality of three-dimensional flash memory structures.

13. The method for manufacturing a three-dimensional flash memory module chip according to claim 10, characterized in that, The formation of the memory chip also includes: A plurality of first transistors are formed on the first substrate; and The plurality of three-dimensional flash memory structures are formed above the plurality of first transistors.

14. The method for manufacturing a three-dimensional flash memory module chip according to claim 10, characterized in that, The control chip and the memory chip are coupled together via a bonding structure.

15. The method for manufacturing a three-dimensional flash memory module chip according to claim 10, characterized in that, The plurality of three-dimensional flash memory structures include a plurality of three-dimensional AND flash memory structures, a three-dimensional NAND flash memory structure, or a plurality of three-dimensional NOR flash memory structures.

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