Method for manufacturing a single-chip and chip structure

Abstract

The embodiment of the present application provides a single-chip preparation method and a chip structure, and belongs to the technical field of chips. The preparation method comprises the following steps: providing at least two bare chips and a heat dissipation plate; fixing the at least two bare chips with the back surface downward on the chip fixing area on the surface of the heat dissipation plate through an interface heat dissipation material layer; forming a first chip frame by connecting the second group of bumps of the at least two bare chips through flip chip bonding; carrying out bottom filling on the first chip frame; flip chip bonding the first group of bumps of the at least two bare chips to the upper surface of a substrate to form a second chip frame; carrying out bottom filling on the second chip frame; and manufacturing a contact array package on the lower surface of the substrate to obtain a single chip. The present application is designed for a single chip, avoids the influence of chip displacement on the bonding accuracy of the chip in large-area preparation, and simplifies the processes such as mold pressing, RDL adding and cutting.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, in particular to a single-chip preparation method and chip structure. BACKGROUND

[0002] The existing single-chip preparation scheme is to first prepare a wafer, then prepare multiple bare chips on the wafer in a large area and realize the connection between the bare chips, and then cut to obtain a single-chip containing one or more bare chips. This large-area preparation scheme can be based on a large plate for molding, adding a redistribution layer (RDL), etc., which is conducive to reducing chip preparation costs. However, this large-area preparation process relies on expensive equipment investment and the quality of the wafer itself, and the equipment or wafer failure will cause good chip loss, thereby making it difficult to take advantage of large-area manufacturing, and it is also difficult to ensure the accuracy of the single chip. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a single-chip preparation method and chip structure to at least partially solve the above technical problems.

[0004] In order to achieve the above-mentioned purpose, the embodiments of the present application provide a single-chip preparation method, comprising the following steps executed in sequence: providing at least two bare chips and a heat dissipation plate suitable for arranging the at least two bare chips, wherein the front surface of the bare chip has a first group of bumps and a second group of bumps with a height smaller than the first group of bumps, and the surface of the heat dissipation plate forms a chip fixing area through an interface heat dissipation material layer; the back surface of the at least two bare chips is downwardly fixed on the chip fixing area of the surface of the heat dissipation plate through the interface heat dissipation material layer; the second group of bumps of the at least two bare chips is flip-chip bonded through a connection chip to form a first chip frame; the first chip frame is subjected to underfilling; the first group of bumps of the first chip frame after underfilling is flip-chip mounted to the upper surface of a substrate to form a second chip frame; the second chip frame is subjected to underfilling; and a contact array package is made on the lower surface of the substrate for the second chip frame after underfilling to obtain a single-chip.

[0005] Optionally, the interface heat dissipation material layer adopts any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

[0006] Optionally, providing a heat dissipation plate comprises: providing a planar heat dissipation plate or a heat dissipation plate with a groove; providing a metal plating layer on the surface of the planar heat dissipation plate or the surface of the groove; and providing the chip fixing area formed by the interface heat dissipation material layer on the metal plating layer for each bare chip.

[0007] Optionally, the heat dissipation plate further comprises: for each chip fixing area, setting a unique label to identify the coordinate of the chip fixing area on the heat dissipation plate.

[0008] Optionally, the preparation method further comprises: after the bottom filling of the second chip frame, dispensing and fixing the heat dissipation plate.

[0009] Optionally, the manufacturing of the contact array package on the lower surface of the substrate comprises: implanting solder balls on the lower surface of the substrate to generate a ball grid array package; adding a planar grid array package on the lower surface of the substrate; or performing a pin placement operation on the lower surface of the substrate to generate a pin grid array package.

[0010] Another embodiment of the present application provides a chip structure prepared by the above preparation method, which comprises: at least two bare chips, wherein the front surface of the bare chip has a first group of bumps and a second group of bumps with a height smaller than the first group of bumps; a heat dissipation plate, the surface of which has a chip fixing area formed by an interface heat dissipation material layer, wherein the back surface of the at least two bare chips is downwardly fixed on the chip fixing area through the interface heat dissipation material layer; a connecting chip, which flip-chip bonds the second group of bumps of the at least two bare chips after the bare chips are fixed on the chip fixing area, to form a first chip frame; a first bottom filling structure formed by bottom filling the first chip frame; a substrate, wherein the first group of bumps is flip-chip attached to the upper surface of the substrate to form a second chip frame for the first chip frame after bottom filling; a second bottom filling structure formed by bottom filling the second chip frame; and a contact array package, which is manufactured on the lower surface of the substrate for the second chip frame after bottom filling.

[0011] Optionally, the heat dissipation plate is a planar heat dissipation plate or a heat dissipation plate with a groove, and the surface of the planar heat dissipation plate or the surface of the groove is provided with a metal plating layer, and for each bare chip, a chip fixing area formed by the interface heat dissipation material layer is provided on the metal plating layer; wherein each chip fixing area has a unique label to identify the coordinate of the chip fixing area on the heat dissipation plate.

[0012] Optionally, the interface heat dissipation material layer is a material layer formed based on any of the following heat dissipation materials: any of nickel, tin, copper, gold, aluminum, silver; an alloy of any of nickel, tin, copper, gold, aluminum, silver; and graphene.

[0013] Optionally, the contact array package comprises a ball grid array package, a planar grid array package, or a pin grid array package.

[0014] Through the technical solution, all packaging processes of the embodiment of the application are aimed at single-chip product processing, avoiding the influence of chip displacement on chip bonding precision in large-area preparation, and being easy to obtain single chips with higher precision; meanwhile, the processes such as mold pressing, RDL adding and cutting involved in large-area preparation are avoided, and the difficulty and cost of chip preparation are reduced through process simplification for the scene with low chip quantity requirement.

[0015] Other features and advantages of the embodiments of the application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the embodiments of the application, and constitute a part of the specification, and are used together with the following specific implementation to explain the embodiments of the application, but do not constitute a limitation on the embodiments of the application.

[0017] In the drawings:

[0018] Figure 1 is a flowchart of a single-chip preparation method of the first embodiment of the application;

[0019] Fig. 2 (a1) - Fig. 2 (g) are schematic diagrams of various processes of preparing a chip involved in the example of the first embodiment of the application, and simultaneously show an example chip structure of the second embodiment of the application; and

[0020] Fig. 3 (a) - Fig. 3 (b) are planar top views respectively showing the distribution of two bare chips and four bare chips on a heat sink.

[0021] Explanation of reference signs:

[0022] 100, heat sink; 110, interface heat dissipation material layer;

[0023] 210, first bare chip; 220, second bare chip; 230, first group of bumps; 240, second group of bumps;

[0024] 300, connected chip; 400, first chip frame; 500, first underfill structure; 600, substrate; 700, second chip frame; 800, second underfill structure; 900, solder ball; 1000, chip structure. DETAILED DESCRIPTION

[0025] The specific implementation of the embodiments of the application will be described in detail below in combination with the drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiments of the application, and is not used to limit the embodiments of the application.

[0026] Before introducing the scheme of the embodiment of the present application, some terms involved are introduced first, so that the technical personnel in the field can better understand the scheme of the embodiment of the present application.

[0027] 1) Chip packaging: refers to protecting the bare chip from damage from the outside world, and different packaging technologies differ greatly in preparation procedures and processes.

[0028] 2) Flip: flip technology, refers to the connection point of the chip facing down for operation, for example, flip chip refers to the connection point of the chip facing down to connect with the substrate, carrier, circuit board, another chip, etc. Among them, the connection point can also be called contact point or contact point, and the bump is a typical connection point.

[0029] 3) Compression molding: chip compression molding process, refers to placing the connection frame of the chip in the mold, and then injecting the solidified material into the mold to form a mold structure for protecting the chip connection frame by compression.

[0030] 4) Bottom filling: refers to applying epoxy resin glue and the like to the edge of the flip chip frame through "capillary effect", the glue is absorbed to the opposite side of the frame, the bottom filling process is completed, and the glue is solidified by heating to obtain a reliable and stable chip process.

[0031] 5) Single chip: refers to a single chip that has been cut and separated (i.e. does not need to be cut again), which can realize specific computing independently after packaging, and can be integrated with multiple bare chips to realize multiple computing, such as powerful CPU, GPU and AI chip.

[0032] 6) Substrate and carrier plate: the substrate has electrical properties and has internal wiring to enable the bare chip to transmit signals horizontally and vertically through the wiring; the carrier plate does not have electrical properties and only serves as a mechanical carrier.

[0033] Embodiment one.

[0034] Figure 1 is a flowchart of the preparation method of the single chip of the embodiment one of the present application, which includes steps S100 to S700 executed in sequence, and figures 2(a1) to 2(g) are process schematic diagrams of examples applying the preparation method, including processes s1-s8. In combination with Figure 1 and figures 2(a1) to 2(g), the implementation of the preparation method includes steps S100-S700.

[0035] Step S100, providing at least two bare chips and a heat sink suitable for arranging the at least two bare chips.

[0036] This step S100 corresponds to the example processes s1-s2.

[0037] Step s1: as shown in FIG. 2(a1) and FIG. 2(a2), a heat sink 100 is provided.

[0038] Specifically, the heat sink 100 is a planar heat sink (as shown in FIG. 2(a1)) or a heat sink with grooves (as shown in FIG. 2(a2)), a metal plating layer is arranged on the surface of the planar heat sink or the surface of the grooves, the metal plating layer is for example a multi-layer structure containing nickel and gold, and a chip fixing area formed by an interface heat dissipation material layer 110 is arranged on the metal plating layer for each bare chip. Among them, the grooves are designed to accommodate the bare chip, and the depth can be determined by the thickness of the chip. It should be noted that the following steps are taken as an example of the planar heat sink shown in FIG. 2(a1).

[0039] Among them, the interface heat dissipation material layer 110 adopts any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver; and graphene.

[0040] Further, for each chip fixing area, a unique label can be arranged to identify the coordinates of the chip fixing area on the heat sink. Accordingly, through the label, it is easy to determine the fixed position of the bare chip on the heat sink.

[0041] Step s2: as shown in FIG. 2(b), bare chips are provided, including a first bare chip 210 and a second bare chip 220.

[0042] Among them, the front surface of the bare chip has a first group of bumps 230 and a second group of bumps 240, and the height of the second group of bumps 240 is less than that of the first group of bumps 230. The second group of bumps is for example a copper (Cu) bump, and the first group of bumps is for example a higher Cu column. In a preferred embodiment, the height difference between the two groups of bumps requires that a connecting chip for realizing chip bonding in the subsequent process can be accommodated.

[0043] In addition, for each bare chip, another material layer (for example, a metal plating layer) corresponding to the interface heat dissipation material layer of the heat sink can be prepared on the back surface of the bare chip to facilitate the subsequent fixing of the bare chip on the heat sink.

[0044] Step S200, the at least two bare chips are fixed on the chip fixing area of the surface of the heat sink by the bonding of the interface heat dissipation material layer with the back surface facing down.

[0045] Corresponding step s3: as shown in FIG. 2(c), the first bare chip 210 and the second bare chip 220 are distributed on the heat sink 100.

[0046] Specifically, the back surface of the bare chip (e.g. with a gold plating layer) is bonded to the surface of the heat sink 100 (e.g. also with a gold plating layer) through the interface heat dissipation material layer 110, so that the corresponding bare chip is fixed to the chip fixing region formed by the interface heat dissipation material layer 110. For example, the back surface of the bare chip is plated with a multi-layer metal plating layer of titanium, nickel, vanadium, and gold, which helps to improve the bonding between the interface heat dissipation material layer and the bare chip, prevent surface oxidation, and prevent delamination between the interface heat dissipation material layer and the bare chip at high temperatures. Similarly, the heat sink and the chip fixing region on the heat sink can also be plated with a metal plating layer of nickel, gold, etc. to prevent surface oxidation and delamination of the interface bonding.

[0047] It should be noted that, considering that the second group of bumps 240 of the bare chip will be used for chip bonding in subsequent processes, the first bare chip 210 and the second bare chip 220 can be fixed on the heat sink 100 with the second group of bumps 240 close to each other.

[0048] Step S300: The second group of bumps of the at least two bare chips are connected by flip chip bonding to form a first chip frame.

[0049] Corresponding process s4: As shown in FIG. 2(d), the second group of bumps 240 of the two bare chips are connected by flip chip bonding 300 to obtain a first chip frame 400.

[0050] Specifically, the connection chip 300 is also a bare chip, but preferably has a smaller size than the first bare chip 210 and the second bare chip 220, and more preferably has a thickness smaller than the height difference between the two groups of bumps on the bare chip, i.e. the height difference between the two groups of bumps can accommodate the connection chip 300. In addition, the connection chip 300 preferably adopts a low-power chip to reduce the overall power consumption of the finally formed chip structure. The connection chip 300 is flip-chip mounted on the second group of bumps 240 of the two bare chips to realize signal transmission between the first bare chip 210 and the second bare chip 220, and obtain the first chip frame 400 shown in the entire FIG. 2(d).

[0051] Step S400: The first chip frame is subjected to underfilling, for example, to protect the connection points of the chip 300 and the chips 210 and 220.

[0052] Corresponding process s5: As shown in FIG. 2(d), the first chip frame 400 is subjected to underfilling, and a first underfilling structure 500 is shown in the figure.

[0053] Step S500: For the first chip frame after underfilling, the first group of bumps is flip-chip mounted to the upper surface of the substrate to form a second chip frame.

[0054] Corresponding process s6: As shown in FIG. 2(e), the substrate 600 is flip-chip mounted to obtain a second chip frame 700.

[0055] Step S600, bottom filling is performed on the second chip frame.

[0056] Corresponding process s7: as shown in FIG. 2(f), bottom filling is performed on the second chip frame 700, and a second bottom filling structure 800 is shown in the figure. Preferably, dispensing fixing can also be performed on the heat sink to ensure the stability of the heat sink.

[0057] Step S700, for the second chip frame after bottom filling, a land grid array package (LGA) is added to the lower surface of the substrate to obtain a single chip.

[0058] The S700 of manufacturing the land grid array package on the lower surface of the substrate can include: implanting solder balls on the lower surface of the substrate to generate a ball grid array (BGA); adding a land grid array (LGA) to the lower surface of the substrate; or pinning the lower surface of the substrate to generate a pin grid array (PGA).

[0059] Corresponding process s8: as shown in FIG. 2(g), solder balls 900 are implanted on the lower surface of the substrate 600 to generate a BGA, and a final chip structure 1000 is obtained.

[0060] Thus, through the above processes s1 to s8, the example chip structure 1000 is obtained, and the planar top view distributed on the heat sink is shown in FIG. 3(a). It is easy to know that the first bare chip 210 and the second bare chip 220 can be bare chips with the same size or different sizes, for example, the first bare chip 210 and the second bare chip 220 are CPU chips with the same size, and through the above processes s1 to s8, a chip with stronger computing function is generated for large data operation of a server, etc.; and for example, the first bare chip 210 and the second bare chip 220 are CPU chips and GPU chips with different sizes, respectively, so that through the above processes s1 to s8, a multifunctional chip integrating data processing function and image processing function is generated, for example, for a vehicle terminal for automatic driving, etc.

[0061] In addition, the above example takes two bare chips as an example, but it should be clear that more bare chips can also be included, as shown in FIG. 3(b), and four bare chips can also be interconnected based on a connection chip, that is, the four bare chips (for example, Die1-Die4) around the connection chip (for example, Die5) in the middle of FIG. 3(b) are bonded through the connection chip.

[0062] In summary, the embodiment of the present application has the following advantages over the prior art method of preparing a large-area chip.

[0063] 1) The embodiment of the present application is specifically designed for a single chip, avoiding the influence of chip displacement (such as displacement of the carrier plate or wafer thermal expansion or interface material) on the bonding accuracy of the chip in the large-area preparation process, and is easy to obtain a single chip with higher accuracy; at the same time, the processes such as mold pressing, RDL adding, and cutting involved in the large-area preparation are avoided, and for scenes with low chip quantity requirements, the difficulty and cost of chip preparation are reduced through process simplification. Through experiments, it is known that the single chip preparation method of the embodiment of the present application can obtain a yield of more than 99.9%, and the cost of equipment and process is less than 10% of the wafer process.

[0064] 2) In the single chip preparation method of the embodiment of the present application, a heat sink is first provided, and then the bare chip is placed on the heat sink for chip packaging, so that compared with the prior art process of first packaging the chip and then adding a heat sink, the interface heat dissipation material between the heat sink and the chip can adopt a wider range of heat dissipation materials, and a metal with good thermal conductivity can be selected to improve heat dissipation. These metals all have a high melting point, for example, nickel, tin, copper, gold, aluminum, silver and their alloys, etc., all of which have a melting point higher than 240 degrees Celsius. If the prior art process first flip-chip bonds the chip and then adds a heat sink, it will cause the failure of the bonding connection point, but this application can use high-melting-point high-thermal-conductivity interface heat dissipation material, and then bond the chip, which can maintain a good heat dissipation interface and also have a good bonding of the electrical connection point of the chip.

[0065] 3) The embodiment of the present application realizes the interconnection of multiple bare chips, and further realizes high-speed electrical connection and signal transmission between bare chips to obtain stronger chip performance.

[0066] 4) The embodiment of the present application first provides a heat sink, and then the bare chip can be directly soldered on the heat sink, so that it is not easy to displace in the subsequent process, while the prior art process generally needs to use organic glue to fix, which will displace in the subsequent high-temperature process and cause bonding failure in the subsequent process.

[0067] 5) The prior art process often attaches a heat sink after the chip is bonded, which will affect the stability of the soldering point, while the embodiment of the present application can avoid this defect.

[0068] 6) In the prior art, the bare chip is first placed on a carrier plate, which is removed by high temperature or laser in the subsequent process. This carrier plate removal process not only introduces additional cost, but also introduces additional stress and causes poor performance of the product. The embodiment of the present application uses a heat sink as a carrier plate, eliminating the need for subsequent carrier plate removal process, improving heat dissipation performance, and helping to maintain the reliability of electrical connections.

[0069] Embodiment two.

[0070] Embodiment two of the present application provides a chip structure, as shown in FIGS. 2(a1) to 2(g), which is prepared by the preparation method of embodiment one described above, and the chip structure 1000 includes: at least two bare chips, wherein the front surface of the bare chip has a first group of bumps 230 and a second group of bumps 240 with a height smaller than the first group of bumps; a heat sink 100 having a chip fixing area formed by an interface heat dissipation material layer 110 on its surface, wherein the at least two bare chips are fixed on the chip fixing area by the interface heat dissipation material layer with the back surface facing down; a connection chip 300 which, after the bare chip is fixed on the chip fixing area, flip-chip bonds the second group of bumps 240 of the at least two bare chips to form a first chip frame 400; a first underfill structure 500 formed by underfilling the first chip frame 400; a substrate 600, wherein for the first chip frame 400 after underfilling, the first group of bumps 230 is flip-chip mounted to the upper surface of the substrate 600 to form a second chip frame 700; a second underfill structure 800 formed by underfilling the second chip frame 700; and a contact array package, wherein for the second chip frame after underfilling, the contact array package is made on the lower surface of the substrate, such as solder ball 900 implantation.

[0071] In a preferred embodiment, the heat sink 100 is a planar heat sink or a heat sink with grooves, and the surface of the planar heat sink or the surface of the grooves has a metal plating layer in a specific area, and the chip fixing area formed by the interface heat dissipation material layer is provided on the metal plating layer for each bare chip; wherein each chip fixing area has a unique label for identifying the coordinates of the chip fixing area on the heat sink 100.

[0072] In a preferred embodiment, the interface heat dissipation material layer 110 is a material layer formed based on any of the following heat dissipation materials: any of nickel, tin, copper, gold, aluminum, silver; an alloy of any of nickel, tin, copper, gold, aluminum, silver; and graphene.

[0073] In a preferred embodiment, the contact array package includes BGA, LGA or PGA.

[0074] More implementation details and effects of the chip structure can refer to the aforementioned embodiment one about the preparation method, and will not be described here again.

[0075] It should also be noted that the terms "comprising", "containing", or any other variant thereof, are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0076] The above is only an embodiment of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for fabricating a single chip, characterized in that, This includes the following steps performed sequentially: S1, providing at least two bare chips and a heat sink (100) suitable for arranging the at least two bare chips, wherein the front side of the bare chip has a first set of bumps (230) and a second set of bumps (240) with a height smaller than the first set of bumps (230), and the back side of the bare chip has a metal plating layer, and the surface of the heat sink forms a chip fixing area through an interface heat dissipation material layer (110), wherein providing the heat sink (100) includes: providing a planar heat sink or a heat sink with a groove; providing a metal plating layer on the surface of the planar heat sink or the surface of the groove; and providing the chip fixing area formed by the interface heat dissipation material layer (110) on the metal plating layer for each bare chip; S2, the at least two bare chips are fixed to the chip fixing area on the surface of the heat sink by bonding the interface heat dissipation material layer (110) with the back side facing down; S3, the second set of bumps (240) of the at least two bare chips are flip-bonded by the connecting chip (300) to form a first chip frame (400); the height of the connecting chip (300) is less than the height difference of the second set of bumps (240) of the first set of bumps (230); S4, the first chip frame (400) is bottom-filled to form a first bottom-fill structure (500); the first bottom-fill structure (500) covers the second set of bumps (240). S5, for the first chip frame (400) after bottom filling, the first set of bumps (230) are flip-chip bonded to the upper surface of the substrate (600) to form the second chip frame (700). S6, the second chip frame (700) is bottom-filled to form a second bottom-fill structure (800); the first part of the second bottom-fill structure (800) covers the first set of bumps (230), and the second part of the second bottom-fill structure (800) covers the heat sink and the substrate; And, S7, for the second chip frame (700) after bottom filling, a contact array package is formed on the lower surface of the substrate (600) to obtain a single chip.

2. The preparation method according to claim 1, characterized in that, The interface heat dissipation material layer (110) can be made of any of the following heat dissipation materials: Any one of nickel, tin, copper, gold, aluminum, and silver; Alloys of any of nickel, tin, copper, gold, aluminum, and silver; and Graphene.

3. The preparation method according to claim 1, characterized in that, The heat sink (100) also includes: For each chip fixing area, a unique label is set to identify the coordinates of the chip fixing area on the heat sink (100).

4. The preparation method according to claim 1, characterized in that, Also includes: After the bottom of the second chip frame (700) is filled, the heat sink (100) is fixed with adhesive by dispensing.

5. The preparation method according to claim 1, characterized in that, Fabricating a contact array package on the lower surface of the substrate (600) includes: Solder balls (900) are implanted on the lower surface of the substrate (600) to form a ball grid array package (BGA); A planar grid array package LGA is added to the lower surface of the substrate (600); or A pin placement operation is performed on the lower surface of the substrate (600) to generate a pin grid array package (PGA).

6. A chip structure (1000) prepared by the preparation method according to any one of claims 1 to 5, characterized in that, The chip structure (1000) includes: At least two bare chips, wherein the front side of the bare chip has a first set of bumps (230) and a second set of bumps (240) with a height smaller than the first set of bumps (230), and the back side of the bare chip has a metal plating layer; A heat sink (100) has a chip fixing area formed by an interface heat dissipation material layer (110) on its surface, wherein at least two bare chips are fixed in the chip fixing area with their back faces down by bonding through the interface heat dissipation material layer (110), wherein the heat sink (100) is a planar heat sink or a heat sink with a groove, and a metal plating layer is provided on the surface of the planar heat sink or the surface of the groove, and a chip fixing area formed by the interface heat dissipation material layer (110) is provided on the metal plating layer for each bare chip; A connecting chip (300) is formed by flip-bonding a second set of bumps (240) of at least two bare chips after the bare chips are fixed in the chip fixing area to form a first chip frame (400); the height of the connecting chip (300) is less than the height difference between the second set of bumps (240) of the first set of bumps (230); A first bottom filling structure (500) is formed by bottom filling the first chip frame (400); the first bottom filling structure (500) covers the second set of bumps (240). Substrate (600), wherein, for the first chip frame (400) after bottom filling, the first set of bumps (230) are flip-chip bonded to the upper surface of the substrate (600) to form a second chip frame (700). A second bottom filling structure (800) is formed by bottom filling the second chip frame (700); a first part of the second bottom filling structure (800) covers the first set of bumps (230), and a second part of the second bottom filling structure (800) covers the heat sink and the substrate; as well as, A contact array package is fabricated on the lower surface of the substrate (600) for the second chip frame (700) after bottom filling.

7. The chip structure (1000) according to claim 6, characterized in that, Each chip mounting area has a unique label to identify the coordinates of that chip mounting area on the heat sink.

8. The chip structure (1000) according to claim 6, characterized in that, The interface heat dissipation material layer (110) is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum, and silver; an alloy of any one of nickel, tin, copper, gold, aluminum, and silver; and graphene.

9. The chip structure (1000) according to claim 6, characterized in that, The contact array package includes a ball grid array package (BGA), a planar grid array package (LGA), or a pin grid array package (PGA).

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