A logical optimization method to improve AGC indicators

Abstract

The present invention discloses a method for improving the logic optimization of AGC indicators, wherein the AGC instruction and the load instruction after rate limiting are sent to the DEV deviation block, the DEV deviation block judges the calculation result, and the judged signal is output to the s end and r end of the RS trigger, the RS trigger output signal and the AGC input signal are sent to the AND block, and the judged signal is output to the AXSEL switching block. The outputs of the two switching blocks are summed by the SUM addition block, and finally superimposed on the load instruction after rate limiting, and the next step of unit adjustment is carried out. When the unit increases or decreases the load, a 1MW bias is added to the unit load instruction, so that the unit adjustment can respond quickly and reduce the time to reach the target value. When the load increase or decrease is about to end, the 1MW bias is canceled, which will not affect the final instruction. During the bias cancellation process, the final instruction will not change, effectively extending the unit stabilization time, thereby improving the adjustment accuracy.

Description

Technical Field

[0001] The present invention relates to the field of automatic control, and in particular to a method for improving AGC index logic optimization. Background Art

[0002] AGC (Automatic Generation Control) is short for automatic generation control. Dispatchers use AGC to balance grid power output with grid load, adjust grid frequency deviation to zero, and maintain the rated frequency. When a unit is operating with AGC, it must respond to dispatcher instructions at all times. Dispatchers assess power plants based on AGC indicators. Due to the increasing proportion of renewable energy in the power grid, influenced by weather and electricity load, dispatchers are increasingly stringent in setting AGC indicators for power plants. Furthermore, AGC activations are becoming more frequent, resulting in many power plants having low AGC indicators and facing severe grid scrutiny.

[0003] The AGC index is mainly related to the unit's regulation rate, regulation accuracy, and response time. Among them, the regulation rate and regulation accuracy are the main reasons for the low AGC index. How to improve the regulation rate and regulation accuracy is particularly important in the entire unit control and is directly related to the unit's economy. Summary of the Invention

[0004] The object of the present invention is to overcome the above-mentioned deficiencies in the prior art and to provide a method for improving the logic optimization of AGC indicators. When the AGC command changes, a 1MW bias is instantaneously added (or subtracted) on the basis of the current load command, so that the unit operates faster, thereby improving the unit's regulation rate and response time. When the load command approaches the AGC target value, the increased (or decreased) 1MW bias is canceled. There is a rate limit when the bias is canceled, and this rate is consistent with the load change rate of the unit itself, so that the actual load command remains unchanged during this period, extending the unit's stabilization time, and thus improving the unit's regulation accuracy.

[0005] The technical solution adopted by the present invention to solve the above problems is: a method for improving the logic optimization of AGC indicators, which is characterized in that the AGC instruction and the load instruction after rate limiting are sent to the DEV deviation block, the DEV deviation block judges the calculation result, and the judged signal is output to the s end and r end of the RS trigger, the RS trigger output signal and the AGC input signal are sent to the AND block, and the judged signal is output to the AXSEL switching block. The outputs of the two switching blocks are summed by the SUM addition block and finally superimposed on the load instruction after rate limiting for the next step of unit adjustment.

[0006] When the load starts to increase, the AGC instruction rises in steps. The AGC instruction and the load instruction after rate limitation are input into the X1 and X2 pins of the DEV deviation block respectively. When the deviation is greater than 2, D1 outputs signal "1" and D2 outputs signal "0". The DEV deviation block outputs to the s end of the RS trigger, and the RS trigger outputs signal "1". The RS trigger output and the AGC input signal are judged by the AND block and the output signal "1" is sent to the Z pin of the AXSEL switching block; when the AXSEL switching block pin Z changes from signal "0" to signal "1", the AXSEL switching block output changes from 0 to 1, and the AXSEL switching block outputs 1, which is superimposed on the load instruction after rate limitation by the SUM addition block to form a new load instruction to adjust the unit.

[0007] After the load is increased for a period of time, the AGC instruction and the load instruction after rate limitation are input into the X1 and X2 pins of the DEV deviation block respectively. When the deviation is less than 1, D1 outputs signal "0" and D2 outputs signal "1". The DEV deviation block outputs to the r end of the RS trigger, and the RS trigger outputs signal "0". The RS trigger output and the AGC input signal are judged by the AND block and the output signal "0" is sent to the Z pin of the AXSEL switching block; when the AXSEL switching block pin Z changes from signal "1" to signal "0", the AXSEL switching block output changes from 1 to 0, and the load instruction is no longer superimposed with 1, and becomes the original load instruction value.

[0008] When the load starts to drop, the AGC instruction decreases in steps. The AGC instruction and the load instruction after rate limitation are input into the X2 and X1 pins of the DEV deviation block respectively. When the deviation is greater than 2, D1 outputs signal "1" and D2 outputs signal "0". The DEV deviation block outputs to the s end of the RS trigger, and the RS trigger outputs signal "1". The RS trigger output and the AGC input signal are judged by the AND block and the output signal "1" is sent to the Z pin of the AXSEL switching block; when the Z pin of the AXSEL switching block changes from signal "0" to signal "1", the output of the AXSEL switching block changes from 0 to -1. The AXSEL switching block outputs -1, which is superimposed on the load instruction after rate limitation after the SUM addition block and the LEADLAG block to form a new load instruction to regulate the unit.

[0009] After the load is reduced for a period of time, the AGC instruction and the load instruction after rate limitation are input into the X2 and X1 pins of the DEV deviation block respectively. When the deviation is less than 1, D1 outputs signal "0" and D2 outputs signal "1". The DEV deviation block outputs to the reset terminal of the RS trigger, and the RS trigger outputs signal "0". The RS trigger output and the AGC input signal are judged by the AND block, and the output signal "0" is sent to the Z pin of the AXSEL switching block; when the AXSEL switching block pin Z changes from signal "1" to signal "0", the AXSEL switching block output changes from -1 to 0, and the load instruction no longer adds -1, and becomes the original load instruction value.

[0010] When the unit is put into AGC mode, the AGC input signal is "1", and the AND block may output signal "1". When the unit exits AGC mode, the AGC input signal is "0", and the AND block continuously outputs signal "0". The loop does not work to prevent the loop from causing disturbances to the unit regulation when the AGC exits.

[0011] When the AXSEL switching block output switches from X1 to X2, it has a rate limiting function, and its switching rate is R1, which is the same as the unit load change rate; when the AXSEL switching block output switches from X2 to X1, no rate limiting function is set; the R1 rate of the AXSEL switching block is consistent with the load change rate, and the decrease (increase) of the switching block is consistent with the increase (decrease) of the unit instruction. During this period, the final instruction remains unchanged, effectively extending the unit's stabilization time.

[0012] The input pin X1 of the SUM addition block corresponds to the superimposed value of the load instruction during the unit's load increase process, and the input pin X2 of the SUM addition block corresponds to the superimposed value of the load instruction during the unit's load reduction process; when the load is increased, X2 is 0, and the SUM addition block outputs X1; when the load is reduced, X1 is 0, and the SUM addition block outputs X2.

[0013] Compared with existing technologies, this invention offers the following advantages and effects: When the unit increases or decreases load, a 1MW offset is added to the unit load command, enabling faster unit regulation and reducing the time it takes to reach the target value. When the load increase or decrease is nearing completion, the 1MW offset is canceled without affecting the final command. During the offset cancellation process, the final command remains unchanged, effectively extending the unit's stabilization time and improving regulation accuracy. This invention effectively improves the unit's AGC performance, creating valuable benefits for the unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow chart of the existing technical solution.

[0015] Figure 2This is a schematic diagram of the logical structure of the RTLMT rate limiting block in the existing technical solution.

[0016] Figure 3 This is a control logic diagram corresponding to the method for improving the AGC index logic optimization in an embodiment of the present invention.

[0017] Figure 4 Schematic diagram of the logical structure of the DEV deviation block in an embodiment of the present invention.

[0018] Figure 5 Schematic diagram of the logical structure of the AXSEL switching block in an embodiment of the present invention.

[0019] Figure 6 It is a schematic diagram of a comparative test between the prior art solution and the present invention in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and through examples. The following examples are intended to explain the present invention but the present invention is not limited to the following examples.

[0021] Example

[0022] See also Figure 1 In the prior art, the AGC instruction generates a unit load instruction after a certain load change rate, and the unit performs the next adjustment based on the load instruction. The rate limit block uses the algorithm block model RTLMT in the distributed control system. The algorithm block is described as follows:

[0023] like Figure 2 As shown, RTLMT is a rate limiting block, X is an input pin, PR is a positive rate limit, NR is a negative rate limit, and the unit is MW / min. This embodiment takes a 330MW unit as an example, and the change rate is 10MW / min.

[0024] See also Figure 3 In this embodiment, a method for improving the logic optimization of AGC indicators is established based on the existing technology. A DEV deviation block is established to send the AGC instruction and the load instruction after rate limitation to the DEV deviation block for calculation and judgment. The DEV deviation module uses the algorithm block model DEV in the distributed control system. The algorithm block is described as follows:

[0025] like Figure 4As shown, DEV is a deviation calculation block with judgment functionality. Pins X1 and X2 are inputs. The deviation is X1-X2. H is the output upper limit, L is the output lower limit, D1 is the upper limit exceeding alarm signal, and D2 is the lower limit exceeding alarm signal. When the deviation (X1-X2) exceeds H, D1 outputs a "1" signal and D2 outputs a "0" signal. When the deviation (X1-X2) falls below L, D1 outputs a "0" signal and D2 outputs a "1" signal. In this example, using a 330MW unit as an example, the output upper limit H is set to 2 and the output lower limit L is set to 1.

[0026] Preferably, there are two DEV deviation blocks in this embodiment.

[0027] Load raising process, schematic diagram Figure 3 The DEV deviation block in the middle and lower part works. When the load starts to rise, the AGC instruction rises in steps. The deviation between the AGC instruction and the load instruction after rate limiting is greater than 2. At this time, D1 outputs a signal "1" and D2 outputs a signal "0". After the load is raised for a period of time, the deviation between the AGC instruction and the load instruction after rate limiting gradually decreases. When the deviation is less than 1, D1 outputs a signal "0" and D2 outputs a signal "1". During the entire load raising process, the diagram Figure 3 The DEV deviation block D1 in the middle continuously outputs a signal of "0", and D2 continuously outputs a signal of "1", which does not work.

[0028] Load reduction process, schematic diagram Figure 3 The DEV deviation block above works. When the load starts to drop, the AGC instruction drops in steps. The deviation between the load instruction after rate limiting and the AGC instruction is greater than 2. At this time, D1 outputs a signal "1" and D2 outputs a signal "0". After the load is dropped for a period of time, the deviation between the load instruction after rate limiting and the AGC instruction gradually decreases. When the deviation is less than 1, D1 outputs a signal "0" and D2 outputs a signal "1". During the entire load drop process, the diagram Figure 3 The DEV deviation block D1 in the middle and bottom continuously outputs the signal "0", and D2 continuously outputs the signal "1", which is ineffective.

[0029] An RS trigger is established to receive the signal from the DEV deviation block. The output D1 of the DEV deviation block is sent to the S end of the RS trigger to set the output signal "1". The output D2 of the DEV deviation block is sent to the R end of the RS trigger to reset the output signal "0".

[0030] As a preference, there are two RS triggers in this embodiment. Figure 3 The RS trigger above continuously receives the signal "0" at the S end, and continuously outputs the signal "0" at the R end, which does not work. Figure 3 The RS trigger below the middle outputs the signal based on the judgment. Figure 3 The RS trigger at the bottom of the middle continuously receives the signal "0", the R terminal continuously receives the signal "1", and continuously outputs the signal "0", which does not work. Figure 3 The RS flip-flop above determines the output signal. An AND block is built to receive the RS flip-flop signal and the AGC input signal.

[0031] Preferably, in this embodiment, there are two AND blocks. When the unit is in AGC mode, the AGC engagement signal is "1," and the AND block may output a signal "1." When the unit exits AGC mode, the AGC engagement signal is "0," and the AND block continuously outputs a signal "0," rendering the circuit inoperative. This prevents disturbances to the unit's regulation when the AGC is exited.

[0032] Create an AXSEL switching block and use the output of the AND block as the switching condition. The AXSEL switching block uses the algorithm block model AXSEL in the distributed control system. The algorithm block is described as follows:

[0033] like Figure 5 As shown, the AXSEL switching block is an analog switching function block. When the switching signal Z changes, the output of the function block can switch between signal X1 and signal X2, and the rate of change of the module output during switching can be limited to the set range. When Z changes from 1 to 0, the output Y switches from X1 to X2 at the rate of change of R1. When Z changes from 0 to 1, the output Y switches from X2 to X1 at the rate of change of R2. R1 and R2 are 0 by default, that is, there is no rate limit. This embodiment takes a 330MW unit as an example, Figure 3 In the middle, the AXSEL switch block X1 is set to -1MW, X2 is set to 0MW, R1 is the load change rate 8MW / min, and R2 has no rate limit; Figure 3 In the middle and lower AXSEL switching block, X1 is set to 1MW, X2 is set to 0MW, R1 is the load change rate of 8MW / min, and R2 has no rate limit.

[0034] As a preference, there are two AXSEL switching blocks in this embodiment. When the unit is put into AGC mode and the load is increased, if the deviation between the AGC instruction and the load instruction after rate limitation is greater than 2, it indicates Figure 3 The AXSEL switch block Z below changes from "0" to "1", and the AXSEL switch block output changes from 0MW to 1MW, with no rate limit. When the load is increased for a period of time, the deviation between the AGC instruction and the load instruction after rate limit is less than 1MW, indicating that Figure 3 The AXSEL switch block Z below changes from "1" to "0", and the AXSEL switch block output changes from 1MW to 0MW at a rate of 8MW / min. Figure 3The AXSEL switch block Z above is continuously “0”, and the switch block output is continuously 0 and does not work. When the unit is put into AGC mode and the load is reduced, if the deviation between the load instruction after rate limitation and the AGC instruction is greater than 2MW, it indicates Figure 3 The AXSEL switch block Z above changes from "0" to "1", and the AXSEL switch block output changes from 0MW to -1MW, with no rate limit. When the load is reduced for a period of time, the deviation between the AGC instruction and the load instruction after rate limit is less than 1MW, indicating Figure 3 The AXSEL switch block Z above changes from "1" to "0", and the AXSEL switch block output changes from -1MW to 0MW at a rate of 8MW / min. Figure 3 The Z of the AXSEL switch block below is continuously "0", and the switch block output is continuously 0 and does not work.

[0035] Preferably, in this embodiment, the R1 rate of the AXSEL switching block is consistent with the load change rate. When the output of the switching block switches from 1 (or -1) to 0, the decrease (increase) of the switching block is consistent with the increase (decrease) of the unit instruction, so that the final load instruction of this process remains unchanged, effectively extending the stabilization time of the unit. The R2 rate of the AXSEL switching block is unlimited. When the output of the switching block instantly steps from 0 to 1 (-1), the response speed of the unit load is effectively improved. In order to verify and illustrate the technical effects adopted in the present invention, this embodiment selects a traditional technical solution and the present invention for comparative testing, and compares the test results by means of scientific demonstration to test the true effect of the present invention. See Figure 6 As can be seen from the figure, the present invention is significantly different from the traditional technical solution and has a better control effect.

[0036] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

[0037] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the scope of protection of the present invention. Any changes and modifications made by any technician familiar with the technology without departing from the concept and scope of the present invention should fall within the scope of protection of the present invention.

Claims

1. A method for improving AGC index logic optimization, characterized by: The AGC command and the load command after rate limitation are sent to the DEV deviation block. The DEV deviation block judges the calculation result and outputs the judged signal to the s and r terminals of the RS trigger. The RS trigger output signal and the AGC input signal are sent to the AND block. The judged signal is output to the AXSEL switching block. The outputs of the two switching blocks are summed by the SUM addition block and finally added to the load command after rate limitation for the next unit adjustment. When the load starts to increase, the AGC instruction increases in steps. The AGC instruction and the load instruction after rate limiting are input into the X1 and X2 pins of the DEV deviation block respectively. When the deviation is greater than 2, D1 outputs a signal "1" and D2 outputs a signal "0". The DEV deviation block outputs to the s end of the RS trigger, and the RS trigger outputs a signal "1". The RS trigger output and the AGC input signal are judged by the AND block and output a signal "1" which is sent to the Z pin of the AXSEL switching block. When the Z pin of the AXSEL switching block changes from a signal "0" to a signal "1", the AXSEL switching block output changes from 0 to 1. The AXSEL switching block outputs 1, which is superimposed on the load instruction after rate limiting by the SUM addition block to form a new load instruction for regulating the unit. After the load is increased for a period of time, the AGC instruction and the load instruction after rate limitation are input into the X1 and X2 pins of the DEV deviation block respectively. When the deviation is less than 1, D1 outputs a signal "0", and D2 outputs a signal "1". The DEV deviation block outputs to the r terminal of the RS trigger, and the RS trigger outputs a signal "0". The RS trigger output and the AGC input signal are judged by the AND block, and the output signal "0" is sent to the Z pin of the AXSEL switch block; when the Z pin of the AXSEL switch block changes from signal "1" to signal "0", the output of the AXSEL switch block changes from 1 to 0, and the load instruction no longer adds 1, and returns to the original load instruction value; When the load starts to drop, the AGC instruction decreases in steps. The AGC instruction and the load instruction after rate limiting are input into the X2 and X1 pins of the DEV deviation block respectively. When the deviation is greater than 2, D1 outputs a signal "1", and D2 outputs a signal "0". The DEV deviation block outputs a signal to the s end of the RS trigger, and the RS trigger outputs a signal "1". The RS trigger output and the AGC input signal are judged by the AND block and output a signal "1", which is sent to the Z pin of the AXSEL switching block. When the Z pin of the AXSEL switching block changes from a signal "0" to a signal "1", the output of the AXSEL switching block changes from 0 to -1. The AXSEL switching block outputs -1, which is added to the load instruction after rate limiting after the SUM addition block and the LEADLAG block to form a new load instruction for regulating the unit. After the load is reduced for a period of time, the AGC instruction and the load instruction after rate limitation are input into the X2 and X1 pins of the DEV deviation block respectively. When the deviation is less than 1, D1 outputs signal "0", D2 outputs signal "1", and the DEV deviation block outputs to the reset terminal of the RS trigger. The RS trigger outputs signal "0". The RS trigger output and the AGC input signal are judged by the AND block and output signal "0", which is sent to the Z pin of the AXSEL switching block; when the Z pin of the AXSEL switching block changes from signal "1" to signal "0", the output of the AXSEL switching block changes from -1 to 0, and the load instruction no longer adds -1, but returns to the original load instruction value.

2. The method for improving AGC index logic optimization according to claim 1, characterized in that: When the unit is put into AGC mode, the AGC input signal is "1" and the AND block outputs signal "1"; when the unit exits AGC mode, the AGC input signal is "0" and the AND block continuously outputs signal "0". This loop does not work to prevent the loop from causing disturbances to the unit regulation when AGC exits.

3. The method for improving AGC index logic optimization according to claim 1, wherein: When the AXSEL switching block output switches from X1 to X2, it has a rate limiting function, and the switching rate is R1, which is the same as the unit load change rate; when the AXSEL switching block output switches from X2 to X1, the rate limiting function is not set; the R1 rate of the AXSEL switching block is consistent with the load change rate, and the decrease / increase of the switching block is consistent with the increase / decrease of the unit instruction. During this period, the final instruction remains unchanged, thereby extending the unit's stabilization time.

4. The method for improving AGC index logic optimization according to claim 1, wherein: The input pin X1 of the SUM addition block corresponds to the superimposed value of the load instruction during the unit's load increase process, and the input pin X2 of the SUM addition block corresponds to the superimposed value of the load instruction during the unit's load reduction process; when the load is increased, X2 is 0, and the SUM addition block outputs X1; when the load is reduced, X1 is 0, and the SUM addition block outputs X2.

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