Power factor correction converter, controller and zero current prediction circuit thereof

Abstract

A power factor correction converter, a controller and a zero current prediction circuit thereof. The power factor correction converter includes a power stage circuit, a current sensing circuit and a zero current prediction circuit. The power stage circuit is used to convert a rectified power source to generate an output power source, wherein the power stage circuit operates in a boundary conduction mode to correct the power factor of the rectified power source. The current sensing circuit is used to sense a current of an inductor to generate a current sensing signal. The zero current prediction circuit is used to control at least one switch according to the following steps: generating a second time period from a first time period between a first threshold value and a second threshold value according to a level of the current sensing signal; and switching a state of the at least one switch at an end point of the second time period, wherein the end point of the second time period corresponds to a zero current point when a current value of the inductor reaches zero.

Description

TECHNICAL FIELD

[0001] The present invention relates to a converter, and more particularly, to a power factor correction converter. The present invention also relates to a power factor correction controller and a zero current prediction circuit suitable for a power factor correction converter. BACKGROUND

[0002] Please refer to Figure 1 , Figure 1 is a circuit schematic diagram of a prior art power factor correction converter 100. As shown, a common power factor correction converter is a boost switching converter operating in a boundary conduction mode (BCM) to convert a rectified power supply into an output power supply to improve the power factor of a power supply system. The rectified power supply has a rectified voltage Vi, and the output power supply has an output voltage Vo.

[0003] Please further refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B is a waveform diagram of the prior art power factor correction converter 100 operating in a boundary conduction mode with a fixed conduction time ton. Figure 2A and Figure 2B In the prior art of Figure 2A , the waveform W1 is the current I L of the inductor L, the waveform W2 is the current I L of the diode D5, and the waveform W2' is the current I1 of the transistor Q1. L,avg When the current I D of the inductor L drops to zero, the control signal G1 will be converted from a low potential state to a high potential state, at which time the transistor Q1 of the power factor correction converter 100 will be controlled to be in an on state with a fixed conduction time ton. This periodic switching causes the average current I L of the inductor to be in phase with the rectified voltage Vi to improve the power factor of an AC input power supply, which has an AC input voltage Vac.

[0004] As shown in Figure 2B , the waveform W2 is the current I D of the diode D5, and the waveform W2' is the current I1 of the transistor Q1 (dashed line). When the transistor Q1 is in an on state, the current I L of the inductor L will flow through the transistor Q1 and not through the diode D5, at which time the current I L of the diode D5 is zero, and the current I1 of the transistor Q1 is the current I D of the inductor L. When the transistor Q1 is in an off state, the current I L of the inductor L will flow through the diode D5 and not through the transistor Q1, at which time the current I L of the diode D5 is the current I D of the inductor L, and the current I1 of the transistor Q1 is 0.

[0005] To achieve boundary conduction mode functionality, zero-current sensing circuitry becomes an essential component in power factor correction converters. For example... Figure 1 As shown, a prior art power factor correction converter 100 includes a zero current sensing circuit 101, wherein the zero current sensing circuit 101 is used to sense the current I of the inductor L. L The point at which the current turns to zero (hereinafter referred to as the zero current point of inductor L).

[0006] The existing zero-current sensing circuit 101 can generate a fixed delay time by using a fixed threshold to sense the zero-current point of the inductor L. However, the accuracy of this sensing method is not ideal. Please refer to... Figure 3 , Figure 3 This is a comparison diagram of the operating waveforms in a prior art power factor correction converter 100. For example... Figure 3 As shown, waveforms W3 and W4 (dashed lines) represent the current I of inductor L under different rectified voltages Vi. L Since the rectified voltage Vi changes over time, the current I in the inductor L will also change. L The slope also changes over time, therefore the required delay time varies when detecting zero current with a fixed threshold. Figure 3 For example, when the fixed threshold is 4 millivolts (mV), the current value of inductor L in waveform W3 starts from 4 millivolts and needs a delay time Td1 to become zero; while the current value of inductor L in waveform W4 starts from 4 millivolts and needs a delay time Td2 to become zero, where the value of delay time Td1 is less than the value of delay time Td2. Therefore, if the zero-current sensing circuit 101 uses only a fixed threshold and a fixed delay time to sense the zero-current point of inductor L, it will produce an error, causing the power factor correction converter 100 to receive an incorrect zero-current point, thus preventing the power factor correction converter 100 from operating stably in the boundary conduction mode.

[0007] In view of this, the present invention addresses the shortcomings of the prior art by proposing a power factor correction controller and a zero current prediction circuit suitable for a power factor correction converter, enabling the power factor correction converter to accurately sense the zero current point of the inductor, thereby enabling the power factor correction converter to operate stably in the boundary conduction mode. Summary of the Invention

[0008] In one aspect, the present application provides a power factor correction converter, comprising: a power stage circuit including at least one switch for switching a coupling relationship between an inductor and a rectified power source and an output power source to convert the rectified power source to the output power source, wherein the power stage circuit is configured to operate in a boundary conduction mode to correct a power factor of the rectified power source; a current sensing circuit for sensing a current of the inductor to generate a current sensing signal; and a zero current prediction circuit for controlling the at least one switch, wherein the zero current prediction circuit controls the at least one switch according to the following steps: generating a second time period from a first time period between a first threshold and a second threshold according to a level of the current sensing signal; and switching a state of the at least one switch at an end point of the second time period, wherein the end point of the second time period corresponds to a zero current point when the current of the inductor reaches zero.

[0009] In another aspect, the present application also provides a power factor correction controller for a power factor correction converter, comprising: a zero current prediction circuit for controlling at least one switch of a power stage circuit to switch a coupling relationship between an inductor and a rectified power source and an output power source to convert the rectified power source to the output power source, wherein the power stage circuit is configured to operate in a boundary conduction mode to correct a power factor of the rectified power source; wherein the zero current prediction circuit controls the at least one switch according to the following steps: generating a second time period from a first time period between a first threshold and a second threshold according to a level of a current sensing signal generated by a current sensing circuit, wherein a length of the second time period is related to a length of the first time period; and switching a state of the at least one switch at an end point of the second time period, wherein the end point of the second time period corresponds to a zero current point when the current of the inductor reaches zero; an error amplifier for generating an error amplified signal according to a difference between a reference voltage and a feedback voltage; and a pulse width modulation circuit for generating a control signal according to the error amplified signal and a signal related to the zero current point, wherein the control signal is used to control switching of the at least one switch.

[0010] In some embodiments, the power factor correction converter further comprises: a feedback circuit for generating a feedback voltage according to the output power source; an error amplifier for generating an error amplified signal according to a difference between a reference voltage and the feedback voltage; and a pulse width modulation circuit for generating a control signal according to the error amplified signal and a signal related to the zero current point, wherein the control signal is used to control switching of the at least one switch.

[0011] In some embodiments, the first time period has a same length as the second time period.

[0012] In some embodiments, an absolute value of a difference between the first threshold and the second threshold is less than a peak-to-peak value of the current sense signal.

[0013] In some embodiments, an absolute value of a difference between the first threshold and the second threshold is less than 1 / 2 of a peak-to-peak value of the current sense signal.

[0014] In some embodiments, the zero-current prediction circuit comprises a first comparator configured to generate a first comparison signal according to a level of the current sense signal and the first threshold, and a second comparator configured to generate a second comparison signal according to the level of the current sense signal and the second threshold, and the zero-current prediction circuit is configured to generate the first time period according to the first comparison signal and the second comparison signal.

[0015] In some embodiments, the zero-current prediction circuit further comprises a timing circuit configured to generate a timing signal according to the first comparison signal and the second comparison signal, the timing signal indicating a time period during which the level of the current sense signal passes between the first threshold and the second threshold, and the timing circuit is configured to generate the second time period according to the timing signal, wherein the second time period has a time ratio with the first time period.

[0016] In some embodiments, the timing circuit comprises at least one integrating capacitor and at least one current source, and the zero-current prediction circuit is configured to control the at least one switch according to the following steps: when the level of the current sense signal passes the second threshold at a first time point, the at least one current source starts a first integration of the at least one integrating capacitor from an initial voltage; when the level of the current sense signal passes the first threshold at a second time point, the at least one current source stops the first integration of the at least one integrating capacitor, wherein the at least one integrating capacitor generates a first integrated voltage at the second time point; the at least one current source starts a second integration of the at least one integrating capacitor from the second time point, wherein a time difference between the first time point and the second time point is the first time period; and during the second integration, a third time point is determined according to a voltage of the at least one integrating capacitor and the first integrated voltage, wherein a time difference between the second time point and the third time point is the second time period, and the third time point corresponds to the zero-current time point.

[0017] In some embodiments, an absolute value of a difference between the first threshold and the second threshold is equal to an absolute value of a difference between the first threshold and the level of the current sense signal at the third time point.

[0018] In some embodiments, the at least one integrating capacitor includes a first integrating capacitor and a second integrating capacitor, the at least one current source includes a first current source and a second current source, and the timing circuit further includes a third comparator configured to compare the first integrated voltage with a voltage of the second integrating capacitor to generate a third comparison signal; wherein the zero-current prediction circuit controls the at least one switch according to the following steps: at the first time point, the voltage of the first integrating capacitor is reset to the initial potential, the first current source starts the first integration of the first integrating capacitor from the initial potential; at the second time point, the first current source stops the first integration of the first integrating capacitor, the first integrated voltage is generated by the first integrating capacitor, and the voltage of the second integrating capacitor is reset to the initial potential, the second current source starts the second integration of the second integrating capacitor from the initial potential; and during the second integration, according to the third comparison signal, when the voltage of the second integrating capacitor reaches the first integrated voltage, the third time point is determined; wherein the time period ratio between the first time period and the second time period is related to a current source ratio between the first current source and the second current source and a capacitance value ratio between a capacitance value of the first integrating capacitor and a capacitance value of the second integrating capacitor.

[0019] In some embodiments, the timing circuit further includes a sample-and-hold circuit configured to sample and hold the first integrated voltage to generate a sample-and-hold voltage, and a third comparator configured to compare the sample-and-hold voltage with a voltage of the at least one integrating capacitor to generate a third comparison signal; wherein the zero-current prediction circuit controls the at least one switch according to the following steps: at the first time point, the voltage of the at least one integrating capacitor is reset to the initial potential, the at least one current source starts the first integration of the at least one integrating capacitor from the initial potential; at the second time point, the at least one current source stops the first integration of the at least one integrating capacitor, the first integrated voltage is generated by the at least one integrating capacitor, and the sample-and-hold circuit samples and holds the first integrated voltage to generate the sample-and-hold voltage, and then the voltage of the at least one integrating capacitor is reset to the initial potential, the at least one current source starts the second integration of the at least one integrating capacitor from the initial potential; during the second integration, when the third comparison signal indicates that the voltage of the at least one integrating capacitor reaches the sample-and-hold voltage, the third time point is determined.

[0020] In some embodiments, the at least one current source includes a first current source and a second current source, and the timing circuit further includes a third comparator configured to compare the voltage of the at least one integrating capacitor with a preset potential to generate a third comparison signal; wherein the zero-current prediction circuit controls the at least one switch according to the following steps: at the first time point, the voltage of the at least one integrating capacitor is reset to the initial potential, and the first current source starts the first integration of the at least one integrating capacitor from the initial potential; at the second time point, the first current source stops the first integration of the at least one integrating capacitor, and the at least one integrating capacitor generates the first integrated voltage, and then the second current source starts the second integration of the at least one integrating capacitor from the first integrated voltage; and during the second integration, when the third comparison signal indicates that the voltage of the at least one integrating capacitor reaches the preset potential, the third time point is determined; wherein the time period ratio between the first time period and the second time period is related to a current source ratio between the first current source and the second current source.

[0021] In another aspect, the present application also provides a control method of a power factor correction converter, comprising: controlling a switch to switch a coupling relationship between an inductor and a rectified power source and an output power source, thereby converting the rectified power source into the output power source, wherein the inductor is configured to operate in a boundary conduction mode to correct the power factor of the rectified power source; sensing a current of the inductor to generate a current sensing signal; generating a second time period through a first time period between a first threshold value and a second threshold value according to a level of the current sensing signal, wherein a length of the second time period is related to a length of the first time period; and switching a state of at least one switch at an end point of the second time period; wherein the end point of the second time period corresponds to a zero-current point when the current value of the inductor reaches 0.

[0022] In some embodiments, the step of generating the second time period includes: starting to time the first time period when the level of the current sensing signal passes through the second threshold value at a first time point; ending to time the first time period when the level of the current sensing signal passes through the first threshold value at a second time point; and timing according to the length of the first time period to generate the second time period from the second time point.

[0023] The purposes, technical contents, characteristics and effects of the present application will be further illustrated in detail by specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a circuit schematic diagram of a power factor correction converter of the prior art.

[0025] Figure 2Ais a waveform diagram of a prior art power factor correction converter operating in boundary conduction mode (one).

[0026] Figure 2B is a waveform diagram of a prior art power factor correction converter operating in boundary conduction mode (two).

[0027] Figure 3 is a waveform comparison diagram of inductor current at different rectified voltages in a prior art power factor correction converter.

[0028] Figure 4A is a circuit schematic diagram of a power factor correction converter in an embodiment of the present invention.

[0029] Figure 4B is a block diagram of a power factor correction converter in an embodiment of the present invention.

[0030] Figure 5A is a circuit schematic diagram of a current sensing circuit in an embodiment of the present invention.

[0031] Figure 5B is a circuit schematic diagram of a current sensing circuit in another embodiment of the present invention.

[0032] Figure 5C is a waveform diagram of a current sensing signal and inductor current in different embodiments of the present invention.

[0033] Figure 6 is a block diagram of a zero current prediction circuit in an embodiment of the present invention.

[0034] Figure 7 is a circuit schematic diagram of a zero current prediction circuit in an embodiment of the present invention.

[0035] Figure 8 is a waveform diagram of signals in a zero current prediction circuit in an embodiment of the present invention.

[0036] Figure 9A is a circuit schematic diagram of a falling edge sensor in an embodiment of the present invention.

[0037] Figure 9B is a waveform diagram of input voltage of a falling edge sensor and output voltage of a falling edge sensor in an embodiment of the present invention.

[0038] Figure 10 is a circuit schematic diagram of a timing circuit (one) in another embodiment of the present invention.

[0039] Figure 11 is a waveform diagram of signals in a zero current prediction circuit in another embodiment of the present invention.

[0040] Figure 12 is a circuit diagram of a timing circuit (two) in another embodiment of the present application.

[0041] Figure 13 is a flow chart of a control method of a power factor correction converter in an embodiment of the present application.

[0042] Figure 14 is a block diagram of a power factor correction controller in an embodiment of the present application.

[0043] Legend of symbols

[0044] 100: power factor correction converter

[0045] 101: zero current sensing circuit

[0046] 200: power factor correction converter

[0047] 210: power stage circuit

[0048] 220: current sensing circuit

[0049] 220A: power factor correction converter

[0050] 220B: power factor correction converter

[0051] 230: zero current prediction circuit

[0052] 230A: zero current prediction circuit

[0053] 230B: zero current prediction circuit

[0054] 230C: zero current prediction circuit

[0055] 231A: first comparator

[0056] 231B: second comparator

[0057] 231C: third comparator

[0058] 232: falling edge sensor

[0059] 232A: falling edge sensor

[0060] 232B: falling edge sensor

[0061] 232C: falling edge sensor

[0062] 233A: latch circuit

[0063] 233B: latch circuit

[0064] 235: timing circuit

[0065] 235A: timing circuit

[0066] 235B: timing circuit

[0067] 235C: timing circuit

[0068] 240: feedback circuit

[0069] 250: rectifier

[0070] 260: error amplifier

[0071] 270: pulse width modulation circuit

[0072] 400: power factor correction converter

[0073] 410: power stage circuit

[0074] 420: power factor correction controller

[0075] 421: zero current prediction circuit

[0076] 422: error amplifier

[0077] 423: pulse width modulation circuit

[0078] 430: current sense circuit

[0079] 440: feedback circuit

[0080] AND: AND gate

[0081] BUF: buffer

[0082] C1-C2: capacitor

[0083] Cramp1: first integration capacitor

[0084] Cramp2: second integration capacitor

[0085] CMPC: third comparison signal

[0086] CMP_Vth1: first comparison signal

[0087] CMP_Vth1_nedge: falling edge of first comparison signal

[0088] CMP_Vth2: second comparison signal

[0089] CMP_Vth2_nedge: falling edge of first comparison signal

[0090] D1-D5: diode

[0091] Ddst: second latch signal

[0092] Delay: delay circuit

[0093] Din: input signal

[0094] Dout: output signal

[0095] Dsrc: first latch signal

[0096] G1: control signal

[0097] GNDin: input-side ground

[0098] GNDout: output-side ground

[0099] Iramp1: first current source

[0100] Iramp2: second current source

[0101] I D : current of diode

[0102] I L : current of inductor

[0103] I L,avg : average current of inductor

[0104] INV: inverter

[0105] L: inductor

[0106] OR: OR gate

[0107] Q1: transistor

[0108] R1: dashed box

[0109] Rcs: current sense resistor

[0110] Rfb1: resistor

[0111] Rfb2: resistor

[0112] Ro: output terminal

[0113] S1: switch

[0114] S2: switch

[0115] SH: sample-and-hold circuit

[0116] t1: first time point

[0117] t2: second time point

[0118] t3: third time point

[0119] toff: turn-off time

[0120] ton: turn-on time

[0121] Td1: delay time

[0122] Td2: delay time

[0123] Tdst: second period

[0124] Tsrc: first period

[0125] Vac: AC input voltage

[0126] Vc1: voltage

[0127] Vc2: voltage

[0128] Vdst: second integral voltage

[0129] Vfb: feedback voltage

[0130] Vi: rectified voltage

[0131] Vo: output voltage

[0132] Vpre: preset potential

[0133] Vref: reference voltage

[0134] Vsrc: first integral voltage

[0135] Vsrc_sh: sample hold voltage

[0136] VCS: current sense signal

[0137] VEOA: error amplifier signal

[0138] W1-W6: waveforms

[0139] ZC: zero current crossing signal DETAILED DESCRIPTION

[0140] The drawings in the present disclosure are schematic and mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to the scale. For the purpose of clear illustration, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application.

[0141] Please refer to Figure 4A , Figure 4A is a circuit schematic diagram of a power factor correction converter 200 in an embodiment of the present disclosure. As shown in Figure 4AAs shown, the power factor correction converter 200 includes a power stage circuit 210, a current sensing circuit 220, a zero current prediction circuit 230, a feedback circuit 240, and a rectifier 250. The power stage circuit 210 is coupled to the current sensing circuit 220, and the current sensing circuit 220 is coupled to the zero current prediction circuit 230. The power stage circuit 210 includes a switch Q1, an inductor L, a diode D5, and a capacitor C2. In this embodiment, the power stage circuit 210 is, for example, as shown below. Figure 4A The illustrated boost power stage circuit switches the coupling relationship between inductor L and the rectified power supply (which has a rectified voltage Vi) and the output power supply (which includes an output voltage Vo) to convert the rectified power supply into the output power supply. In this embodiment, power stage circuit 210 is used to operate in boundary conduction mode (BCM) to correct the power factor (PF) of the rectified power supply (which has a rectified voltage Vi). Current sensing circuit 220 is used to sense the current I of inductor L. L This generates a current sensing signal VCS. The zero-current prediction circuit 230 generates a control signal G1 to control switch Q1. The zero-current prediction circuit 230 controls switch Q1 according to the following steps:

[0142] The second time period is generated based on the level of the current sensing signal VCS through a first time period between a first threshold and a second threshold; and

[0143] The state of switch Q1 is switched at the end of the second time period, where the end of the second time period corresponds to the zero current point when the current value of inductor L reaches 0.

[0144] Please refer to Figure 4B , Figure 4B This is a block diagram of a power factor correction converter 200 according to one embodiment of the present invention. Figure 4B As shown, in some embodiments, the power factor correction converter 200 includes a power stage circuit 210, a current sensing circuit 220, a zero-current prediction circuit 230, a feedback circuit 240, a rectifier 250, an error amplifier 260, and a pulse width modulation circuit 270. The feedback circuit 240 is coupled to the power stage circuit 210, the rectifier 250 is coupled to the power stage circuit 210, the error amplifier 260 is coupled to the feedback circuit 240, and the pulse width modulation circuit 270 is coupled to both the zero-current prediction circuit 230 and the error amplifier 260. The structure and function of each of the power stage circuit 210, current sensing circuit 220, zero-current prediction circuit 230, feedback circuit 240, rectifier 250, error amplifier 260, and pulse width modulation circuit 270 will be explained in detail below, along with their interrelationships.

[0145] In some embodiments, the power stage circuit 210 includes at least one switch, wherein the at least one switch may be a bipolar junction transistor (BJT) or a metal-oxide-semiconductor (MOSFET). Figure 4A As shown, the power stage circuit 210 is, for example, a boost power stage circuit, including an inductor L, a diode D5, a transistor Q1, and a capacitor C2. In some embodiments, the power stage circuit 210 is used to switch the coupling relationship between the inductor L and the rectified power supply and the output power supply to convert the rectified power supply into the output power supply. The operation of the power stage circuit 210 is controlled by a control signal G1. In the application of the present invention, the output voltage Vo is higher than the rectified voltage Vi. When the control signal G1 is in a high potential state, the transistor Q1 is controlled to be in the conducting state and the diode D5 is in the non-conducting state. At this time, the voltage across the inductor L is positive, causing the current I of the inductor L to be positive. L When the control signal G1 is at a low potential, transistor Q1 is controlled to be in the non-conducting state and diode D5 is in the conducting state. At this time, the voltage across inductor L is negative, causing the current I in inductor L to rise. L The current I in inductor L decreases, and at the same time... L It remains positive and charges capacitor C2 to generate output power so that the output voltage Vo is higher than the rectified voltage Vi.

[0146] In some embodiments, the current sensing circuit 220 is used to sense the current I of the inductor L. L This generates a current sensing signal, VCS. Please also refer to... Figure 5A , Figure 5B and Figure 5C , Figure 5A and Figure 5B These are circuit diagrams of different embodiments of the power factor correction converter 200 according to the present invention, including different current sensing circuits 220 (current sensing circuit 220A and current sensing circuit 220B). Figure 5A and Figure 5B In the circuit, current sensing circuits 220A and 220B each include a current sensing resistor Rcs. One end of the current sensing resistor Rcs is coupled to transistor Q1, and the other end of the current sensing resistor Rcs is coupled to the input side ground GNDin. Figure 5C This invention is as follows Figure 5A and Figure 5B In the different embodiments shown, the current sensing signal (VCS, VCS') and the current I of the inductor L are... L The waveform diagram. For example... Figure 5A and Figure 5C As shown in waveform W5, in Figure 5AIn the illustrated embodiment, the reference ground potential of the power factor correction converter 200 is the input-side ground GNDin. Since one end of the current sensing resistor Rcs is sensed and the reference ground potential of the current sensing resistor Rcs is the input-side ground GNDin, the current sensing signal VCS is related to the current I of the inductor L. L They are in phase. On the other hand, such as Figure 5B and Figure 5C As shown in waveform W6, in Figure 5B In the illustrated embodiment, the reference ground potential of the power factor correction converter 200 is the output-side ground GNDout. Since the other end of the current sensing resistor Rcs is sensed and the reference ground potential of the current sensing resistor Rcs is the output-side ground GNDout, the current sensing signal VCS' is relative to the current I of the inductor L. L It is the opposite phase.

[0147] In some embodiments, the zero-current prediction circuit 230 is used to predict the current I of the inductor L. L And by using a time-period resetting method, the zero-current point is accurately predicted, thereby controlling at least one switch of the power stage circuit 210. Figure 4A Taking the power factor correction converter 200 shown as an example, the power stage circuit 210 includes a boost power stage circuit. When switch Q1 switches from the on state to the off state, the current I of inductor L... L Linear descent, zero current prediction circuit 230 based on current I L The level during the descent passes through two time points, while the estimated current I... L The rate of descent is used to determine the current I. L The point at which the current drops to zero.

[0148] Please refer to Figure 6 This is a block diagram of a zero-current prediction circuit 230A in one embodiment of the present invention. Figure 6As shown, the zero-current prediction circuit 230A includes a first comparator 231 A, a second comparator 231B, and a timing circuit 235. In the present embodiment, the first comparator 231 A compares the level of the current sense signal VCS with a first threshold Vthl to generate a first comparison signal CMP_Vthl. The second comparator 231B compares the level of the current sense signal VCS with a second threshold Vth2 to generate a second comparison signal CMP_Vth2. The zero-current prediction circuit 230A generates a first time period based on the first comparison signal CMP_Vthl and the second comparison signal CMP_Vth2. The timing circuit 235 generates a timing signal based on the first comparison signal CMP_Vthl and the second comparison signal CMP_Vth2, and generates a zero-current point signal ZC based on the timing signal and a second time period, wherein the second time period has a time period ratio with the first time period.

[0149] In some embodiments, the timing circuit 235 includes at least one integrating capacitor and at least one current source, wherein the zero-current prediction circuit 230 controls at least one switch of the power stage circuit 210 according to the following steps (see Figure 5C ): when the level of the current sense signal VCS passes the second threshold Vth2 at a first time point tl, the at least one current source starts to perform a first integration of the at least one integrating capacitor from an initial voltage; when the level of the current sense signal VCS passes the first threshold Vthl at a second time point t2, the at least one current source stops the first integration of the at least one integrating capacitor and starts a second integration of the at least one integrating capacitor, wherein the at least one integrating capacitor generates a first integrated voltage Vsrc at the second time point t2, and the time difference between the first time point tl and the second time point t2 is a first time period Tsrc; and during the second integration, a third time point t3 is determined based on the voltage of the at least one integrating capacitor and the first integrated voltage Vsrc, wherein the time difference between the second time point t2 and the third time point t3 is a second time period Tdst, and the third time point corresponds to the zero-current point. In the above description, a third time point t3 is generated based on the first integrated voltage Vsrc, for example, when the level of the current sense signal VCS passes the third time point t3, the at least one current source stops the second integration of the at least one integrating capacitor.

[0150] Please refer to Figure 7 and Figure 8 , Figure 7 is a circuit schematic diagram of the zero-current prediction circuit 230A in an embodiment of the present application, Figure 8This is a waveform diagram of multiple signals in the zero-current prediction circuit 230A according to one embodiment of the present invention. In this embodiment, the current sensing signal VCS is relative to the current I of the inductor L. L The zero-current prediction circuit 230A is in phase. In some embodiments, the zero-current prediction circuit 230A includes a first comparator 231A, a second comparator 231B, and a timing circuit 235A. The first comparator 231A and the second comparator 231B are comparators well-known to those skilled in the art, and therefore will not be described in detail. In some embodiments, the first comparator 231A compares the level of the current sensing signal VCS with a first threshold Vth1 to generate a first comparison signal CMP_Vth1. The second comparator 231B compares the level of the current sensing signal VCS with a second threshold Vth2 to generate a second comparison signal CMP_Vth2. The zero-current prediction circuit 230A generates a first time period Tsrc based on the first comparison signal CMP_Vth1 and the second comparison signal CMP_Vth2. The structure of the zero-current prediction circuit 230 will be described below using three embodiments, and all steps of the zero-current prediction circuit 230 controlling at least one switch of the power stage circuit 210 will be explained in detail.

[0151] like Figure 7 As shown, in this embodiment, the zero-current prediction circuit 230A includes a first comparator 231A, a second comparator 231B, and a timing circuit 235A. The timing circuit 235A includes a first integrating capacitor Cramp1, a second integrating capacitor Cramp2, a first current source Iramp1, a second current source Iramp2, a third comparator 231C, falling edge sensors 232A, 232B, and 232C, and latching circuits 233A and 233B. The third comparator 231C compares the first integrating voltage Vsrc with the voltage Vc2 of the second integrating capacitor Cramp2 to generate a third comparison signal CMPC.

[0152] like Figure 7In some embodiments, as shown, when the level of the current sense signal VCS falls through the second threshold Vth2 at the first time point t1, the first integrating capacitor Cramp1 is first reset to an initial potential, such as zero potential, by the falling edge pulse CMP_Vth2_nedge of the second comparison signal, and then the first current source Iramp1 starts to perform the first integration on the first integrating capacitor Cramp1 to generate the voltage Vc1 of the first integrating capacitor Cramp1, and the level of the voltage Vc1 of the first integrating capacitor Cramp1 gradually rises. Then, when the level of the current sense signal VCS falls through the first threshold Vth1 at the second time point t2, the first current source Iramp1 stops the first integration on the first integrating capacitor Cramp1, and the voltage Vc1 of the first integrating capacitor Cramp1 is the first integrated voltage Vsrc at this time. Meanwhile, the second integrating capacitor Cramp2 is reset to the initial potential by the falling edge pulse CMP_Vth1_nedge of the first comparison signal, and the second current source Iramp2 starts to perform the second integration on the second integrating capacitor Cramp2, so that the level of the voltage Vc2 of the second integrating capacitor Cramp2 gradually rises. Subsequently, when the level of the voltage Vc2 of the second integrating capacitor Cramp2 reaches the level of the first integrated voltage Vsrc, i.e., the second integrated voltage Vdst, for example, the second current source Iramp2 can stop the second integration on the second integrating capacitor Cramp2, and the third comparison signal CMPC indicates that this is the third time point t3, wherein the third time point t3 indicates the zero current time point of the inductor L. Finally, the timing circuit 235A outputs the zero current time point signal ZC through the falling edge sensor 232C at the third time point t3, thereby controlling at least one switch (such as the switch S1) of the power stage circuit 210 to be turned off. Figure 4AThe transistor Q1 in the circuit switches its state, for example, turning on again, to achieve a boundary conduction mode. In this embodiment, the ratio of the first time period Tsrc to the second time period Tdst is related to the ratio of the current sources Iramp1 and Iramp2, and the ratio of the capacitance values ​​of the first integrating capacitor Cramp1 and the second integrating capacitor Cramp2. In a preferred embodiment, the ratio of the first time period Tsrc to the second time period Tdst is 1:1 (the length of the first time period Tsrc is equal to the length of the second time period Tdst), and the absolute value of the difference between the first threshold Vth1 and the second threshold Vth2 is equal to the absolute value of the difference between the first threshold Vth1 and zero potential, thus achieving volt-second balance. In steady state, the inductor L starts conducting at zero current, and the zero current point can be predicted by directly copying the first time period Tsrc to the second time period Tdst. In another embodiment, the absolute value of the difference between the first threshold Vth1 and the second threshold Vth2 is less than the peak-to-peak value of the current sensing signal VCS. In another embodiment, the absolute value of the difference between the first threshold Vth1 and the second threshold Vth2 is less than 1 / 2 of the peak-to-peak value of the current sensing signal VCS.

[0153] In some embodiments, since the current sensing signal VCS changes over time, the level of the current sensing signal VCS will cross the first threshold Vth1 and the second threshold Vth2 at two points in one cycle, one when the current sensing signal VCS rises and the other when the current sensing signal VCS falls. This invention aims to sense the zero current point of inductor L; therefore, the first time point t1 and the second time point t2 sensed by this invention are both the current I of inductor L. L When the current sensing signal VCS level decreases, the time points when the level passes through the second threshold Vth2 and the first threshold Vth1 respectively (e.g., when...) Figure 8 (As shown in the first time point t1 and the second time point t2). In some embodiments, the timing circuit 235A uses falling edge sensors 232A and 232B to sense the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 and the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1, respectively, and then senses the first time point t1 and the second time point t2 to generate a first time period Tsrc, wherein the falling edge pulse CMP_Vth2_nedge of the second comparison signal corresponds to the first time point t1, and the falling edge pulse CMP_Vth1_nedge of the first comparison signal corresponds to the second time point t2.

[0154] Please refer to the following at the same time Figure 9A and 9B , Figure 9Ais a circuit schematic diagram of the falling edge sensor 232 in an embodiment of the present application, wherein the falling edge sensor 232 comprises the falling edge sensors 232A, 232B, 232C as previously described. Figure 9B is a waveform diagram of the input voltage of the falling edge sensor 232 and the output voltage of the falling edge sensor 232 in an embodiment of the present application. As shown in Figure 9A and Figure 9B In some embodiments, the falling edge sensor 232 comprises an inverter INV, a delay circuit DLY comprising a plurality of buffers BUF, and an AND gate, wherein the falling edge sensor 232 can sense the falling edge of the input signal Din to generate an output signal Dout in the form of a pulse, wherein the output signal Dout corresponds to the falling edge of the input signal Din, and the pulse width of the output signal Dout is related to the delay time of the delay circuit DLY.

[0155] In some embodiments, the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 and the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 are also used to control the second integration capacitor Cramp2 and the first integration capacitor Cramp1 to be reset to the initial potential, respectively. As shown in Figure 8 at the first time point t1, the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 controls the switch S1 to be in the on state, so that the first integration capacitor Cramp1 is grounded and reset to the initial potential of the low potential; at the second time point t2, the falling edge pulse CMP_Vth1_nedge of the first comparison signal controls the switch S2 to be in the on state, so that the second integration capacitor Cramp2 is grounded and reset to the initial potential of the low potential.

[0156] In some embodiments, the timing circuit 235A controls the first current source Iramp1 and the second current source Iramp2 through the first latch signal Dsrc and the second latch signal Ddst generated by the latch circuit 233A, 233B, respectively, wherein when the first latch signal Dsrc is in the high potential state, the first current source Iramp1 performs the first integration on the first integration capacitor Cramp1; when the second latch signal Ddst is in the high potential state, the second current source Iramp2 performs the second integration on the second integration capacitor Cramp2. The latch circuit 233A, 233B is a latch circuit known to those skilled in the art, and thus will not be described in detail.

[0157] Please refer to Figure 10 and Figure 11 , Figure 10 is a circuit schematic diagram of the timing circuit 235B in another embodiment of the present application.Figure 11 is another embodiment of the present application, the waveform diagram of the plurality of signals in the zero-current prediction circuit 230B, wherein the current sensing signal VCS is relative to the current I of the inductor L L is in phase. As Figure 10 shown in the present embodiment, the timing circuit 235B comprises a sample-and-hold circuit SH, a first integrating capacitor Cramp1, a first current source Iramp1, a third comparator 231C, falling edge sensors 232A, 232B, 232C, and latch circuits 233A, 233B, wherein the sample-and-hold circuit SH is used to sample-and-hold the first integrating voltage Vsrc to generate a sample-and-hold voltage Vsrc_sh, and the third comparator 231C is used to compare the sample-and-hold voltage Vsrc_sh with the voltage Vc1 of the first integrating capacitor Cramp1 to generate a third comparison signal CMPC. In some embodiments, the zero-current prediction circuit 230B further comprises a first comparator 231A and a second comparator 231B, wherein the functions of the first comparator 231A and the second comparator 231B are as previously described, and thus are not elaborated here.

[0158] As Figure 11 shown in some embodiments, when the level of the current sensing signal VCS passes the first time point t1 of the second threshold Vth2, the first integrating capacitor Cramp1 is first reset to an initial potential, for example, a zero potential, at which time the first current source Iramp1 starts to perform the first integration on the first integrating capacitor Cramp1 to generate the voltage Vc1, and the level of the voltage Vc1 gradually rises. Then, when the level of the current sensing signal VCS passes the second time point t2 of the first threshold Vth1, the voltage Vc1 of the first integrating capacitor Cramp1 reaches the first integrating voltage Vsrc, the sample-and-hold circuit SH samples-and-holds the first integrating voltage Vsrc to generate a sample-and-hold voltage Vsrc_sh, and the first current source Iramp1 stops the first integration on the first integrating capacitor Cramp1. At the same time point (the second time point t2), the first integrating capacitor Cramp1 is again reset to the initial potential, at which time the first current source Iramp1 starts to perform the second integration on the first integrating capacitor Cramp1 to generate the voltage Vc2. Subsequently, when the level of the voltage Vc2 reaches the level of the sample-and-hold voltage Vsrc_sh, at which time the third comparison signal CMPC indicates that this is the third time point t3, wherein the third time point t3 is the zero-current time point of the inductor L, at which time the first current source Iramp1 can stop the second integration on the first integrating capacitor Cramp1. Finally, the timing circuit 235B outputs the zero-current time point signal ZC through the falling edge sensor 232C at the third time point t3 to control at least one switch (for example, the switch S1) of the power stage circuit 210. Figure 4Athe switching state of the transistor Q1) is switched, for example, again to the on state, to achieve the boundary conduction mode.

[0159] In some embodiments, the timing circuit 235B senses the first time point t1 and the second time point t2 by sensing the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 and the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 through the falling edge sensors 232A, 232B, respectively, to generate the first time period Tsrc.

[0160] In some embodiments, the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 and the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 are also used to control the first integrating capacitor Cramp1 to be reset to the initial potential. As shown in FIG. 6, since the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 and the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 control the switch S1 through the OR gate OR, when either the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 or the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 is converted to the high potential state, the switch S1 can be controlled to be in the on state. Figure 10 Figure 11 As shown in FIG. 6, at the first time point t1, the falling edge pulse CMP_Vth2_nedge of the second comparison signal controls the switch S1 to be in the on state, so that the first integrating capacitor Cramp1 is grounded and reset to the initial low potential. At the second time point t2, the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 controls the switch S1 to be in the on state, so that the first integrating capacitor Cramp1 is again grounded and reset to the initial low potential.

[0161] ​In some embodiments, the timing circuit 235B controls the first current source Iramp1 by the first latch signal Dsrc and the second latch signal Ddst generated by the latch circuit 233A, 233B, wherein the first current source Iramp1 performs a first integration on the first integration capacitor Cramp1 when the first latch signal Dsrc is in a high state, and the first current source Iramp1 performs a second integration on the first integration capacitor Cramp1 when the second latch signal Ddst is in a high state.

[0162] Please refer to Figure 12 , Figure 12 is an embodiment of the present application, a circuit schematic diagram of the timing circuit 235C. As shown in Figure 12 the present embodiment, the timing circuit 235C includes a first integration capacitor Cramp1, a first current source Iramp1, a second current source Iramp2, a third comparator 231C, falling edge sensors 232A, 232B, 232C, and a latch circuit 233A, 233B, wherein the third comparator 231C is used to compare the voltage Vc1 / Vc2 of the first integration capacitor Cramp1 with a preset potential Vpre to generate a third comparison signal CMPC, wherein the voltage of the first integration capacitor Cramp1 is voltage Vc1 or voltage Vc2. In some embodiments, the zero current prediction circuit 230C further includes a first comparator 231A and a second comparator 231B, wherein the functions of the first comparator 231A and the second comparator 231B are as shown above, and thus are not described in detail.

[0163] In some embodiments, when the level of the current sensing signal VCS passes the first time point t1 of the second threshold Vth2, the first integration capacitor Cramp1 is first reset to an initial potential, at which time the first current source Iramp1 starts to perform a first integration on the first integration capacitor Cramp1 to generate the voltage Vc1, and the level of the voltage Vc1 gradually rises, wherein the initial potential is, for example, a zero potential (e.g. 0V) or a negative potential (e.g. -1V). Figure 12The first current source Iramp1 stops the first integration of the first integrating capacitor Cramp1 when the level of the current sensing signal VCS passes the second time point t2 of the first threshold Vth1, at which time the voltage Vc1 of the first integrating capacitor Cramp1 reaches the first integration voltage Vsrc, and the second current source Iramp2 starts the second integration of the first integrating capacitor Cramp1, causing the level of the voltage Vc2 of the first integrating capacitor Cramp1 to gradually decrease. The second current source Iramp2 stops the second integration of the first integrating capacitor Cramp1 when the level of the second integration voltage Vdst reaches the level of the preset voltage Vpre, at which time the third comparison signal CMPC indicates the third time point t3, which is the zero current time point of the inductor L. The preset voltage Vpre can be zero or a non-zero voltage. In one embodiment, the preset voltage Vpre is the same as the initial voltage. Finally, the timing circuit 235C outputs the zero current time point signal ZC through the falling edge sensor 232C at the third time point t3, thereby controlling the switching state of at least one switch (e.g., transistor Q1 in the power stage circuit 210) to be turned on again to achieve the boundary conduction mode. In this embodiment, the time ratio between the first time period Tsrc and the second time period Tdst is related to the current source ratio between the first current source Iramp1 and the second current source Iramp2. In a preferred embodiment, the current source ratio is 1:1. Figure 4A

[0164] In some embodiments, the timing circuit 235C generates the first time period Tsrc by sensing the first time point t1 and the second time point t2 through the falling edge sensors 232A, 232B to sense the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 corresponding to the first time point t1 and the falling edge pulse CMP_Vth1_nedge of the first comparison signal CMP_Vth1 corresponding to the second time point t2, respectively.

[0165] In some embodiments, the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 is also used to control the first integrating capacitor Cramp1 to be reset to the initial voltage. When the level of the current sensing signal VCS passes the first time point t1 of the second threshold Vth2, the falling edge pulse CMP_Vth2_nedge of the second comparison signal CMP_Vth2 controls the switch S1 to be in the on state, so that the first integrating capacitor Cramp1 is grounded and reset to the initial voltage of the low voltage.​

[0166] In some embodiments, the timing circuit 235C controls the first current source Irampi by the first latch signal Dsrc and the second latch signal Ddst generated by the latch circuit 233A, 233B, wherein the first current source Irampi performs the first integration on the first integration capacitor Crampi when the first latch signal Dsrc is in the high state, and the second current source Iramp2 performs the second integration on the first integration capacitor Crampi when the second latch signal Ddst is in the high state.

[0167] Please refer back Figure 4A and Figure 4B In some embodiments, the feedback circuit 240 generates a feedback voltage Vfb according to the output voltage Vo of the output power supply, wherein the output voltage Vo and the feedback voltage Vfb have a proportional relationship. In some embodiments, the feedback circuit 240 includes a voltage divider circuit formed by a plurality of resistors, wherein the values of the resistors affect the value of the proportional relationship. As shown in FIG. 4, in the present embodiment, the feedback circuit 240 includes two resistors Rfb1, Rfb2, wherein the values of the resistors Rfb1 and Rfb2 determine the proportional relationship between the output voltage Vo and the feedback voltage Vfb. For example, when the value of the resistor Rfb1 is 4 kilo-ohms (kΩ) and the value of the resistor Rfb2 is 1 kilo-ohm, the proportional relationship between the output voltage Vo and the feedback voltage Vfb is 5 to 1, that is, the level of the output voltage Vo is 5 times the level of the feedback voltage Vfb. Figure 4A

[0168] In some embodiments, the rectifier 250 rectifies an alternating input power supply into a rectified power supply, wherein the rectified voltage Vi of the rectified power supply is a half-wave signal or a full-wave signal. When the rectified voltage Vi is the half-wave signal, it means that the rectifier 250 eliminates the negative voltage in the alternating input voltage Vac of the alternating input power supply, thereby rectifying it into the rectified voltage Vi with half-wave rectification; when the rectified voltage Vi is the full-wave signal, it means that the rectifier 250 converts the negative voltage in the alternating input voltage Vac into a positive voltage, thereby rectifying it into the rectified voltage Vi with full-wave rectification. The structure and function of the rectifier 250 are well known to those skilled in the art, and thus are not described in detail.

[0169] As shown in FIG. 4, in the present embodiment, the feedback circuit 240 includes two resistors Rfb1, Rfb2, wherein the values of the resistors Rfb1 and Rfb2 determine the proportional relationship between the output voltage Vo and the feedback voltage Vfb. For example, when the value of the resistor Rfb1 is 4 kilo-ohms (kΩ) and the value of the resistor Rfb2 is 1 kilo-ohm, the proportional relationship between the output voltage Vo and the feedback voltage Vfb is 5 to 1, that is, the level of the output voltage Vo is 5 times the level of the feedback voltage Vfb. Figure 4B ​As shown, in some embodiments, the error amplifier 260 is used to generate an error amplification signal VEOA based on the difference between the feedback voltage Vfb and a reference voltage Vref. In some embodiments, the error amplifier 260 has a non-inverting input, an inverting input, and an output, wherein the non-inverting input is used to receive the reference voltage Vref, the inverting input is used to receive the feedback voltage Vfb, and the output is used to output the error amplification signal VEOA. The structure and function of the error amplifier 260 are well known to those skilled in the art and will not be described in detail here.

[0170] In some embodiments, the pulse width modulation circuit 270 is used to perform pulse-width modulation on the zero-current point-time signal ZC according to the error amplification signal VEOA, thereby generating a control signal G1. In some embodiments, the pulse width modulation circuit 270 performs pulse width modulation according to the error amplification signal VEOA in, for example, but not limited to, a fixed conduction mode. Pulse width modulation technology is well known to those skilled in the art and will not be described in detail here.

[0171] Please refer to Figure 13 , Figure 13 This is a flowchart of a control method for a power factor correction converter 200 according to one embodiment of the present invention. When the power factor correction converter 200 starts operating in a boundary conduction mode, the power stage circuit 210 of the power factor correction converter 200 receives a rectified power supply and generates a current I in an inductor L. L The rectified power supply is generated by converting an AC input power supply Vac through a rectifier 250. For example... Figure 13 As shown, firstly, a switch Q1 is controlled to switch the coupling relationship between an inductor L and a rectified power supply and an output power supply, thereby converting the rectified power supply into the output power supply. The inductor L is used to operate in a boundary conduction mode to correct the power factor of the rectified power supply (step S100). Next, the current sensing circuit 220 of the power factor correction converter 200 senses the current I of the inductor L. L This generates a current sensing signal VCS, in which the current sensing circuit 220 senses the current I of the inductor L. LThe zero-current prediction circuit 230 of the power factor correction controller 420 generates the second time period Tdst according to the level of the current sense signal VCS through a first time period Tsrc between a first threshold value Vthl and a second threshold value Vth2 (step S300), wherein the zero-current prediction circuit 230 generates the second time period Tdst in the manner as previously described, and thus, the description is omitted. Finally, the zero-current prediction circuit 230 switches the state of the at least one switch in the power stage circuit 210 at the end point of the second time period Tdst (i.e., the zero-current point at which the current value of the inductor L is converted to zero) to convert the rectified power source Vi to generate an output power source Vo (step S300), wherein the zero-current prediction circuit 230 controls the at least one switch in the manner as previously described, and thus, the description is omitted.

[0172] Please refer to Figure 14 , Figure 14 is a block diagram of modules of the power factor correction controller 420 in an embodiment of the present application, wherein the power factor correction controller 420 is adapted to a power factor correction converter 400. As shown in Figure 14 , in some embodiments, the power factor correction converter 400 comprises a power stage circuit 410, a power factor correction controller 420, a current sense circuit 430, and a feedback circuit 440, wherein the power factor correction controller 420 comprises a zero-current prediction circuit 421. In some embodiments, the power factor correction controller 420 further comprises an error amplifier 422 and a pulse width modulation circuit 423. In some embodiments, the power factor correction converter 400 corresponds to the power factor correction converter 200 in Figure 4A , the power stage circuit 410, the current sense circuit 430, and the feedback circuit 440 correspond to the power stage circuit 210, the current sense circuit 220, and the feedback circuit 240 in Figure 4A , respectively, the zero-current prediction circuit 421 of the power factor correction controller 420 corresponds to the zero-current prediction circuit 230 in Figure 4A , and the error amplifier 422 and the pulse width modulation circuit 423 correspond to the error amplifier 260 and the pulse width modulation circuit 270 in Figure 4B .

[0173] In summary, compared with the prior art, the power factor correction converter 200 of the present application is provided with the zero-current prediction circuit 230, so that the power factor correction converter 200 of the present application can more accurately predict the zero-current point of the inductor L, and thus, the power factor correction converter 200 of the present application can stably operate in the boundary conduction mode.

[0174] It is to be noted that the "zero current point at which the end point of the second period corresponds to the time point at which the current value of the inductor reaches 0" does not mean that it must be absolutely error-free and exactly at the time point at which the current value of the inductor reaches 0, but can have a slight deviation. Other examples such as "wherein the time length of the first period is equal to the time length of the second period" also do not mean that it must be absolutely error-free and exactly equal to the time length of the second period, but can have a slight deviation. Other units such as time points, time lengths, sizes, etc. should also be considered to have a slight error range, which will not be described here.

[0175] The above has described the present application with respect to preferred embodiments, but the above description is only to make those skilled in the art easily understand the content of the present application, and is not intended to limit the scope of the present application. The described embodiments are not limited to separate applications, but can be combined, for example, two or more embodiments can be combined, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, those skilled in the art can think of various equivalent changes and various combinations under the same spirit of the present application, for example, the present application refers to "processing or operating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, if necessary, voltage-current conversion, current-voltage conversion, and / or proportional conversion, etc., and then processing or operating according to the converted signal to generate an output result. Therefore, those skilled in the art can think of various equivalent changes and various combinations under the same spirit of the present application, and the combination methods are various, which will not be enumerated here. Therefore, the scope of the present application should cover all the above and other equivalent changes.

Claims

1. A power factor correction converter, comprising: A power stage circuit includes at least one switch for switching the coupling relationship between an inductor and a rectified power supply and an output power supply to convert the rectified power supply into the output power supply, wherein the power stage circuit is configured to operate in a boundary conduction mode to correct the power factor of the rectified power supply. A current sensing circuit is used to sense the current of the inductor and generate a current sensing signal; as well as A zero-current prediction circuit is used to control the at least one switch; The zero-current prediction circuit controls the at least one switch according to the following steps: A second time period is generated based on the level of the current sensing signal through a first time period between a first threshold and a second threshold; and The state of at least one switch is switched at the end of the second time period, wherein the end of the second time period corresponds to a zero current point when the current value of the inductor reaches 0.

2. The power factor correction converter as described in claim 1, wherein, Also includes: A feedback circuit is used to generate a feedback voltage based on the output power supply; An error amplifier is used to generate an error amplification signal based on the difference between a reference voltage and the feedback voltage. as well as A pulse width modulation circuit is used to generate a control signal based on the error amplification signal and a signal related to the zero current point, wherein the control signal is used to control the switching of the at least one switch.

3. The power factor correction converter as described in claim 1, wherein, The length of the first time period is equal to the length of the second time period.

4. The power factor correction converter as described in claim 1, wherein, The absolute value of the difference between the first threshold and the second threshold is less than the peak-to-peak value of the current sensing signal.

5. The power factor correction converter as described in claim 1, wherein, The absolute value of the difference between the first threshold and the second threshold is less than 1 / 2 of the peak-to-peak value of the current sensing signal.

6. The power factor correction converter as claimed in claim 1, wherein, The zero-current prediction circuit includes a first comparator and a second comparator. The first comparator generates a first comparison signal based on the level of the current sensing signal and the first threshold. The second comparator generates a second comparison signal based on the level of the current sensing signal and the second threshold. The zero-current prediction circuit generates the first time period based on the first comparison signal and the second comparison signal.

7. The power factor correction converter as described in claim 6, wherein, The zero-current prediction circuit further includes a timing circuit for timing the level of the current sensing signal through the first time period between the first threshold and the second threshold based on the first comparison signal and the second comparison signal, thereby generating a timing signal, and timing the second time period based on the timing signal, wherein the second time period has a time period ratio with respect to the first time period.

8. The power factor correction converter as claimed in claim 7, wherein, The timing circuit includes at least one integrating capacitor and at least one current source; The zero-current prediction circuit controls the at least one switch according to the following steps: When the level of the current sensing signal passes the second threshold at a first time point, the at least one current source begins to perform a first integration of the at least one integrating capacitor from an initial potential. When the level of the current sensing signal passes the first threshold at a second time point, the at least one current source stops performing the first integration on the at least one integrating capacitor, wherein the at least one integrating capacitor generates a first integrated voltage at the second time point. Starting from the second time point, the current source begins a second integration of the at least one integrating capacitor, wherein the time difference between the first time point and the second time point is the first time period; and During the second integration period, a third time point is determined based on the voltage of the at least one integrating capacitor and the first integrating voltage, wherein the time difference between the second time point and the third time point is the second time period, and the third time point corresponds to the zero current time point.

9. The power factor correction converter as claimed in claim 8, wherein, The absolute value of the difference between the first threshold and the second threshold is equal to the absolute value of the difference between the first threshold and the level of the current sensing signal at the third time point.

10. The power factor correction converter as claimed in claim 8, wherein, The at least one integrating capacitor includes a first integrating capacitor and a second integrating capacitor, the at least one current source includes a first current source and a second current source, and the timing circuit further includes a third comparator, which is used to compare the first integrating voltage with the voltage of the second integrating capacitor to generate a third comparison signal. The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the first integrating capacitor is reset to the initial potential, and the first current source begins to perform the first integration on the first integrating capacitor from the initial potential; At the second time point, the first current source stops performing the first integration on the first integrating capacitor, the first integrating capacitor generates the first integrating voltage, and the voltage of the second integrating capacitor is reset to the initial potential. The second current source then begins performing the second integration on the second integrating capacitor from the initial potential. During the second integration period, the third time point is determined based on the third comparison signal when the voltage of the second integrating capacitor reaches the first integrating voltage. The time period ratio between the first time period and the second time period is related to a current source ratio between the first current source and the second current source and a capacitance value ratio between the capacitance value of the first integrating capacitor and the capacitance value of the second integrating capacitor.

11. The power factor correction converter as claimed in claim 8, wherein, The timing circuit also includes: A sample-and-hold circuit is used to sample and hold the first integral voltage to generate a sample-and-hold voltage; and A third comparator is used to compare the sampling sustaining voltage with the voltage of the at least one integrating capacitor to generate a third comparison signal; The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the at least one integrating capacitor is reset to the initial potential, and the at least one current source begins to perform the first integration on the at least one integrating capacitor from the initial potential; At the second time point, the at least one current source stops performing the first integration on the at least one integrating capacitor, the at least one integrating capacitor generates the first integrating voltage, and the sample-and-hold circuit samples and holds the first integrating voltage to generate the sample-and-hold voltage. Then, the voltage of the at least one integrating capacitor is reset to the initial potential, and the at least one current source begins performing the second integration on the at least one integrating capacitor from the initial potential. During the second integration period, the point at which the voltage of the at least one integrating capacitor reaches the sampling sustaining voltage, indicated by the third comparison signal, is determined as the third time point.

12. The power factor correction converter as claimed in claim 8, wherein, The at least one current source includes a first current source and a second current source. The timing circuit also includes a third comparator, which is used to compare the voltage of the at least one integrating capacitor with a preset potential to generate a third comparison signal. The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the at least one integrating capacitor is reset to the initial potential, and the first current source begins to perform the first integration on the at least one integrating capacitor from the initial potential; At the second time point, the first current source stops performing the first integration on the at least one integrating capacitor, which generates the first integrated voltage. Then, the second current source begins performing the second integration on the at least one integrating capacitor from the first integrated voltage; and During the second integration period, the point at which the voltage of the at least one integrating capacitor reaches the preset potential, indicated by the third comparison signal, is determined as the third time point; The ratio of the first time period to the second time period is related to the ratio of the first current source to the second current source.

13. A power factor correction controller, suitable for a power factor correction converter, comprising: A zero-current prediction circuit is used to control at least one switch of a power stage circuit to switch the coupling relationship between an inductor and a rectified power supply and an output power supply, thereby converting the rectified power supply into the output power supply, wherein the power stage circuit is used to operate in a boundary conduction mode to correct the power factor of the rectified power supply. in, The zero-current prediction circuit controls the at least one switch according to the following steps: A second time period is generated based on the level of a current sensing signal generated by a current sensing circuit, passing through a first time period between a first threshold and a second threshold, wherein the length of the second time period is related to the length of the first time period; and The state of the at least one switch is switched at the end of the second time period, wherein the end of the second time period corresponds to a zero current point when the current value of the inductor reaches 0; An error amplifier is used to generate an error amplification signal based on the difference between a reference voltage and a feedback voltage. as well as A pulse width modulation circuit is used to generate a control signal based on the error amplification signal and the signal at the zero current point, wherein the control signal is used to control the switching of the at least one switch.

14. The power factor correction controller as described in claim 13, wherein, The length of the first time period is equal to the length of the second time period.

15. The power factor correction controller as claimed in claim 13, wherein, The absolute value of the difference between the first threshold and the second threshold is less than the peak-to-peak value of the current sensing signal.

16. The power factor correction controller as claimed in claim 13, wherein, The absolute value of the difference between the first threshold and the second threshold is less than 1 / 2 of the peak-to-peak value of the current sensing signal.

17. The power factor correction controller of claim 13, wherein the zero current prediction circuit includes a first comparator and a second comparator, the first comparator being configured to generate a first comparison signal based on the level of the current sensing signal and the first threshold, the second comparator being configured to generate a second comparison signal based on the level of the current sensing signal and the second threshold, and the zero current prediction circuit generating the first time period based on the first comparison signal and the second comparison signal.

18. The power factor correction controller as claimed in claim 17, wherein, The zero-current prediction circuit further includes a timing circuit for timing the level of the current sensing signal through the first time period between the first threshold and the second threshold based on the first comparison signal and the second comparison signal, thereby generating a timing signal, and timing the second time period based on the timing signal, wherein the second time period has a time period ratio with respect to the first time period.

19. The power factor correction controller as claimed in claim 18, wherein, The timing circuit includes at least one integrating capacitor and at least one current source; The zero-current prediction circuit controls the at least one switch according to the following steps: When the level of the current sensing signal passes the second threshold at a first time point, the at least one current source begins to perform a first integration of the at least one integrating capacitor from an initial potential. When the level of the current sensing signal passes the first threshold at a second time point, the at least one current source stops performing the first integration on the at least one integrating capacitor, wherein the at least one integrating capacitor generates a first integrated voltage at the second time point. Starting from the second time point, the current source begins a second integration of the at least one integrating capacitor, wherein the time difference between the first time point and the second time point is the first time period; and During the second integration period, a third time point is determined based on the voltage of the at least one integrating capacitor and the first integrating voltage, wherein the time difference between the second time point and the third time point is the second time period, and the third time point corresponds to the zero current time point.

20. The power factor correction controller as claimed in claim 19, wherein, The absolute value of the difference between the first threshold and the second threshold is equal to the absolute value of the difference between the first threshold and the level of the current sensing signal at the third time point.

21. The power factor correction controller as claimed in claim 19, wherein, The at least one integrating capacitor includes a first integrating capacitor and a second integrating capacitor, the at least one current source includes a first current source and a second current source, and the timing circuit further includes a third comparator, which is used to compare the first integrating voltage with the voltage of the second integrating capacitor to generate a third comparison signal. The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the first integrating capacitor is reset to an initial potential, and the first current source begins the first integration of the at least one integrating capacitor. At the second time point, the first current source stops performing the first integration on the first integrating capacitor, the first integrating capacitor generates the first integrating voltage, the voltage of the second integrating capacitor is reset to the initial potential, and the second current source begins performing the second integration on the second integrating capacitor from the initial potential; and During the second integration period, the third time point is determined based on the third comparison signal when the voltage of the second integrating capacitor reaches the first integrating voltage. The time period ratio between the first time period and the second time period is related to a current source ratio between the first current source and the second current source and a capacitance value ratio between the capacitance value of the first integrating capacitor and the capacitance value of the second integrating capacitor.

22. The power factor correction controller as claimed in claim 19, wherein, The timing circuit also includes: A sample-and-hold circuit is used to sample and hold the first integral voltage to generate a sample-and-hold voltage; and A third comparator is used to compare the sampling holding voltage with a voltage of the at least one integrating capacitor to generate a third comparison signal; The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the at least one integrating capacitor is reset to the initial potential, and the at least one current source begins to perform the first integration on the at least one integrating capacitor from the initial potential; At the second time point, the at least one current source stops performing the first integration on the at least one integrating capacitor, the at least one integrating capacitor generates the first integrating voltage, and the sample-and-hold circuit samples and holds the first integrating voltage to generate the sample-and-hold voltage. Then, the voltage of the at least one integrating capacitor is reset to the initial potential, and the at least one current source begins performing the second integration on the at least one integrating capacitor from the initial potential. During the second integration period, the point at which the voltage of the at least one integrating capacitor reaches the sampling sustaining voltage, indicated by the third comparison signal, is determined as the third time point.

23. The power factor correction controller as described in claim 19, wherein, The at least one current source includes a first current source and a second current source. The timing circuit also includes a third comparator, which is used to compare the voltage of the at least one integrating capacitor with a preset potential to generate a third comparison signal. The zero-current prediction circuit controls the at least one switch according to the following steps: At the first point in time, the voltage of the at least one integrating capacitor is reset to an initial potential, and the first current source begins to perform the first integration on the at least one integrating capacitor from the initial potential. At the second time point, the first current source stops performing the first integration on the at least one integrating capacitor, which generates the first integrated voltage. Then, the second current source begins performing the second integration on the at least one integrating capacitor from the first integrated voltage; and During the second integration period, the point at which the voltage of the at least one integrating capacitor reaches the preset potential, indicated by the third comparison signal, is determined as the third time point; The ratio of the first time period to the second time period is related to the ratio of the first current source to the second current source.

24. A control method for a power factor correction converter, comprising: A switch is controlled to switch the coupling relationship between an inductor and a rectified power supply and an output power supply, thereby converting the rectified power supply into the output power supply, wherein the inductor is used to operate in a boundary conduction mode to correct the power factor of the rectified power supply. A current sensing signal is generated by sensing the current of the inductor. A second time period is generated based on the level of the current sensing signal through a first time period between a first threshold and a second threshold, wherein the length of the second time period is related to the length of the first time period; and At the end of the second time period, switch the state of at least one switch. in, The end of this second time period corresponds to the zero current point when the current value of the inductor reaches 0.

25. The control method as described in claim 24, wherein, The steps to generate this second time period include: When the level of the current sensing signal passes the second threshold at a first time point, the first time period is started; When the level of the current sensing signal passes the first threshold at a second time point, the timing of the first time period ends; and Starting from the second time point, the second time period is generated based on the length of the first time period.

26. The control method as described in claim 24, wherein, The length of the first time period is equal to the length of the second time period.

27. The control method as described in claim 24, wherein, The absolute value of the difference between the first threshold and the second threshold is less than the peak-to-peak value of the current sensing signal.

28. The control method as described in claim 24, wherein, The absolute value of the difference between the first threshold and the second threshold is less than 1 / 2 of the peak-to-peak value of the current sensing signal.

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