Transceiver device with phase tracking mechanism and transceiver device operation method

Abstract

The present disclosure relates to a transceiver device with a phase tracking mechanism and a method for operating the transceiver device. A transceiver device with a frequency offset adjustment and phase tracking mechanism. The receiving circuit includes: a phase detection circuit, a proportional gain circuit and a clock and data recovery circuit. The phase detection circuit samples an input data signal and performs phase detection according to a sampling clock signal to generate a phase detection result. The proportional gain circuit performs a proportional gain operation on the phase detection result to generate a phase adjustment signal. The clock and data recovery circuit receives a source clock signal to generate a sampling clock signal, and performs phase adjustment according to the phase adjustment signal. The integral gain circuit performs an integral gain operation on the phase detection result to generate a frequency adjustment signal. The source clock generation circuit receives a reference clock signal to generate a source clock signal and performs frequency adjustment according to the frequency adjustment signal. The transmission circuit transmits a signal according to the source clock signal.

Description

Technical Field

[0001] The present invention relates to transceiver technology, and more particularly to a transceiver device with frequency adjustment and phase tracking mechanisms and a method for operating the transceiver device. Background Art

[0002] A repeater is any active component that processes a signal to increase the physical transmission distance and / or reduce the loss in the transmission line in the medium in which the signal is transmitted, thereby allowing the signal to be successfully transmitted. One type of repeater is a retimer, which is a component that contains a clock data recovery circuit to re-time the signal.

[0003] In the design of a general retimer, phase tracking is easily affected by frequency tracking at low frequencies that easily cause system delays. In addition, when the receiving circuit and the transmitting circuit need to operate at the same frequency, additional hardware components must be set up. Therefore, the retimer needs to improve performance and cost. Summary of the invention

[0004] In view of the problems in the prior art, one object of the present invention is to provide a transceiver device with frequency adjustment and phase tracking mechanisms and a transceiver device operating method thereof to improve the prior art.

[0005] The present invention includes a transceiver device with a phase tracking mechanism, including: a receiving circuit, an integral gain circuit, a source clock generation circuit and a transmitting circuit. The receiving circuit includes: a phase detection circuit, a proportional gain circuit and a clock and data recovery circuit. The phase detection circuit is configured to sample and phase-detect an input data signal according to a sampling clock signal with a complex phase to generate a phase detection result. The proportional gain circuit is configured to perform a proportional gain operation on the phase detection result to generate a phase adjustment signal. The clock and data recovery circuit is configured to receive a source clock signal to generate a sampling clock signal, and to phase-adjust the sampling clock signal according to the phase adjustment signal. The integral gain circuit is configured to perform an integral gain operation on the phase detection result to generate a frequency adjustment signal. The source clock generation circuit is configured to receive a reference clock signal to generate a source clock signal and to frequency-adjust the source clock signal according to the frequency adjustment signal. The transmission circuit is configured to perform signal transmission according to the source clock signal.

[0006] The present invention further includes a method for operating a transceiver device with a phase tracking mechanism, comprising: a phase detection circuit included in a receiving circuit samples and phase-detects an input data signal according to a sampling clock signal with a complex phase to generate a phase detection result; a proportional gain circuit included in the receiving circuit performs a proportional gain operation on the phase detection result to generate a phase adjustment signal; a clock and data recovery circuit included in the receiving circuit receives a source clock signal to generate a sampling clock signal, and performs phase adjustment on the sampling clock signal according to the phase adjustment signal; an integral gain circuit performs an integral gain operation on the phase detection result to generate a frequency adjustment signal; a source clock generation circuit receives a reference clock signal to generate a source clock signal and performs frequency adjustment on the source clock signal according to the frequency adjustment signal; and a transmitting circuit transmits a signal according to the source clock signal.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a transceiver device with a phase tracking mechanism according to an embodiment of the present invention is shown respectively;

[0009] Figure 2 A block diagram showing a clock and data recovery circuit in another embodiment of the present invention;

[0010] Figure 3 A block diagram showing a source clock generating circuit in another embodiment of the present invention; and

[0011] Figure 4 The flowchart shows a transceiver device operating method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] One of the purposes of the present invention is to provide a transceiver device with frequency adjustment and phase tracking mechanism and a transceiver device operation method thereof to improve the tracking performance and enable the transceiver to receive and send without additional hardware components when using the same source clock signal.

[0013] Please refer to Figure 1 . Figure 1 A block diagram of a transceiver device 100 with frequency adjustment and phase tracking mechanism in one embodiment of the present invention is shown. The transceiver device 100 can perform data reception and data transmission. In one embodiment, the transceiver device 100 is a repeater, such as but not limited to a re-timer using a passive optical network (PON) serializer and deserializer (SERDES) architecture.

[0014] The transceiver device 100 comprises a receiving circuit 105 (in Figure 1 Marked as RX), integral gain circuit 110 (in Figure 1 KI), source clock generating circuit 115 (in Figure 1 denoted as SCG) and the transmission circuit 120 (in Figure 1 Marked as TX).

[0015] The receiving circuit 105 is configured to receive data and includes a phase detection circuit 125 (in Figure 1 denoted as PD), proportional gain circuit 130 (in Figure 1 KP) and the clock and data recovery circuit 135 (in Figure 1 (denoted as CDR).

[0016] The phase detection circuit 125 receives an input data signal DI from an external electronic device (not shown in the figure) through a network. In one embodiment, an equalizer (not shown in the figure) may be provided before the phase detection circuit 125 so that the phase detection circuit 125 receives the equalized input data signal DI.

[0017] The phase detection circuit 125 is configured to sample and phase-detect the input data signal DI according to a sampling clock signal SACLK having multiple phases to generate a sampled data signal SD and a phase detection result UD.

[0018] In one embodiment, the sampling clock signal SACLK includes a set of clock signals with different phases to sample the input data signal DI and generate a plurality of sampling results.

[0019] The sampled data signal SD may be further generated according to the sampling result. In one embodiment, the sampled data signal SD is transmitted to the digital signal processing circuit 190 (at Figure 1 The digital signal processing circuit 190 processes the sampled data signal SD. In one embodiment, the digital signal processing circuit 190 may perform, for example, but not limited to, demultiplexing, decoding, or other digital signal processing on the sampled data signal SD.

[0020] Furthermore, a phase detection result UD can be obtained according to the sampling result, wherein the phase detection result UD indicates the relationship between the edge of the input data signal DI and different phases of the sampling clock signal SACLK.

[0021] The phase detection result UD includes information about the phase relationship between the sampling clock signal SACLK and the input data signal DI. In one embodiment, the phase detection result UD includes a first value indicating a phase leading condition (i.e., a "front" condition) or a second value indicating a phase lagging condition (i.e., a "back" condition). For example, the first value is +1 and the second value is -1. However, the present invention is not limited thereto.

[0022] The proportional gain circuit 130 is configured to extract phase relationship information from the phase detection result UD. More specifically, the proportional gain circuit 130 is configured to perform a proportional gain operation on the phase detection result UD to generate the phase adjustment signal PA. In one embodiment, the proportional gain circuit 130 multiplies the value included in the phase detection result UD by a gain value to generate the phase adjustment signal PA.

[0023] The clock and data recovery circuit 135 is configured to receive the source clock signal SOCLK to generate a sampling clock signal SACLK, and perform phase adjustment on the sampling clock signal SACLK according to the phase adjustment signal PA.

[0024] In one embodiment, the clock and data recovery circuit 135 may be Figure 1 The architecture shown is implemented in Figure 1 The structure includes a clock generating circuit 140 (in Figure 1 QCG) and phase interpolation circuit 145 (in Figure 1 The clock generation circuit 140 is configured to generate a clock signal QCLK (eg, a four-phase or eight-phase clock signal) according to the source clock signal SOCLK. The phase interpolation circuit 145 is configured to perform phase interpolation on the clock signal QCLK to generate a sample clock signal SACLK.

[0025] In another embodiment, the clock and data recovery circuit 135 may also only include the phase interpolation circuit 145 to directly perform phase interpolation on the source clock signal SOCLK having multiple phases.

[0026] Please refer to Figure 2 . Figure 2 A block diagram of a clock and data recovery circuit 135 is shown in another embodiment of the present invention.

[0027] like Figure 2 As shown, in this embodiment, the clock and data recovery circuit 135 includes a phase and frequency detection circuit 205 (in Figure 2 denoted as PFD), charge pump circuit 210 (in Figure 2 denoted as CP), voltage controlled oscillator 215 (in Figure 2 denoted as VCO), phase interpolation circuit 220 (in Figure 2PI) and the frequency dividing circuit 225 (in Figure 2 Marked as DIV).

[0028] The phase and frequency detection circuit 205 is configured to perform phase and clock frequency detection on the source clock signal SOCLK and the feedback signal FS to generate an error signal ES, wherein the error signal ES represents the phase relationship and the frequency relationship between the signals.

[0029] The charge pump circuit 210 is configured to generate the control signal CS according to the error signal ES. In more detail, the charge pump circuit 210 performs current charging or current sinking according to the error signal ES to generate the control signal CS with different voltage levels.

[0030] The voltage controlled oscillator 215 is configured to generate a sampling clock signal SACLK according to the control signal CS.

[0031] The phase interpolation circuit 220 is configured to perform phase interpolation on the sampled clock signal SACLK to generate a phase interpolation signal PIS.

[0032] The frequency division circuit 225 is configured to divide the phase interpolation signal PIS to generate the feedback signal FS. Therefore, the circuits in the clock and data recovery circuit 135 together form a feedback path to track the phase of the input data signal DI by adjusting the phase of the sampling clock signal SACLK according to the phase adjustment signal PA.

[0033] It should be noted that the clock and data recovery circuit 135 can be implemented by any clock and data recovery technology, but the present invention is not limited thereto.

[0034] Therefore, the proportional gain circuit 130 and the clock and data recovery circuit 135 together form a proportional path of the digital loop filter. By adjusting the phase of the sampling clock signal SACLK according to the phase relationship information displayed by the phase detection result UD, the phase of the input data signal DI can be tracked, thereby reducing the phase difference between the sampling clock signal SACLK and the input data signal DI.

[0035] In addition to the phase relationship information, the phase detection result UD also includes the frequency relationship information between the sampling clock signal SACLK and the input data signal DI. The frequency relationship information requires a longer observation time to capture.

[0036] The integral gain circuit 110 is configured to extract the frequency relationship information. More specifically, the integral gain circuit 110 is configured to perform an integral gain operation on the phase detection result UD to generate the frequency adjustment signal FA. In one embodiment, the integral gain circuit 110 may be disposed outside the receiving circuit 105 .

[0037] It should be noted that the phase detection result UD is Figure 1 In the figure, it is shown as being transmitted by a dotted line across the proportional gain circuit 130. However, the phase detection result UD can bypass the proportional gain circuit 130 and be directly transmitted to the integral gain circuit 110, or be processed by a demultiplexer (not shown in the figure) disposed in one of the integral gain circuit 110 and the proportional gain circuit 130 for down-conversion.

[0038] In one embodiment, the integral gain circuit 110 accumulates the values ​​included in the phase detection result UD to generate the frequency adjustment signal FA, and then transmits the frequency adjustment signal FA to the source clock generation circuit 115 .

[0039] In one embodiment, the transceiver device 100 further selectively includes an averaging circuit 150 (in Figure 1 The averaging circuit 150 is configured to average the frequency adjustment signal FA to generate an average frequency adjustment signal FA, so that the source clock generation circuit 115 substantially receives the average frequency adjustment signal FA.

[0040] More specifically, in one embodiment, the operating frequency of the integral gain circuit 110 (e.g., 805 MHz) is higher than the operating frequency of the source clock generation circuit 115 (e.g., 156.25 MHz). The averaging circuit 150 can store information of the frequency adjustment signal FA over a period of time to average the information to generate an averaged frequency adjustment signal FA. Therefore, the averaging circuit 150 provides a frequency conversion mechanism to convert a relatively high-frequency frequency adjustment signal FA into a relatively low-frequency averaged frequency adjustment signal FA, so that the source clock generation circuit 115 operates according to the averaged frequency adjustment signal FA. It should be noted that the above-mentioned operating frequency values ​​are only examples. The present invention is not limited to this.

[0041] The source clock generating circuit 115 is configured to receive the reference clock signal RCLK to generate the source clock signal SOCLK and to adjust the frequency of the source clock signal SOCLK according to the average frequency adjustment signal FA.

[0042] In one embodiment, the source clock generation circuit 115 may be Figure 1 The architecture is implemented. Figure 1 The architecture includes a phase and frequency detection circuit 155 (in Figure 1 denoted as PFD), charge pump circuit 160 (in Figure 1 denoted as CP), voltage controlled oscillator 165 (in Figure 1 denoted as VCO), the frequency dividing circuit 170 (in Figure 1 DIV) and delta-sigma modulation circuit 175 (in Figure 1Labeled as SDM).

[0043] The phase and frequency detection circuit 155 is configured to perform phase and frequency error detection on the reference clock signal RCLK and the feedback signal FSS to generate an error signal ESS.

[0044] The charge pump circuit 160 is configured to generate the control signal CSS according to the error signal ESS. More specifically, the charge pump circuit 210 performs current charging or current draining according to the error signal ESS to generate the control signal CSS with different voltage levels.

[0045] The voltage controlled oscillator 165 is configured to generate a source clock signal SOCLK according to the control signal CSS.

[0046] The frequency dividing circuit 170 is configured to divide the source clock signal SOCLK to generate the feedback signal FSS.

[0047] The delta-sigma modulation circuit 175 is configured to adjust the divisor for frequency division according to the average frequency adjustment signal FA, so that the frequency division circuit 170 and the delta-sigma modulation circuit 175 operate together as a fractional-N frequency division circuit. In more detail, the code of the delta-sigma modulation circuit 175 can be adjusted according to the average frequency adjustment signal FA containing frequency difference information, thereby adjusting the divisor. Frequency tracking can be performed without adjusting the phase interpolation circuit 145 of the clock and data recovery circuit 135.

[0048] Please refer to Figure 3 . Figure 3 A block diagram of the source clock generating circuit 115 in another embodiment of the present invention is shown.

[0049] The source clock generation circuit 115 may be composed of Figure 3 The structure shown is implemented, where Figure 3 The structure contains Figure 1 The components shown are, for example, a phase and frequency detection circuit 155 , a charge pump circuit 160 , a voltage controlled oscillator 165 , a frequency division circuit 170 , and a delta-sigma modulation circuit 175 . Figure 3 The structure further comprises a phase interpolation circuit 300 (in Figure 3 Marked as PI).

[0050] The operation of the phase and frequency detection circuit 155, the charge pump circuit 160 and the voltage controlled oscillator 165 is similar to Figure 1 Therefore, the above-mentioned elements correspond to Figure 3 The operation of this will not be described in detail.

[0051] The frequency dividing circuit 170 is configured to divide the source clock signal SOCLK to generate the feedback signal FSS.

[0052] The phase interpolation circuit 300 is configured to perform phase interpolation on the feedback signal FSS according to an interpolation parameter to generate an interpolated feedback signal IFS.

[0053] The delta-sigma modulation circuit 175 is configured to adjust the interpolation parameters according to the average frequency adjustment signal FA, so that the phase interpolation circuit 300 performs phase interpolation on the feedback signal FSS according to the interpolation parameters. Therefore, the phase interpolation circuit 300, the frequency division circuit 170 and the delta-sigma modulation circuit 175 operate together as a fractional-N frequency division circuit. In more detail, the codeword of the delta-sigma modulation circuit 175 can be adjusted according to the average frequency adjustment signal FA containing the frequency difference information, thereby adjusting the interpolation parameters.

[0054] Therefore, the integral gain circuit 110 and the source clock generation circuit 115 work together as the integral path of the digital filter. By adjusting the frequency of the source clock signal SOCLK according to the frequency relationship information displayed by the phase detection result UD, the frequency of the input data signal DI can be tracked, thereby reducing the frequency difference between the sampling clock signal SACLK and the input data signal DI.

[0055] In one embodiment, when the phase detection result UD shows that the value of the frequency relationship information has a frequency difference, the value of the phase adjustment signal PA will have a DC offset, and the AC term of the value of the phase adjustment signal PA will show that the probability of occurrence of one of the phase leading condition and the phase lagging condition is greater than the other.

[0056] When the phase detection result UD shows that the value of the frequency relationship information is minimized and there is almost no frequency difference, the DC offset will be 0, and the AC term of the value of the phase adjustment signal PA shows that the probability of the phase leading state and the phase lagging state occurring is substantially equal.

[0057] The transmitting circuit 120 is configured to transmit signals according to the source clock signal SOCLK to transmit the output data signal DO. Therefore, the receiving circuit 105 and the transmitting circuit 120 can use the same source clock signal SOCLK so that data reception and data transmission are performed at the same frequency.

[0058] In some technologies, the clock and data recovery circuit uses a proportional-integral-derivative (PID) circuit to track both phase and frequency. In this case, the integral part of the PID circuit requires a long processing time, which affects the speed of phase tracking and causes system delays.

[0059] Furthermore, in order to make the transmission circuit operate at the same frequency as the input data of the receiving circuit, a phase interpolator for storing the frequency difference information of the receiving circuit is required to transmit the source clock signal to the transmission circuit, and enable the transmission circuit to operate at the same frequency even when the receiving circuit stops receiving new input data signals. Furthermore, in order for the transmission circuit to receive a clean source clock signal, a low-pass filter is also required to be additionally provided. The above-mentioned architecture thus has a larger area consumption and power consumption.

[0060] In the present invention, the transceiver device separates the proportional path and the integral path of the digital loop filter, and makes the proportional path track the phase at a higher frequency, and makes the integral path that works together with the source clock generation circuit track the frequency at a lower frequency. Since the frequency tracking mechanism is implemented in the source clock generation circuit, the receiving circuit and the transmitting circuit can operate at the same frequency without the need to set up an additional phase interpolator. Furthermore, the source clock generation circuit itself includes a low-pass filtering mechanism, so that the transmitting circuit does not need to set up an additional low-pass filter.

[0061] Therefore, the transceiver device of the present invention not only improves the performance of the receiving circuit, but also reduces the area cost and power consumption. In addition, since the digital loop filter is implemented by a digital circuit, process migration is easier to achieve.

[0062] Please refer to Figure 4 . Figure 4 A flow chart of a transceiver device operating method 400 is shown in one embodiment of the present invention.

[0063] In addition to the aforementioned devices, the present invention further discloses a transceiver device operating method 400 which is applied to, for example, but not limited to Figure 1 In the transceiver device 100. One embodiment of the transceiver device operation method 400 is as follows. Figure 4 As shown, the following steps are included.

[0064] In step S410 , the phase detection circuit 125 included in the receiving circuit 105 samples and performs phase detection on the input data signal DI according to the sampling clock signal SACLK to generate a phase detection result UD.

[0065] In step S420 , the proportional gain circuit 130 included in the receiving circuit 105 performs a proportional gain operation on the phase detection result UD to generate a phase adjustment signal PA.

[0066] In step S430 , the clock and data recovery circuit 135 included in the receiving circuit 105 receives the source clock signal SOCLK to generate a sampling clock signal SACLK, and performs phase adjustment on the sampling clock signal SACLK according to the phase adjustment signal PA.

[0067] In step S440 , the integral gain circuit 110 performs an integral gain operation on the phase detection result UD to generate a frequency adjustment signal FA.

[0068] In step S450 , the source clock generating circuit 115 receives the reference clock signal RCLK to generate a source clock signal SOCLK and adjusts the frequency of the source clock signal SOCLK according to the frequency adjustment signal FA.

[0069] In step S460 , the transmitting circuit 120 performs signal transmission according to the source clock signal SOCLK.

[0070] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without violating the spirit of the present invention.

[0071] In summary, the transceiver device with phase tracking mechanism and the transceiver device operation method of the present invention separate the proportional path and the integral path of the digital loop filter, so that the phase is tracked at a higher frequency by the clock and data recovery circuit, and the frequency is tracked at a lower frequency by the source clock generation circuit. The tracking performance can be improved, and the transceiver circuit can use the same source clock signal without setting up additional hardware.

[0072] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit contents of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope of the patent application defined in this specification.

[0073]

Explanation of symbols

[0074] 100: transceiver device

[0075] 105: Receiving circuit

[0076] 110: Integral gain circuit

[0077] 115: Source clock generation circuit

[0078] 120: Transmission circuit

[0079] 125: Phase detection circuit

[0080] 130: Proportional gain circuit

[0081] 135: Clock and Data Recovery Circuit

[0082] 140: Clock generation circuit

[0083] 145: Phase interpolation circuit

[0084] 150: Average circuit

[0085] 155: Phase and frequency detection circuit

[0086] 160: Charge pump circuit

[0087] 165: Voltage Controlled Oscillator

[0088] 170: Frequency division circuit

[0089] 175: Delta-sigma modulation circuit

[0090] 190: Digital signal processing circuit

[0091] 205: Phase and frequency detection circuit

[0092] 210: Charge pump circuit

[0093] 215: Voltage Controlled Oscillator

[0094] 220: Phase interpolation circuit

[0095] 225: Frequency division circuit

[0096] 300: Phase interpolation circuit

[0097] 400: Transceiver device operation method

[0098] S410~S460: Steps

[0099] CS, CSS: control signal

[0100] DI: Input data signal

[0101] DO: output data signal

[0102] ES: Error signal

[0103] FS, FSS: Feedback signal

[0104] IFS:Interpolated Feedback Signal

[0105] PA: Phase adjustment signal

[0106] PIS: Phase Interpolation Signal

[0107] QCLK: clock signal

[0108] RCLK: Reference clock signal

[0109] SACLK: sampling clock signal

[0110] SD: Sampled data signal

[0111] SOCLK: source clock signal

[0112] UD: Phase detection results

Claims

1. A transceiver device with a phase tracking mechanism, comprising: A receiving circuit comprising: A phase detection circuit is configured to sample and phase-detect an input data signal according to a sampling clock signal having multiple phases to generate a phase detection result; a proportional gain circuit configured to perform a proportional gain operation on the phase detection result to generate a phase adjustment signal; and a clock and data recovery circuit configured to receive a source clock signal to generate the sampled clock signal, and to perform phase adjustment on the sampled clock signal according to the phase adjustment signal; an integral gain circuit configured to perform an integral gain operation on the phase detection result to generate a frequency adjustment signal; a source clock generating circuit configured to receive a reference clock signal to generate the source clock signal and to adjust the frequency of the source clock signal according to the frequency adjustment signal; and A transmission circuit is configured to transmit a signal according to a source clock signal.

2. The transceiver device according to claim 1, wherein the clock and data recovery circuit further comprises: a clock generating circuit configured to generate a clock signal according to the source clock signal; and A phase interpolation circuit is configured to perform phase interpolation on the clock signal to generate the sampled clock signal.

3. The transceiver device according to claim 1, wherein the clock and data recovery circuit further comprises: a phase and frequency detection circuit configured to detect phase and frequency errors between the source clock signal and a feedback signal to generate an error signal; a charge pump circuit configured to generate a control signal according to the error signal; a voltage controlled oscillator configured to generate the sampling clock signal according to the control signal; a phase interpolation circuit configured to perform phase interpolation on the sampled clock signal to generate a phase interpolation signal; and A frequency dividing circuit is configured to perform frequency division on the phase interpolation signal to generate the feedback signal.

4. The transceiver device according to claim 1, further comprising an averaging circuit configured to average the frequency adjustment signal to generate an average frequency adjustment signal, so that the source clock generating circuit performs frequency adjustment substantially according to the average frequency adjustment signal.

5. The transceiver device according to claim 1, wherein the source clock generating circuit comprises: a phase and frequency detection circuit configured to detect phase and frequency errors between the reference clock signal and a feedback signal to generate an error signal; a charge pump circuit configured to generate a control signal according to the error signal; a voltage controlled oscillator configured to generate the source clock signal according to the control signal; a frequency dividing circuit configured to divide the source clock signal to generate the feedback signal; and A Sigma Delta modulation circuit is configured to adjust a divisor for frequency division according to the frequency adjustment signal.

6. The transceiver device according to claim 1, wherein the source clock generation circuit comprises: a phase and frequency detection circuit configured to perform phase and frequency error detection on the reference clock signal and a reference clock signal to generate an error signal; a charge pump circuit configured to generate a control signal according to the error signal; a voltage controlled oscillator configured to generate the source clock signal according to the control signal; A frequency dividing circuit configured to divide the source clock signal to generate a feedback signal; a phase interpolation circuit configured to perform phase interpolation on the feedback signal according to an interpolation parameter to generate the interpolated feedback signal; and A delta-sigma modulation circuit is configured to adjust the interpolation parameter according to the frequency adjustment signal. 7 . The transceiver device of claim 1 , wherein the phase detection result comprises a first value indicating a phase leading condition or a second value indicating a phase lagging condition.

8. The transceiver device of claim 1, wherein the phase detection circuit is further configured to generate a sampled data signal, so that a digital signal processing circuit processes the sampled data signal.

9. A method for operating a transceiver device having a phase tracking mechanism, comprising: A phase detection circuit included in a receiving circuit samples an input data signal and performs phase detection according to a sampling clock signal with multiple phases to generate a phase detection result; A proportional gain circuit included in the receiving circuit performs a proportional gain operation on the phase detection result to generate a phase adjustment signal; A clock and data recovery circuit included in the receiving circuit receives a source clock signal to generate the sampling clock signal, and performs phase adjustment on the sampling clock signal according to the phase adjustment signal; An integral gain circuit performs an integral gain operation on the phase detection result to generate a frequency adjustment signal; A source clock generating circuit receives a reference clock signal to generate the source clock signal and adjusts the frequency of the source clock signal according to the frequency adjustment signal; and A transmission circuit transmits signals according to a source clock signal.

10. The transceiver device operating method according to claim 9, further comprising: A clock generating circuit generates a clock signal according to the source clock signal; and A phase interpolation circuit performs phase interpolation on the clock signal to generate the sampled clock signal.

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