A distributed chassis device and its time synchronization method

Abstract

This application provides a distributed chassis device and a method for time synchronization therewith. The distributed chassis device includes a main control board and service boards. The method includes: the main control board acquiring the current CPU utilization Umx of the main control board and the CPU utilization Usx of the service boards; the main control board determining a first processing delay value Tdmx corresponding to the utilization Umx and a second processing delay value Tdsx corresponding to the utilization Usx; the main control board determining that the current delay value Tdx of the main control board and the service boards is the sum of Td0, Tdmx, and Tdsx, and notifying the service boards that Td0 is the delay value between the main control board and the service boards in their initial state; and the service boards adjusting their local clocks according to the received Tdx to achieve time synchronization with the main control board. This application fully considers the impact of the respective CPU utilization on message processing speed when synchronizing time between the service boards and the main control board, thus achieving accurate time synchronization.

Description

Technical Field

[0001] This application relates to the field of switch and router technology, and in particular to a distributed chassis device and a method for time synchronization therewith. Background Technology

[0002] With the rapid development of networks and the continuous improvement of network performance, the demand for distributed chassis devices is increasing. Most of the communication equipment currently used in core and aggregation networks is distributed chassis devices.

[0003] During equipment operation, such as Figure 1 In the distributed chassis device shown, both the main control board and each service board need to record their own service operation logs, anomaly alarms, and debugging information. When a problem occurs in the device, the system logs on the main control board alone are insufficient for accurate location, so the service boards also need to provide detailed log information to assist in the troubleshooting. However, when the time information carried by the two logs is inconsistent, not only is the maximum value of the log information not utilized, but it also brings certain difficulties to troubleshooting.

[0004] In existing technologies, the latency between the main control board and the service board is calculated using four timestamps carried in the exchange messages between them. However, this method does not take into account the CPU utilization of each board in the device. Since the CPUs of each board are responsible for processing various messages, when the device is running in idle mode, the CPU utilization is a relatively small and stable value, which is considered an ideal state. Under this condition, the latency value obtained is also a relatively stable and accurate value. However, when the boards of the distributed chassis device are under different load states, the CPU utilization of each board will change significantly. In this case, the latency value between the main control board and the service board will no longer be consistent with the latency value when the device is running in idle mode, and may even have a large variation. If the latency value when the device is running in idle mode is still used, the time synchronization between the main control board and the service board will not be achieved in practice, affecting the accuracy of data acquisition and the reliability of the entire device. Summary of the Invention

[0005] This application provides a distributed chassis device and a method for time synchronization, which solves the problem of inaccurate time synchronization caused by the failure of existing distributed chassis devices to consider the CPU utilization of the main control board and the service board.

[0006] According to a first aspect of the embodiments of this application, a method for time synchronization of a distributed chassis device is provided, the distributed chassis device including a main control board and a plurality of service boards connected to the main control board, the method comprising:

[0007] The main control board obtains the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board;

[0008] The main control board determines the first processing latency value Tdmx corresponding to the utilization rate Umx, and the second processing latency value Tdsx corresponding to the utilization rate Usx;

[0009] The main control board determines that the current latency value Tdx of the main control board and the service board is the sum of the initial state latency values ​​Td0, Tdmx and Tdsx, and notifies the service board that the initial state latency value Td0 is the latency value between the main control board and the service board in the initial state.

[0010] The service board adjusts its local clock according to the received current delay value Tdx to achieve time synchronization with the main control board.

[0011] The main control board determines the first processing latency value Tdmx corresponding to the utilization rate Umx, including:

[0012] Determine the current preset interval (Umi, Umj) in which the utilization rate Umx is located;

[0013] Based on the correspondence between the interval endpoint values ​​of the main control board CPU utilization and the first processing latency value, obtain the latency value Tdmi corresponding to the interval endpoint value Umi and the latency value Tdmj corresponding to Umj.

[0014] calculate

[0015] In one or more possible implementations, the main control board determines the second processing latency value Tdsx corresponding to the utilization rate Usx, including:

[0016] The main control board determines the second processing delay value Tdsx corresponding to the utilization rate Usx in the following way, or the receiving service board determines the second processing delay value Tdsx corresponding to the utilization rate Usx in the following way:

[0017] Determine the current preset interval (Usm, Usn) in which the utilization rate Usx is located;

[0018] Based on the correspondence between the interval endpoint values ​​of the recorded service board CPU utilization and the second processing latency value, obtain the latency value Tdsm corresponding to the interval endpoint value Usm and the latency value Tdsn corresponding to Usn.

[0019] calculate

[0020] In one or more possible implementations, when the main control board determines the second processing latency value Tdsx corresponding to the utilization rate Usx, the main control board pre-records the correspondence between the interval endpoint values ​​of the service board CPU utilization rate and the second processing latency value.

[0021] When the main control board receives the second processing delay value Tdsx corresponding to the utilization rate Usx determined by the service board, the service board pre-records the correspondence between the interval endpoint values ​​of the service board's CPU utilization rate and the second processing delay value.

[0022] In one or more possible implementations, the initial state delay value Td0 is the delay value of the main control board when the main control board CPU utilization is Umi and the service board CPU utilization is the initial value Us0, and the delay value between the main control board CPU utilization and the service board CPU utilization is the initial value Um0 and the service board CPU utilization is Usm.

[0023] Wherein, the initial value Um0 is the utilization rate corresponding to the main control board starting up in an idle state, and the initial value Us0 is the utilization rate corresponding to the service board starting up in an idle state.

[0024] In one or more possible implementations, the latency values ​​Tdmi and Tdmj corresponding to the interval endpoint values ​​Umi and Umj, respectively, are the latency values ​​corresponding to the initial value Us0 of the service board CPU utilization and the CPU utilization of the main control board Umi and Umj, respectively.

[0025] The latency values ​​Tdsm and Tdsn corresponding to the interval endpoint values ​​Usm and Usn are the latency values ​​corresponding to the initial value Um0 of the main control board CPU utilization and the CPU utilization of the service board Usm and Usn, respectively.

[0026] In one or more possible implementations, a preset range for the CPU utilization of the main control board is set in the following manner:

[0027] When the CPU utilization of the main control board is linearly related to the message processing time, a preset range (Um0, Ummax) is set. Um0 is the initial value of the CPU utilization of the main control board in the idle state, and Ummax is the predetermined peak value of the utilization of the main control board.

[0028] When the CPU utilization of the main control board is not linearly related to the message processing time, Um0-Ummax is divided into multiple preset intervals and the endpoint values ​​of each preset interval are determined.

[0029] In one or more possible implementations, a preset range for the CPU utilization of the service board is set in the following manner:

[0030] When the CPU utilization of the service board is linearly related to the message processing time, a preset range (Us0, Usmax) is set, where Us0 is the initial value of the CPU utilization of the service board in the idle state, and Usmax is the predetermined peak utilization of the service board.

[0031] When the CPU utilization of the service board is not linearly related to the message processing time, Us0-Usmax is divided into multiple preset intervals and the endpoint values ​​of each preset interval are determined.

[0032] In one or more possible implementations, when recording the correspondence between the interval endpoints of the main control board CPU utilization and the first processing latency value / the correspondence between the interval endpoints of the service board CPU utilization and the second processing latency value, the main control board CPU utilization / the service board CPU utilization are increased to the corresponding interval endpoints in the following manner:

[0033] Send configuration protocol messages to the main control board CPU / service board CPU via an external tester to continuously increase the main control board CPU utilization / service board CPU utilization to the corresponding interval endpoint value; or

[0034] The main control board actively sends test messages to non-test service boards, so that after receiving the test messages, the non-test service boards send attack messages to the main control board / service board according to a preset strategy until the required main control board CPU utilization / service board CPU utilization is achieved.

[0035] In one or more possible implementations, the following method is used to determine whether the main control board CPU utilization / service board CPU utilization is linearly related to the message processing time:

[0036] While the CPU utilization of the service board remains at the initial value Us0, and the CPU utilization of the main control board increases from the initial value Um0 to reach the predetermined utilization peak Ummax, a set number of delay values ​​between the main control board and the service board are obtained. If the error values ​​between the obtained set number of delay values ​​and the calculated delay values ​​are all within the first error range, it is determined that the CPU utilization of the main control board is linearly related to the message processing time.

[0037] While the CPU utilization of the main control board remains at the initial value Um0, and the CPU utilization of the service board increases from the initial value Us0 to reach the predetermined utilization peak Usmax, a set number of delay values ​​between the main control board and the service board are acquired. If the error values ​​between the acquired set number of delay values ​​and the calculated delay values ​​are all within the second error range, it is determined that the CPU utilization of the service board is linearly related to the message processing time.

[0038] In one or more possible implementations, the main control board obtains the current main control board CPU utilization Umx and the service board CPU utilization Usx, including:

[0039] The service board periodically obtains the current CPU utilization rate of the service board and reports it to the main control board;

[0040] When the main control board receives the current CPU utilization reported by the service board, it obtains the current CPU utilization of the main control board locally.

[0041] According to a second aspect of the embodiments of this application, a distributed chassis device is provided, the distributed chassis device comprising:

[0042] The main control board is used to obtain the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board; determine the first processing latency value Tdmx corresponding to the utilization rate Umx and the second processing latency value Tdsx corresponding to the utilization rate Usx; determine that the current latency value Tdx of the main control board and the service board is the sum of the initial state latency values ​​Td0, Tdmx and Tdsx, and notify the service board that the initial state latency value Td0 is the latency value between the main control board and the service board in the initial state;

[0043] Multiple service boards; receive the current delay value Tdx sent by the main control board, and adjust the local clock according to the current delay value to achieve time synchronization with the main control board.

[0044] The distributed chassis device and its time synchronization method provided in this application have the following advantages:

[0045] The time synchronization method in this application fully considers the CPU utilization of the main control board and the CPU utilization of the service board, making the latency calculation results between the two more accurate. It can effectively ensure that the time information carried by the log information recorded by the service board is consistent with the time information carried by the system log recorded by the main control board, which facilitates real-time alignment between the log information of the service board and the system log of the main control board. This provides an effective and reliable source of information for product maintenance and a powerful means for system optimization and product maintenance. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0047] Figure 1 This is a structural diagram of a distributed chassis device in related technologies;

[0048] Figure 2 This is a schematic diagram illustrating a distributed frame-based method for determining latency values ​​in related technologies.

[0049] Figure 3 This is a flowchart of the distributed frame device time synchronization method provided in the embodiments of this application;

[0050] Figure 4 This is a schematic diagram of the structure of the distributed chassis device provided in the embodiments of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] The existing technology for calculating latency between the main control board and the service board refers to... Figure 2 As shown, it is usually calculated using the following formula (1):

[0053] t_delay=((t4- t1)-(t3-t2)) / 2 (1)

[0054] Where: t_delay is the delay between the main control board and the service board n; t1 is the local clock carried when the main control board sends a synchronization message to the service board n; t2 is the local clock when the service board n receives the synchronization message; t3 is the local clock carried when the service board n sends a delay response message Delay_Req to the main control board; t4 is the local clock when the main control board receives the Delay_Req message. It should be noted that the delay between the main control board and different service boards needs to be calculated separately, and the delay between the main control board and each service board is not necessarily equal or unequal.

[0055] As can be seen, in the existing technology, the latency between the main control board and the service board is calculated by using the four timestamps carried in the interaction messages between the two. However, this method does not take into account the CPU utilization of each board in the device. As a result, when the device is running with an empty configuration, the latency values ​​between the main control board and the service board cannot be synchronized, which affects the accuracy of data acquisition and the reliability of operation of the entire device.

[0056] To address the aforementioned problems, this application proposes a time synchronization method for distributed chassis devices. This method is applied to distributed chassis devices consisting of a main control board and multiple service boards to achieve time synchronization between the main control board and each service board. The time synchronization method of this application fully considers the CPU utilization of both the main control board and the service boards, making the latency calculation results between them more accurate. This effectively ensures that the time information carried in the log information recorded by the service boards is consistent with the time information carried in the system logs recorded on the main control board. This facilitates real-time alignment between the log information of the service boards and the system logs of the main control board, providing an effective and reliable information source for product maintenance and a powerful means for system optimization and product maintenance.

[0057] This application proposes a time synchronization method applied to a distributed chassis device consisting of a main control board and service boards. (Refer to...) Figure 3 As shown, the method includes:

[0058] S1: The main control board obtains the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board;

[0059] In this step, the current CPU utilization rate Usx of the service board is obtained locally on the service board using existing technology and reported to the main control board.

[0060] Optionally, the service board periodically obtains the current CPU utilization rate Usx of the service board and reports it to the main control board;

[0061] When the main control board receives the current CPU utilization Usx reported by the service board, it obtains the current CPU utilization Umx of the main control board locally using existing technology.

[0062] S2: The main control board determines the first processing latency value Tdmx corresponding to the utilization rate Umx, and the second processing latency value Tdsx corresponding to the utilization rate Usx;

[0063] In this step, the main control board determines the first processing latency value Tdmx corresponding to the current CPU utilization Umx, which can be obtained through the following methods:

[0064] Determine the current CPU utilization Umx of the main control board within the preset range (Umi, Umj);

[0065] Based on the correspondence between the interval endpoint values ​​of the main control board CPU utilization and the first processing latency value, obtain the latency value Tdmi corresponding to the interval endpoint value Umi and the latency value Tdmj corresponding to Umj.

[0066] The first processing latency value Tdmx corresponding to the current CPU utilization Umx of the main control board is determined according to the following formula:

[0067]

[0068] Among them, the latency values ​​Tdmi and Tdmj corresponding to the interval endpoints Umi and Umj of the current CPU utilization range of the main control board are the latency values ​​corresponding to the initial value Us0 of the service board CPU utilization and the CPU utilization of the main control board Umi and Umj respectively. The specific way to obtain the corresponding latency values ​​can be obtained by using the four timestamps in the existing technology.

[0069] In this embodiment, the initial value of the main control board CPU utilization Um0 is the utilization corresponding to the main control board starting up in an idle state, and the initial value of the service board CPU utilization Us0 is the utilization corresponding to the service board starting up in an idle state.

[0070] In this step, the second processing latency value Tdsx corresponding to the current CPU utilization Usx of the service board can be determined in the following way:

[0071] Determine the current CPU utilization of the service board, Usx, within the preset range (Usm, Usn).

[0072] Based on the correspondence between the interval endpoint values ​​of the recorded service board CPU utilization and the second processing latency value, obtain the latency value Tdsm corresponding to the interval endpoint value Usm and the latency value Tdsn corresponding to Usn.

[0073] The second processing latency value Tdsx corresponding to the current CPU utilization Usx is determined according to the following formula:

[0074]

[0075] Among them, the latency values ​​Tdsm and Tdsn corresponding to the interval endpoint values ​​Usm and Usn of the current CPU utilization range of the service board are the latency values ​​corresponding to the initial value Um0 of the main control board CPU utilization and the CPU utilization of the service board Usm and Usn respectively. The specific method to obtain the corresponding latency values ​​can be obtained by using the four timestamps in the existing technology.

[0076] In this step, the second processing latency value Tdsx can be determined locally by the service board using the above method and reported to the main control board when reporting the current CPU utilization Usx. At this time, the service board should pre-record the correspondence between the interval endpoints of the CPU utilization of the service board and the second processing latency value. Alternatively, the main control board can determine the second processing latency value locally based on the current CPU utilization Usx of the service board. However, in this case, the main control board should pre-record the correspondence between the interval endpoints of the CPU utilization of each service board and the second processing latency value.

[0077] S3: The main control board determines that the current latency value Tdx of the main control board and the service board is the sum of the initial latency values ​​Td0, Tdmx and Tdsx, that is, Tdx = Td0 + Tdmx + Tdsx, and notifies the service board that the initial latency value Td0 is the latency value between the main control board and the service board in the initial state.

[0078] In this step, the initial state delay value Td0 is the delay value between the main control board and the service board when the CPU utilization of the main control board is the initial value Um0 and the CPU utilization of the service board is the initial value Us0.

[0079] For the above method of determining Tdmx and Tdsx by setting a range, the initial state delay value Td0 is the delay value of the main control board when the main control board CPU utilization is Umi and the service board CPU utilization is the initial value Us0, and the delay value between the main control board CPU utilization is the initial value Um0 and the service board CPU utilization is Usm. The specific method for determining the delay value can be determined by existing technology.

[0080] S4: The service board adjusts its local clock according to the received current delay value Tdx to achieve time synchronization with the main control board.

[0081] In step S2 above, the main control board can set a preset range for the CPU utilization of the main control board in the following way:

[0082] When the CPU utilization of the main control board is linearly related to the message processing time, there is a preset interval. In this case, the preset interval (Umi, Umj] is (Um0, Ummax], where Um0 is the initial value of the CPU utilization of the main control board in the idle state, and Ummax is the predetermined peak utilization of the main control board, which can be, but is not limited to, 90%.

[0083] When the CPU utilization of the main control board is not linearly related to the message processing time, multiple preset intervals are set. Those skilled in the art determine the number of preset intervals and the endpoint values ​​of each preset interval according to the system design requirements. For example, if Um0 = 20% and Ummax = 90%, five intervals can be divided as follows: (20%, 40%), (40%, 60%), (60%, 75%), (75%, 85%), and (85%, 90%). The specific interval division here is only for better illustration and does not specifically limit the number and size of intervals involved in the embodiments of this application. However, when setting multiple preset intervals, one possible approach for those skilled in the art is that the larger the endpoint value of the interval, the smaller the range of the preset intervals involved should be.

[0084] Following the same concept, the service board can set a preset range for its CPU utilization in the following way:

[0085] When the CPU utilization of the service board is linearly related to the message processing time, there is a preset interval. In this case, the preset interval (Usm, Usn] is (Us0, Usmax], where Us0 is the initial value of the CPU utilization of the service board in the idle state, and Usmax is the predetermined peak utilization of the service board, which can be, but is not limited to, 90%.

[0086] When the CPU utilization of the service board is not linearly related to the message processing time, multiple preset intervals are set. Those skilled in the art can determine the number of preset intervals and the endpoint values ​​of each preset interval according to the system design requirements. There is no specific limitation on the number of intervals and the size of the intervals. However, when setting multiple preset intervals, in one possible implementation, the larger the endpoint value of the interval, the smaller the range of the preset intervals involved should be.

[0087] In implementation, the peak CPU utilization of the main control board and the peak CPU utilization of the service board represent the maximum CPU utilization achievable during normal operation of the equipment under system design. The peak CPU utilization of the main control board and the peak CPU utilization of the service board can be determined separately based on the scenario design, and they are not required to be equal or unequal. When the CPUs of the main control board and the service board are operating at different utilization rates, the latency value between the main control board and the service board is determined according to existing technology and can be used as a reference. Figure 1 The method shown in formula (1) is directly quoted here and will not be repeated.

[0088] Furthermore, in the above implementation process of this application, in order to pre-record the correspondence between the interval endpoint values ​​of the main control board CPU utilization and the first processing delay value, the utilization of the main control board CPU can be adjusted in the following way:

[0089] (1) Send a setting protocol message to the main control board CPU through an external tester so that the utilization rate of the main control board CPU can be continuously improved to reach the corresponding interval endpoint value.

[0090] (2) The main control board actively sends test messages to non-test service boards. After receiving the test messages, the non-test service boards send attack messages to the main control board according to a preset strategy until the corresponding interval endpoint value is reached, i.e., the CPU utilization of the main control board corresponding to the interval endpoint value. The attack messages are messages that the main control board can recognize and are set only to increase the CPU load of the main control board, and the sending frequency can be increased as the required CPU utilization increases. The non-test service boards are service boards that are not currently performing latency value tests with the main control board.

[0091] Based on the same concept, in the above implementation process of this application, in order to pre-record the correspondence between the endpoint values ​​of the utilization range of the service board CPU and the second processing latency value, the utilization of the service board CPU can be adjusted in the following way:

[0092] (1) Send a setting protocol message to the CPU of the service board through an external tester so that the CPU utilization of the service board can be continuously improved to reach the corresponding interval endpoint value.

[0093] (2) The main control board actively sends test messages to non-test service boards. After receiving the test messages, the non-test service boards send attack messages to the service boards that need to be tested for latency value according to a preset strategy until the corresponding interval endpoint value is reached, i.e., the CPU utilization of the service board corresponding to the interval endpoint value. The attack message is a message that can be identified by the service board being tested for latency value and is set only to increase the CPU load of the service board. The sending frequency can be increased as the required CPU utilization increases. The non-test service boards are those that are not currently being tested for latency value with the main control board.

[0094] In the above implementation process, whether the CPU utilization of the main control board / service board is linearly related to the message processing time can be known during system design, or it can be determined in advance through the following methods:

[0095] (1) While the CPU utilization of the service board remains at the initial value Us0, and the CPU utilization of the main control board increases from the initial value Um0 to reach the predetermined utilization peak Ummax, a set number of delay values ​​between the main control board and the service board are obtained. If the error values ​​between the set number of delay values ​​obtained and the delay values ​​obtained by calculating Tdx as described above are all within the first error range, it is considered that the CPU utilization of the main control board and the message processing time are linearly related. The first error range is determined by those skilled in the art based on the system design requirements.

[0096] (2) While the CPU utilization of the main control board remains at its initial value Um0, and the CPU utilization of the service board increases from its initial value Us0 to reach the predetermined peak utilization Usmax, a set number of delay values ​​between the main control board and the service board are acquired. If the error values ​​between the acquired set number of delay values ​​and the delay values ​​calculated using the above-mentioned Tdx calculation method are all within the second error range, then the CPU utilization of the service board is considered to be linearly related to the message processing time. The second error range is determined by those skilled in the art based on system design requirements.

[0097] In the aforementioned time synchronization process between the main control board and each service board, the main control board only needs to periodically obtain the local CPU utilization and the CPU utilization of the service board to be tested for latency. It then uses the different latency values ​​resulting from the different CPU utilization of the main control board and the service boards as compensation for the initial latency value, making the time synchronization process between the main control board and the service boards more accurate. Furthermore, the different latency values ​​resulting from the different CPU utilization of the main control board and the service boards are obtained and recorded before the actual equipment operation, and do not affect the equipment's operation on the network.

[0098] The above describes a method for time synchronization of a distributed chassis device according to this application. The following describes the distributed chassis device that performs the above method.

[0099] Please see Figure 4 This application provides a distributed chassis device, including:

[0100] The main control board 401 is used to obtain the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board; determine the first processing latency value Tdmx corresponding to the utilization rate Umx and the second processing latency value Tdsx corresponding to the utilization rate Usx; determine that the current latency value Tdx of the main control board and the service board is the sum of the initial state latency values ​​Td0, Tdmx and Tdsx, and notify the service board that the initial state latency value Td0 is the latency value between the main control board and the service board in the initial state;

[0101] Multiple service boards 402 receive the current delay value Tdx sent by the main control board, and adjust the local clock according to the current delay value to achieve time synchronization with the main control board.

[0102] The distributed chassis device provided in this application embodiment and the time synchronization method of the distributed chassis device provided in the above embodiment of this application belong to the same inventive concept. The steps of each method executed by the main control board and the service board in the time synchronization method provided in the above embodiment can be applied to the distributed chassis device in this embodiment for implementation, and will not be repeated here.

[0103] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for time synchronization of a distributed chassis device, the distributed chassis device comprising a main control board and multiple service boards connected to the main control board, characterized in that, The method includes: The main control board obtains the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board; The main control board determines the first processing latency value Tdmx corresponding to the utilization rate Umx, and the second processing latency value Tdsx corresponding to the utilization rate Usx; The main control board determines that the current latency value Tdx of the main control board and the service board is the sum of the initial state latency values ​​Td0, Tdmx and Tdsx, and notifies the service board that the initial state latency value Td0 is the latency value between the main control board and the service board in the initial state. The service board adjusts its local clock according to the received current delay value Tdx to achieve time synchronization with the main control board.

2. The method according to claim 1, characterized in that, The main control board determines the first processing latency value Tdmx corresponding to the utilization rate Umx, including: Determine the current preset interval (Umi, Umj) in which the utilization rate Umx is located; Based on the correspondence between the interval endpoint values ​​of the main control board CPU utilization and the first processing latency value, obtain the latency value Tdmi corresponding to the interval endpoint value Umi and the latency value Tdmj corresponding to Umj. calculate 3. The method according to claim 1, characterized in that, The main control board determines the second processing latency value Tdsx corresponding to the utilization rate Usx, including: The main control board determines the second processing delay value Tdsx corresponding to the utilization rate Usx in the following way, or the receiving service board determines the second processing delay value Tdsx corresponding to the utilization rate Usx in the following way: Determine the current preset interval (Usm, Usn) in which the utilization rate Usx is located; Based on the correspondence between the interval endpoint values ​​of the recorded service board CPU utilization and the second processing latency value, obtain the latency value Tdsm corresponding to the interval endpoint value Usm and the latency value Tdsn corresponding to Usn. calculate 4. The method according to claim 3, characterized in that, When the main control board determines the second processing latency value Tdsx corresponding to the utilization rate Usx, the main control board pre-records the correspondence between the interval endpoint values ​​of the service board CPU utilization rate and the second processing latency value. When the main control board receives the second processing delay value Tdsx corresponding to the utilization rate Usx determined by the service board, the service board pre-records the correspondence between the interval endpoint values ​​of the service board's CPU utilization rate and the second processing delay value.

5. The method according to claim 2 or 3, characterized in that, The initial state delay value Td0 is the delay value of the main control board when the main control board CPU utilization is Umi and the service board CPU utilization is the initial value Us0, and the delay value between the main control board CPU utilization is the initial value Um0 and the service board CPU utilization is Usm. Wherein, the initial value Um0 is the utilization rate corresponding to the main control board starting up in an idle state, and the initial value Us0 is the utilization rate corresponding to the service board starting up in an idle state.

6. The method according to claim 2 or 3, characterized in that, The latency values ​​Tdmi and Tdmj corresponding to the interval endpoint values ​​Umi and Umj, respectively, are the latency values ​​corresponding to the initial value Us0 of the service board CPU utilization and the CPU utilization of the main control board Umi and Umj, respectively. The latency values ​​Tdsm and Tdsn corresponding to the interval endpoint values ​​Usm and Usn are the latency values ​​corresponding to the initial value Um0 of the main control board CPU utilization and the CPU utilization of the service board Usm and Usn, respectively.

7. The method according to claim 2, characterized in that, The following method is used to set a preset range for the CPU utilization of the main control board: When the CPU utilization of the main control board is linearly related to the message processing time, a preset range (Um0, Ummax) is set. Um0 is the initial value of the CPU utilization of the main control board in the idle state, and Ummax is the predetermined peak value of the utilization of the main control board. When the CPU utilization of the main control board is not linearly related to the message processing time, Um0-Ummax is divided into multiple preset intervals and the endpoint values ​​of each preset interval are determined.

8. The method according to claim 3, characterized in that, The following method is used to set a preset range for the CPU utilization of the service board: When the CPU utilization of the service board is linearly related to the message processing time, a preset range (Us0, Usmax) is set, where Us0 is the initial value of the CPU utilization of the service board in the idle state, and Usmax is the predetermined peak utilization of the service board. When the CPU utilization of the service board is not linearly related to the message processing time, Us0-Usmax is divided into multiple preset intervals and the endpoint values ​​of each preset interval are determined.

9. The method according to claim 2 or 3, characterized in that, When recording the correspondence between the endpoint values ​​of the main control board CPU utilization interval and the first processing latency value, and the correspondence between the endpoint values ​​of the service board CPU utilization interval and the second processing latency value, the main control board CPU utilization and the service board CPU utilization are increased to the corresponding endpoint values ​​in the following manner: Send setting protocol messages to the main control board CPU / service board CPU through an external tester to continuously increase the main control board CPU utilization / service board CPU utilization to the corresponding interval endpoint value. or The main control board actively sends test messages to non-test service boards, so that after receiving the test messages, the non-test service boards send attack messages to the main control board / service board according to a preset strategy until the corresponding interval endpoint value is reached.

10. The method according to claim 7, characterized in that, The following method is used to determine whether the CPU utilization of the main control board / the CPU utilization of the service board is linearly related to the message processing time: While the CPU utilization of the service board remains at the initial value Us0, and the CPU utilization of the main control board increases from the initial value Um0 to reach the predetermined utilization peak Ummax, a set number of delay values ​​between the main control board and the service board are obtained. If the error values ​​between the obtained set number of delay values ​​and the calculated delay values ​​are all within the first error range, it is determined that the CPU utilization of the main control board is linearly related to the message processing time. While the CPU utilization of the main control board remains at the initial value Um0, and the CPU utilization of the service board increases from the initial value Us0 to reach the predetermined utilization peak Usmax, a set number of delay values ​​between the main control board and the service board are acquired. If the error values ​​between the acquired set number of delay values ​​and the calculated delay values ​​are all within the second error range, it is determined that the CPU utilization of the service board is linearly related to the message processing time.

11. The method according to claim 1, characterized in that, The main control board obtains the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board, including: The service board periodically obtains the current CPU utilization rate (Usx) of the service board and reports it to the main control board; When the main control board receives the current CPU utilization Usx reported by the service board, it obtains the current CPU utilization Umx of the main control board locally.

12. A distributed frame-type device, characterized in that, The distributed chassis device includes: The main control board is used to obtain the current CPU utilization rate Umx of the main control board and the CPU utilization rate Usx of the service board; determine the first processing latency value Tdmx corresponding to the utilization rate Umx and the second processing latency value Tdsx corresponding to the utilization rate Usx; determine that the current latency value Tdx of the main control board and the service board is the sum of the initial state latency values ​​Td0, Tdmx and Tdsx, and notify the service board that the initial state latency value Td0 is the latency value between the main control board and the service board in the initial state; Multiple service boards; receive the current delay value Tdx sent by the main control board, and adjust the local clock according to the current delay value to achieve time synchronization with the main control board.

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