A compensable digitally controlled passive vector modulator and its implementation method

Abstract

The present invention discloses a compensable digitally controlled passive vector modulator, comprising a mixer, an I-channel inverter, an I-channel digital attenuator, a combiner, a Q-channel inverter, and a Q-channel digital attenuator; wherein the function and implementation of the Q-channel inverter are the same as those of the I-channel inverter; the function and implementation of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator; the 0° phase of the mixer is connected to the I-channel inverter, and the 90° phase of the mixer is connected to the Q-channel inverter, so as to split the input radio frequency signal into two signals of nominally equal amplitude; the I-channel inverter is connected to the I-channel digital attenuator; the Q-channel inverter is connected to the Q-channel digital attenuator; and both the I-channel digital attenuator and the Q-channel digital attenuator are connected to the combiner. The present invention implements an LC phase shift network using a digitally controlled capacitor array device. While selecting an appropriate control word to reduce the inverter phase error, it can also compensate for the phase imbalance between the I-channel and Q-channel signals, thereby significantly improving modulation accuracy.

Description

Technical Field

[0001] The present invention relates to a compensable digitally controlled passive vector modulator and also to a corresponding implementation method, belonging to the technical field of carrier communication. Background Art

[0002] A vector modulator is a circuit module that uses an in-phase baseband signal, I, and a quadrature-phase baseband signal, Q, to adjust the amplitude and phase of the input signal. Due to its advantages such as high phase-amplitude modulation accuracy, low cost, and ease of integration, it has been widely used to suppress carrier leakage signals in self-interference systems such as ultra-high frequency RFID and continuous wave radar.

[0003] Vector modulators can be categorized as active or passive, depending on whether amplification or signal shaping circuits are used in the signal path. Active vector modulators introduce additional phase and amplitude noise because the signal passes through active components. Because this noise is uncorrelated with the noise in the leakage signal, it enters the receiver chain as an error signal after carrier leakage cancellation, affecting receiver sensitivity. Passive vector modulation, because it does not introduce additional noise, is often used in high-performance carrier cancellation loops to achieve amplitude and phase control.

[0004] Based on the type of IQ signal, vector modulators can be categorized as analog and digitally controlled vector modulators. Traditional analog vector modulators typically use PIN diode technology. Because the control signal is analog, it's difficult to avoid noise on the control signal being modulated onto the RF signal. However, the control signal of a digitally controlled vector modulator is a switching quantity, which doesn't introduce additional noise into the signal path, making it particularly suitable for high-sensitivity reception in self-interference systems. However, existing digitally controlled vector modulators suffer from significant phase and amplitude imbalances due to non-idealities in the device parameters. Consequently, modulation accuracy is low, and high-suppression carrier leakage cancellation cannot be achieved.

[0005] In the Chinese patent application with application number 202111065455.8, a digitally controlled vector modulator is disclosed. The digitally controlled vector modulator uses a 0° / 180° phase shifter and a digitally adjustable attenuator to implement a digitally controlled vector modulator solution, but it cannot solve the impact caused by irrational factors in actual operation. In addition, in the Chinese patent application with application number 202110823211.5, an S-band high-power double-balanced vector modulator based on a PIN diode and its control method are disclosed. However, this technical solution uses analog signal control, which poses the risk of introducing additional noise. Summary of the Invention

[0006] The primary technical problem to be solved by the present invention is to provide a compensable digitally controlled passive vector modulator.

[0007] Another technical problem to be solved by the present invention is to provide a method for realizing a compensable digitally controlled passive vector modulator.

[0008] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a compensable digitally controlled passive vector modulator is provided, comprising a mixer, an I-channel inverter, an I-channel digital attenuator, a power combiner, a Q-channel inverter, and a Q-channel digital attenuator; wherein the function and implementation of the Q-channel inverter are the same as those of the I-channel inverter; and the function and implementation of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator.

[0010] The 0° phase of the mixer is connected to the I-way inverter, and the 90° phase of the mixer is connected to the Q-way inverter, so as to split the input RF signal into two signals with the same nominal amplitude;

[0011] The I-way inverter is connected to the I-way digital attenuator; the Q-way inverter is connected to the Q-way digital attenuator;

[0012] The I-channel attenuator connection and the Q-channel attenuator connection are both connected to the power combiner.

[0013] Preferably, the I-way inverter includes an input single-pole double-throw switch, a first inductor, a first capacitor array, a second inductor, an output single-pole double-throw switch, a third inductor, a second capacitor array, and a fourth inductor;

[0014] The first inductor, the first capacitor array, and the second inductor form a high-pass LC phase-shifting network, which is a PI-type structure; the third inductor, the second capacitor array, and the fourth inductor form a low-pass LC phase-shifting network, which is a T-type structure;

[0015] In which, the first port 1 of the single-pole double-throw switch at the input end is connected to the 0° phase of the mixer, the second port of the single-pole double-throw switch at the input end is connected to one end of the fourth inductor, and the third port of the single-pole double-throw switch at the input end is respectively connected to one end of the first inductor and the first capacitor array; the other end of the fourth inductor is respectively connected to one end of the second capacitor array and one end of the third inductor, the other end of the second capacitor array is grounded, and the other end of the third inductor is connected to the second port of the single-pole double-throw switch at the output end; the other end of the first inductor is grounded; the other end of the first capacitor array is respectively connected to one end of the second inductor and the third port of the single-pole double-throw switch at the output end; and the other end of the second inductor is grounded.

[0016] According to a second aspect of an embodiment of the present invention, a method for implementing a compensable digitally controlled passive vector modulator is provided, comprising the following steps:

[0017] S1: Build the I-path low-pass phase-shift network and the Q-path low-pass phase-shift network;

[0018] S2: Measure the initial phase of the I-channel low-pass phase-shift network;

[0019] S3: Measure the initial phase of the Q-path low-pass phase-shift network;

[0020] S4: Calculate the initial phase difference between the I path and the Q path, and determine whether the absolute value of the initial phase difference is greater than 1°;

[0021] If yes, proceed to step S5; if no, record the current I-way capacitor array control word as CCW_I_L and the Q-way capacitor array control word as CCW_Q_L, and proceed to step S7;

[0022] S5: Adjust the phase of the I-channel low-pass phase-shift network until it meets the requirements, and record CCW_I_L;

[0023] S6: Adjust the phase of the Q-path low-pass phase-shift network until it meets the requirements, and record CCW_Q_L;

[0024] S7: Adjust the phase of the I-channel high-pass phase-shift network until it meets the requirements, and record CCW_I_H;

[0025] S8: Adjust the phase of the Q-path high-pass phase-shift network until it meets the requirements, and record CCW_Q_H;

[0026] S9: All recorded digitally tuned capacitor array control words are saved, and the parameter calibration process ends.

[0027] Preferably, the first port of the vector network analyzer is connected to the input port of the digital controlled passive vector modulator, and the second port is connected to the output port of the digital controlled passive vector modulator. The control module is used to generate a digital attenuation control word, an inverter control word and a capacitor array control word, and is connected to the digital controlled passive vector modulator.

[0028] Preferably, the I-way switch is switched to the low-pass phase-shift network; the I-way digital-adjustable capacitor array control word is set to 0X0C; the I-way digital-adjustable attenuator is set to 0dB; the Q-way digital-adjustable attenuator is set to 63.5dB, and the phase of the vector modulator is measured using a vector network analyzer. This phase is the initial phase of the I-way low-pass phase-shift network, recorded as Phase0(I_L).

[0029] Preferably, the Q-path switch is switched to the low-pass phase-shift network; the Q-path digital adjustment capacitor array control word is set to 0X0C; the Q-path digital adjustment attenuator is set to 0dB; the I-path digital adjustment attenuator is set to 63.5dB, and the phase of the vector modulator is measured using a vector network analyzer. This phase is the initial phase of the Q-path low-pass phase-shift network, recorded as Phase0(Q_L).

[0030] Optimally, switch the I-channel switch to the low-pass phase-shift network; set the I-channel digital attenuator to 0dB; set the Q-channel digital attenuator to 63.5dB, and adjust the I-channel digitally tuned capacitor array until the phase of the I-channel low-pass network, Phase(I_L), satisfies Phase0(I_L)+ΔPhase0 / 2±0.5°. Record the digitally tuned capacitor array control word at this time as CCW_I_L.

[0031] Optimally, the Q-path switch is switched to the low-pass phase-shift network; the Q-path digital attenuator is set to 0dB; the I-path digital attenuator is set to 63.5dB, and the Q-path digitally adjustable capacitor array is adjusted until the phase of the Q-path low-pass network, Phase(Q_L), satisfies Phase0(Q_L)+ΔPhase0 / 2±0.5°. The control word for the digitally adjustable capacitor array at this time is recorded as CCW_Q_L.

[0032] Optimally, switch the I-channel switch to the high-pass phase-shift network; set the I-channel digital attenuator to 0dB; set the Q-channel digital attenuator to 63.5dB, and adjust the I-channel digitally adjustable capacitor array until the phase of the I-channel high-pass network Phase (I_H) satisfies Phase (I_L) + 180° ± 1°. Record the digitally adjustable capacitor array control word at this time as CCW_I_H.

[0033] Optimally, the Q-path switch is switched to the high-pass phase-shift network; the Q-path digital attenuator is set to 0dB; the I-path digital attenuator is set to 63.5dB, and the Q-path digital-tunable capacitor array is adjusted until the phase of the Q-path high-pass network, Phase (Q_H), satisfies Phase (Q_L) + 180° ± 1°. The control word for the digital-tunable capacitor array at this time is recorded as CCW_Q_H.

[0034] Compared to existing technologies, this invention implements an LC phase-shift network using digitally controlled capacitor array devices. By selecting appropriate control words to reduce inverter phase error, it also compensates for phase imbalance between the I and Q paths, significantly improving modulation accuracy. Furthermore, by placing the digitally adjustable attenuator after the inverter, this invention increases the input power of the vector modulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a circuit diagram of the digitally controlled passive vector modulator provided by the present invention;

[0036] Figure 2 A schematic diagram of a hardware testing platform in an embodiment of the present invention;

[0037] Figure 3 This is a flow chart of the implementation method of the digitally controlled passive vector modulator provided by the present invention. DETAILED DESCRIPTION

[0038] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] This embodiment of the present invention first provides a compensable digitally controlled passive vector modulator. This vector modulator can be used to eliminate carrier leakage in UHF and RFID readers. The following description uses an operating frequency of 800 MHz and an output power greater than 20 dBm.

[0040] <First embodiment>

[0041] like Figure 1 As shown, the first embodiment of the present invention discloses a compensable digitally controlled passive vector modulator, which includes at least a mixer 1, an I-channel inverter 2, an I-channel digital attenuator 3, a power combiner 4, a Q-channel inverter 5, and a Q-channel digital attenuator 6. The specific components and operating principles thereof are described below:

[0042] In the first embodiment of the present invention, the 0° phase of the mixer 1 is connected to the I-phase inverter 2, and the 90° phase of the mixer 1 is connected to the Q-phase inverter 5. The function of the mixer 1 is to split the input RF signal into two signals with nominally equal amplitudes, namely, an I signal with a 0° phase and a Q signal with a 90° phase.

[0043] In the first embodiment of the present invention, the hybrid 1 uses the device XC0900A-03S, which introduces an amplitude deviation of 0.2 dB and a phase deviation of 2°.

[0044] In the first embodiment of the present invention, inverter 2 (I) includes an input single-pole double-throw switch 201, a first inductor 202, a first capacitor array 203, a second inductor 204, and an output single-pole double-throw switch 205, a third inductor 206, a second capacitor array 207, and a fourth inductor 208. The first inductor 202, the first capacitor array 203, and the second inductor 204 form a high-pass LC phase-shifting network with a PI structure; the third inductor 206, the second capacitor array 207, and the fourth inductor 208 form a low-pass LC phase-shifting network with a T structure. The theoretical calculation formulas for the components in these two LC phase-shifting networks are provided below.

[0045] The capacitance value in the T-type low-pass LC phase-shifting network is:

[0046]

[0047] The two inductor values ​​in the T-type low-pass LC phase-shift network are:

[0048]

[0049] The capacitance value in the PI type high-pass LC phase shift network is:

[0050]

[0051] The two inductor values ​​in the PI type high-pass LC phase-shift network are:

[0052]

[0053] Where φ is the phase of the phase shift network, ω is the angular frequency of the signal, and Z0 is the characteristic impedance of the circuit, 50 ohms.

[0054] The first port 1 of the input single-pole double-throw switch 201 is connected to the 0° phase of the mixer 1, the second port 2 of the input single-pole double-throw switch 201 is connected to one end of the fourth inductor 208, and the third port 3 of the input single-pole double-throw switch 201 is connected to one end of the first inductor 202 and the first capacitor array 203 respectively. The other end of the fourth inductor 208 is connected to one end of the second capacitor array 207 and one end of the third inductor 206 respectively. The other end of the second capacitor array 207 is grounded. The other end of the third inductor 206 is connected to the second port 2 of the output single-pole double-throw switch 205. The other end of the first inductor 202 is grounded. The other end of the first capacitor array 203 is connected to one end of the second inductor 204 and the third port 3 of the output single-pole double-throw switch 205 respectively. The other end of the second inductor 204 is grounded.

[0055] The first inductor 202 and the second inductor 204 used in the first embodiment of the present invention have a device model of 0201DS-9N6XJE, an inductance of 9.6 nH, and a tolerance of 3%. According to the theoretical calculation formula of each component in the LC phase shift network, the inductance here is 9.94 nH.

[0056] In the first embodiment of the present invention, the first capacitor array 203 is composed of a digitally adjustable capacitor array and a fixed capacitor connected in parallel. Theoretically, the capacitance value here is 3.94 pF.

[0057] The digitally adjustable capacitor array model is PE64906, with a control bit width of 5 bits, a capacitance value of 0.9 to 4.6 pF, and an adjustment step of 119 fF. The fixed capacitor model is GJM1555C 1H2R0GB01, with a capacitance value of 2 pF and a tolerance of 2%.

[0058] The third inductor 206 and the fourth inductor 208 used in the first embodiment of the present invention have a device model of 0201DS-9N6XJE, an inductance of 9.6 nH, and a tolerance of 3%. According to the theoretical calculation formula of each component in the LC phase shift network, the inductance here is 9.94 nH.

[0059] In the first embodiment of the present invention, the second capacitor array 207 is composed of a digitally adjustable capacitor array and a fixed capacitor connected in parallel. Theoretically, the capacitance value here is 3.94 pF.

[0060] The digitally adjustable capacitor array model is PE64906, with a control bit width of 5 bits, a capacitance value of 0.9 to 4.6 pF, and an adjustment step of 119 fF. The fixed capacitor model is GJM1555C 1H2R0GB01, with a capacitance value of 2 pF and a tolerance of 2%.

[0061] In the first embodiment of the present invention, the input end of the digital attenuator 3 is connected to the first port 1 of the output single-pole double-throw switch 205, and the output end of the digital attenuator 3 is connected to the power combiner.

[0062] The purpose of connecting the I-way attenuator 3 to the I-way inverter 2 in the aforementioned manner is to obtain a larger overall input power.

[0063] The device model of the I-channel digital attenuator 3 used in the first embodiment of the present invention is attenuator PE43705, and the maximum attenuation is 63.5dB.

[0064] In the first embodiment of the present invention, the function and implementation of the Q-path inverter 5 are the same as those of the I-path inverter 2, and the present invention will not elaborate on them here.

[0065] In the first embodiment of the present invention, the function and implementation of the Q-channel digital attenuator 6 are the same as those of the I-channel digital attenuator 3, and the present invention will not elaborate on them here.

[0066] In the first embodiment of the present invention, the combiner 4 combines the I-path signal and the Q-path signal into one-path signal for output.

[0067] The power combiner 4 used in the first embodiment of the present invention has a device model of ADP-2-4+, and the phase imbalance of the device is 0.7° and the amplitude imbalance is 0.1 dB.

[0068] The working principle of the compensable digitally controlled passive vector modulator provided by the present invention is described as follows:

[0069] The RF signal input to mixer 1 is set as:

[0070] S i (t) = A0Cos(ω0t)

[0071] Among them, S i (t) is the input time domain signal, A0 is the amplitude of the input signal, ω0 is the angular frequency of the signal, and t is time. After passing through the mixer, it is divided into an in-phase signal I and an orthogonal phase signal Q. The gain of the I channel is A I , the gain of Q path is AQ .

[0072] The gain amplitude of the I channel is changed by the I channel digital attenuator 3, and the gain amplitude of the Q channel is changed by the Q channel digital attenuator 6.

[0073] The sign of the gain of the I channel is changed by the I channel inverter 2, and the sign of the gain of the Q channel is changed by the Q channel inverter 5. Because there is a 90° phase difference between the two phase output ports of the mixer 1, the output RF signal after being combined by the power combiner 4 is:

[0074] S o (t) = A0A I cos(ω0t)+A0A Q sin(ω0t)=kA0 cos(ω0t+θ)

[0075] in: θ=arctan(A Q / A I ).

[0076] According to the above formula, after the RF signal passes through the vector modulator, the amplitude of the RF signal changes by k times and the phase changes by θ.

[0077] Therefore, there are two important irrational factors in the practical application of vector modulators, namely amplitude imbalance and phase imbalance.

[0078] Amplitude imbalance refers to the difference in gain between the I and Q channels under the same control word. Compensation can be achieved by simply adding a certain offset to the gain control word. The specific implementation method is well known in the art and will not be detailed here.

[0079] Phase imbalance refers to a phase deviation between the I-path signal and the Q-path signal. In the circuit of the present invention, the phase imbalance is caused by the discreteness and tolerance of the inductors in the high-pass LC phase-shifting network and the low-pass LC phase-shifting network. Therefore, by adjusting the capacitance value of the capacitor array connected to the inductors, the effect of the discreteness and tolerance of the inductors on the phase can be reduced, thereby compensating for the phase deviation between the I-path signal and the Q-path signal.

[0080] The present invention selects a reasonable control word through the capacitor array, which can not only introduce less phase deviation during the 0° to 180° phase switching process, but also be used to compensate for the phase deviation introduced by the mixer, attenuator and combiner.

[0081] The digitally controlled capacitor array device used in the present invention only selects a Pi-type structure in the high-pass filter and a T-type structure in the low-pass filter. Compared with the capacitor devices used in the prior art, the number of capacitor array devices used is reduced, thereby greatly saving costs.

[0082] <Second embodiment>

[0083] like Figure 3 As shown, the second embodiment of the present invention discloses a method for implementing a compensable digitally controlled passive vector modulator, comprising the following steps:

[0084] S1: Build the I-channel low-pass phase-shift network and the Q-channel low-pass phase-shift network.

[0085] like Figure 2 As shown, the vector network analyzer is used to test the phase of a digitally controlled passive vector modulator under different control words. Its first port 1 is connected to the input port of the digitally controlled passive vector modulator, and its second port 2 is connected to the output port of the digitally controlled passive vector modulator. The control module is used to generate the digital attenuation control word, the inverter control word, and the capacitor array control word, and is connected to the digitally controlled passive vector modulator.

[0086] S2: Measure the initial phase of the I-channel low-pass phase-shift network.

[0087] Switch the I-channel switch to the low-pass phase-shift network; set the I-channel digitally adjustable capacitor array control word to 0X0C (corresponding to a capacitance of 1.90pF); set the I-channel digitally adjustable attenuator to 0dB; set the Q-channel digitally adjustable attenuator to 63.5dB, and use a vector network analyzer to measure the phase of the vector modulator. This phase is the initial phase of the I-channel low-pass phase-shift network, recorded as Phase0(I_L).

[0088] Here, 63.5 dB is the maximum attenuation of the Q-path attenuator used in the first embodiment of the present invention.

[0089] S3: Measure the initial phase of the Q-path low-pass phase-shift network.

[0090] Switch the Q-path switch to the low-pass phase-shift network; set the Q-path digital adjustment capacitor array control word to 0X0C (corresponding to a capacitance of 1.90pF); set the Q-path digital adjustment attenuator to 0dB; set the I-path digital adjustment attenuator to 63.5dB, and use a vector network analyzer to measure the phase of the vector modulator. This phase is the initial phase of the Q-path low-pass phase-shift network, recorded as Phase0(Q_L).

[0091] Here, 63.5 dB is the maximum attenuation of the I-channel digital attenuator used in the first embodiment of the present invention.

[0092] S4: Calculate the initial phase difference ΔPhase0 between the I path and the Q path = Phase0(Q_L)-Phase0(I_L), and determine whether the absolute value of the initial phase difference |ΔPhase0| is greater than 1°.

[0093] If yes, proceed to step S5; if no, record the current I-way capacitor array control word as CCW_I_L and the Q-way capacitor array control word as CCW_Q_L, and proceed to step S7.

[0094] S5: Adjust the phase of the I-channel low-pass phase-shift network until it meets the requirement, and record CCW_I_L.

[0095] Switch the I-channel switch to the low-pass phase-shift network; set the I-channel digital attenuator to 0 dB; set the Q-channel digital attenuator to 63.5 dB, and adjust the I-channel digitally tuned capacitor array until the phase of the I-channel low-pass network, Phase(I_L), satisfies Phase0(I_L)+ΔPhase0 / 2±0.5°. Record the digitally tuned capacitor array control word at this point as CCW_I_L, and proceed to step S6.

[0096] S6: Adjust the phase of the Q-path low-pass phase-shift network until it meets the requirements and record CCW_Q_L.

[0097] Switch the Q-path switch to the low-pass phase-shift network; set the Q-path digital attenuator to 0 dB; set the I-path digital attenuator to 63.5 dB, and adjust the Q-path digitally adjustable capacitor array until the phase of the Q-path low-pass network, Phase(Q_L), satisfies Phase0(Q_L)+ΔPhase0 / 2±0.5°. Record the digitally adjustable capacitor array control word at this point as CCW_Q_L, and proceed to step S7.

[0098] S7: Adjust the phase of the I-channel high-pass phase-shift network until it meets the requirement, and record CCW_I_H.

[0099] Switch the I-channel switch to the high-pass phase-shift network; set the I-channel digital attenuator to 0dB; set the Q-channel digital attenuator to 63.5dB, and adjust the I-channel digitally adjustable capacitor array until the phase of the I-channel high-pass network, Phase(I_H), satisfies Phase(I_L)+180°±1°. Record the digitally adjustable capacitor array control word at this time as CCW_I_H, and proceed to step S8.

[0100] S8: Adjust the phase of the Q-path high-pass phase-shift network until it meets the requirements, and record CCW_Q_H.

[0101] Switch the Q-channel switch to the high-pass phase-shift network; set the Q-channel digital attenuator to 0dB; set the I-channel digital attenuator to 63.5dB, and adjust the Q-channel digitally adjustable capacitor array until the phase of the Q-channel high-pass network, Phase (Q_H), satisfies Phase (Q_L) + 180° ± 1°. Record the digitally adjustable capacitor array control word at this time as CCW_Q_H.

[0102] S9: All recorded digitally tuned capacitor array control words are saved, and the parameter calibration process ends.

[0103] The purpose of parameter calibration is to obtain the four parameters of the compensation CNC passive vector modulator, namely:

[0104] Control word CCW_I_L for the digitally adjustable capacitor in the I-channel LC low-pass phase-shift network;

[0105] The control word CCW_Q_L for the digitally adjustable capacitor in the Q-path LC low-pass phase-shift network;

[0106] Control word CCW_I_H for the digitally tuned capacitor in the I-channel LC high-pass phase-shift network;

[0107] The control word CCW_Q_H for the digitally tuned capacitor in the Q-path LC high-pass phase-shift network;

[0108] The completion of parameter correction means that the digital controlled passive vector modulator has completed the compensation of the phase deviation of the I-channel signal and the Q-channel signal.

[0109] Compared to existing technologies, this invention implements an LC phase-shift network using digitally controlled capacitor array devices. By selecting appropriate control words to reduce inverter phase error, it also compensates for phase imbalance between the I and Q paths, significantly improving modulation accuracy. Furthermore, by placing the digitally adjustable attenuator after the inverter, this invention increases the input power of the vector modulator.

[0110] The above describes in detail the compensated digitally controlled passive vector modulator and its implementation method provided by the present invention. Any obvious modification made to the present invention without departing from its essence would constitute an infringement of the present invention's patent rights and would incur corresponding legal liability.

Claims

1. A compensable digitally controlled passive vector modulator, characterized in that The invention comprises a mixer, an I-channel phase inverter, an I-channel digital attenuator, a power combiner, a Q-channel phase inverter and a Q-channel digital attenuator; wherein the function and implementation method of the Q-channel phase inverter are the same as those of the I-channel phase inverter; and the function and implementation method of the Q-channel digital attenuator are the same as those of the I-channel digital attenuator; The 0° phase of the mixer is connected to the I-way inverter, and the 90° phase of the mixer is connected to the Q-way inverter, so as to split the input RF signal into two signals with the same nominal amplitude; The I-way inverter is connected to the I-way digital attenuator; the Q-way inverter is connected to the Q-way digital attenuator; The I-channel attenuator connection and the Q-channel attenuator connection are both connected to the power combiner; The I-way inverter includes an input single-pole double-throw switch, a first inductor, a first capacitor array, a second inductor, an output single-pole double-throw switch, a third inductor, a second capacitor array, and a fourth inductor; The first inductor, the first capacitor array, and the second inductor form a high-pass LC phase-shifting network, which is a PI-type structure; the third inductor, the second capacitor array, and the fourth inductor form a low-pass LC phase-shifting network, which is a T-type structure; The first port of the single-pole double-throw switch at the input end is connected to the 0° phase of the mixer, the second port of the single-pole double-throw switch at the input end is connected to one end of the fourth inductor, and the third port of the single-pole double-throw switch at the input end is respectively connected to one end of the first inductor and the first capacitor array; the other end of the fourth inductor is respectively connected to one end of the second capacitor array and one end of the third inductor, the other end of the second capacitor array is grounded, and the other end of the third inductor is connected to the second port of the single-pole double-throw switch at the output end; the other end of the first inductor is grounded; the other end of the first capacitor array is respectively connected to one end of the second inductor and the third port of the single-pole double-throw switch at the output end; and the other end of the second inductor is grounded.

2. A method for implementing a compensable digitally controlled passive vector modulator, based on the digitally controlled passive vector modulator according to claim 1, characterized in that The steps include: S1: Build the I-path low-pass phase-shift network and the Q-path low-pass phase-shift network; S2: Measure the initial phase of the I-channel low-pass phase-shift network; S3: Measure the initial phase of the Q-path low-pass phase-shift network; S4: Calculate the initial phase difference between the I path and the Q path, and determine whether the absolute value of the initial phase difference is greater than 1°; If yes, proceed to step S5; If not, record the current I-channel capacitor array control word as CCW_I_L and the Q-channel capacitor array control word as CCW_Q_L, and proceed to step S7; S5: Adjust the phase of the I-channel low-pass phase-shift network until it meets the requirements, and record CCW_I_L; S6: Adjust the phase of the Q-path low-pass phase-shift network until it meets the requirements, and record CCW_Q_L; S7: Adjust the phase of the I-channel high-pass phase-shift network until it meets the requirements, and record CCW_I_H; S8: Adjust the phase of the Q-path high-pass phase-shift network until it meets the requirements, and record CCW_Q_H; S9: All recorded digitally tuned capacitor array control words are saved, and the parameter calibration process ends.

3. The implementation method according to claim 2, characterized in that: The first port of the vector network analyzer is connected to the input port of the digital controlled passive vector modulator, and the second port is connected to the output port of the digital controlled passive vector modulator. The control module is used to generate a digital attenuation control word, an inverter control word and a capacitor array control word, and is connected to the digital controlled passive vector modulator.

4. The implementation method according to claim 2, wherein: Switch the I-way switch to the low-pass phase-shift network; set the I-way digitally adjustable capacitor array control word to 0X0C; set the I-way digitally adjustable attenuator to 0dB; set the Q-way digitally adjustable attenuator to 63.5dB, and use a vector network analyzer to measure the phase of the vector modulator. This phase is the initial phase of the I-way low-pass phase-shift network, which is recorded as .

5. The implementation method according to claim 2, wherein: Switch the Q-path switch to the low-pass phase-shift network; set the Q-path digital adjustment capacitor array control word to 0X0C; set the Q-path digital adjustment attenuator to 0dB; set the I-path digital adjustment attenuator to 63.5dB, and use a vector network analyzer to measure the phase of the vector modulator. This phase is the initial phase of the Q-path low-pass phase-shift network, which is recorded as .

6. The implementation method according to claim 2, wherein: Switch the I-channel switch to the low-pass phase-shift network; set the I-channel digital attenuator to 0dB; set the Q-channel digital attenuator to 63.5dB, and adjust the I-channel digital capacitor array until the phase of the I-channel low-pass network is satisfy , record the control word of the digitally adjustable capacitor array as CCW_I_L at this time.

7. The implementation method according to claim 2, wherein: Switch the Q-path switch to the low-pass phase-shift network; set the Q-path digital attenuator to 0dB; set the I-path digital attenuator to 63.5dB, and adjust the Q-path digital attenuator capacitors until the phase of the Q-path low-pass network is satisfy , record the control word of the digital capacitor array at this time as CCW_Q_L.

8. The implementation method according to claim 2, wherein: Switch the I-way switch to the high-pass phase-shift network; set the I-way digital attenuator to 0dB; set the Q-way digital attenuator to 63.5dB, and adjust the I-way digital capacitor array until the phase of the I-way high-pass network is satisfy , record the control word of the digitally adjustable capacitor array at this time as CCW_I_H.

9. The implementation method according to claim 2, wherein: Switch the Q-path switch to the high-pass phase-shift network; set the Q-path digital attenuator to 0dB; set the I-path digital attenuator to 63.5dB, and adjust the Q-path digital attenuator capacitors until the phase of the Q-path high-pass network is satisfy , record the control word of the digitally adjustable capacitor array at this time as CCW_Q_H.

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