Semiconductor structure and manufacturing method thereof

Abstract

The present application discloses a semiconductor structure and a method for manufacturing the same, in which word lines and bit lines in the semiconductor structure are crossed, and the bit lines are arranged in a zigzag shape, so that vertical transistors arranged at the crossing positions are arranged in a hexagonal dense stack, reducing the proportion of useless area and avoiding area waste, thereby solving the problem that the cross array of the square structure formed in the manufacturing method of the prior art does not have the highest area efficiency when manufacturing storage capacitors.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the current 4F2 DRAM manufacturing method for vertical transistors, word lines and bit lines cross each other perpendicularly, forming silicon pillars at the intersections on which transistors and storage capacitors are fabricated. The resulting array is a square structure, but the square structure does not have the highest area efficiency when making storage capacitors. Summary of the Invention

[0003] An embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, in which word lines and bit lines in the semiconductor structure are crossed to increase storage density.

[0004] A first aspect of an embodiment of the present application provides a semiconductor structure, including:

[0005] substrate;

[0006] a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines located on the substrate;

[0007] The bit lines are bent in a sawtooth shape, with a first angle between adjacent bending line segments, and each bit line has at least one first angle. The bit lines intersect with the word lines to form a second angle.

[0008] In an exemplary embodiment, the second angle ranges from 50 to 70 degrees.

[0009] In an exemplary embodiment, the second angle is 60 degrees.

[0010] In an exemplary embodiment, the number of word line bars crossed by each bending line segment is L, and L is greater than or equal to 2 and less than or equal to 10.

[0011] In an exemplary embodiment, the period of the word line is 35 nm to 45 nm, and L is equal to 10.

[0012] In an exemplary embodiment, the method further includes: a vertical transistor, which is arranged at the intersection of the word line and the bit line, wherein a lower end of the vertical transistor is connected to the bit line, and a channel region of the vertical transistor is connected to the word line.

[0013] A second aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0014] include:

[0015] providing a substrate;

[0016] forming a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines on the substrate;

[0017] The bit lines are bent in a sawtooth shape, with a first angle between adjacent bending line segments, and each bit line has at least one first angle. The bit lines intersect with the word lines to form a second angle.

[0018] In one exemplary embodiment, forming a plurality of mutually parallel bit lines on the substrate includes:

[0019] forming a bit line stack on the substrate;

[0020] forming a bent, sawtooth-shaped photoresist bit line pattern on the bit line stack by using a photolithography process;

[0021] The bit line is formed using the photoresist bit line pattern and a SADP or SAQP process.

[0022] In an exemplary embodiment, the period of the word lines is 35 nm to 45 nm, and the number of word line lines crossed by each bending line segment is greater than or equal to 10.

[0023] In one exemplary embodiment, forming a plurality of mutually parallel bit lines on the substrate includes:

[0024] forming a bit line stack on the word line;

[0025] forming a mask layer on the bit line stack;

[0026] forming a first mask pattern on the mask layer;

[0027] The first mask pattern and the word line intersect to form a second angle;

[0028] A second mask pattern is formed on the mask layer, wherein the second mask pattern and the word line intersect to form a second angle, and the first mask pattern and the second mask pattern intersect to form a first angle.

[0029] In one exemplary embodiment, the first mask pattern includes a plurality of first line segments parallel to each other;

[0030] The second mask pattern includes a plurality of second line segments parallel to each other;

[0031] The first line segment and the second line segment have the same size and pitch.

[0032] In an exemplary embodiment, the method for forming the first line segment includes:

[0033] forming a first initial mask pattern on the mask layer, wherein the first initial mask pattern comprises a plurality of first lines parallel to each other;

[0034] forming a first trim mask layer on the first initial mask pattern, wherein the first trim mask layer includes a plurality of first trim lines parallel to each other, and an extending direction of the first trim lines is the same as an extending direction of the word lines;

[0035] The first line is etched using the first trimming line to trim the first line into a plurality of first line segments.

[0036] In an exemplary embodiment, the method for forming the second line segment includes:

[0037] forming a second initial mask pattern on the first line segment, wherein the second initial mask pattern includes a plurality of second lines parallel to each other;

[0038] forming a second trim mask layer on the second initial mask pattern, wherein the second trim mask layer includes a plurality of second trim lines parallel to each other, and an extending direction of the second trim lines is the same as an extending direction of the word lines;

[0039] The second line is etched using the second trimming line to trim the second line into a plurality of second line segments.

[0040] In an exemplary embodiment, the first trimming line and the second trimming line have the same size and pitch.

[0041] In one exemplary embodiment, the first lines or the second lines are formed using a SADP or SAQP process.

[0042] In an exemplary embodiment, the bit line is formed before the word line; and further comprising: forming a vertical transistor on the substrate, the vertical transistor being arranged at the intersection of the word line and the bit line, the bottom end of the vertical transistor being connected to the bit line, and the channel region of the vertical transistor being connected to the word line.

[0043] The embodiment of the present application forms a bent zigzag-shaped bit line, thereby reducing the proportion of useless area and avoiding area waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0045] Figure 1 This is a schematic diagram comparing the storage unit area of ​​a square array structure and a hexagonal close-packed structure in an example;

[0046] Figure 2 This is a schematic diagram of a hexagonal close-packed arrangement structure formed by the digit line and the word line crossing at 60 degrees in an example;

[0047] Figure 3 2 is a schematic diagram of a sawtooth structure in which the bit line and the word line intersect at a second angle and the bit line is bent in an embodiment of the present application;

[0048] Figure 4 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application;

[0049] Figure 5 is a method for forming a bit line in an exemplary embodiment;

[0050] Figures 6-10 is another exemplary embodiment of a method for forming a bit line. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of this application more clearly understood, this application is further described below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely illustrative and are not intended to limit the scope of this application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of this application.

[0052] Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] In the process of manufacturing semiconductor structures, for example, vertical transistors in the DRAM memory cell array area often adopt a square arrangement structure. However, the square arrangement structure does not have the highest area efficiency. Figure 1 As shown in (a), the unit area of ​​the vertical transistor using the quadrilateral arrangement structure is the square of the vertical transistor period (Pitch) P. In some embodiments, the following can be used: Figure 1(b) shows a hexagonal close-packed arrangement. The unit area of ​​the vertical transistor using the hexagonal close-packed arrangement is the vertical transistor period (Pitch) P*P*sin60°. Compared with the square arrangement structure, it can reduce the area occupied by about 14% and improve the density of the memory. The angle of the bit line can be adjusted so that the bit line and the word line intersect to form a second angle, such as 60 degrees. The vertical transistor can be set at the intersection of the word line and the bit line to form a hexagonal close-packed arrangement structure. However, simply making the bit line and the word line intersect to form a 60-degree angle may cause greater area waste. Figure 2 The schematic diagram of the hexagonal close-packed arrangement structure formed by the bit line and the word line crossing 60 degrees is shown. Figure 2 As shown in FIG, four memory arrays are shown. In each memory array, the word lines are connected to word line drivers, and the bit lines are connected to sense amplifiers. The area pointed by the arrow, that is, the area where the word lines and bit lines do not intersect, is the unused area. The unused area S can be calculated by the following formula:

[0054] S=1 / 2*tan30*(Pwl*Nwl) 2

[0055] Where Pwl is the pitch of the word line, and Nwl is the number of word lines. The ratio of the unused area S to the area of ​​a single memory array is:

[0056] tan30*(Pwl*Nwl) / (Pbl*Nbl)

[0057] Where Pbl is the bit line pitch, and Nbl is the number of bit lines. Assuming the word lines and bit lines have the same pitch and number, the unused area S accounts for approximately 58%. Such a high unused area is unacceptable in semiconductor memory design.

[0058] Therefore, in the embodiment of the present application, not only the angle of the bit line needs to be adjusted, but also the routing of the bit line needs to be adjusted to a bent zigzag shape to improve the above problem.

[0059] According to the first embodiment of the present application, Figure 3 As shown, Figure 3 A schematic diagram of a hexagonal close-packed arrangement structure in which the bit lines and word lines directly intersect at a second angle and the bit lines are bent and zigzag is shown in an embodiment of the present application. An embodiment of the present application provides a semiconductor structure comprising:

[0060] substrate;

[0061] a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines located on the substrate;

[0062] The bit lines are bent in a sawtooth shape, with a first angle between adjacent bending line segments, and each bit line has at least one first angle. The bit lines intersect with the word lines to form a second angle.

[0063] In some embodiments, as Figure 5 As shown, the substrate (not shown) may include a silicon substrate, a germanium substrate, a gallium arsenide substrate, a gallium carbide substrate, a silicon-on-insulator (SOI) substrate, etc. For example, a plurality of mutually parallel bit lines 50 may be formed on the substrate. The bit lines 50 are in a meandering sawtooth shape, with first angles 70 formed between adjacent meandering line segments. Each bit line 50 has at least one first angle 70. The bit lines 50 intersect with the word lines 60 to form a second angle 71.

[0064] For example, a plurality of vertical transistors may be disposed on the bit line 50 . The vertical transistors may be arranged in a hexagonal close-packed manner, and the lower ends of the vertical transistors are connected to the bit line 50 .

[0065] For example, a plurality of mutually parallel word lines 60 may be provided, and each word line 60 may connect the channel regions of the vertical transistors on a plurality of bit lines 50 , that is, the vertical transistors may be provided at the intersection of the word lines 50 and the bit lines 60 .

[0066] For example, the top of the vertical transistor may be electrically connected to a memory, such as a capacitive memory, a magnetic memory, a resistive memory, a phase change memory, etc.

[0067] In some embodiments, the second angle 71 ranges from 50 to 70 degrees. For example, the second angle 71 is 60 degrees, so as to facilitate a hexagonal close-packed arrangement.

[0068] In some embodiments, the number of word lines 60 crossed by each meandering line segment in the bit line 50 is L, and L is greater than or equal to 2 and less than or equal to 10. Figure 3 The schematic diagram shows a hexagonal close-packed structure where the bit lines and word lines intersect at 60 degrees and the bit lines are bent in a zigzag shape. In this case, the area ratio of the unused area is:

[0069] [m / L*1 / 2*L*Pwl*(tan30*1 / 2*L*Pwl)*2] / (m*n*Pwl*Pbl)

[0070] Where m is the total number of word lines, n is the total number of bit lines, L is the number of word lines crossed by a single zigzag line, Pwl is the pitch between word lines, and Pbl is the pitch between bit lines. If Pbl = Pwl, then the proportion of unused area is:

[0071] 1 / 2*tan30*L / n

[0072] For example, when n is 1080 and L = 10, the useless area accounts for only 0.2%. The smaller L is, the smaller the useless area is. At this time, the design can greatly reduce the area ratio of the useless area.

[0073] In some embodiments, the pitch of the word line 60 is 35 nm to 45 nm, and L can be equal to 10. In this case, the length of a single meandering line segment can be long enough to form a meandering bit line pattern using a single photolithography process, thereby reducing the difficulty of manufacturing.

[0074] According to a second embodiment of the present application, a method for manufacturing a semiconductor structure is provided. The flowchart of the method is as follows: Figure 4 As shown, the production method includes the steps of:

[0075] providing a substrate;

[0076] forming a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines on the substrate;

[0077] The bit lines are bent in a sawtooth shape, with a first angle between adjacent bending line segments, and each bit line has at least one first angle. The bit lines intersect with the word lines to form a second angle.

[0078] In some embodiments, a plurality of mutually parallel bit lines are formed on a substrate, including: forming a bit line stack on the substrate, where, for example, the bit line stack may include layers of metal tungsten, titanium nitride, and polysilicon sequentially formed on the substrate; forming a bent, sawtooth-shaped photoresist bit line pattern on the bit line stack using a photolithography process; and forming the bit lines using the photoresist bit line pattern and a SADP (self-aligned double patterning) or SAQP (self-aligned quadruple patterning) process. Figure 5 (a)- Figure 5 As shown in (e), when the pitch of the word line is 35nm to 45nm and the number of word lines crossed by each bending line segment is greater than or equal to 10, a single photolithography process can be used to form the following Figure 5 In the photoresist pattern 10 shown in (a), a first sidewall layer 11 is formed on the sidewalls of the photoresist pattern 10 using a process such as atomic layer deposition. The photoresist pattern 10 is removed, and the bitline stacks are etched using the first sidewall layer 11 to form a curved, zigzag-shaped bitline. In other examples, a second sidewall layer 12 can be further formed on the sidewalls of the first sidewall layer 11, and then the first sidewall layer 11 is removed. The bitline stacks are etched using the second sidewall layer 12 to form a curved, zigzag-shaped bitline. The materials of the first sidewall layer 11 and the second sidewall layer 12 may include silicon oxide, etc.

[0079] In some embodiments, as Figures 6-10 As shown, a plurality of mutually parallel bit lines are formed on the substrate, including:

[0080] A bit line stack is formed on the substrate. For example, a stack including metal tungsten, titanium nitride and polysilicon layers is sequentially formed on the substrate.

[0081] A mask layer is formed on the bit line stack. For example, a silicon nitride or silicon oxide layer is formed on the bit line stack by a chemical vapor deposition process.

[0082] A first mask pattern is formed on the mask layer. The first mask pattern 21 intersects the word line to form a second angle. For example, the first mask pattern includes a plurality of mutually parallel first line segments 21. The first line segments 21 can intersect with the subsequently formed word line to form a second angle, which can be 60 degrees. The second angle can be defined as the acute angle formed by the intersection of the first line segments 21 and the word line.

[0083] A second mask pattern is formed on the mask layer. The second mask pattern and the word line intersect to form a second angle. For example, the second mask pattern includes a plurality of mutually parallel second line segments 41. The second line segments 41 can intersect with the subsequently formed word line to form a second angle, which can be 60 degrees. The second angle can be defined as the acute angle formed by the intersection of the second line segments 41 and the word line.

[0084] In some embodiments, the first line segment 21 and the second line segment 21 have the same size and pitch.

[0085] In some embodiments, a method for forming a first line segment includes:

[0086] A first initial mask pattern is formed on the mask layer. The first initial mask pattern includes a plurality of first lines 20 parallel to each other. Figure 6 As shown;

[0087] A first trimming mask layer is formed on the first initial mask pattern. The first trimming mask layer includes a plurality of first trimming lines 30 parallel to each other. Figure 7 As shown, the extending direction of the first trimming line 30 is the same as the extending direction of the word line;

[0088] The first line 20 is etched by using the first trimming line 30 to trim the first line 20 into a plurality of first line segments 21, as shown in FIG. Figure 8 shown.

[0089] In some embodiments, as Figure 9 As shown, the method for forming the second line segment includes:

[0090] forming a second trim mask layer on the first line segment, wherein the second trim mask layer includes a plurality of second trim lines 31 parallel to each other, and an extending direction of the second trim lines 31 is the same as an extending direction of the word line;

[0091] forming a second initial mask pattern on the second trimming mask layer, wherein the second initial mask pattern includes a plurality of second lines 40 parallel to each other;

[0092] The second line 40 is trimmed into a plurality of second line segments 41 using the second trimming line 21 .

[0093] For example, the second trimming line 21 covers the first line segment 21 . When etching with the second line 40 , due to the obstruction of the second trimming line 21 , part of the pattern of the second line 40 will be transferred to the mask layer to form the second line segment 41 .

[0094] In some embodiments, the first trimming line 30 and the second trimming line 31 have the same size and pitch.

[0095] In some embodiments, the first lines or the second lines are formed using a SADP or SAQP process.

[0096] In some embodiments, a plurality of vertical transistors may be disposed on a bit line. The vertical transistors may be arranged in a hexagonal close-packed manner, and the lower ends of the vertical transistors are connected to the bit line.

[0097] In some embodiments, a plurality of mutually parallel word lines may be provided, and each word line may connect the channel regions of the vertical transistors on a plurality of bit lines, that is, the vertical transistors may be provided at the intersection of the word lines and the bit lines.

[0098] In some embodiments, the top of the vertical transistor may be electrically connected to a memory, such as a capacitive memory, a magnetic memory, a resistive memory, a phase change memory, etc.

[0099] In summary, the present application provides a semiconductor structure and a manufacturing method thereof, in which the word lines and bit lines in the semiconductor structure are crossed, and the bit lines are set as zigzag bend lines, so that the vertical transistors set at the intersection position are arranged in a hexagonal dense stack, reducing the proportion of useless area and avoiding area waste.

[0100] It should be understood that the above-mentioned specific embodiments of the present application are merely illustrative or explain the principles of the present application and do not constitute a limitation of the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present application should be included in the scope of protection of the present application. In addition, the claims attached hereto are intended to cover all variations and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

[0101] The steps in the method of the embodiment of the present application can be adjusted in order, combined, or deleted according to actual needs. The modules in the device of the embodiment of the present application can be combined, divided, or deleted according to actual needs.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines on the substrate; The bit lines are in a bent sawtooth shape, with a first angle between adjacent bent line segments, and each bit line has at least one first angle, and the bit lines intersect with the word lines to form a second angle; The step of forming a plurality of bit lines parallel to each other on the substrate comprises: forming a bit line stack on the word line; forming a mask layer on the bit line stack; forming a first mask pattern on the mask layer; The first mask pattern and the word line intersect to form a second angle; forming a second mask pattern on the mask layer, wherein the second mask pattern and the word line intersect to form a second angle, and the first mask pattern and the second mask pattern intersect to form a first angle; The first mask pattern includes a plurality of mutually parallel first line segments, and the second mask pattern includes a plurality of mutually parallel second line segments; the first line segments and the second line segments have the same size and pitch.

2. The production method according to claim 1, characterized in that The period of the word lines is 35 nm to 45 nm, and the number of word lines crossed by each bending line segment is greater than or equal to 10.

3. The production method according to claim 1, characterized in that The method for forming the first line segment includes: forming a first initial mask pattern on the mask layer, wherein the first initial mask pattern comprises a plurality of first lines parallel to each other; forming a first trim mask layer on the first initial mask pattern, wherein the first trim mask layer includes a plurality of first trim lines parallel to each other, and an extending direction of the first trim lines is the same as an extending direction of the word lines; The first line is etched using the first trimming line to trim the first line into a plurality of first line segments.

4. The production method according to claim 3, characterized in that: The method for forming the second line segment includes: forming a second trim mask layer on the first line segment, wherein the second trim mask layer includes a plurality of second trim lines parallel to each other, and an extension direction of the second trim lines is the same as an extension direction of the word line; forming a second initial mask pattern on the second trimming mask layer, wherein the second initial mask pattern includes a plurality of second lines parallel to each other; The second line is trimmed into a plurality of second line segments using the second trimming line.

5. The production method according to claim 4, characterized in that: The first trimming line and the second trimming line have the same size and pitch.

6. The manufacturing method according to claim 4, characterized in that: The first lines or the second lines are formed by using a SADP or SAQP process.

7. The production method according to claim 1, characterized in that: The bit line is formed before the word line; Also includes: A vertical transistor is formed on the substrate. The vertical transistor is arranged at the intersection of the word line and the bit line. The bottom end of the vertical transistor is connected to the bit line, and the channel region of the vertical transistor is connected to the word line.

8. A semiconductor structure, characterized in that include: substrate; a plurality of mutually parallel word lines and a plurality of mutually parallel bit lines located on the substrate; The bit lines are in a bent sawtooth shape, with a first angle between adjacent bent line segments, and each bit line has at least one first angle, and the bit lines intersect with the word lines to form a second angle; Wherein, the semiconductor structure is obtained by the manufacturing method according to any one of claims 1-7.

9. The semiconductor structure according to claim 8, wherein: The second angle ranges from 50 to 70 degrees.

10. The semiconductor structure according to claim 9, wherein: The second angle is 60 degrees.

11. The semiconductor structure according to claim 10, wherein: The number of word lines crossed by each bending line segment is L, and L is greater than or equal to 2 and less than or equal to 10.

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