Chip and method for magnetically shielding a chip

Abstract

The application discloses a chip anti-magnetic packaging method, which comprises the following steps: preparing a magnetic conductive bottom plate array frame and an electrically conductive substrate array frame; the array arrangement mode of the electrically conductive substrate in the electrically conductive substrate array frame is the same as that of the magnetic conductive bottom plate in the magnetic conductive bottom plate array frame; the magnetic conductive bottom plate array frame and the electrically conductive substrate array frame are aligned and connected, so that the electrically conductive substrate and the magnetic conductive bottom plate correspond to each other; a chip is fixedly arranged on each magnetic conductive bottom plate; each magnetic conductive bottom plate is connected with a magnetic conductive top cover, and plastic sealing film material is injected to obtain a packaging assembly; and the packaging assembly is segmented to obtain independent packaging chips. In the application, the magnetic conductive bottom plate array frame and the electrically conductive substrate array frame are obtained, the array arrangement mode of the magnetic conductive bottom plate is the same as that of the electrically conductive substrate, then the magnetic conductive bottom plate array frame and the electrically conductive substrate array frame are aligned and connected, the alignment of a plurality of electrically conductive substrates and a plurality of magnetic conductive bottom plates is realized through one time of alignment, the packaging time is saved, and the packaging efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of magnetic memory technology, and in particular to a chip and its antimagnetic packaging method. Background Technology

[0002] Spin-Transfer Torque-Based Magnetoresistive Random Access Memory (STT-MRAM) is a novel type of non-volatile magnetic memory. For pSTT-MRAM chips, antimagnetic protection against both horizontal and vertical magnetic fields applied to the chip body is required during packaging. Currently, in the antimagnetic packaging process for pSTT-MRAM, the substrate electrically connected to the chip is aligned and bonded to the antimagnetic structure. Because the antimagnetic structure is pre-processed and exists independently, multiple alignment and bonding operations are required for each individual antimagnetic structure's corresponding substrate. This results in a lengthy packaging process, low packaging efficiency, and hinders the mass production of antimagnetic solutions.

[0003] Therefore, how to shorten the packaging time and improve the packaging efficiency should be a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a chip and its antimagnetic packaging method to shorten packaging time and improve packaging efficiency.

[0005] To address the aforementioned technical problems, this application provides a chip antimagnetic packaging method, comprising:

[0006] A magnetically conductive substrate array frame and a conductive substrate array frame are fabricated; the array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetically conductive substrates in the magnetically conductive substrate array frame.

[0007] The magnetic base plate array frame and the conductive substrate array frame are aligned and connected so that the conductive substrate corresponds one-to-one with the magnetic base plate.

[0008] The chip is fixedly mounted on each of the magnetic substrates;

[0009] Each of the magnetic base plates and magnetic top covers is connected and injected with molding compound to obtain a package assembly. The package assembly is then divided to obtain individual packaged chips.

[0010] Optionally, before connecting each of the magnetically conductive base plates to the magnetically conductive top cover, the method further includes:

[0011] The magnetically conductive patches are connected to the two opposite side walls of the magnetically conductive top cover.

[0012] Optionally, connecting the magnetically conductive patch to the two opposite sidewalls of the magnetically conductive top cover includes:

[0013] Adhesive is applied to the surfaces where the magnetic patch and the two sidewalls are connected, so that the magnetic patch is bonded to the two sidewalls.

[0014] Optionally, aligning and connecting the magnetic substrate array frame and the conductive substrate array frame further includes:

[0015] The area in contact between each of the magnetic base plates and the magnetic top cover is etched; the etching width is equal to the first thickness of the sidewall of the magnetic top cover, and the etching depth is less than the thickness of the magnetic base plate.

[0016] Optionally, when the upper surface of the magnetically conductive base plate in the magnetically conductive base plate array frame is a flat surface, after obtaining the magnetically conductive base plate array frame, the process further includes:

[0017] The upper surface of the magnetic base plate is etched to form a groove that matches the magnetic top cover, so that the magnetic top cover can be connected to the magnetic base plate through the groove.

[0018] Optionally, the second thickness of the magnetically conductive top cover corresponding to the recessed area is greater than or equal to 0.2 mm, and the first thickness of the sidewall of the magnetically conductive top cover is greater than or equal to 2 to 3 times the second thickness.

[0019] Optionally, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes:

[0020] Prepare a single magnetically conductive top cover;

[0021] Each of the magnetically conductive top covers is connected to each of the magnetically conductive bottom plates.

[0022] Optionally, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes:

[0023] A magnetically conductive top cover array frame is fabricated; the array arrangement of the magnetically conductive top covers in the magnetically conductive top cover array frame is the same as the array arrangement of the magnetically conductive bottom plate;

[0024] The magnetic top cover array frame is connected to the magnetic bottom plate array frame; the magnetic top cover and the magnetic bottom plate correspond one-to-one.

[0025] Optionally, the fabricated magnetically conductive top cover array frame includes:

[0026] The magnetic top cover array frame was fabricated by etching.

[0027] Optionally, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes:

[0028] Each of the magnetic base plates is connected to the magnetic top cover by welding.

[0029] Optionally, the fabricated magnetic substrate array frame and conductive substrate array frame include:

[0030] The magnetic substrate array frame and the conductive substrate array frame were fabricated by etching.

[0031] Optionally, before aligning and connecting the magnetic substrate array frame and the conductive substrate array frame, the method further includes:

[0032] Alignment marks are made on the magnetic base plate array frame and the conductive substrate array frame, respectively.

[0033] Accordingly, aligning and connecting the magnetic substrate array frame and the conductive substrate array frame includes:

[0034] The magnetic base plate array frame and the conductive substrate array frame are aligned and connected according to the alignment mark.

[0035] This application also provides a packaged chip, which is obtained by any of the above-described antimagnetic chip packaging methods.

[0036] This application provides a chip antimagnetic packaging method, comprising fabricating a magnetic substrate array frame and a conductive substrate array frame; the array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetic substrates in the magnetic substrate array frame; aligning and connecting the magnetic substrate array frame and the conductive substrate array frame so that the conductive substrates correspond one-to-one with the magnetic substrates; fixing the chip on each of the magnetic substrates; connecting each magnetic substrate to a magnetic top cover and injecting molding compound to obtain a package assembly; and dividing the package assembly to obtain individual packaged chips.

[0037] As can be seen, the antimagnetic packaging method in this application first obtains a magnetic substrate array frame and a conductive substrate array frame during packaging. The array arrangement of the magnetic substrates in the magnetic substrate array frame is the same as the array arrangement of the conductive substrates in the conductive substrate array frame. Then, the magnetic substrate array frame and the conductive substrate array frame are aligned and connected so that multiple conductive substrates correspond one-to-one with multiple magnetic substrates. Subsequently, chip fixing and connection, connection of the magnetic top cover to the magnetic substrate, injection of molding compound, and division steps are performed to obtain an independent packaged chip. That is, in this application, the alignment of multiple conductive substrates with multiple magnetic substrates is achieved by aligning the magnetic substrate array frame and the conductive substrate array frame in one step, without the need to align multiple conductive substrates one by one, saving packaging time and improving packaging efficiency.

[0038] In addition, this application also provides a packaged chip. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a chip antimagnetic packaging method provided in this application embodiment;

[0041] Figure 2 This is a schematic diagram of the structure of a magnetically conductive base plate array frame provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of a conductive substrate array frame provided in an embodiment of this application;

[0043] Figure 4 This is a cross-sectional schematic diagram of the magnetically conductive top cover provided in an embodiment of this application;

[0044] Figure 5 A schematic diagram showing the connection of a magnetically conductive patch to the side wall of the magnetically conductive top cover;

[0045] Figure 6 A flowchart illustrating another antimagnetic chip packaging method provided in this application embodiment;

[0046] Figure 7 This is a schematic diagram of the structure of a magnetically conductive base plate provided in an embodiment of this application;

[0047] Figure 8 This is a schematic diagram of the structure of a magnetically conductive base plate and a magnetically conductive top cover connected according to an embodiment of this application;

[0048] Figure 9 A flowchart illustrating another antimagnetic chip packaging method provided in this application embodiment;

[0049] Figure 10 This is a schematic diagram of another magnetically conductive base plate provided in an embodiment of this application;

[0050] Figure 11 This is a schematic diagram of another connection between a magnetically conductive base plate and a magnetically conductive top cover provided in an embodiment of this application.

[0051] Figures 12 to 15 This is a schematic diagram of the chip structure provided in this application. Detailed Implementation

[0052] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0054] As described in the background section, in the current process of antimagnetic packaging of pSTT-MRAM, when the substrate that is electrically connected to the chip is aligned and bonded to the antimagnetic structure, since the antimagnetic structure is pre-processed and exists in an independent state, it is necessary to align and bond the substrate corresponding to each independent antimagnetic structure, which results in a long packaging process and low packaging efficiency.

[0055] In view of this, this application provides a chip antimagnetic packaging method, please refer to... Figure 1 , Figure 1 A flowchart of a chip antimagnetic packaging method provided in this application embodiment, the method including:

[0056] Step S101: A magnetic substrate array frame and a conductive substrate array frame are obtained; the array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetic substrates in the magnetic substrate array frame.

[0057] In the magnetic substrate array frame, the magnetic substrates can be arranged in an m×n array. This application does not specify the exact values ​​of m and n, but rather determines them depending on the circumstances. Similarly, in the conductive substrate array frame, the conductive substrates are also arranged in an m×n array.

[0058] Taking an example where both m and n are 2, the structural schematic diagram of the magnetic substrate array frame is as follows: Figure 2 As shown, the magnetic substrate array frame 1' includes four magnetic substrates 1, and the structural schematic diagram of the conductive substrate array frame is shown below. Figure 3 As shown, the conductive substrate array frame 2' includes four conductive substrates 2.

[0059] Optionally, as one embodiment, the fabrication of the magnetically conductive substrate array frame and the conductive substrate array frame includes: fabricating the magnetically conductive substrate array frame and the conductive substrate array frame by etching. However, this application does not specifically limit this; in other embodiments, the fabrication of the magnetically conductive substrate array frame and the conductive substrate array frame includes: fabricating the magnetically conductive substrate array frame and the conductive substrate array frame by stamping technology.

[0060] It should be noted that this application does not limit the material of the magnetically conductive base plate, and it can be set by the user. For example, the material of the magnetically conductive base plate can be a soft magnetic material or a composite material composed of a soft magnetic material / medium, and the material type includes, but is not limited to, silicon steel with high iron content, permalloy, etc.

[0061] Step S102: Align and connect the magnetic base plate array frame and the conductive substrate array frame so that the conductive substrate corresponds one-to-one with the magnetic base plate.

[0062] The connection methods between the magnetic base plate array frame and the conductive substrate array frame include, but are not limited to, adhesive bonding and welding.

[0063] Step S103: Fix the chip onto each of the magnetic substrates.

[0064] It should be noted that this application does not limit the type of chip; any chip that needs to shield against static magnetic fields is acceptable.

[0065] Furthermore, this application does not limit the method by which the chip is mounted on the magnetic substrate, such as adhesive bonding, soldering, etc.

[0066] It should be noted that when the chip is a storage chip in a sub-random access memory, after the storage chip is fixed, it is necessary to perform operations such as wire bonding. The process of fixing the storage chip and wire bonding is well known to those skilled in the art, and will not be described in detail here.

[0067] The conductive substrate has pins distributed on it, which are electrically connected to the chip via wires and solder joints. The solder joints, which are aligned with the conductive substrate array frame, facilitate the creation of a near-closed magnetic loop. Optionally, for chip designs with solder joints distributed on all four sides, the method of using flip-chip or multilayer substrate wiring is not limited to meeting the needs of electrical signal connection.

[0068] Step S104: Connect each of the magnetic base plates to the magnetic top cover and inject molding film material to obtain a package assembly, and divide the package assembly to obtain an independent package chip.

[0069] The connection methods between the magnetic base plate and the magnetic top cover include, but are not limited to, adhesive bonding and welding.

[0070] The magnetically conductive top cover has an upward indentation, and a cross-sectional schematic diagram of the magnetically conductive top cover 3 is shown below. Figure 4 As shown, the recess corresponds to the chip position when connected to the magnetically conductive base plate. The second thickness b of the portion of the magnetically conductive top cover corresponding to the recessed area is greater than or equal to 0.2 mm, and the first thickness a of the sidewall of the magnetically conductive top cover is greater than or equal to 2 to 3 times the second thickness b, in order to improve the antimagnetic performance.

[0071] The material of the magnetically conductive top cover can be a soft magnetic material or a composite material composed of a soft magnetic material / medium. The material types include, but are not limited to, silicon steel with high iron content, permalloy, etc. When the magnetically conductive base plates in the magnetically conductive base plate array frame are arranged in an m×n array, the resulting package assembly includes m×n arrayed chips, which can be divided to obtain m×n individual chips.

[0072] The routine operations of performing quality checks on individual chips after segmentation are well known to those skilled in the art and will not be described in detail here.

[0073] In one specific embodiment, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes: connecting each of the magnetically conductive base plates to the magnetically conductive top cover by welding. However, this application does not specifically limit this; in other embodiments, adhesive bonding can also be used to connect each of the magnetically conductive base plates to the magnetically conductive top cover.

[0074] The antimagnetic packaging method in this application first obtains a magnetic substrate array frame and a conductive substrate array frame during packaging. The array arrangement of the magnetic substrates in the magnetic substrate array frame is the same as the array arrangement of the conductive substrates in the conductive substrate array frame. Then, the magnetic substrate array frame and the conductive substrate array frame are aligned and connected so that multiple conductive substrates correspond one-to-one with multiple magnetic substrates. Subsequently, chip fixing, connecting the magnetic top cover to the magnetic substrate, injecting molding film material, and dividing steps are performed to obtain an independent packaged chip. That is, in this application, the alignment of multiple conductive substrates with multiple magnetic substrates is achieved in one alignment of the magnetic substrate array frame and the conductive substrate array frame, eliminating the need to align multiple conductive substrates one by one, saving packaging time and improving packaging efficiency.

[0075] The following describes the different ways in which the magnetic base plate and the magnetic top cover are connected to form the encapsulated assembly.

[0076] Optionally, in one embodiment of this application, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes:

[0077] Prepare a single magnetically conductive top cover;

[0078] Each of the magnetically conductive top covers is connected to each of the magnetically conductive bottom plates.

[0079] The individual magnetic top cover can be manufactured by metalworking, casting, or other methods, and this application does not limit the methods.

[0080] Optionally, in another embodiment of this application, connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes:

[0081] A magnetically conductive top cover array frame is fabricated; the array arrangement of the magnetically conductive top covers in the magnetically conductive top cover array frame is the same as the array arrangement of the magnetically conductive bottom plate;

[0082] The magnetic top cover array frame and the magnetic bottom plate array frame are connected to form an encapsulation assembly; the magnetic top cover and the magnetic bottom plate correspond one-to-one.

[0083] The magnetic top cover array frame includes multiple magnetic top covers. When the magnetic bottom plates in the magnetic base plate array frame are arranged in an m×n array, the magnetic top covers in the magnetic top cover array frame are also arranged in an m×n array.

[0084] It should be noted that this application does not limit the manufacturing method of the magnetic top cover array frame, and the method can be chosen freely. For example, the magnetic top cover array frame can be manufactured by etching, or by stamping, etc.

[0085] Based on the above embodiments, in one embodiment of this application, before connecting each of the magnetically conductive base plates and the magnetically conductive top cover to obtain the encapsulation assembly, the method further includes:

[0086] The magnetically conductive patches are connected to the two opposite side walls of the magnetically conductive top cover.

[0087] like Figure 5 As shown, the magnetic patch 4 can increase the thickness of the sidewall of the magnetic top cover 3, thereby increasing the ratio of the sidewall thickness after connecting the magnetic patch to the top length of the magnetic top cover. This effectively improves the antimagnetic performance without reducing the vertical wiring space. The second thickness of the portion of the magnetic top cover corresponding to the recessed area is greater than or equal to 0.2 mm, and the first thickness of the sidewall of the magnetic top cover is greater than or equal to 2 to 3 times the second thickness to improve the antimagnetic performance.

[0088] This application does not limit the connection method between the magnetic patch and the sidewall of the magnetic top cover; any method can be chosen. For example, connecting the magnetic patch to the two opposite sidewalls of the magnetic top cover includes: applying adhesive to the surfaces where the magnetic patch and the two sidewalls connect, thereby adhering the magnetic patch to the two sidewalls. Alternatively, welding can be used to connect the magnetic patch to the sidewall of the magnetic top cover.

[0089] Please refer to Figure 6 , Figure 6A flowchart of another chip antimagnetic packaging method provided in this application includes:

[0090] Step S201: A magnetic substrate array frame and a conductive substrate array frame are obtained; the array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetic substrates in the magnetic substrate array frame.

[0091] Step S202: Align and connect the magnetic base plate array frame and the conductive substrate array frame so that the conductive substrate corresponds one-to-one with the magnetic base plate.

[0092] Step S203: Etch the area in contact between each of the magnetic base plates and the magnetic top cover; the etching width is equal to the first thickness of the sidewall of the magnetic top cover, and the etching depth is less than the thickness of the magnetic base plate.

[0093] A schematic diagram of the area where the magnetic base plate 1 contacts the magnetic top cover after etching is shown below. Figure 7 As shown in the diagram, the structural schematic diagram of the connection between the magnetic base plate 1 and the magnetic top cover 3 at this time is as follows. Figure 8 As shown.

[0094] Step S204: Fix the chip onto each of the magnetic substrates.

[0095] Step S205: Connect each of the magnetic base plates to the magnetic top cover and inject molding film material to obtain a package assembly, and divide the package assembly to obtain an independent package chip.

[0096] In this embodiment, the second thickness of the corresponding recessed area of ​​the magnetic top cover is greater than or equal to 0.2 mm, and the first thickness of the sidewall of the magnetic top cover is greater than or equal to 2 to 3 times the second thickness, so as to improve the antimagnetic performance.

[0097] In this embodiment, the area in contact between the magnetic base plate and the magnetic top cover is etched to increase the contact area between the magnetic base plate and the magnetic top cover, reduce magnetic leakage in the contact area between the magnetic base plate and the magnetic top cover, and further improve the packaging efficiency.

[0098] Please refer to Figure 9 , Figure 9 A flowchart of another chip antimagnetic packaging method provided in this application includes:

[0099] Step S301: A magnetic base plate array frame and a conductive substrate array frame are obtained; the array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetic base plates in the magnetic base plate array frame, and the upper surface of the magnetic base plate in the magnetic base plate array frame is a flat surface.

[0100] Step S302: Etch the upper surface of the magnetic base plate to form a groove that matches the magnetic top cover, so that the magnetic top cover can be connected to the magnetic base plate through the groove.

[0101] The schematic diagram after the groove is etched into the magnetic base plate 1 in this step is shown below. Figure 10 As shown in the diagram, the structural schematic diagram of the connection between the magnetic base plate 1 and the magnetic top cover 3 at this time is as follows. Figure 11 As shown, the magnetic top cover 3 is embedded in the groove and connected to the magnetic base plate 1. The groove width d must be greater than the top length w of the magnetic top cover 3. Preferably, the groove width is less than a preset width threshold, which is the top length of the magnetic top cover plus 0.02mm. This increases the contact area between the magnetic base plate and the magnetic top cover, reduces magnetic leakage in the contact area, and further improves the packaging efficiency.

[0102] The second thickness of the portion of the magnetically conductive top cover corresponding to the recessed area is greater than or equal to 0.2 mm, and the first thickness of the sidewall of the magnetically conductive top cover is greater than or equal to 2 to 3 times the second thickness, so as to improve the antimagnetic performance.

[0103] Step S303: Align and connect the magnetic base plate array frame and the conductive substrate array frame so that the conductive substrate corresponds one-to-one with the magnetic base plate.

[0104] Step S304: Fix the chip on each of the magnetic substrates.

[0105] Step S305: Connect each of the magnetic base plates to the magnetic top cover and inject molding film material to obtain a package assembly, and divide the package assembly to obtain an independent package chip.

[0106] To improve the speed and accuracy of aligning and connecting the magnetic base plate array frame and the conductive substrate array frame, in one embodiment of this application, based on any of the above embodiments, the method further includes the following before aligning and connecting the magnetic base plate array frame and the conductive substrate array frame:

[0107] Alignment marks are made on the magnetic base plate array frame and the conductive substrate array frame, respectively.

[0108] Accordingly, aligning and connecting the magnetic substrate array frame and the conductive substrate array frame includes:

[0109] The magnetic base plate array frame and the conductive substrate array frame are aligned and connected according to the alignment mark.

[0110] The alignment markings include, but are not limited to, single holes, combination holes, single slots, or combination slots.

[0111] This application also provides a packaged chip, which is obtained by the antimagnetic packaging method of the chip described in any of the above embodiments.

[0112] The schematic diagram of the chip structure is as follows: Figures 12 to 15 As shown, it includes a magnetically conductive top cover 3, a chip 5, a magnetically conductive bottom plate 1, and a conductive substrate 2. Figure 13 The chip also includes a magnetically conductive patch 4.

[0113] To ensure the chip achieves a magnetic diffusivity greater than 50%@10000e, the thickness of the top of the magnetic top cover and the thickness of the magnetic bottom plate can be selected as 0.3mm.

[0114] To ensure the chip achieves a diamagnetic efficiency greater than 70% at 12000e, the thickness of the top of the magnetically conductive top cover and the magnetically conductive base plate can be selected as 0.3mm, and the thickness of the sidewall of the magnetically conductive top cover can be selected as 0.9mm. When the thickness of the magnetically conductive sidewall is three times that of the magnetically conductive top cover, the diamagnetic efficiency is improved by 20% to 30% compared to a structure of the same thickness.

[0115] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0116] The chip and its packaging method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method of magnetically shielding a chip, characterized by, include: A magnetically conductive substrate array frame and a conductive substrate array frame were fabricated. The array arrangement of the conductive substrates in the conductive substrate array frame is the same as the array arrangement of the magnetic base plate in the magnetic base plate array frame. The magnetic base plate array frame and the conductive substrate array frame are aligned and connected so that the conductive substrate corresponds one-to-one with the magnetic base plate. The chip is fixedly mounted on each of the magnetic substrates; Each of the magnetic base plates and magnetic top covers is connected and injected with molding compound to obtain a package assembly. The package assembly is then divided to obtain individual packaged chips. Before connecting each of the magnetically conductive base plates to the magnetically conductive top cover, the method further includes: Connect the magnetically conductive patches to the two opposite sidewalls of the magnetically conductive top cover; The step of connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes: A magnetically conductive top cover array frame is fabricated; the array arrangement of the magnetically conductive top covers in the magnetically conductive top cover array frame is the same as the array arrangement of the magnetically conductive bottom plate; The magnetic top cover array frame is connected to the magnetic bottom plate array frame; the magnetic top cover and the magnetic bottom plate correspond one-to-one.

2. The chip antimagnetic packaging method as described in claim 1, characterized in that, The process of connecting the magnetically conductive patch to the two sidewalls opposite to the magnetically conductive top cover includes: Adhesive is applied to the surfaces where the magnetic patch and the two sidewalls are connected, so that the magnetic patch is bonded to the two sidewalls.

3. The chip antimagnetic packaging method as described in claim 1, characterized in that, The step of aligning and connecting the magnetically conductive base plate array frame and the conductive substrate array frame further includes: The area in contact between each of the magnetic base plates and the magnetic top cover is etched; the etching width is equal to the first thickness of the sidewall of the magnetic top cover, and the etching depth is less than the thickness of the magnetic base plate.

4. The chip antimagnetic packaging method as described in claim 1, characterized in that, When the upper surface of the magnetically conductive base plate in the magnetically conductive base plate array frame is a flat surface, the process of fabricating the magnetically conductive base plate array frame further includes: The upper surface of the magnetic base plate is etched to form a groove that matches the magnetic top cover, so that the magnetic top cover can be connected to the magnetic base plate through the groove.

5. The chip antimagnetic packaging method as described in claim 4, characterized in that, The second thickness of the portion of the magnetically conductive top cover corresponding to the recessed area is greater than or equal to 0.2 mm, and the first thickness of the sidewall of the magnetically conductive top cover is greater than or equal to 2 to 3 times the second thickness.

6. The chip antimagnetic packaging method as described in claim 1, characterized in that, The fabricated magnetically conductive top cover array frame includes: The magnetic top cover array frame was fabricated by etching.

7. The chip antimagnetic packaging method as described in claim 1, characterized in that, The step of connecting each of the magnetically conductive base plates to the magnetically conductive top cover includes: Each of the magnetic base plates is connected to the magnetic top cover by welding.

8. The chip antimagnetic packaging method as described in claim 1, characterized in that, The fabricated magnetically conductive substrate array frame and conductive substrate array frame include: The magnetic substrate array frame and the conductive substrate array frame were fabricated by etching.

9. The chip antimagnetic packaging method according to any one of claims 1 to 8, characterized in that, Before aligning and connecting the magnetic substrate array frame and the conductive substrate array frame, the method further includes: Alignment marks are made on the magnetic base plate array frame and the conductive substrate array frame, respectively. Accordingly, aligning and connecting the magnetic substrate array frame and the conductive substrate array frame includes: The magnetic base plate array frame and the conductive substrate array frame are aligned and connected according to the alignment mark.

10. A packaged chip, characterized in that, The packaged chip is obtained by the antimagnetic chip packaging method as described in any one of claims 1 to 9.

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