Display control method, display control device, and display device

Abstract

The display control method comprises: performing a first display mode using input image data. The first display mode comprises: rearranging the input image data to obtain rearranged image data, wherein the input image data comprises an effective row part for actual display on a display panel and an ineffective row part for non-actual display on the display panel, and the rearranged image data comprises a rearranged effective row part and a rearranged ineffective row part corresponding to the effective row part and the ineffective row part respectively; generating a first image display control signal and a first delay control signal corresponding to the rearranged image data; and outputting the rearranged image data, the first image display control signal and the first delay control signal for display operation on the display panel. The display control method can increase the applicable scenarios of the display and save costs.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a display control method, a display control device and a display device. BACKGROUND

[0002] Currently, with the development of outdoor or indoor advertising business, for example, a large number of screens are widely used, and long strip screens are widely used as advertising display screens. In addition, the current screen use scene also becomes rich, and diversified screen forms such as spliced screens, electronic whiteboards and reflective display screens gradually appear. SUMMARY

[0003] Some embodiments of the present disclosure provide a display control method, comprising: performing a first display mode using input image data, wherein the first display mode comprises: rearranging the input image data to obtain rearranged image data, wherein the input image data comprises an effective row part for actual display on a display panel and an ineffective row part for non-actual display on the display panel, and the rearranged image data comprises a rearranged effective row part and a rearranged ineffective row part corresponding to the effective row part and the ineffective row part, respectively; generating a first image display control signal and a first delay control signal corresponding to the rearranged image data; and outputting the rearranged image data, the first image display control signal and the first delay control signal for display operation on the display panel, wherein the first image display control signal is used for frame display corresponding to the rearranged image data during the display operation, and the first delay control signal is used for triggering a row scanning process of the rearranged effective row part in the display panel during the frame display.

[0004] For example, in the display control method provided by some embodiments of the present disclosure, rearranging the input image data to obtain the rearranged image data comprises: performing an overall inversion rearrangement operation on the input image data to obtain the rearranged image data, wherein the first delay control signal is obtained according to the position of the rearranged effective row part in the rearranged image data, or the first delay control signal is obtained by presetting.

[0005] For example, the display control method provided by some embodiments of the present disclosure further comprises: obtaining a display control instruction; and selecting to perform the first display mode or to perform a second display mode in response to the display control instruction, wherein the second display mode is different from the first display mode.

[0006] For example, in the display control method provided by at least some embodiments of the present disclosure, the second display mode includes: generating the second image display control signal corresponding to the input image data, wherein the second image display control signal is used for frame display corresponding to the input image data in the display operation; and outputting the input image data and the second image display control signal for display operation of the display panel.

[0007] For example, in the display control method provided by at least some embodiments of the present disclosure, the display control instruction is obtained by reading an input port of a display system to which the display panel belongs and obtaining the display control instruction according to different states of the input port.

[0008] For example, in the display control method provided by at least some embodiments of the present disclosure, the display system includes a first executable code corresponding to the first display mode and a second executable code corresponding to the second display mode, and the selection of the first display mode or the second display mode in response to the display control instruction includes: selecting the execution of the first executable code or the second executable code according to the display control instruction.

[0009] For example, in the display control method provided by at least some embodiments of the present disclosure, in the first display mode, the display panel is in an inverted state relative to a reference position; and in the second display mode, the display panel is in a normal state relative to the reference position.

[0010] For example, in the display control method provided by at least some embodiments of the present disclosure, the display panel includes a gate drive circuit for implementing the row scanning process, and the first delay control signal is used to generate a scanning start signal of the gate drive circuit.

[0011] For example, the display control method provided by at least some embodiments of the present disclosure further includes: receiving and storing the input image data.

[0012] The display control apparatus includes an image processing module, a timing generation module, a delay processing module, and an output circuit. The image processing module is configured to rearrange received input image data to obtain rearranged image data, wherein the input image data includes an effective row portion for actual display on a display panel and an ineffective row portion for non-actual display on the display panel, and the rearranged image data includes a rearranged effective row portion and a rearranged ineffective row portion corresponding to the effective row portion and the ineffective row portion, respectively. The timing generation module is configured to generate a first image display control signal corresponding to the rearranged image data, wherein the first image display control signal is used for frame display corresponding to the rearranged image data during the display operation. The delay processing module is configured to generate a first delay control signal corresponding to the rearranged image data, wherein the first delay control signal is used to trigger a row scanning process of the rearranged effective row portion in the display panel during the frame display. The output circuit is configured to output the rearranged image data, the first image display control signal, and the first delay control signal for display operation on the display panel.

[0013] For example, in the display control apparatus provided by at least some embodiments of the present disclosure, the image processing module includes an image data rearrangement circuit, wherein the image data rearrangement circuit is configured to perform an overall inversion rearrangement operation on the input image data to obtain the rearranged image data.

[0014] For example, in the display control apparatus provided by at least some embodiments of the present disclosure, the first delay control signal is obtained according to the position of the rearranged effective row portion in the rearranged image data, or the first delay control signal is obtained by a preset.

[0015] For example, in the display control apparatus provided by at least some embodiments of the present disclosure, the delay processing module includes a gate signal timing adjustment module, wherein the gate signal timing adjustment module is configured to set the first delay control signal to be later than the first image display control signal by a predetermined time, wherein the predetermined time is obtained according to the position of the rearranged effective row portion in the rearranged image data, or the predetermined time is obtained by the preset.

[0016] For example, the display control apparatus provided by at least some embodiments of the present disclosure further includes a control apparatus, wherein the control apparatus is configured to select to perform the first display mode or a second display mode in response to a display control instruction, wherein the second display mode is different from the first display mode, and the first display mode includes performing display operation on the display panel using the rearranged image data, the image display control signal, and the first delay control signal.

[0017] For example, in the display control apparatus provided by at least some embodiments of the present disclosure, the timing generation module is further configured to generate a second image display control signal corresponding to the input image data, wherein the second image display control signal is used for frame display corresponding to the input image data in the display operation; the second display mode comprises using the input image data and the image display control signal to perform display operation on the display panel; and the output circuit is further configured to output the input image data and the second image display control signal for performing display operation in the second display mode on the display panel.

[0018] For example, the display control apparatus provided by at least some embodiments of the present disclosure further comprises a second storage apparatus, wherein the second storage apparatus is configured to store a first executable code corresponding to the first display mode and a second executable code corresponding to the second display mode, and the display control apparatus is further configured to, in response to the display control instruction indicating, select to execute the first executable code or the second executable code according to the display control instruction.

[0019] For example, the display control apparatus provided by at least some embodiments of the present disclosure further comprises an input port, wherein the input port is configured to obtain the display control instruction according to different states of the input port.

[0020] For example, the display control apparatus provided by at least some embodiments of the present disclosure further comprises a first storage apparatus, wherein the first storage apparatus is configured to store the received input image data.

[0021] At least some embodiments of the present disclosure further provide a display apparatus, comprising the display control apparatus of any of the above and a display panel.

[0022] For example, in the display apparatus provided by at least some embodiments of the present disclosure, the display panel comprises a gate drive circuit, a data drive circuit and a pixel array. The gate drive circuit is configured to receive a scan control signal to scan the pixel array; the data drive circuit is configured to receive an image data signal and provide the image data signal to the pixel array; and the pixel array is configured to receive the image data from the data drive circuit for display operation under the control of the gate drive circuit. The first image display control signal comprises the scan control signal, and the image data signal comprises the rearranged image data. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0024] Figure 1 is a schematic diagram of a display process of a bar display;

[0025] Figure 2 is a schematic diagram of a display process of an inverted bar display;

[0026] Figure 3 is a structural schematic diagram of a display panel device;

[0027] Figure 4 is a schematic diagram of a gate drive circuit;

[0028] Figure 5A is a structural schematic diagram of a shift register;

[0029] Figure 5B is a timing diagram of the shift register in Figure 5A

[0030] Figure 6 is a flowchart of a display driving method provided by an embodiment of the present disclosure;

[0031] Figure 7A is an exemplary input image;

[0032] Figure 7B is a rearranged image after rearranging the input image of Figure 7A

[0033] Figure 7C is a timing diagram of a delay processing of the display driving method provided by an embodiment of the present disclosure;

[0034] Figure 8 is a flowchart of a display driving method provided by another embodiment of the present disclosure;

[0035] Figure 9 is a schematic diagram of a display driving device provided by an embodiment of the present disclosure;

[0036] Figure 10 is a schematic diagram of a display driving device provided by another embodiment of the present disclosure; and

[0037] Figure 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] ​​In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings for the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0039] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include", "contain", and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, without excluding other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0040] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of known functions and known components can be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0041] Under the current display driving mode, the input image data of a long strip display (or display screen) is usually still in full-frame specifications. The full-frame specifications include, for example, standard definition (480*320, 640*480), high definition (1024*720p, 1920*1080i), full high definition (1920*1080p), ultra high definition (3840*2160, 7680*4320), and the like.

[0042] Figure 1 is a schematic diagram of a display process of a strip display. As shown in FIG. 1, the display process of the strip display includes the following steps. Figure 1As shown, the input image data input to the bar display can be acquired from a storage device (e.g. a hard disk) or received from a receiving device (e.g. a modem), for example, the input image data can be of a size of 1920*1080. The bar display has a resolution of 1920*360, for example, and includes a timing controller (TCON). The size of the input image data in the column direction (i.e. the number of rows) is greater than the size of the image actually displayed by the bar display in the column direction, so only a part of the input image data is displayed in the bar display, which can be referred to as the valid row part, and the rest is the invalid row part. However, it should be noted that the "invalid row part" can also have substantial image content, and embodiments of the present disclosure do not limit this. For example, the invalid row part can be a valid row part for display on another display panel. For example, for a spliced screen, different valid row parts can be spliced together to form a complete image on the spliced screen, and for a display panel of a splicing unit of the spliced screen, the corresponding invalid part can be a valid part of a display panel of another splicing unit.

[0043] For example, the timing controller generates timing control signals for controlling the display panel to display according to the input image data. The TCON provides the input image data and the generated timing control signals to the bar display, and the bar display displays according to the timing control signals and the input image data. For example, the first 360 rows of the input image data, which are the valid row part (the part indicated by the upward arrow in the figure), can be normally displayed by the bar display, while the remaining 361st to 1080th rows (a total of 720 rows) of the invalid row part are not displayed on the bar display (indicated by the dashed part in the figure). Moreover, the timing control signals corresponding to the invalid row part will not actually drive the bar display, and during the corresponding time period, the bar display is not refreshed and remains to display the image part corresponding to the aforementioned valid row part.

[0044] Figure 2 is a schematic diagram of the display process of a bar display in an inverted state. Compared with Figure 1 , Figure 2 the difference is only that the bar display is placed in an inverted state, for example, the bar display is inadvertently inverted during installation, or in some application scenarios, the bar display is intentionally inverted according to the needs of use. For example, the gate signal scanning direction of the gate driver of the bar display is fixed, and if the bar display is used in an inverted state, the picture displayed on the bar display will be inverted, as shown in Figure 2 . At this time, if inverted image data is input to the bar display described above, the invalid row part in the original input image data will be displayed in the bar display, and normal display cannot be achieved.

[0045] Figure 3 is a structural schematic diagram of a display panel device. For example, Figure 1 or Figure 2 The display panel in the bar display in Figure 3 may be as shown in Figure 3 . As shown in , the display panel device 1 includes an array substrate 11, a gate driver 12, a timing controller 13 and a data driver 14, and the array substrate 11 is electrically connected with the gate driver 12, the timing controller 13 and the data driver 14. The array substrate 11 includes a pixel array, the pixel array includes a plurality of rows and a plurality of columns of pixel units, each pixel unit is used to realize the display of one sub-pixel, and the array substrate 11 further includes a plurality of scan lines GL and a plurality of data lines DL, the plurality of scan lines GL respectively provide gate signals for the plurality of rows of pixel units, and the plurality of data lines DL respectively provide data signals for the plurality of rows of pixel units. The gate driver 12 is connected with the plurality of scan lines GL, and is used to provide a gate scanning signal to drive the plurality of scan lines GL. The data driver 14 is connected with the plurality of data lines DL, and is used to provide a data signal to drive the plurality of data lines DL. The timing controller 13 is used to process image data RGB input from outside the display panel device 1, provide the processed image data RGB, a row data start signal (STH), a data clock signal (CPH) or a data output signal (TP) to the data driver 14, and output a frame start trigger signal STV, one or more clock signals CLK, a reset signal RST and the like to the gate driver 12 and the data driver 14, so as to control the gate driver 12 and the data driver 14, so that the pixel array can display the image data RGB row by row or line by line in a manner such as row-by-row scanning or interlaced scanning.

[0046] Figure 4 is a schematic diagram of a gate drive circuit. Figure 3 The gate driver 12 in Figure 4 may be implemented as the gate drive circuit shown in , but is not limited to this gate drive circuit, and can also be other types of gate drive circuits.

[0047] As shown in Figure 4 , the gate drive circuit 20 includes a plurality of cascaded shift register units 10. As shown in Figure 4 , each shift register unit 10 includes a plurality of shift register stages 100, and each shift register stage 100 includes a plurality of shift register units 101.As shown, except for the first-stage shift register unit, the input terminal INPUT of each of the remaining shift register units is connected to the first output terminal OUTPUT of the previous-stage shift register unit. Except for the last-stage shift register unit, the reset terminal RESET of each of the remaining shift register units is connected to the first output terminal OUTPUT of the next-stage shift register unit. For example, the input terminal INPUT of the first-stage shift register unit can be configured to receive the trigger signal STV, and the reset terminal RESET of the last-stage shift register unit can be configured to receive the reset signal RST.

[0048] like Figure 4 As shown, each shift register unit is configured to output a corresponding gate scan signal in response to a clock signal CLK. The clock signal CLK may include, for example, different clock signals CLK1 and CLK2. The timing controller 30 is configured to provide one or more clock signals CLK to each shift register unit, and the timing controller 30 may also be configured to provide a trigger signal STV and a reset signal RST. Figure 4 In this embodiment, the timing controller 30 provides two different clock signals to each shift register unit through two clock signal lines. In other cases, the timing controller 30 may also be configured to provide four different clock signals to each shift register unit through four clock signal lines, etc. The embodiments disclosed herein do not limit this.

[0049] Figure 5A The circuit structure of an exemplary shift register unit is shown. Figure 4 The shift register units at each stage in the gate drive circuit shown can be implemented as follows: Figure 5A The shift register unit circuit shown is, but not limited to, the shift register unit circuit shown. Figure 5A The structure shown can also be other types of circuit structures, and the embodiments disclosed herein are not limited to these.

[0050] like Figure 5A As shown, the shift register unit includes: an input circuit, a pull-up node reset circuit, an output circuit, a pull-down circuit, a pull-down control circuit, and an output reset circuit.

[0051] The input circuit includes a first transistor M1, the gate of which is connected to the input terminal INPUT of the shift register unit, the first terminal is connected to the first voltage terminal VGH (e.g., input high level), and the second terminal is connected to the pull-up node PU.

[0052] The pull-up node reset circuit includes a second transistor M2 and a third transistor M3. The gate of the second transistor M2 is connected to the reset terminal of the shift register unit, the first terminal is connected to the pull-up node PU, and the second terminal is connected to the second voltage terminal VGL (e.g., input low level). The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal is connected to the pull-up node PU, and the second terminal is connected to the second voltage terminal VGL.

[0053] The output circuit includes a fourth transistor M4 and a storage capacitor C1. The gate of the fourth transistor M4 is connected to the pull-up node PU, the first terminal is connected to the clock signal terminal CLK, and the second terminal is connected to the first output terminal OUTPUT of the shift register unit. The storage capacitor C1 is connected in parallel between the gate and the second terminal of the output transistor M4.

[0054] The pull-down circuit includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is connected to the first pull-down control node PD_CN, the first terminal is connected to the first voltage terminal VGH, and the second terminal is connected to the pull-down node PD. The gate of the sixth transistor M6 is connected to the pull-up node PU, the first terminal is connected to the pull-down node PD, and the second terminal is connected to the second voltage terminal VGL.

[0055] The pull-down control circuit includes a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is connected to the first terminal and the first voltage terminal VGH, and its second terminal is connected to the first pull-down control node PD_CN. The gate of the eighth transistor M8 is connected to the pull-up node PU, its first terminal is connected to the first pull-down control node PD_CN, and its second terminal is connected to the second voltage terminal VGL.

[0056] The output reset circuit includes a ninth transistor M9, whose gate and pull-down node PD are connected, its first terminal and first output terminal OUTPUT are connected, and its second terminal and second voltage terminal VGL are connected.

[0057] For example, the transistors described above are all N-type transistors, but the embodiments of this disclosure are not limited to this case.

[0058] The following is combined Figure 5B The exemplary signal timing shown is used to illustrate this. Figure 5A The working principle of the shift register unit shown is illustrated. Figure 5B In the three stages shown—first stage A, second stage B, and third stage C—the shift register unit performs the following operations.

[0059] In the first stage A, the clock signal end CLK inputs a low level, the first voltage end VGH inputs a high level (for example, the first voltage end can be set to input a high level signal), and the input end INPUT inputs a high level. For the first stage shift register in the gate drive circuit, the high level signal is the STV signal, and for other stage shift registers, the high level signal is the output signal (OUT) of the upper stage in cascade. Since the input end INPUT inputs a high level, the first transistor M1 is turned on, so that the high level input by the first voltage end VGH charges the pull-up node PU, and the potential of the pull-up node PU is charged to a first high level.

[0060] Since the first voltage end VGH keeps inputting a high level, the seventh transistor M7 is turned on to charge the first pull-down control node PD CN, so that the high level input by the first voltage end VGH charges the pull-down node PD. Since the pull-up node PU is at the first high level, the sixth transistor M6 and the eighth transistor M8 are turned on, so that the pull-down node PD, the first pull-down control node PD CN and the second voltage end VGL are electrically connected (for example, the second voltage end can be set to input a low level signal). In the design of the transistor, the seventh transistor M7 and the eighth transistor M8 can be configured (for example, the size ratio, threshold voltage, etc. of the two are configured) to be turned on at the same time, and the level of the first pull-down control node PD CN is pulled down to a low level; similarly, the fifth transistor M5 and the sixth transistor M6 can be configured (for example, the size ratio, threshold voltage, etc. of the two are configured) to be turned on at the same time, and the level of the pull-down node PD is pulled down to a low level, so as to ensure that the third transistor M3 and the ninth transistor M9 are in the off state at this stage.

[0061] Since the pull-up node PU is at the first high level, the fourth transistor M4 is turned on, and at this time, the clock signal end CLK inputs a low level, so in this stage, the first output end OUTPUT outputs the low level signal.

[0062] In the second stage B, the clock signal end CLK inputs a high level, the first voltage end VGH still inputs a high level, and the input end INPUT inputs a low level. Since the input end INPUT inputs a low level, the first transistor M1 is turned off, the pull-up node PU keeps the first high level of the last stage, so that the fourth transistor M4 keeps being turned on. Since the clock signal end inputs a high level at this stage, the first output end OUTPUT outputs a high level signal.

[0063] Due to the bootstrap effect of the storage capacitor C1, the level of the pull-up node PU is further pulled up to a second high level, making the fourth transistor M4 more fully turned on. Since the pull-up node PU is at a high level, the sixth transistor M6 and the eighth transistor M8 continue to be turned on, respectively pulling down the pull-down node PD and the first pull-down control node PD_CN to the low level input by the second voltage terminal. Since the pull-down node PD is at a low level, the third transistor M3 and the ninth transistor M9 remain in an off state, so as not to affect the normal output of the shift register unit.

[0064] In the third phase C, the clock signal terminal CLK inputs a low level, the first voltage terminal VGH continues to input a high level, the input terminal INPUT continues to input a low level, and the reset terminal RESET inputs a high level. For the last stage of the shift register in the gate drive circuit, the high level signal is the RST signal, and for other stages of the shift register, the high level signal is the output signal (OUTPUT) of the next stage in cascade. Since the reset terminal RESET inputs a high level, the second transistor M2 is turned on, and the pull-up node PU is pulled down to the low level input by the second voltage terminal VGL, so that the fourth transistor M4 is turned off.

[0065] Since the first voltage terminal VGH continues to input a high level, the seventh transistor M7 is turned on, charging the first pull-down control node PD_CN, and then making the fifth transistor M5 turned on, so as to charge the pull-down node PD. Since the pull-up node PU is at a low level, the sixth transistor M6 and the eighth transistor M8 are turned off, and the discharge path of the pull-down node PD is turned off, the pull-down node PD is charged to a high level, thereby making the third transistor M3 and the ninth transistor M9 turned on, so as to respectively pull down the pull-up node PU and the first output terminal OUTPUT to the low level input by the second voltage terminal VGL, eliminating the noise that may be generated at the first output terminal OUTPUT and the pull-up node PU of the shift register unit in the non-output phase.

[0066] It should be particularly pointed out that, Figure 5A and Figure 5B only one exemplary illustration, and the present disclosure is not limited to Figure 5A the shift register circuit shown in Figure 5B the timing diagram.

[0067] The present disclosure at least some embodiments provide a display control method and a display control device. Figure 6 is a flowchart of a display driving method provided by an embodiment of the present disclosure.

[0068] As Figure 6As shown, the display driving method can include performing a first display mode using the input image data. The first display mode includes the following steps:

[0069] In step S102, the input image data is rearranged to obtain rearranged image data;

[0070] In step S103, first image display control signals and first delay control signals corresponding to the rearranged image data are generated; and

[0071] In step S104, the rearranged image data, the first image display control signals and the first delay control signals are output.

[0072] In step S102, the input image data can include an effective row portion for actual display on the display panel and an ineffective row portion for non-actual display on the display panel, and the rearranged image data includes a rearranged effective row portion and a rearranged ineffective row portion corresponding to the effective row portion and the ineffective row portion, respectively.

[0073] In the above method, the first image display control signals are used to perform frame display corresponding to the rearranged image data during the display operation, and the first delay control signals are used to trigger the row scanning process of the rearranged effective row portion in the display panel during the frame display. As described above, the "first" in the expressions such as "first image display control signals" and "first delay control signals" is only used for differentiation, and is not used for limitation, so in appropriate context, "image display control signals" and "delay control signals" are also directly used.

[0074] The display driving method of the embodiments of the present disclosure is applicable to the case where only part of the row data of the input image is displayed in the display panel, for example, a bar-shaped display panel (only displaying part of the picture instead of the full picture), which includes a gate driving circuit, a data driving circuit and a pixel array. The gate driving circuit is used to receive a gate scanning signal to scan the pixel array; the data driving circuit is used to receive an image data signal and provide the image data signal to the pixel array; and the pixel array is used to receive the image data from the data driving circuit under the control of the gate driving circuit to perform a display operation.

[0075] For example, the above-mentioned first display mode can enable the bar-shaped display used upside down to realize normal square viewing (opposite to the upside-down direction) without changing the size specification of the input image data and without changing the scanning direction of the gate driving circuit of the display panel, thus saving cost and expanding the application scenarios of the bar-shaped display.

[0076] For example, the input image can be full-frame, for example, can be 1920*1080 in size (i.e. 1920 columns and 1080 rows); the input image has a valid row part and an invalid row part, for example, the first 360 rows of the input image are the valid row part of the input image, and the remaining 720 rows are the invalid row part of the input image. The display panel can be a bar-shaped display panel, for example, a bar-shaped display area of 1920*360 (i.e. 1920 columns and 360 rows). It should be noted that embodiments of the present disclosure are not limited to the input image of the above-mentioned size and the display panel of the above-mentioned size.

[0077] As described above, if the input image is not processed, the inverted bar-shaped display panel only displays the first 360 rows of the 1920*1080 image, and the remaining 720 rows will not be displayed on the bar-shaped display panel, but since the bar-shaped display panel is inverted, for example, relative to the ground (here as a reference surface), the audience standing on the ground also sees an inverted image. In the following examples, inversion, forward, etc. are all relative to the ground, but embodiments of the present disclosure are not limited to this scenario.

[0078] In the display driving method of embodiments of the present disclosure, the input image is rearranged to normally use the display panel without changing the placement state of the display panel. For example, the entire input image can be inverted and rearranged, or only the valid row part can be inverted and rearranged.

[0079] The input image has a valid row part and an invalid row part, and correspondingly, the rearranged image after rearrangement includes a rearranged valid row part and a rearranged invalid row part. For example, after the 1920*1080 input image is inverted and rearranged, the valid rows of the inverted and rearranged image can be the bottom 721-1080 rows (360 rows in total), i.e. the valid row part corresponding to the first 360 rows of the original input image, and the invalid rows of the inverted and rearranged image can be the top 1-720 rows, i.e. the invalid row part corresponding to the 361-1080 rows of the original image.

[0080] In step S103, a first image display control signal and a first delay control signal are generated corresponding to the rearranged image data. For example, the first image display control signal can include various control signals generated corresponding to the rearranged image after rearrangement, for example, these control signals can include STH (row data start signal) for data driving circuit, CPH (data clock signal), data output signal (TP), etc., and can also include STV (frame scanning start signal) for gate driving circuit, CLK signal (clock signal), etc., but the STV signal does not actually work during scanning and is only used to set the start time of a frame display, so as to determine the time point at which the delay control signal works.

[0081] For example, the first delay control signal can be used to generate the scan start signal of the gate driving circuit of the display panel. For example, the first delay control signal (DCI) can be a trigger signal similar to the STV signal, but delayed by a set time from the STV signal. The first delay control signal can be determined according to the position of the first row of the rearranged active row portion in the rearranged image data. For example, in the above example, when the input image data is 1920*1080 and the active row portion is 1~360 rows, the position of the first row of the rearranged active row portion in the rearranged image data is the 721st row, and thus the time for scanning from the 1st row to the 720th row, i.e. the time for rearranging the inactive row portion, can be used to determine the first delay control signal.

[0082] For example, assuming that the display refresh rate of the display panel is 60Hz, and the display time of each frame (i.e. the display of the rearranged image data) is 1 / 60 second, then in the above example, for each frame, the first delay control signal is delayed by (1 / 60)*(720 / 1080)=1 / 90 second compared with the STV signal of the frame, i.e. 1 / 90 second after the STV signal, without considering the relatively small interframe blanking interval.

[0083] Then, the rearranged image data, the first image display control signal and the first delay control signal are output to the display panel for display. The first image display control signal is used to perform frame display corresponding to the rearranged image data during the display operation, and the first delay control signal is used to trigger the row scanning process of the rearranged active row portion in the display panel during the frame display. Thus, the originally rear rows in the active row portion of the input image data become the front rows in the rearranged active row portion of the rearranged image data, and are displayed first in the display panel, thus for the display panel itself which is inverted relative to the ground, it displays an inverted image, and for the audience standing on the ground, it sees a normal image.

[0084] For example, in one embodiment, the first image display control signal can be normally generated and output, but in the non-active state before the first delay control signal arrives, i.e. not actually provided to the display panel, or at least the STV (frame scanning start signal) is not actually provided to the gate drive circuit of the display panel or not actually generated, thus the gate drive circuit of the display panel does not output the gate scanning signal, thus not actually performing the display operation; in this case, when the first delay control signal arrives, the image display control signal is actually applied to the frame display of the display panel, specifically, the gate drive circuit of the display panel is triggered by the first delay control signal to start generating the gate scanning signal according to the timing signal, and the data drive circuit of the display panel synchronously outputs the data signal, realizing, for example, line-by-line display or interlaced display, etc.

[0085] For example, the CLK signal can be provided to the gate drive circuit of the display panel in the delay interval of the rearranged image data (corresponding to the rearranged invalid row part of the rearranged image data). For another example, the CLK signal is not actually provided to the gate drive circuit of the display panel or not actually generated in the delay interval of the rearranged image data (corresponding to the rearranged invalid row part of the rearranged image data).

[0086] For example, the inverted rearranged image data (i.e. the image data of the rearranged image), the first image display control signal and the first delay control signal can be output simultaneously, but the rearranged valid row part of the display panel performs line scanning under the trigger of the first delay control signal (e.g. another similar STV signal). For example, in the above example of input image data of 1920*1080 and display refresh rate of 60Hz, the first row of the rearranged valid row part is in the 721st row in the rearranged image data, thus when the starting time of the first image display control signal (i.e. the time of the STV signal) passes 1 / 90 seconds, i.e. the time corresponds to the line scanning in the 720th row, the first delay control signal triggers the gate drive circuit of the display panel, thus the gate drive circuit starts sequentially outputting the gate scanning signal in each output port OUT1 (corresponding to the actual first row of the display panel) to OUT360 (corresponding to the actual 360th row of the display panel), and the data drive circuit starts sequentially outputting the image data by row, thus outputting the rearranged valid row part (i.e. the 721st to 1080th row) in the rearranged image data and displaying on the display panel (for this, please refer to the description of the following embodiment). Figure 7CFor example, in the case of line-by-line scanning, the gate circuit of the display panel outputs the gate scanning signals one by one in the order from the output port OUT1 to OUT360, and at the same time, the data driving circuit outputs the image data line by line in the order from the 721st row to the 1080th row in the rearranged valid row part, so as to realize display. The 360th row of the valid row part of the input image data (corresponding to the 721st row of the rearranged valid part) is displayed first, and the 1st row of the valid row part of the input image data (corresponding to the 1080th row of the rearranged valid part) is displayed last, so that the valid row part in the input image data is displayed in an inverted manner for the display panel itself, but a viewer standing on the ground and watching the display panel inverted relative to the ground sees a right-side-up image.

[0087] For example, in at least some embodiments of the present disclosure, the above-mentioned display driving method can further include step S101 and / or step S105.

[0088] In step S101, input image data is received, and the input image data is received for subsequent processing. The input image may, for example, be input image data received by a modem, for example, through a wired or wireless network. The input image data can be a static image, a dynamic image, or a video. Alternatively, the input image may, for example, be from a storage device known to the display device itself, which may, for example, be a hard disk (mechanical hard disk or solid state hard disk), or a pluggable storage device, such as a U disk, etc.

[0089] In step S105, the input image data is stored, for example, by a volatile storage method or a non-volatile storage method, without limitation, to facilitate subsequent image data processing.

[0090] Thus, by the above technical solution, the technical problem of inversion of the picture displayed on the long strip-shaped display when the long strip-shaped display is used in an inverted manner can be solved, so that the technical effect that the long strip-shaped display can still normally display the input image without inversion processing of the input image data at the client of the system is achieved, and the versatility and compatibility of the long strip-shaped display are improved.

[0091] Figure 8 is a flowchart of a display driving method provided by another embodiment of the present disclosure. As shown in Figure 8 For example, the display control method can further include, on the basis of the display control method shown in Figure 6

[0092] Step S202, obtaining a display control instruction;

[0093] ​Step S203, in response to the display control instruction, selecting to perform the first display mode or to perform the second display mode.

[0094] The display control method can include two display modes, i.e., the first display mode and the second display mode. For example, the display driving method described in the above embodiment corresponds to the first display mode, and the display panel is operated using the rearranged image data, the first image display control signal and the first delay control signal in the first display mode. In the first display mode, the display panel is placed upside down, e.g., installed in an upside-down position relative to its normal position reference direction. In the second display mode, the display panel is operated using the input image data and the second image display control signal. In the second display mode, the display panel is placed right side up, i.e., placed or installed in a normal position relative to its normal position reference direction. It should be noted that the first and second display modes are only used to distinguish between the two different display modes, and do not constitute a limitation on the embodiments of the present disclosure.

[0095] For example, in the second display mode, the display driving method of the embodiment includes:

[0096] Step S221, generating the second image display control signal corresponding to the input image data; and

[0097] Step S222, outputting the input image data and the second image display control signal.

[0098] For example, in one example, in step S202, the display control instruction is obtained, e.g., the input port of the display system to which the display panel belongs can be read, and the display control instruction can be obtained according to the different states of the input port. The display control instruction can be obtained when the input image data is received, or the display control instruction can be obtained at other times, e.g., after the input image data is received. For example, the input port can be a pin or a switch of the display device, if the pin or switch is set to high (H), it indicates that the first display mode is used, and if it is set to low (L), it indicates that the second display mode is used. For another example, the input port is in communication (e.g., directly connected) with a sensing element (e.g., a gravity sensing element), which can sense the orientation of the display panel relative to a predetermined direction (e.g., the direction of gravity). For example, when the display panel is placed right side up (e.g., placed right side up relative to the ground), the sensing element outputs high (H), indicating that the second display mode is used; when the display panel is placed upside down (e.g., placed upside down relative to the ground), the sensing element outputs low (L), indicating that the first display mode is used. The gravity sensing element is, for example, a switch that opens and closes using gravity, e.g., when placed right side up, the switch is closed due to the gravity of the switch itself, and when placed upside down, the switch is opened due to the gravity of the switch itself.

[0099] The display control instruction can be executable instruction data for judging selection of the first display mode or the second display mode, for example, can be a first executable code, for example, instruction code code1, representing the first display mode, and a second executable code, for example, instruction code code2, representing the second display mode.

[0100] For example, in step S203, in response to the display control instruction, selection of executing the first executable code or the second executable code is performed, thereby selection of performing the first display mode or the second display mode is performed. For example, when the instruction code code1 is received, selection of performing the first display mode is performed, and when the instruction code code2 is received, selection of performing the second display mode is performed. For example, the first executable code and the second executable code can be saved in a storage device, so that the system calls and executes by a processor, thereby corresponding operations of the first display mode or the second display mode are performed.

[0101] For example, in step S221, the second image display control signal corresponding to the input image data is generated. The second image display control signal can be used for frame display corresponding to the input image data in the display operation process.

[0102] For example, in step S222, the input image data and the second image display control signal are outputted. The input image data and the second image display control signal can be directly outputted to an output circuit without image inversion processing and delay processing, so that the display panel performs normal display operation to realize the second display mode, for example, a normal display mode in a forward placement state when the display panel is normally used.

[0103] For example, in an embodiment, since the input image data and the rearranged image data have the same specification, i.e., have the same number of rows and columns, the second image display control signal and the above-mentioned first image display control signal have similar specifications, i.e., have the same STV, CLK, STH, CPH, TP, etc. The difference between the two is that the first image display control signal and the first delay control signal cooperate to not directly drive the gate drive circuit of the display panel at the beginning but to drive the gate drive circuit of the display panel to display when there is the first delay control signal, delay driving the gate drive circuit of the display panel, thereby realizing the effect of delay display, while the second image display control signal can not have a corresponding delay control signal, so it can directly drive the gate drive circuit of the display panel to display from the beginning, i.e., the STV included in the second image display control signal acts on the gate drive circuit of the display panel from the beginning, thereby the gate drive circuit sequentially generates the gate scanning signal.

[0104] For the example of the input image whose valid row part is the first row to the 360th row, for the second image display control signal used for displaying the input image on the display panel, the gate driving circuit of the display panel is driven to display at the beginning.

[0105] However, in another example, the input image data is 1920*1080, and the valid row part is from the 281st row to the 720th row, i.e., the approximately middle part of the input image; correspondingly, the rearranged image data after the inversion processing is also 1920*1080, and the rearranged valid part is from the 361st row to the 800th row in the rearranged image. Then, in the first display mode, the first image display control signal is generated based on the rearranged image data and the first delay control signal including a delay of 360 row scanning time, so that the inverted image display can be realized in the inverted display panel; in the second display mode, the second image display control signal is generated based on the input image data and the second delay control signal including a delay of 280 row scanning time, so that the forward image display can be realized in the forward display panel. Therefore, for the case that the valid row part is located in the middle part of the input image, in the second display mode, the input image data without the rearrangement processing also needs to be added with the corresponding delay control signal.

[0106] Figure 9 is a schematic diagram of a display driving apparatus provided by at least some embodiments of the present disclosure. The display driving apparatus can be used to implement the display driving method as shown in Figure 6 .

[0107] As shown in Figure 9 , the display driving apparatus 100 can include an image processing module 101, a timing generation module 102, a delay processing module 103, an output circuit 104, an input port 105, and a first storage device 106. For example, the display control apparatus can be at least partially implemented in the form of a TCON chip, for example, the TCON chip includes the above-mentioned image processing module 101, the timing generation module 102, the delay processing module 103, and the output circuit 104, for example, the first storage device 206 can be in the TCON chip, or can be arranged outside the TCON chip, but arranged on the same printed circuit board, so that the two are connected through a bus. The display control apparatus can also be implemented as a combination of a CPU and a memory, or in the form of SoC, FPGA, ASIC, etc., and the present disclosure does not limit the implementation manner of the display control apparatus. Moreover, the image processing module 101, the timing generation module 102, the delay processing module 103, the output circuit 104, etc. can be combined in one or more circuit devices or components.

[0108] For example, the image processing module 101 can be configured to rearrange the received input image data to obtain rearranged image data. For example, the image processing module 101 can include image data rearrangement circuitry configured to perform a whole inversion rearrangement operation on the input image data, such as inversion rearrangement on the whole of 1920*1080, or in some examples, only on the valid row part, such as inversion rearrangement on the valid row part of 1920*360, to obtain the rearranged image data.

[0109] For example, the timing generation module 102 can be configured to generate first image display control signals, such as STH (row data start signal) and CPH (data clock signal) for the data driving circuit, according to the rearranged image data (number of rows and columns of the image) and considering the display refresh rate of the display panel. For example, the first image display control signals can also include STV (frame scanning start signal) and CLK signal (clock signal) for the gate driving circuit, wherein the first image display control signals are used to display a frame corresponding to the rearranged image data during the display operation, and the STV signal does not actually work during the scanning process but is only used to set the start time of a frame display, so as to determine the time point at which the delay control signal works. For example, when the display panel displays an image, the rearranged image data will be displayed according to the first image display control signals.

[0110] For example, the delay processing module 103 is configured to generate first delay control signals according to the rearranged image data, wherein the first delay control signals are used to trigger the row scanning process of the rearranged valid row part in the display panel during the frame display, such as triggering the process of correctly displaying the rearranged image data according to the first image display control signals when the display panel displays an image. For example, the first delay control signals are obtained according to the position of the rearranged valid row part in the rearranged image data, or the first delay control signals are obtained by presetting. Here, the “presetting” can be the output time of the delay control signal preset in the system, which can be fixedly preset (such as written in the system and cannot be changed), or can be preset by the user according to needs or preset according to the system board instruction.

[0111] For example, the delay processing module 103 can include a gate signal timing adjustment module, which can be configured to set the first delay control signal later than the STV signal included in the first image display control signal by a predetermined time, which can be obtained according to the position of the rearranged active row portion in the rearranged image data, or which can be obtained by presetting. Similarly, the "presetting" here can mean that the predetermined time is preset in the system, for example, can be fixedly preset (for example, written in the system and cannot be changed), or can be preset by the user according to needs or preset according to system board instructions.

[0112] For example, the delay processing module 103 can also be configured to implement a delay control mode, for example, the above-mentioned delay control mode can be that the delay processing module 103 calculates a delay time T1 corresponding to the rearranged dummy row portion and a working time T2 corresponding to the rearranged active row portion, respectively, according to the number of data lines of the rearranged dummy row portion (N_Dummy) and the number of data lines of the rearranged active row portion (N_Active). For example, the data driving circuit always normally outputs the rearranged image data of the full frame, for example, 1920*1080, row by row, and in the T1 time interval, there is no STV signal acting on the gate driving circuit, and the delay processing module 103 also does not send a scan start signal STV to the gate driver, so in the T1 time interval, the gate driver does not generate a gate output signal, for example, GOUT signal; in the T2 time interval, for example, at the junction point of the T1 time interval and the T2 time interval, for example, the time point corresponding to the 720th row of data, the delay processing module 103 starts to send a trigger signal (i.e., DCI) similar to the scan start signal STV to the gate driver, so in the T2 time interval, the gate driver starts to generate a gate scanning signal, for example, GOUT signal, step by step, thereby starting to display the rearranged active row portion from the 721st row of the rearranged image data on the display panel row by row.

[0113] For example, the output circuit 104 communicates with the display panel, and is configured to output the rearranged image data, the first image display control signal and the first delay control signal to the display panel, so that the display panel performs display operation under the driving of these signals.

[0114] For example, the input port 105 can be configured to obtain input image data, or in some examples, can also be configured to obtain other signals related to the display of the input image data, such as display mode control instruction signals, etc. The input port 105 is, for example, a port of an input circuit, which can be, for example, a modem or a USB driving circuit, etc. For example, the input port includes a pin or a switch, if the pin or the switch is set to high (H), it indicates that the first display mode is used, and if it is set to low (L), it indicates that the second display mode is used.

[0115] For example, the first storage device 106 can be used to temporarily or permanently store input image data. For instance, temporarily storing input image data can facilitate subsequent image processing operations. For example, when the input port 105 cannot acquire the input image stably and at high speed in real time, the input image data can be pre-stored into the memory to achieve a caching function. The first storage device 106 can be, for example, a semiconductor memory device.

[0116] The aforementioned display driver can enable conventional input images to be displayed normally on a bar screen used upside down (relative to, for example, the ground) for viewers standing on the ground without changing the way the system client provides input image data, thereby improving the compatibility of the display panel.

[0117] Figure 10 This is a schematic diagram of a display driving device provided in another embodiment of the present disclosure. Figure 10 The display driver 200 shown can be Figure 9 The display driver 100 shown is supplemented with a control device 207 and a second storage device 208.

[0118] For example, the timing generation module 202 can also be used to directly generate a second image display control signal corresponding to the input image data. For example, the second image display control signal can be used to perform frame display corresponding to the input image data during the display operation. For example, when the display panel displays an image, the input image data is correctly displayed according to the second image display control signal. For example, the second image display control signal includes signals such as STV and CLK generated corresponding to the input image to control the display panel to perform display operations.

[0119] For example, the control device 207 can be used to select between the first display mode and the second display mode according to the display control command. For example, executable codes code1 and code2 corresponding to the first display mode and the second display mode, respectively, are stored in the second storage device. For example, when the display control command received by the control device 207 is to enter the first display mode, it retrieves code1 from the storage device and executes it, thereby entering the first display mode. This causes the image processing module 201 to rearrange the input image and obtain rearranged image data; the delay processing module 203 generates a first delay control signal corresponding to the rearranged image data; the timing generation module 202 generates a first image display control signal corresponding to the rearranged image data; and then the output circuit 204 outputs the rearranged image data, the first delay control signal, and the first image display control signal to the display panel for display in the first display mode.

[0120] For example, the output circuit 204 can also be configured to output the input image data and the second image display control signal for the display panel to perform the display operation in the second display mode. For example, when the display control instruction received by the control device 207 is to perform the second display mode, the code2 is retrieved from the storage device and executed, thereby selecting the second display mode, the image processing module does not perform the rearrangement processing on the input image, the timing generation module 202 generates the second image display control signal corresponding to the input image data, and then the output circuit 204 outputs the input image data and the second image display control signal to the display panel for display in the second display mode.

[0121] For example, the second storage device 208 can be configured to store a first executable code (code1) corresponding to the first display mode and a second executable code (code2) corresponding to the second display mode. For example, the control device 207 can read the corresponding code from the second storage device 208 to determine the corresponding display mode. The second storage device 208 can be a semiconductor storage device, such as an EEPROM or a flash memory (Flash), and can be connected to the control device, the image processing module, etc. through an I2C bus, for example.

[0122] The display control device can implement multiple display modes according to the user's selection, thereby achieving that the user can easily and conveniently switch different display modes according to the need for normal display, regardless of whether the bar-shaped display panel is normally placed or installed or invertedly placed or installed.

[0123] The display driving method and the display driving device will be further described below in conjunction with exemplary Figure 7A 、 Figure 7B and Figure 7C . Figure 7A is an exemplary input image. As shown in Figure 7A , the input image obtained from the input port is, for example, an image with a size of 1920*1080. Figure 7A The upper bar-shaped area in may be, for example, a normally displayed area (effective row part) of the bar-shaped display panel with a size of 1920*360, and the lower blank area is an area that does not need to be normally displayed (invalid row part).

[0124] For example, the image in Figure 7A may be rearranged by the image processing module, for example, can be flipped up and down according to the actual situation, and it should be noted that the specific rearrangement manner is not limited in the present disclosure. For example, the input image can be flipped up and down for inversion rearrangement corresponding to the inversion of the display panel, to obtain the rearranged image as shown in Figure 7B , thereby, the input image in Figure 7AThe upper part of the valid lines, such as the first 360 lines, appears after being inverted and rearranged. Figure 7B The lower part becomes the effective row portion for rearrangement, such as the last 360 rows, which were originally in Figure 7A Invalid lines at the bottom, such as the last 720 lines, appear after being inverted and rearranged. Figure 7B The upper part becomes the invalid part of the rearrangement, such as the first 720 lines.

[0125] For example, Figure 7C It corresponds to Figure 7B The timing diagram for the display-driven method of rearranging image data. (e.g.) Figure 7C In the illustrated embodiment, corresponding Figure 7B The first image display control signal generated by the rearranged image data shown includes STV and CLK1, CLK2, ..., CLK6 (and may include more CLKs as needed). However, during the time period corresponding to the invalid rearranged rows, these signals do not generate gate scan signals in the display panel (their function may be timing). Alternatively, in other embodiments, the first image display control signal may not include the STV signal. At the beginning of the time period corresponding to the valid rearranged rows, a delay control signal (DCI) similar to the function of the STV signal is provided to the gate drive circuit of the display panel, thereby causing the gate drive circuit of the display panel to sequentially output gate scan signals. In the illustrated embodiment, H represents the actual on-time allocated to each row of gate lines, the period of each CLK signal (CLK1, CLK2, ..., CLK6) is 6H, and the corresponding high-level phase is 3H. The high-level phase of the resulting gate scan signals OUT1, OUT2, OUT3, ..., etc., is also 3H.

[0126] During the continuous display process of the display panel, the STV signal and / or DCI signal are both periodic signals with a frequency equal to the display refresh rate of the display panel. For example, the STV signal and / or DCI signal can be obtained by dividing the system clock signal, and the delay of the DCI signal relative to the STV signal can be achieved by, for example, a counting circuit driven by CLK, or the delay relative to the preset start time of the frame display when no STV signal is generated.

[0127] For example, in Figure 7CIn the timing diagram shown, the blank area is followed by a delay interval corresponding to the rearranged image data, which corresponds to the rearranged invalid row portion of the rearranged image data, such as the first 720 rows of the rearranged image data. During this delay interval, the timing control signals, such as CLK and STV, can be in the inactive state, and thus the signals at the outputs of the gate driver, such as OUT1, OUT2, OUT3, and so on, can also be in the inactive state. At the stage corresponding to the 720th row, the delay control signal (DCI) is applied to the input of the first shift register of the gate driving circuit, and thus the gate driving circuit starts to work to sequentially generate the gate scanning signals OUT1, OUT2, OUT3, and so on, each of which corresponds to one row of image data, and the data driving circuit outputs the image data signals corresponding to the 721st to 1080th rows.

[0128] Figure 7C In the timing diagram shown, the active stages (i.e., the high level portions of the waveforms in the figure) of the gate scanning signals OUT1, OUT2, OUT3, and so on, after the delay control signal correspond to the rearranged valid row portion of the rearranged image data. During this interval, the display panel starts to work, and the rearranged valid row portion can be normally displayed on the inverted strip-shaped display panel, so that the upper valid row portion of the original input image is located at the lower portion of the rearranged image data after the inversion rearrangement, and the rearranged valid row portion at the lower portion is displayed on the inverted strip-shaped display panel after the delay of the rearranged image data. Since the strip-shaped display panel is placed in the inverted manner, the final result is to invert the rearranged image again, and thus the display effect can be a normally placed image.

[0129] The above process can realize the normal display of the input image data on the display panel in different placement manners by rearranging the input image data and delaying the rearranged image data without changing the manner in which the existing system client provides the image data.

[0130] Figure 11 is a schematic diagram of a display device provided by at least some embodiments of the present disclosure, as Figure 11As shown, the display device 300 includes any display control device 310 provided by embodiments of the present disclosure, which can be a timing control circuit (TCON) for example. The display device 300 includes a display panel 330 including a pixel array composed of a plurality of pixel units. For example, the display device 300 can further include a data driving circuit 320 and a gate driving circuit 340. The data driving circuit 320 is configured to provide a data signal to the pixel array; the gate driving circuit 340 is configured to receive a scan control signal to provide a gate scan signal to the pixel array. The display control device 310 is electrically connected to the data driving circuit 320 through a signal line 312, and is electrically connected to the gate driving circuit 340 through a signal line 311. The data driving circuit 320 is electrically connected to the pixel unit through a data line 321, and the gate driving circuit 340 is electrically connected to the pixel unit through a gate line 341.

[0131] In one specific embodiment, the inverted use of the display device 300 refers to rotating the display device 300 by 180° while keeping the light-out direction of the display device 300 unchanged. For example, when the display device 300 is used in a hanging manner, the light-out direction of the light-out surface is parallel to the ground, the data driving circuit 320 is located on the top side and / or the ground side of the display device 300, and the gate driving circuit 340 is located on the left side and / or the right side of the display device 300. For example, when the display device 300 is used in a hanging manner, the light-out direction of the light-out surface is parallel to the ground, and the data driving circuit 320 is located on the ground side of the display device 300, the display device 300 can be operated by inversion, and the data driving circuit 320 is arranged on the top side of the display device 300. The display device 300 can realize the normal display of the image when used in an inverted manner. Further, the display device 300 can be a strip-shaped display screen, and the display area of the display device 300 includes a long side and a short side. The data driving circuit 320 can be located on the long side, and the gate driving circuit 340 can be located on the short side. Preferably, the gate driving circuit 340 can be a GOA driving circuit. The strip-shaped display screen can realize the normal display of the image when used in an inverted manner.

[0132] In one specific embodiment, the inverted use of the display device 300 refers to rotating the display device 300 by 180° while keeping the light-out direction of the display device 300 unchanged. For example, when the display device 300 is used in a hanging manner relative to the ground, the light-out direction of the light-out surface is parallel to the ground, the gate line 341 is arranged parallel to the ground, and the extension direction of the data line 321 can be a direction intersecting the ground (for example, the data line 321 is perpendicular to the ground). The display device 300 can realize normal display of an image in the inverted use. Further, the display device 300 can be a bar-shaped display screen, and the display area of the display device 300 includes a long side and a short side. The gate line 341 can extend along a direction parallel to the long side, and the data line 321 can extend along a direction parallel to the short side. The bar-shaped display screen can realize normal display of an image in the inverted use.

[0133] The display panel 330 can be, for example, a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an electronic paper display panel, a plasma display panel, etc., and embodiments of the present disclosure do not limit the display panel 330.

[0134] It should be noted that the display device in the present embodiment can be any product or component having a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. The display device can further include other conventional components such as a display panel, and embodiments of the present disclosure do not limit the display device.

[0135] The display device 1 provided by the embodiments of the present disclosure has the technical effects described above with reference to the display control device, which will not be described herein again.

[0136] For the present disclosure, the following points need to be explained:

[0137] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0138] (2) For the sake of clarity, the thickness and size of the layers or structures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being “on” or “under” another element, the element can be “directly” on or under the other element, or there can be an intermediate element.

[0139] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0140] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display control method applied to a bar display device, the bar display device including a display panel, the display control method comprising: The first display mode is executed using the input image data, wherein... The first display mode includes: The input image data is inverted and rearranged to obtain rearranged image data. The input image data includes valid rows for actual display on the display panel and invalid rows for non-actual display on the display panel. The rearranged image data includes rearranged valid rows and rearranged invalid rows corresponding to the valid rows and invalid rows, respectively. The column dimension of the input image data is larger than the column dimension of the image actually displayed on the bar display device. The valid rows are the portions of the input image data displayed on the bar display device, and the invalid rows are the portions of the input image data not displayed on the bar display device. Corresponding to the rearranged image data, a first image display control signal and a first delay control signal are generated. The rearranged image data, the first image display control signal, and the first delay control signal are output for display operations on the display panel. Wherein, the first image display control signal is used to perform frame display corresponding to the rearranged image data during the display operation, and the first delay control signal is used to trigger a line scanning process for the rearranged valid line portion in the display panel during the frame display process. The display panel includes a gate driving circuit, a data driving circuit, and a pixel array. The gate driving circuit is configured to receive a scan control signal to scan the pixel array; The data driving circuit is configured to receive image data signals and provide the image data signals to the pixel array; The pixel array is configured to receive image data from the data driving circuit under the control of the gate driving circuit for display operation. Wherein, the first image display control signal includes the scan control signal, and the image data signal includes the rearranged image data; The display area of ​​the bar display device includes a long side and a short side, the data driving circuit is located on the long side, and the gate driving circuit is located on the short side; The bar display device is also configured to display the image in an upright position when the data driving circuit is located on the side of the display panel away from the ground.

2. The display control method according to claim 1, wherein, The rearranged image data is obtained by rearranging the input image data, including: The input image data is completely inverted and rearranged to obtain the rearranged image data. The first delay control signal is obtained based on the position of the rearranged valid row portion in the rearranged image data, or the first delay control signal is obtained by a preset.

3. The display control method according to claim 1 further includes: Obtain display control commands; In response to the display control command, either the first display mode or the second display mode is selected, wherein the second display mode is different from the first display mode.

4. The display control method according to claim 3, wherein, The second display mode includes: A second image display control signal is generated in response to the input image data, wherein the second image display control signal is used to perform frame display in response to the input image data during the display operation; The input image data and the second image display control signal are output for performing the display operation on the display panel.

5. The display control method according to claim 3, wherein, Obtaining the display control command includes: Read the input port of the display system to which the display panel belongs. The display control command is obtained based on the different states of the input port.

6. The display control method according to claim 5, wherein, The display system includes a first executable code corresponding to the first display mode and a second executable code corresponding to the second display mode. In response to the display control command, selecting either the first display mode or the second display mode includes: According to the display control instructions, the first executable code or the second executable code is selected to be executed.

7. The display control method according to claim 3, wherein, In the first display mode, the display panel is in an inverted state; In the second display mode, the display panel is in a positive orientation, which is the opposite of the inverted orientation.

8. The display control method according to any one of claims 1-7, wherein, The first delay control signal is used to generate the scan start signal of the gate drive circuit.

9. The display control method according to any one of claims 1-7, further comprising: Receive and store the input image data.

10. A bar-shaped display device, comprising a display panel and a display control device, wherein, The display control device includes: an image processing module, a timing generation module, a delay processing module, and an output circuit. The image processing module is configured to invert and rearrange the received input image data to obtain rearranged image data. The input image data includes valid rows for actual display on the display panel and invalid rows for non-actual display on the display panel. The rearranged image data includes rearranged valid rows and rearranged invalid rows corresponding to the valid rows and invalid rows, respectively. The column dimension of the input image data is larger than the column dimension of the image actually displayed on the bar display device. The valid rows are the portions of the input image data displayed on the bar display device, and the invalid rows are the portions of the input image data not displayed on the bar display device. The timing generation module is configured to generate a first image display control signal in response to the rearranged image data, wherein the first image display control signal is used to perform frame display in response to the rearranged image data during the display operation. The delay processing module is configured to generate a first delay control signal in response to the rearranged image data, wherein the first delay control signal is used to trigger a line scanning process for the rearranged valid line portion in the display panel during the display of the frame. The output circuit is configured to output the rearranged image data, the first image display control signal, and the first delay control signal for display operations on the display panel. The display panel includes a gate driving circuit, a data driving circuit, and a pixel array. The gate driving circuit is configured to receive a scan control signal to scan the pixel array; The data driving circuit is configured to receive image data signals and provide the image data signals to the pixel array; The pixel array is configured to receive image data from the data driving circuit under the control of the gate driving circuit for display operation. Wherein, the first image display control signal includes the scan control signal, and the image data signal includes the rearranged image data; The display area of ​​the bar display device includes a long side and a short side, the data driving circuit is located on the long side, and the gate driving circuit is located on the short side; The bar display device is also configured to display the image in an upright position when the data driving circuit is located on the side of the display panel away from the ground.

11. The bar display device according to claim 10, wherein, The first delay control signal is obtained based on the position of the rearranged valid row portion in the rearranged image data, or the first delay control signal is obtained by a preset.

12. The bar display device according to claim 11, wherein, The delay processing module includes a gate signal timing adjustment module. The gate signal timing adjustment module is configured to set the first delay control signal later than the first image display control signal by a predetermined time, wherein the predetermined time is obtained based on the position of the rearranged valid row portion in the rearranged image data, or the predetermined time is obtained through the preset.

13. The bar display device according to claim 10, further comprising a control device, wherein, The control device is configured to select either a first display mode or a second display mode in response to a display control command. The second display mode is different from the first display mode. The first display mode includes using the rearranged image data, the image display control signal, and the first delay control signal to perform the display operation on the display panel.

14. The bar display device according to claim 13, wherein, The timing generation module is further configured to generate a second image display control signal corresponding to the input image data. The second image display control signal is used to display frames corresponding to the input image data during the display operation. The second display mode includes performing the display operation on the display panel using the input image data and the image display control signal; The output circuit is further configured to output the input image data and the second image display control signal for displaying the second display mode on the display panel.

15. The bar display device according to claim 13, further comprising: Second storage device, The second storage device is configured to store a first executable code corresponding to the first display mode and a second executable code corresponding to the second display mode. The display control device is further configured to, in response to the display control instruction, select to execute either the first executable code or the second executable code according to the display control instruction.

16. The bar display device according to claim 13, further comprising an input port, in, The input port is configured to receive the display control command based on different states of the input port.

17. The bar display device according to any one of claims 10-16, further comprising a first storage device, in, The first storage device is configured to store the received input image data.

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