Semiconductor storage device and memory system

Abstract

A semiconductor storage device according to an embodiment of the present invention includes a first pin, a first receiving circuit, and a first terminal circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin, and outputs a third signal based on a comparison between the first signal and a first voltage. In addition, the first receiving circuit outputs a fourth signal having a smaller amplitude than the third signal based on a comparison between the second signal and a second voltage. The first terminal circuit is connected to the first pin, and is in a disabled state when the first pin receives the first signal, and is in an enabled state when the first pin receives the second signal.

Description

Technical Field

[0001] Embodiments generally relate to a semiconductor memory device. Background Art

[0002] A NAND-type flash memory that can store data in a nonvolatile manner is known.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] Patent Document 1: Japanese Patent No. 6158960

[0006] Patent Document 2: U.S. Patent No. 9431078

[0007] Patent Document 3: U.S. Patent No. 9564185 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] High-speed communication in memory systems.

[0010] [Technical means to solve the problem]

[0011] A semiconductor storage device according to an embodiment includes a first pin, a first receiving circuit, and a first terminal circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin, and outputs a third signal based on a comparison between the first signal and a first voltage. In addition, the first receiving circuit outputs a fourth signal having a smaller amplitude than the third signal based on a comparison between the second signal and a second voltage. The first terminal circuit is connected to the first pin, and is in a disabled state when the first pin receives the first signal, and is in an enabled state when the first pin receives the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram schematically showing the system of the first embodiment.

[0013] Figure 2 It is a block diagram showing a configuration example of the semiconductor memory device 200 according to the first embodiment.

[0014] Figure 3 1 shows the functional blocks of the NAND chip A 200A according to the first embodiment and related elements.

[0015] Figure 4 An example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 200 according to the first embodiment is shown.

[0016] Figure 5 It is a block diagram showing a configuration example of the memory controller 300 according to the first embodiment.

[0017] Figure 6 It is a block diagram showing a configuration example of the input / output circuit 12 of the semiconductor memory device 200 according to the first embodiment.

[0018] Figure 7 This is a circuit diagram showing a configuration example of the termination circuits 203 and 303 of the semiconductor memory device 200 according to the first embodiment.

[0019] Figure 8 2 is a waveform diagram showing the voltage amplitude of the node DQO terminated by the termination circuits 203 and 303 according to the first embodiment.

[0020] Fig. 9 This is a circuit diagram showing a configuration example of the transmission unit 302 of the semiconductor memory device 200 according to the first embodiment.

[0021] Fig.10 This is a circuit diagram showing a configuration example of the transmission unit 202 of the semiconductor memory device 200 according to the first embodiment.

[0022] Fig.11 This is a circuit diagram showing a configuration example of the transmission unit of the semiconductor memory device 200 according to the first embodiment.

[0023] Fig.12 This is a circuit diagram showing a configuration example of the transmission unit of the semiconductor memory device 200 according to the first embodiment.

[0024] Fig.13 This is a circuit diagram showing a configuration example of the receiving unit 301 of the semiconductor storage device 200 according to the first embodiment.

[0025] Fig.14 This is a circuit diagram showing a configuration example of the receiving unit 201 of the semiconductor storage device 200 according to the first embodiment.

[0026] Fig.15 This is a circuit diagram showing a configuration example of the differential amplifier circuit 201A of the receiving unit 201 according to the first embodiment.

[0027] Fig.16 This is a circuit diagram showing a configuration example of a receiving unit of the semiconductor storage device 200 according to the first embodiment.

[0028] Fig.17 2 is a circuit diagram showing a configuration example of the receiving unit 201 , the latch circuit 206 , and the differential amplifier circuit 207 of the semiconductor memory device 200 according to the first embodiment.

[0029] Fig.18 The following describes a method of terminating the signal DQ in the semiconductor storage device 200 and the memory controller 300 according to the first embodiment.

[0030] Fig.19 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0031] Fig. 20 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment.

[0032] Fig.21 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment.

[0033] Fig. 22 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment.

[0034] Fig.23 It is a circuit diagram showing a configuration example of the transmission unit 202_B of the semiconductor memory device 200 according to the second embodiment.

[0035] Fig.24 It is a circuit diagram showing a configuration example of the receiving unit 301_B of the semiconductor storage device 200 according to the second embodiment.

[0036] Fig.25 A method of terminating the signal DQ of the semiconductor storage device 200 and the memory controller 300 according to the second embodiment is shown.

[0037] Fig.26 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0038] Fig. 27 This is an example of a timing chart of signals in the memory system 100 according to the second embodiment.

[0039] Fig.28 It is a circuit diagram showing a configuration example of the transmission unit 302_C of the semiconductor memory device 200 according to the third embodiment.

[0040] Fig.29 It is a circuit diagram showing a configuration example of a receiving unit 201_C of a semiconductor storage device 200 according to the third embodiment.

[0041] Fig.30 The following is a method of terminating the signal DQ of the semiconductor storage device 200 and the memory controller 300 according to the third embodiment.

[0042] Fig.31 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0043] Fig.32 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment.

[0044] Fig.33 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment.

[0045] Fig.34 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment.

[0046] Fig.35 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment.

[0047] Fig.36 A method of terminating the signal DQ in the semiconductor storage device 200 and the memory controller 300 according to the fourth embodiment is shown.

[0048] Fig.37 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0049] Fig.38 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment.

[0050] Fig.39 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment.

[0051] Fig.40 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment.

[0052] Fig.41 A method of terminating the signal DQ in the semiconductor storage device 200 and the memory controller 300 according to the fifth embodiment is shown.

[0053] Fig.42 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0054] Fig.43 This is an example of a timing chart of signals in the memory system 100 according to the fifth embodiment.

[0055] Fig.44 A method of terminating the signal DQ in the semiconductor storage device 200 and the memory controller 300 according to the sixth embodiment is shown.

[0056] Fig.45 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals.

[0057] Fig.46This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment.

[0058] Fig.47 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment.

[0059] Fig.48 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment.

[0060] Fig.49 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment. DETAILED DESCRIPTION

[0061] The following describes the embodiments with reference to the drawings. Each embodiment illustrates an apparatus and method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual drawings, and the dimensions and ratios of each drawing may not be the same as the actual ones. Unless explicitly stated or explicitly excluded, the entire content of the description of a certain embodiment is also suitable as the description of other embodiments. The technical idea of ​​the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements.

[0062] In addition, in the following description, the same symbols are marked for components having substantially the same function and structure. The numbers after the characters constituting the reference symbols are referenced by the reference symbols containing the same characters, and are used to distinguish the components having the same structure from each other. In the case where it is not necessary to distinguish the components represented by the reference symbols containing the same characters from each other, these components are respectively referenced by reference symbols containing only characters.

[0063] [1] First Embodiment

[0064] [1-1] Composition (Structure)

[0065] Hereinafter, the memory controller 300 and the semiconductor storage device 200 according to the embodiment will be described.

[0066] [1-1-1] Memory system configuration

[0067] Figure 1 : is a block diagram schematically showing a system of the first embodiment. Figure 1 As shown, the memory system 100 includes, for example, a memory controller 300 and a semiconductor memory device 200. The memory system 100 is controlled by a host device 400. The memory system 100 is, for example, a memory card such as an SSD (solid state drive), a USB memory, or an SD card.

[0068] The number of semiconductor storage devices 200 is not limited to one, and may be two or more. The semiconductor storage device 200 is a NAND flash memory that can store data in a nonvolatile manner. The semiconductor storage device 200 is controlled by a memory controller 300 .

[0069] The memory controller 300 receives a request signal from the host device 400 via a host bus. The type of the host bus and the request signal transmitted via the host bus depend on the application program using the semiconductor memory device 200. When the memory system 100 is an SSD, SAS (Serial Attached SCSI), SATA (Serial ATA), PCIe, etc. are used as the host bus. TM (Programmable Communications Interface Express). When the memory system 100 is a USB (Universal Serial Bus) memory, the USB is used as the host bus. When the memory system 100 is an MMC (Multi-Media Card), an interface of the eMMC specification is used as the host bus. When the memory system 100 is an SD card, an interface of the SD memory specification is used as the host bus.

[0070] The memory controller 300 controls the semiconductor memory device 200 according to the request signal received from the host device 400. Therefore, the memory controller 300 is connected to the semiconductor memory device 200 via the NAND bus. The NAND bus transmits a plurality of control signals and an input / output signal DQ of 8-bit width. The control signal includes signals CEn, CLE, ALE, WEn, REn, RE, WPn, RBn, DQS, and DQSn. The NAND bus includes a plurality of wirings for transmitting signals CEn, CLE, ALE, WEn, REn, RE, WPn, RBn, DQS, and DQSn, respectively. The symbol "n" after the name of the signal indicates the inversion logic of the signal without the name of the symbol "n", which means that the signal accompanying the symbol "n" is asserted when the signal is at a low level. The details of these signals are described below.

[0071] The memory controller 300 includes a host interface 350, a memory interface 320, a ROM (read only memory) 360, a CPU (central processing unit) 370, and a RAM (random access memory) 380. The memory controller 300 performs various operations and a part of the functions of the host interface 350 and the memory interface 320 by executing the firmware (program) stored in the ROM 360 and loaded into the RAM 380 by the CPU 370. The firmware is configured to enable the memory controller 300 to perform the operations described as the embodiments.

[0072] The host interface 350 is connected to the host device 400 via a host bus and is responsible for communication between the memory controller 300 and the host device 400. The memory interface 320 is connected to the semiconductor memory device 200 via a NAND bus and is responsible for communication between the memory controller 300 and the semiconductor memory device 200.

[0073] For example, when the memory controller 300 writes data to the semiconductor memory device 200 in response to a request signal received from the host device 400, the memory controller 300 supplies the data to the semiconductor memory device 200 through the wiring for transmitting the input / output signal DQ. In addition, when the memory controller 300 reads data from the semiconductor memory device 200 in response to a request signal received from the host device 400, the memory controller 300 receives the data read from the semiconductor memory device 200 through the wiring for transmitting the input / output signal DQ.

[0074] Figure 2 1 is a block diagram showing a configuration example of the semiconductor memory device 200 according to the first embodiment. Figure 2 As shown, the semiconductor storage device 200 includes, for example, an I / F chip 250, a NAND chip A 200A, a NAND chip B 200B, a NAND chip C 200C, and a NAND chip D 200D. The number of NAND chips is not limited to four, and may be less than four or more than four. The NAND chip A 200A, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D are connected to a common data bus DB. The NAND chips do not necessarily have to be connected via a common data bus, and a configuration in which a plurality of NAND chips are connected to one data bus DB is sufficient.

[0075] Signal CEn includes, for example, two signals CEn1 and CEn2. Signal CEn is not limited to two, and may be less than two or more than two. Signal RBn includes, for example, two signals RBn1 and RBn2. Signal RBn is not limited to two, and may be less than two or more than two.

[0076] The I / F chip 250 receives signals CEn1 and CEn2, CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ from the memory controller 300. The I / F chip 250 transmits the received signals CLE, ALE, WEn, REn, RE, WPn, DQS, DQSn, and DQ to the NAND chip A 200A, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D. The I / F chip 250 transmits the received signal CEn1 to the NAND chip A 200A and the NAND chip B 200B. The I / F chip 250 transmits the received signal CEn2 to the NAND chip C 200C and the NAND chip D 200D.

[0077] The NAND chip A 200A and the NAND chip B 200B transmit a signal RBn1 to the memory controller 300. The NAND chip C and the NAND chip D transmit a signal RBn2 to the memory controller 300.

[0078] The asserted signal CEn1 enables NAND chip A 200A and NAND chip B 200B. One of NAND chip A 200A and NAND chip B 200B is selected by signal CEn1 and address ADD for selecting NAND chip. The asserted signal CEn2 enables NAND chip C 200C and NAND chip D 200D. One of NAND chip C 200C and NAND chip D 200D is selected by signal CEn2 and address ADD for selecting NAND chip. Data is written to the selected one of NAND chip A 200A, NAND chip B 200B, NAND chip C 200C, and NAND chip D 200D. Or, data is read from the selected one of NAND chip A 200A, NAND chip B 200B, NAND chip C 200C, and NAND chip D 200D.

[0079] NAND chip A 200A, NAND chip B 200B, NAND chip C 200C, and NAND chip D 200D each include the following terminal circuits. In the communication between the memory controller 300 and the NAND chips, when a certain NAND chip is selected, the terminal circuit of the selected NAND chip can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In addition, the terminal circuit of the selected NAND chip can be enabled together with the terminal circuit of the non-selected NAND chip. In addition, the memory controller 300 can select which non-selected NAND chip among a plurality of non-selected NAND chips to enable the terminal circuit. For the selected NAND chip, which NAND chip has a terminal circuit that is enabled can be determined based on, for example, a combination of a selected NAND chip and a non-selected NAND chip whose signal characteristics have become good through a test performed in advance.

[0080] In this specification, a "selected NAND chip" means a NAND chip that communicates with the memory controller 300 in the communication between the memory controller 300 and the NAND chip. A "non-selected NAND chip" means a NAND chip that does not communicate with the memory controller 300 in the communication between the memory controller 300 and the NAND chip.

[0081] [1-1-2] NAND chip structure

[0082] Figure 3 200A and its related elements. The following description will focus on the NAND chip A 200A, but the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same structure. Figure 3 The I / F chip 250 is omitted. However, the communication between the NAND chip and the memory controller 300 described below is performed through the I / F chip 250. Figure 3 In the following figures, the I / F chip 250 may be omitted.

[0083] like Figure 2 As described above, the NAND chip A 200A is controlled by the memory controller 300. The NAND chip A 200A includes a memory cell array 11, an input / output circuit 12, a sequencer (control circuit) 13, a potential generating circuit 14, a driver 15, a row decoder 16, and a sense amplifier 17.

[0084] The memory cell array 11 includes a plurality of memory blocks BLK (BLK0, BLK1, ...). The memory blocks are hereinafter referred to as blocks. The data in each block BLK is erased in batches. Data can be erased in units smaller than one block BLK (e.g., half of a block BLK). Each block BLK is a collection of a plurality of string units SU (SU0, SU1, ...). Each string unit SU is a collection of a plurality of NAND strings (strings) STR (STR0, STR1, ...). The string STR includes a plurality of memory cell transistors MT.

[0085] The memory cell array 11 also includes various wirings not shown. Such various wirings include source lines CELSRC, word lines WL, and bit lines BL.

[0086] The memory controller 300 and the input / output circuit 12 mutually transmit and receive signals DQ, DQS, and DQSn. The signal DQ is an 8-bit signal and transmits information. The signal DQ transmits a command (CMD), an address (ADD), write data or read data (DAT), status data (STA), etc. as information. The signals DQS and DQSn are data selection signals indicating the timing at which DQ should be taken in. The signal DQSn is a signal that inverts the high level and the low level of the signal DQS.

[0087] The memory controller 300 sends signals CEn1, CLE, ALE, WEn, REn, RE, and WPn to the input-output circuit 12. The asserted signal CEn1 enables the NAND chip A 200A. The asserted signal CLE notifies the input-output circuit 12 that the signal DQ sent in parallel with the asserted signal CLE is the command CMD. The asserted signal ALE notifies the input-output circuit 12 that the signal DQ sent in parallel with the asserted signal ALE is the address ADD. The asserted signal WEn indicates that the signal DQ sent in parallel with the asserted signal WEn is taken into the input-output circuit 12. The asserted signals REn and RE instruct the input-output circuit 12 to output the signal DQ. The signal RE is a signal that inverts the high level and the low level of the signal REn. The asserted signal WPn instructs the input-output circuit 12 to prohibit the writing and erasing of data during the reception of the asserted signal WPn.

[0088] The memory controller 300 receives a signal RBn1 from the input / output circuit 12. The signal RBn1 indicates that the NAND chip A 200A is in a ready state or a busy state. When RBn1 is at a high level, the NAND chip A 200A is in a ready state. The NAND chip A 200A accepts commands from the memory controller 300 in the ready state. The NAND chip A 200A does not accept commands from the memory controller 300 in the busy state.

[0089] The sequencer 13 receives a command CMD and an address ADD from the input / output circuit 12. The sequencer 13 controls the potential generating circuit 14, the driver 15, the row decoder 16, and the sense amplifier 17 based on the command CMD and the address ADD.

[0090] The potential generating circuit 14 receives a power supply potential from the outside of the NAND chip A 200A, and generates various potentials from the power supply potential. The generated potential is supplied to the elements such as the memory cell array 11, the driver 15, and the sense amplifier 17. The potential supplied from the potential generating circuit 14 to the memory cell array 11 includes, for example, a potential applied to the source line CELSRC. The potential supplied from the potential generating circuit 14 to the driver 15 is applied to the word line WL through the driver 15. The potential supplied from the potential generating circuit 14 to the sense amplifier 17 is applied to the bit line BL, for example.

[0091] The driver 15 receives a plurality of potentials from the potential generating circuit 14. The received potentials are supplied to the row decoder 16 in accordance with a control signal from the sequencer 13.

[0092] The row decoder 16 receives the address ADD from the input / output circuit 12. The row decoder 16 receives various potentials selected by the driver 15 from the driver 15. The row decoder 16 receives a control signal including the address ADD from the sequencer 13. The row decoder 16 selects one block BLK based on the received address ADD, and transmits the potential received from the driver 15 to the selected block BLK.

[0093] The sense amplifier 17 senses the state of the memory cell transistor MT included in the memory cell array 11, generates read data DAT based on the sensed state, and transmits it to the input-output circuit 12. In addition, the sense amplifier 17 transmits the write data DAT received by the input-output circuit 12 to the memory cell transistor MT. The sense amplifier 17 receives a certain potential from the potential generating circuit 14, and supplies it to the bit line BL selected based on the write data DAT.

[0094] [1-1-3] Circuit structure of memory system

[0095] Figure 4 An example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 200 according to the first embodiment is shown by extracting one block BLK from among the plurality of blocks BLK included in the memory cell array 10. For example, all the other blocks BLK also include Figure 4 The number of blocks BLK in the memory cell array 10 and the number of string units SU in one block BLK can be set to any number. The following description is based on an example in which one block BLK includes four string units SU0 to SU3.

[0096] Each string unit SU is a set of multiple NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. The memory cell transistor MT includes a control gate and a charge storage layer to store data in a non-volatile manner. The selection transistors ST1 and ST2 are each used to select the string unit SU during various operations.

[0097] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the group of memory cell transistors MT0 to MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the group of memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0098] In the same block BLK, control gates of memory cell transistors MT0-MT7 are commonly connected to word lines WL0-WL7. Gates of select transistors ST1 in string units SU0-SU3 are commonly connected to select gate lines SGD0-SGD3. Gates of select transistors ST2 are commonly connected to select gate line SGS.

[0099] One NAND string NS of each string unit SU is connected to one bit line BL. The source line SL is shared by, for example, a plurality of blocks BLK.

[0100] A collection of multiple memory cell transistors MT connected to a common word line WL in one string unit SU is called, for example, a cell CU. For example, the storage capacity of a cell CU including memory cell transistors MT each storing 1 bit of data is defined as "1 page of data". The cell CU may have a storage capacity of more than 2 pages of data depending on the number of bits of data stored in the memory cell transistor MT.

[0101] The circuit configuration of the memory cell array 10 included in the NAND chip A 200A of the first embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0102] Figure 5 It is a block diagram showing a configuration example of the memory controller 300 according to the first embodiment. Figure 5 Only the wiring for transmitting one bit of the 8-bit wide input / output signal DQ is shown. Figure 5The following is the same as the structure shown in the figure. Figure 5 The 1-bit signal of the structure process shown is simply referred to as a signal DQ. In addition, among the wirings in the NAND bus, the wiring that transmits the DQ signal is referred to as a DQ wiring.

[0103] In the following description, the first terminal of a transistor refers to one of a source and a drain, and the second terminal refers to the other of the source and the drain. In addition, the control terminal of a transistor refers to a gate.

[0104] As described above, the memory controller 300 receives the request signal from the host device 400 . The memory controller 300 includes receiving units 301 , 306 , and 307 , transmitting units 302 , 309 to 311 , and 314 , termination circuits 303 , 312 , and 313 , an enable signal generating circuit 304 , and a reference voltage generating circuit 305 .

[0105] The enable signal generating circuit 304 generates an LVSTL enable signal LVSTL_EN1, for example, according to a program executed by the CPU 370. The enable signal generating circuit 304 transmits the generated LVSTL enable signal LVSTL_EN1 to the termination circuit 303 and the reference voltage generating circuit 305. In addition, the enable signal generating circuit 304 generates enable signals OUTEN1 and OUTEN2. The enable signal generating circuit 304 transmits the generated enable signals OUTEN1 and OUTEN2 to the transmitting section 302. Furthermore, the enable signal generating circuit 304 generates enable signals INEN1 and INEN2. The enable signal generating circuit 304 transmits the generated enable signals INEN1 and INEN2 to the receiving section 301.

[0106] The reference voltage generating circuit 305 generates reference voltages VREFq1 and VREFq2 based on the received signal LVSTL_EN1. The reference voltage generating circuit 305 can generate a plurality of reference voltages VREFq1 and VREFq2 for supply based on the LVSTL enable signal LVSTL_EN1, or can select a plurality of reference voltages VREFq1 and VREFq2 supplied from the outside for supply. The details of the reference voltages VREFq1 and VREFq2 are described below.

[0107] The receiving unit 301 receives reference voltages VREFq1 and VREFq2. The receiving unit 301 is connected to a node DQO. The receiving unit 301 receives a signal DQ from an input / output circuit 12 (described below) via the node DQO. The receiving unit 301 receives enable signals INEN1 and INEN2 from an enable signal generating circuit 304. The receiving unit 301 performs an operation related to the reception of the signal DQ. The receiving unit 301 determines the level of the signal DQ based on the received enable signals INEN1 and INEN2, for example. The receiving unit 301 can perform different operations depending on the type of information transmitted by the received signal DQ. The receiving unit 301 outputs a signal based on the received signal DQ to other elements in the memory controller 300 that are not shown. The details of the receiving unit 301 are described below. The receiving units 306 and 307 perform operations related to the reception of the signals DQS and DQSn, respectively. Since the receiving units 306 and 307 have the same configuration and function as the receiving unit 301, the description thereof is omitted. For example, wiring etc. connecting the receiving units 306 and 307 to the enable signal generating circuit 304 may be omitted. Figure 5 part of the wiring.

[0108] The terminal circuit 303 is connected to the node DQO. The terminal circuit 303 can terminate the node DQO arbitrarily. That is, the terminal circuit 303 can terminate the node DQO or not. Whether the terminal circuit 303 terminates the node DQO can be selected according to the type of the received signal DQ. The terminal circuit 303 uses the LVST enable signal LVSTL_EN1 received from the enable signal generating circuit 304 for termination. The details of the terminal circuit 303 are described below. The terminal circuits 312 and 313 can terminate the nodes DQSO and DQSnO, respectively. Since the terminal circuits 312 and 313 have the same structure and function as the terminal circuit 303, the description is omitted. For example, the wiring connecting the terminal circuits 312 and 313 to the enable signal generating circuit 304 is omitted. Figure 5 part of the wiring.

[0109] The transmitting unit 302 receives a signal transmitted as the signal DQ from other elements not shown in the figure in the memory controller 300. The transmitting unit 302 receives enable signals OUTEN1 and OUTEN2 from the enable signal generating circuit 304. The transmitting unit 302 outputs the received signal DQ based on the received enable signals OUTEN1 and OUTEN2. The transmitting unit 302 is connected to the node DQO. The transmitting unit 302 transmits the signal DQ to the input-output circuit 12 via the node DQO. The transmitting unit 302 controls the voltage of the node DQO based on the signal transmitted as the signal DQ. The details of the transmitting unit 302 are described below. The transmitting units 309 to 311 and 314 transmit the signals DQS, DQSn, REn and RE to the input-output circuit 12, respectively. Since the transmitting units 309 to 311 and 314 have the same structure and function as the transmitting unit 302, the description thereof is omitted. For example, wiring connecting the transmitting units 309 to 311 and 314 to the enable signal generating circuit 304 and the like are omitted. Figure 5 part of the wiring.

[0110] The signal DQ uses the magnitude of a voltage to transmit a signal. In addition, the memory controller 300 transmits the generated signals CEn1 , CLE, ALE, WEn, and WPn to the input / output circuit 12 via wirings in the NAND bus for transmitting these signals.

[0111] Figure 6 It is a block diagram showing a configuration example of the input / output circuit 12 of the semiconductor memory device 200 according to the first embodiment. Figure 6 and Figure 5 Similarly, only the configuration related to the wiring for transmitting one bit of the 8-bit wide input / output signal DQ is shown. The wiring for transmitting the remaining 7 bits is also provided. Figure 6 The configuration shown is the same configuration.

[0112] The input-output circuit 12 includes: receiving parts 201, 212~214 and 221, sending parts 202, 215 and 216, terminal circuits 203, 218~220 and 222, an enable signal generating circuit 204, a reference voltage generating circuit 205, a latch circuit 206, differential amplifier circuits 207 and 223, and input-output pins 208~211 and 224.

[0113] The input / output pin 208 is connected to the DQ wiring. The input / output pin 208 is connected to the node DQI. The input / output pin 209 is connected to the wiring for transmitting the data strobe signal DQS of the memory controller 300. The input / output pin 209 is connected to the node DQSI. The input / output pin 210 is connected to the wiring for transmitting the data strobe signal DQSn of the memory controller 300. The input / output pin 210 is connected to the node DQSnI. The input / output pin 211 is connected to the wiring for receiving the signal REn of the memory controller 300. The input / output pin 211 is connected to the node REnI. The input / output pin 224 is connected to the wiring for receiving the signal RE of the memory controller 300. The input / output pin 224 is connected to the node REI.

[0114] The enable signal generating circuit 204 generates an LVSTL enable signal LVSTL_EN2 based on the signals CEn1, CLE, ALE, WEn, and WPn received from the memory controller 300. The enable signal generating circuit 204 supplies the generated LVSTL enable signal LVSTL_EN2 to the termination circuit 203 and the reference voltage generating circuit 205. In addition, the enable signal generating circuit 204 generates enable signals OUTEN1 and OUTEN2. The enable signal generating circuit 204 transmits the generated enable signals OUTEN1 and OUTEN2 to the transmitting section 202. Furthermore, the enable signal generating circuit 204 generates enable signals INEN1 and INEN2. The enable signal generating circuit 204 transmits the generated enable signals INEN1 and INEN2 to the receiving section 201.

[0115] The reference voltage generating circuit 205 generates reference voltages VREFq1 and VREFq2 based on the received signal LVSTL_EN2. The reference voltage generating circuit 205 can generate and supply multiple reference voltages VREFq1 and VREFq2 according to the LVSTL enable signal LVSTL_EN2, or select and supply multiple reference voltages VREFq1 and VREFq2 supplied externally.

[0116] The receiving unit 201 receives reference voltages VREFq1 and VREFq2. The receiving unit 201 is connected to a node DQI. The receiving unit 201 receives a signal DQ from the node DQI. The receiving unit 201 receives enable signals INEN1 and INEN2 from the enable signal generating circuit 204. The receiving unit 201 performs an operation related to the reception of the signal DQ. The receiving unit 201 determines the level of the signal DQ based on the received enable signals INEN1 and INEN2, for example. The receiving unit 201 can perform different operations according to the type of information transmitted by the received signal DQ. The receiving unit 201 outputs a signal based on the received signal DQ to the latch circuit 206. The details of the receiving unit 201 are described below. The receiving units 212 to 214 and 221 perform operations related to the reception of the signals DQS, DQSn, REn, and RE, respectively. Since the receiving units 212 to 214 and 221 have the same structure and function as the receiving unit 201, the description thereof is omitted. For example, wiring etc. connecting the receiving units 212 to 214 and 221 to the enable signal generating circuit 204 may be omitted. Figure 6 part of the wiring.

[0117] The terminal circuit 203 is connected to the node DQI. The terminal circuit 203 can terminate the node DQI arbitrarily. That is, the terminal circuit 203 can terminate the node DQI or not. Whether the terminal circuit 203 terminates the node DQI can be selected according to the type of the received signal DQ. The terminal circuit 203 uses the LVST enable signal LVSTL_EN2 received from the enable signal generating circuit 204 for termination. The details of the terminal circuit 203 are described below. The terminal circuits 218 to 220 and 222 can terminate the nodes DQSI, DQSnI, REnI, and REI, respectively. Since the terminal circuits 218 to 220 and 222 have the same structure and function as the terminal circuit 203, the description is omitted. For example, the wiring connecting the terminal circuits 218 to 220 and 222 to the enable signal generating circuit 204 is omitted. Figure 6 part of the wiring.

[0118] The latch circuit 206 receives a signal based on the signal DQ from the receiving section 201 and holds the signal based on the received signal DQ. The latch circuit 206 transmits the signal DQ transmitted to the memory controller 300 to the transmitting section 202. Details of the latch circuit 206 are described below.

[0119] The transmitting unit 202 receives a signal transmitted as the signal DQ from the latch circuit 206. The transmitting unit 202 receives the enable signals OUTEN1 and OUTEN2 from the enable signal generating circuit 204. The transmitting unit 202 outputs the received signal DQ based on the received enable signals OUTEN1 and OUTEN2. The transmitting unit 202 is connected to the node DQI. The transmitting unit 202 transmits the signal DQ to the memory controller 300 via the node DQI and the input / output pin 208. The transmitting unit 202 controls the voltage of the node DQI based on the signal transmitted as the signal DQ. The details of the transmitting unit 302 are described below. The transmitting units 215 and 216 transmit the signals DQS and DQSn to the memory controller 300, respectively. Since the transmitting units 215 and 216 have the same structure and function as the transmitting unit 202, the description thereof is omitted. For example, wiring connecting the transmitting units 215 and 216 to the enable signal generating circuit 204 and the like are omitted. Figure 6 part of the wiring.

[0120] The differential amplifier circuit 207 is connected to the receiving sections 212 and 213. The differential amplifier circuit 207 receives a signal based on the signal DQS from the receiving section 212. The differential amplifier circuit 207 receives a signal based on the signal DQSn from the receiving section 213. The differential amplifier circuit 207 controls the latch circuit 206 based on the received signals DQS and DQSn. The details of the differential amplifier circuit 207 are described below.

[0121] The differential amplifier circuit 223 is connected to the receiving units 214 and 221. The differential amplifier circuit 223 receives a signal based on the signal REn from the receiving unit 214. The differential amplifier circuit 223 receives a signal based on the signal RE from the receiving unit 221. The differential amplifier circuit 223 generates signals REni and REi based on the received signals REn and RE. The differential amplifier circuit 223 outputs the generated signals REni and REi to other elements (not shown) in the input / output circuit 12.

[0122] Figure 7 This is a circuit diagram showing a configuration example of the termination circuits 203 and 303 of the semiconductor memory device 200 according to the first embodiment. Figure 8 2 is a waveform diagram showing the voltage amplitude of the node DQO terminated by the termination circuits 203 and 303 of the first embodiment. Figure 8 ,against Figure 7 Give a description.

[0123] Figure 7 express Figure 5 and 6The detailed circuit structure of the terminal circuits 203 and 303 is described. First, the circuit structure of the terminal circuit 303 is described. As described, the terminal circuit 303 can terminate the node DQO arbitrarily. The terminal circuit 303 includes a resistor 303A and an NMOS transistor 303B. The first end of the resistor 303A is electrically connected to the node DQO. The second end of the resistor 303A is electrically connected to the first end of the NMOS transistor 303B. The second end of the NMOS transistor 303B is electrically connected to the node of the ground voltage VSSq. The LVSTL enable signal LVSTL_EN1 is supplied from the enable signal generating circuit 304 to the control terminal of the NMOS transistor 303B.

[0124] The NMOS transistor 303B is turned on by supplying a high-level LVSTL enable signal LVSTL_EN1 to the control terminal of the NMOS transistor 303B, and is turned off by supplying a low-level LVSTL enable signal LVSTL_EN1 to the control terminal of the NMOS transistor 303B.

[0125] When the NMOS transistor 303B is turned on, the termination circuit 303 terminates the node DQO. In addition, when the NMOS transistor 303B is turned off, the termination circuit 303 does not terminate the node DQO. In this way, the termination circuit 303 can select whether to terminate the signal DQ by adjusting the level of the LVSTL enable signal LVSTL_EN1. Hereinafter, the state in which the NMOS transistor 303B is turned on and the termination circuit 303 terminates the node DQO is described as "the termination circuit 303 is enabled". Similarly, the state in which the NMOS transistor 303B is turned off and the termination circuit 303 does not terminate the node DQO is described as "the termination circuit 303 is not enabled (disabled)".

[0126] When the termination circuit 303 is enabled, the on-resistance of the NMOS transistor 303B and the resistor 303A reduce the voltage of the signal DQ received by the node DQO. Figure 8 Hereinafter, a case will be considered in which the node DQO receives a voltage that periodically oscillates between a high level (VCCq) or a low level (VSSq).

[0127] When the termination circuit 303 is not enabled, the termination circuit 303 does not adjust the resistance value of the node DQO. Figure 8 As shown by the solid line of , the termination circuit 303 does not adjust the voltage amplitude of the signal DQ at the node DQ0. Therefore, the node DQ0 supplies a signal having an amplitude of the voltage VSSq to the voltage VCCq to the receiving unit 301.

[0128] When the termination circuit 303 is enabled, the on-resistance of the NMOS transistor 303B and the resistor 303A reduce the voltage VCCq from the node DQO to the voltage VCCq-α. Figure 8 As shown by the dotted line, the termination circuit 303 adjusts the voltage amplitude of the node DQO to the voltage VSSq to the voltage VCCq-α through the on-resistance of the NMOS transistor 303B and the load resistance of the resistor 303A. Therefore, the node DQO supplies a signal having an amplitude of the voltage VSSq to the voltage VCCq-α to the receiving unit 301.

[0129] The maximum value (i.e., high level) of the signal DQ is different when the termination circuit 303 is enabled and when it is not enabled. Therefore, the reference voltage VREFq used to determine the level of the signal DQ is changed when the termination circuit 303 is enabled and when it is not enabled. More specifically, Figure 8 As shown, the reference voltage generating circuit 305 supplies a reference voltage VREFq1 between the voltage VSSq and the voltage VCCq when the terminal circuit 303 is not enabled. The reference voltage VREFq1 is, for example, an intermediate value between the voltage VSSq and the voltage VCCq, that is, (VCCq+VSSq) / 2. On the other hand, the reference voltage generating circuit 305 supplies a reference voltage VREFq2 between the voltage VSSq and the voltage VCCq-α when the terminal circuit 303 is enabled. For example, the reference voltage VREFq2 is less than (VCCq+VSSq) / 2, and the value of the reference voltage VREFq2 less than (VCCq+VSSq) / 2 is (VCCq+VSSq) / 3, etc., and the above values ​​are described in this specification, but the present invention is not limited thereto.

[0130] Next, refer to Figure 7 , the circuit structure of the terminal circuit 203 is described. As described above, the terminal circuit 203 terminates the node DQI arbitrarily. The terminal circuit 203 has the same structure and function as the terminal circuit 303. The terminal circuit 203 includes a resistor 203A and an NMOS transistor 203B. The first end of the resistor 203A is electrically connected to the node DQI. The second end of the resistor 203A is electrically connected to the first end of the NMOS transistor 203B. The second end of the NMOS transistor 203B is electrically connected to the node of the ground voltage VSSq. The LVSTL enable signal LVSTL_EN2 is supplied from the enable signal generating circuit 204 to the control terminal of the NMOS transistor 203B.

[0131] The control terminal of the NMOS transistor 203B is supplied with a high-level LVSTL enable signal LVSTL_EN2, and the NMOS transistor 203B is turned on. The control terminal of the NMOS transistor 203B is supplied with a low-level LVSTL enable signal LVSTL_EN2, and the NMOS transistor 203B is turned off.

[0132] When the NMOS transistor 303B is turned on, the termination circuit 203 terminates the node DQI. In addition, when the NMOS transistor 203B is turned off, the termination circuit 203 does not terminate the node DQI. In this way, the termination circuit 203 can select whether to terminate the signal DQ by adjusting the level of the LVSTL enable signal LVSTL_EN2. In the following, similarly to the termination circuit 303, the state in which the NMOS transistor 203B is turned on and the termination circuit 203 terminates the node DQI is described as "the termination circuit 203 is enabled". Similarly, the state in which the NMOS transistor 203B is turned off and the termination circuit 203 does not terminate the node DQO is described as "the termination circuit 203 is not enabled (disabled)".

[0133] The termination circuit 203, like the termination circuit 303, adjusts the voltage amplitude of the node DQI to the voltage VSSq to the voltage VCCq-α ( Figure 8 dotted line). Therefore, the node DQI supplies a voltage having an amplitude of the voltage VSSq to the voltage VCCq-α to the receiving unit 201. Similar to the terminal circuit 303, the reference voltage generating circuit 205 supplies the reference voltage VREFq1 (for example, VREFq1=(VCCq+VSSq) / 2)) when the terminal circuit 203 is not enabled. On the other hand, when the terminal circuit 203 is enabled, the reference voltage generating circuit 205 supplies the reference voltage VREFq2 which is the intermediate value between the voltage VSSq and the voltage VCCq-α (VREFq2<(VCCq+VSSq) / 2). The terminal circuits 218 to 220, 222, 312, and 313 have the same structure and function as the terminal circuits 203 and 303, and therefore the description thereof is omitted.

[0134] Fig. 9 This is a circuit diagram showing a configuration example of the transmission unit 302 of the semiconductor memory device 200 according to the first embodiment. Fig. 9 express Figure 5 The detailed circuit structure of the transmission unit 302 is described above. As described above, the transmission unit 302 controls the voltage of the node DQO based on the signal transmitted as the signal DQ. Hereinafter, the signal transmitted as the signal DQ by the transmission unit 302 is referred to as the signal IN1.

[0135] The transmitting section 302 includes a legacy transmitting section 302X and a low voltage swing terminated logic (LVSTL) transmitting section 302Y. The transmitting section 302 can select to use the legacy transmitting section 302X to transmit the signal DQ or to use the LVSTL transmitting section 302Y to transmit the signal DQ based on the type of the received signal IN1. Details of the type of the signal DQ and the transmitting section used (legacy transmitting section 302X or LVSTL transmitting section 302Y) are described below.

[0136] When the legacy transmission section 302X is selected, the enable signal generation circuit 304 transmits a high-level enable signal OUTEN1 and a low-level enable signal OUTEN2 to the transmission section 302. When the LVSTL transmission section 302Y is selected, the enable signal generation circuit 304 transmits a low-level enable signal OUTEN1 and a high-level enable signal OUTEN2 to the transmission section 302.

[0137] The legacy transmission section 302X transmits the signal DQ in a transmission method corresponding to a terminal circuit of a CTT (center tapped termination) method or a POD (pseudo open drain) method, for example. The legacy transmission section 302X includes: a PMOS transistor 302A, an NMOS transistor 302B, a NAND gate 302C, an inverter 302D, and a NOR gate 302E. The legacy transmission section 302X is not limited to Fig. 9 As long as the same signal logic is obtained, in addition to (instead of) the illustrated logic gates, it can also be expressed by appropriately combining logic circuits such as AND gates, NAND gates, OR gates, NOR gates, XOR gates, XNOR gates, inverters, etc.

[0138] A first terminal of the PMOS transistor 302A is electrically connected to a node of a power supply voltage VCCq (high level). The power supply voltage VCCq is equal to or lower than the amplitude (or high level) of the signal IN1. A second terminal of the PMOS transistor 302A is connected to a node DQO.

[0139] A first terminal of the NMOS transistor 302B is connected to the node DQ0. A second terminal of the NMOS transistor 302B is electrically connected to a node of the ground voltage VSSq.

[0140] The NAND gate has a first input terminal, a second input terminal, and an output terminal. The NAND gate outputs the level of the signal received by the first input terminal and the "NAND" of the level of the signal received by the second input terminal from the output terminal. The first input terminal of the NAND gate 302C receives the enable signal OUTEN1 from the enable signal generating circuit 304. The second input terminal of the NAND gate 302C receives the signal IN1 from other elements not shown in the memory controller 300. The output terminal of the NAND gate 302C is connected to the control terminal of the PMOS transistor 302A. The NAND gate 302C sends the "NAND" of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the PMOS transistor 302A from the output terminal.

[0141] The inverter has an input terminal and an output terminal. The inverter outputs a logic inversion of the level of the signal received by the input terminal. The input terminal of the inverter 302D receives the enable signal OUTEN1 from the enable signal generating circuit 304. The inverter 302D sends the logic inversion of the received signal OUTEN1 from the output terminal to the first input terminal of the NOR gate 302E.

[0142] The NOR gate has a first input terminal, a second input terminal, and an output terminal. The NOR gate outputs the level of the signal received at the first input terminal and the "NOR" of the level of the signal received at the second input terminal from the output terminal. The first input terminal of the NOR gate 302E is connected to the output terminal of the inverter 302D. The second input terminal of the NOR gate 302E receives a signal IN1 from other elements not shown in the memory controller 300. The output terminal of the NOR gate 302E is connected to the control terminal of the NMOS transistor 302B. The NOR gate 302E sends the "NOR" of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the NMOS transistor 302B from the output terminal.

[0143] The LVSTL transmission unit 302Y transmits the signal DQ in a transmission method corresponding to the termination circuit of the LVSTL (low voltage swing terminated logic) method. The LVSTL transmission unit 302Y includes NMOS transistors 302F and 302G, an AND gate 302H, an inverter 302I, and a NOR gate 302J. The LVSTL transmission unit 302Y may have a logic circuit such as a NAND gate, an inverter, etc. as long as the same signal logic is obtained, and is not limited to Fig. 9 structure.

[0144] A first terminal of the NMOS transistor 302F is electrically connected to a node of a power supply voltage VCCq, and a second terminal of the NMOS transistor 302F is connected to a node DQO.

[0145] A first terminal of the NMOS transistor 302G is connected to the node DQ0. A second terminal of the NMOS transistor 302G is electrically connected to a node of the ground voltage VSSq.

[0146] The AND gate has a first input terminal, a second input terminal, and an output terminal. The AND gate outputs the AND of the level of the signal received at the first input terminal and the level of the signal received at the second input terminal from the output terminal. The first input terminal of the AND gate 302H receives the enable signal OUTEN2 from the enable signal generating circuit 304. The second input terminal of the AND gate 302H receives the signal IN1 from other elements not shown in the memory controller 300. The output terminal of the AND gate 302H is connected to the control terminal of the NMOS transistor 302F. The AND gate 302H sends the AND of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the NMOS transistor 302F from the output terminal.

[0147] The input terminal of the inverter 302I receives the enable signal OUTEN2 from the enable signal generating circuit 304. The inverter 302I sends the logic inversion of the received signal OUTEN2 from the output terminal to the first input terminal of the NOR gate 302J.

[0148] The first input terminal of the NOR gate 302J is connected to the output terminal of the inverter 302I. The second input terminal of the NOR gate 302J receives a signal IN1 from another element not shown in the memory controller 300. The output terminal of the NOR gate 302J is connected to the control terminal of the NMOS transistor 302G. The NOR gate 302J sends the signal received from the first input terminal and the signal received from the second input terminal "NOR" to the control terminal of the NMOS transistor 302G from the output terminal.

[0149] In this way, the transmission section 302 switches which one of the legacy transmission section 302X and the LVSTL transmission section 302Y generates the DQ signal according to the type of information transmitted by the signal DQ. To perform the switching, the low level and high level of the enable signals OUTEN1 and OUTEN2 are adjusted. In other words, the transmission section 302 has two transmission methods, and which transmission method is selected is determined according to the type of the signal DQ.

[0150] In addition, for the sake of distinction, the signal DQ transmitted based on the enable signal OUTEN1 (the signal DQ generated by the legacy transmission unit 302X according to the signal IN1) is referred to as the signal Legacy_IN1. The signal DQ transmitted based on the enable signal OUTEN2 (the signal DQ generated by the LVSTL transmission unit 302Y according to the signal IN1) is referred to as the signal LVSTL_IN1.

[0151] When the LVSTL transmission section 302Y is used, the voltage VCCq is transmitted through the NMOS transistor 302F, so the transmitted voltage is lower than the voltage VCCq by the threshold voltage of the NMOS transistor 302F. Therefore, the amplitude of the signal LVSTL_IN1 is smaller than the amplitude of the signal Legacy_IN1. That is, by using the LVSTL transmission section 302Y, a signal DQ with a smaller amplitude can be transmitted than when the legacy transmission section 302X is used.

[0152] Next, the circuit structure of the transmission unit 202 will be described. Fig.10 This is a circuit diagram showing a configuration example of the transmission unit 202 of the semiconductor memory device 200 according to the first embodiment. Fig.10 express Figure 6 The detailed circuit structure of the transmission unit 202 is described above. As described above, the transmission unit 202 controls the voltage of the node DQI based on the signal transmitted as the signal DQ. The transmission unit 202 has the same structure and function as the transmission unit 302. Hereinafter, the signal transmitted to the transmission unit 202 as the signal DQ is referred to as the signal IN2.

[0153] The transmission section 202 includes a legacy transmission section 202X and an LVSTL transmission section 202Y. The transmission section 202 can select to use the legacy transmission section 202X to transmit the signal or use the LVSTL transmission section 202Y to transmit the signal IN2 based on the type of the received signal IN2. The details of the type of the signal DQ and the transmission section used (legacy transmission section 202X or LVSTL transmission section 202Y) are described below.

[0154] When the legacy transmission section 202X is selected, the enable signal generation circuit 204 transmits a high-level enable signal OUTEN1 and a low-level enable signal OUTEN2 to the transmission section 202. When the LVSTL transmission section 202Y is selected, the enable signal generation circuit 204 transmits a low-level enable signal OUTEN1 and a high-level enable signal OUTEN2 to the transmission section 202.

[0155] The legacy transmission unit 202X includes: a PMOS transistor 202A, an NMOS transistor 202B, a NAND gate 202C, an inverter 202D, and a NOR gate 202E. The legacy transmission unit 202X may have a logic circuit such as a NAND gate, an inverter, etc. as long as it obtains the same signal logic, and is not limited to Fig.10 structure.

[0156] A first terminal of the PMOS transistor 202A is electrically connected to a node of a power supply voltage VCCq, and a second terminal of the PMOS transistor 202A is connected to a node DQI.

[0157] A first terminal of the NMOS transistor 202B is connected to the node DQI. A second terminal of the NMOS transistor 202B is electrically connected to a node of the ground voltage VSSq.

[0158] The first input terminal of the NAND gate 202C receives the enable signal OUTEN1 from the enable signal generating circuit 204. The second input terminal of the NAND gate 202C receives the signal IN2 from the latch circuit 206. The output terminal of the NAND gate 202C is connected to the control terminal of the PMOS transistor 202A. The NAND gate 202C sends the signal received from the first input terminal and the NAND of the signal received from the second input terminal to the control terminal of the PMOS transistor 302A from the output terminal.

[0159] The input terminal of the inverter 202D receives the enable signal OUTEN1 from the enable signal generating circuit 204. The inverter 202D sends the logic inversion of the received signal OUTEN1 from the output terminal to the first input terminal of the NOR gate 202E.

[0160] The first input terminal of the NOR gate 202E is connected to the output terminal of the inverter 202D. The second input terminal of the NOR gate 202E receives the signal IN2 from the latch circuit 206. The output terminal of the NOR gate 202E is connected to the control terminal of the NMOS transistor 202B. The NOR gate 202E sends the signal received from the first input terminal and the signal received from the second input terminal "NOR" to the control terminal of the NMOS transistor 202B from the output terminal.

[0161] The LVSTL transmission unit 202Y includes: NMOS transistors 202F and 202G, AND gate 202H, inverter 202I, and NOR gate 202J. The LVSTL transmission unit 202Y may have a logic circuit such as a NAND gate, an inverter, etc. as long as the same signal logic is obtained, and is not limited to Fig.10 structure.

[0162] A first terminal of the NMOS transistor 202F is electrically connected to a node of a power supply voltage VCCq, and a second terminal of the NMOS transistor 202F is connected to a node DQI.

[0163] A first terminal of the NMOS transistor 202G is connected to the node DQI. A second terminal of the NMOS transistor 202G is electrically connected to a node of the ground voltage VSSq.

[0164] The first input terminal of the AND gate 202H receives the enable signal OUTEN2 from the enable signal generating circuit 204. The second input terminal of the AND gate 202H receives the signal IN2 from the latch circuit 206. The output terminal of the AND gate 202H is connected to the control terminal of the NMOS transistor 202F. The AND gate 202H sends the AND of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the NMOS transistor 202F from the output terminal.

[0165] The input terminal of the inverter 202I receives the enable signal OUTEN2 from the enable signal generating circuit 204. The inverter 202I sends the logic inversion of the received signal OUTEN2 from the output terminal to the first input terminal of the NOR gate 202J.

[0166] The first input terminal of the NOR gate 202J is connected to the output terminal of the inverter 202I. The second input terminal of the NOR gate 202J receives the signal IN2 from the latch circuit 206. The output terminal of the NOR gate 202J is connected to the control terminal of the NMOS transistor 202G. The NOR gate 202J sends the signal received from the first input terminal and the signal received from the second input terminal "NOR" to the control terminal of the NMOS transistor 202G from the output terminal.

[0167] In this way, the transmitter 202 switches which one of the legacy transmitter 202X and the LVSTL transmitter 202Y generates the DQ signal, similarly to the transmitter 302, according to the type of information transmitted by the signal DQ. To perform the switching, the low level and high level of the enable signals OUTEN1 and OUTEN2 are adjusted. That is, the transmitter 202 has two transmission methods, and which transmission method is selected is determined according to the type of the signal DQ.

[0168] In addition, for the sake of distinction, the signal DQ transmitted based on the enable signal OUTEN1 (the signal DQ generated by the legacy transmission unit 202X according to the signal IN2) is referred to as the signal Legacy_IN2. The signal DQ transmitted based on the enable signal OUTEN2 (the signal DQ generated by the LVSTL transmission unit 202Y according to the signal IN2) is referred to as the signal LVSTL_IN2.

[0169] When the LVSTL transmission unit 202Y is used, since the voltage VCCq is transmitted through the NMOS transistor 202F, the transmitted voltage is lower than the voltage VCCq by the threshold voltage of the NMOS transistor 202F. Therefore, the amplitude of the signal LVSTL_IN2 is smaller than the amplitude of the signal Legacy_IN2. That is, by using the LVSTL transmission unit 202Y, a signal DQ with a smaller amplitude than that of the case where the legacy transmission unit 202X is used can be transmitted. Since the transmission units 215, 216, 309 to 311 and 314 have the same structure and function as the transmission units 202 and 302, the description thereof is omitted. Here, similarly to Legacy_In1 and LVSTL_IN1, the signal transmitted from the transmission unit 309 and received by the receiving unit 212 is referred to as the signal Legacy_DQS1 or LVSTL_DQS1. The signal transmitted from the transmission section 215 and received by the reception section 306 is referred to as a signal Legacy_DQS2 or LVSTL_DQS2. The signals LVSTL_DQS1 and LVSTL_DQS2 have smaller amplitudes than the signals Legacy_DQS1 and Legacy_DQS2, respectively.

[0170] The signal transmitted from the transmission unit 314 and received by the reception unit 221 is referred to as a signal Legacy_RE1 or LVSTL_RE1. The signal LVSTL_RE1 has a smaller amplitude than the signal Legacy_RE1.

[0171] Fig. 9 and Fig.10 The circuit diagrams of the transmission unit 302 and the transmission unit 202 shown in FIG. 1 are examples of the configuration. Therefore, the transmission unit 302 and the transmission unit 202 only need to be connected to the transmission unit 302 and the transmission unit 202. Fig. 9 and Fig.10 Here, the functions of the transmission unit of the memory system 100 of the first embodiment include: having two transmission methods, and determining which transmission method to select according to the type of the signal DQ.

[0172] exist Fig.11 And 12 records for the Fig. 9 as well as Fig.10 Specific examples of applicable structures other than the structure. Fig.11 12 is a circuit diagram showing a configuration example of the transmission unit of the semiconductor memory device 200 according to the first embodiment. Fig. 9 As described above, the transmission unit 202 has the same structure and function as the transmission unit 302. Therefore, only the transmission unit 202 will be described below as a representative example.

[0173] exist Fig.11 An example of the configuration of the sending unit 202 is shown in FIG. Fig.11 The sending unit 202 is shown in order to Fig.10 The transmitting unit 1202 is distinguished from the transmitting unit 202 and is referred to as the transmitting unit 1202. Hereinafter, the transmitting unit 1202 will be mainly described with respect to the points different from the transmitting unit 202.

[0174] The transmission unit 1202 has two transmission methods similar to the transmission unit 202, and selects a transmission method based on the type of the received signal DQ. The selection of the transmission method is based on the level of the enable signal OUTEN1 or OUTEN2. Here, the signal DQ generated by the transmission unit 1202 based on the signal IN2 based on the signal OUTEN1 is called the signal Legacy_IN2. The signal DQ generated by the transmission unit 1202 based on the signal IN2 based on the signal OUTEN2 is called the signal LVSTL_IN2.

[0175] The transmission unit 1202 has a configuration in which the NMOS transistor 202B, the inverter 202D, and the NOR gate 202E are removed from the structure of the transmission unit 202. The functions of the removed NMOS transistor 202B, the inverter 202D, and the NOR gate 202E are compensated by the NMOS transistor 202G, the inverter 202I, and the NOR gate 202J, respectively.

[0176] Specifically, the transmission unit 1202 includes: a PMOS transistor 1202A, a NAND gate 1202C, NMOS transistors 1202F and 1202G, an AND gate 1202H, an inverter 1202I, and a NOR gate 1202J. The transmission unit 1202 may have a logic circuit such as a NAND gate, an inverter, etc. as long as the same signal logic is obtained, and is not limited to Fig.11 The PMOS transistor 1202A, NAND gate 1202C, NMOS transistors 1202F and 1202G, AND gate 1202H, inverter 1202I, and NOR gate 1202J of the transmission unit 1202 have the same structure and function as the PMOS transistor 202A, NAND gate 202C, NMOS transistors 202F and 202G, AND gate 202H, inverter 202I, and NOR gate 202J of the transmission unit 202, respectively.

[0177] When transmitting the signal LVSTL_IN2, the transmitting unit 1202 uses the NMOS transistors 1202F and 1202G, the AND gate 1202H, the inverter 1202I, and the NOR gate 1202J, similarly to the transmitting unit 202. In contrast, when transmitting the signal Legacy_IN2, the transmitting unit 1202 uses the PMOS transistor 1202A, the NMOS transistor 1202G, the NAND gate 1202C, the inverter 1202I, and the NOR gate 1202J. That is, the NMOS transistor 1202G, the inverter 1202I, and the NOR gate 1202J are commonly used not only when transmitting the signal LVSTL_IN2 but also when transmitting the signal Legacy_IN2.

[0178] The inverter 1202I receives not only the signal OUTEN1 but also the signal OUTEN2 from the enable signal generating circuit 204. As described above, when the signal OUTEN1 is at a high level, the signal OUTEN2 is at a low level, and when the signal OUTEN1 is at a low level, the signal OUTEN2 is at a high level. Since the signal OUTEN1 and the signal OUTEN2 are not at a high level at the same time, the inverter 1202I can receive both the signal OUTEN1 and the signal OUTEN2. That is, the inverter 1202I can be used in common in both the case of transmitting the signal Legacy_IN2 and the case of transmitting the signal LVSTL_IN2.

[0179] Similarly, the NOR gate 1202J connected to the inverter 1202I and the NMOS transistor 1202G connected to the NOR gate 1202J can be used in common in both cases of transmitting the signal Legacy_IN2 and transmitting the signal LVSTL_IN2.

[0180] In summary, the transmitting section 202 completely separates the components used according to the signal by using the legacy transmitting section 202X when transmitting the signal Legacy_IN2 and using the LVSTL transmitting section 202Y when transmitting the signal LVSTL_IN2. In this regard, the transmitting section 1202 simplifies the components of the legacy transmitting section 202X by using a part of the components of the LVSTL transmitting section 202Y in common. Since a part of the components can be removed, the transmitting section 1202 can reduce the circuit area compared to the transmitting section 202.

[0181] exist Fig.12 An example of the configuration of the sending unit 202 is shown in FIG. Fig.12 The sending unit 202 is shown in order to Fig.10The transmitting unit 202 is distinguished from the transmitting unit 202 and is referred to as the transmitting unit 2202. Hereinafter, the transmitting unit 2202 will be mainly described with respect to the differences from the transmitting unit 202 and the transmitting unit 1202.

[0182] The transmission unit 2202 has two transmission methods similar to the transmission unit 202, and selects a transmission method based on the type of the received signal DQ. The selection of the transmission method is based on the level of the enable signal OUTEN1 or OUTEN2. Here, the signal IN2 transmitted from the transmission unit 2202 based on the enable signal OUTEN1 is referred to as the signal Legacy_IN2. The signal IN2 transmitted from the transmission unit 2202 based on the enable signal OUTEN2 is referred to as the signal LVSTL_IN2.

[0183] The transmission unit 2202 has a configuration in which the PMOS transistor 1202A and the NAND gate 1202C are removed from the structure of the transmission unit 1202. The functions of the removed PMOS transistor 1202A and the NAND gate 1202C are compensated by the NMOS transistor 1202F and the AND gate 1202H, respectively.

[0184] Specifically, the transmission unit 2202 includes: NMOS transistors 2202F and 2202G, AND gate 2202H, inverter 2202I, and NOR gate 2202J. The transmission unit 2202 may have a logic circuit such as a NAND gate, an inverter, etc. as long as the same signal logic is obtained, and is not limited to Fig.12 The NMOS transistors 2202F and 2202G, the AND gate 2202H, the inverter 2202I, and the NOR gate 2202J of the transmission unit 2202 have the same configuration and function as the NMOS transistors 1202F and 1202G, the AND gate 1202H, the inverter 1202I, and the NOR gate 1202J of the transmission unit 1202. However, the AND gate 2202H is different from the AND gate 202H in the following points.

[0185] That is, the AND gate 2202H receives a voltage dynamically selected between the voltage VCCq and the voltage VCCq+α. At least among the MOS transistors constituting the AND gate 2202H, the second terminal of the PMOS transistor connected to the output terminal and the first terminal of the AND gate 2202H and driving the voltage of the output terminal receives a voltage dynamically selected between the voltage VCCq and the voltage VCCq+α. Hereinafter, the PMOS transistor is referred to as an output PMOSFET.

[0186] When the output PMOSFET receives the voltage VCCq and is turned on, the output of the AND gate 2202H is driven by a voltage based on the voltage VCCq. On the other hand, when the output PMOSFET receives the voltage VCCq+α and is turned on, the output of the AND gate 2202H is driven by a voltage based on the voltage VCCq+α. The voltage based on the voltage VCCq+α is greater than the voltage based on the voltage VCCq. Therefore, the output (H level under the voltage VCCq+α) of the AND gate 2202H when the voltage VCCq+α is used and the output PMOSFET is turned on is greater than the output (H level under the voltage VCCq) of the AND gate 2202H when the voltage VCCq+α is used and the output PMOSFET is turned on. Therefore, when the NMOS transistor 2202F receives the H level under the voltage VCCq+α in the gate, it is turned on more strongly than when the H level under the voltage VCCq is received. Therefore, the amplitude of the output signal is greater when the voltage VCCq+α is used than when the voltage VCCq is used.

[0187] When transmitting the signal LVSTL_IN2, the transmitting unit 2202 uses NMOS transistors 2202F and 2202G, AND gate 2202H, inverter 2202I, and NOR gate 2202J, similarly to the transmitting unit 1202. However, in addition to this, the voltage VCCq is supplied to the AND gate 2202H. In contrast, when transmitting the signal Legacy_IN2, the transmitting unit 2202 also uses NMOS transistors 2202F and 2202G, AND gate 2202H, inverter 2202I, and NOR gate 2202J. However, in addition to this, the voltage VCCq+α is supplied to the AND gate 2202H. That is, the components of the transmitting unit 2202 are commonly used not only when transmitting the signal LVSTL_IN2 but also when transmitting the signal Legacy_IN2.

[0188] AND gate 2202H receives not only signal OUTEN1 but also signal OUTEN2 from enable signal generating circuit 204. As described above, when signal OUTEN1 is at a high level, signal OUTEN2 is at a low level, and when signal OUTEN1 is at a low level, signal OUTEN2 is at a high level. Since signal OUTEN1 and signal OUTEN2 are not at a high level at the same time, inverter 202I can receive both signal OUTEN1 and signal OUTEN2. That is, AND gate 2202H can be used in common in both cases of transmitting signal Legacy_IN2 and transmitting signal LVSTL_IN2.

[0189] As described above, the transmitter 2202 uses all the components of the LVSTL transmitter 202Y in common, thereby eliminating the legacy transmitter 202X. Since the legacy transmitter 202X can be eliminated, the transmitter 2202 can reduce the circuit area compared to the transmitters 202 and 1202.

[0190] Fig.13 This is a circuit diagram showing a configuration example of the receiving unit 301 of the semiconductor storage device 200 according to the first embodiment. Fig.13 express Figure 5 Detailed circuit structure of the receiving unit 301 shown in FIG. As described above, the receiving unit 301 performs operations related to the reception of the signal DQ based on the enable signals INEN1 and INEN2. The receiving unit 301 receives the signal Legacy_IN2 or the signal LVSTL_IN2 transmitted from the transmitting unit 202. When the transmitting unit 202 transmits the signal Legacy_IN2, the enable signal generating circuit 304 transmits the high-level enable signal INEN1 and the low-level enable signal INEN2 to the receiving unit 301. In addition, when the transmitting unit 202 transmits the signal LVSTL_IN2, the enable signal generating circuit 304 transmits the low-level enable signal INEN1 and the high-level enable signal INEN2 to the receiving unit 301.

[0191] The receiving unit 301 includes a legacy receiving unit 301X, an LVSTL receiving unit 301Y, and a selector 301C. The receiving unit 301 can select to use the legacy receiving unit 301X or the LVSTL receiving unit 301Y based on the type of the signal received from the transmitting unit 202. Specifically, when the transmitting unit 202 transmits the signal Legacy_IN2, the receiving unit 301 uses the legacy receiving unit 301X to receive the signal Legacy_IN2. In addition, when the transmitting unit 202 transmits the signal LVSTL_IN2, the receiving unit 301 uses the LVSTL receiving unit 301Y to receive the signal LVSTL_IN2.

[0192] The legacy receiving section 301X includes a differential amplifier circuit 301A. The differential amplifier circuit 301A receives a signal Legacy_IN2 from a first input terminal. A reference voltage VREFq1 is applied to a second input terminal of the differential amplifier circuit 301A. The differential amplifier circuit 301A receives an enable signal INEN1 from an enable signal generating circuit 304. When the enable signal INEN1 is at a high level, the differential amplifier circuit 301A becomes enabled. The differential amplifier circuit 301A differentially amplifies the received signal Legacy_IN2 and the reference voltage VREFq1 to generate a signal Legacy_OUT2. The output terminal of the differential amplifier circuit 301A sends the signal Legacy_OUT2 to the selector 301C. The details of the differential amplifier circuit 301A are described below.

[0193] The LVSTL receiving section 301Y includes a differential amplifier circuit 301B. The differential amplifier circuit 301B receives a signal LVSTL_IN2 from a first input terminal. A reference voltage VREFq2 is applied to a second input terminal of the differential amplifier circuit 301B. The differential amplifier circuit 301B receives an enable signal INEN2 from an enable signal generating circuit 304. When the enable signal INEN2 is at a high level, the differential amplifier circuit 301B becomes enabled. The differential amplifier circuit 301B differentially amplifies the received signal LVSTL_IN2 and the reference voltage VREFq2 to generate a signal LVSTL_OUT2. The output terminal of the differential amplifier circuit 301B sends the signal LVSTL_OUT2 to the selector 301C. The details of the differential amplifier circuit 301B are described below.

[0194] The selector 301C receives the signal Legacy_OUT2 and the signal LVSTL_OUT2. The selector 301C receives the enable signals INEN1 and INEN2 from the enable signal generating circuit 304. When the enable signal INEN1 is at a high level, the selector 301C outputs the received signal Legacy_OUT2 to other elements in the memory controller 300. When the enable signal INEN2 is at a high level, the selector 301C outputs the received signal LVSTL_OUT2 to other elements in the memory controller 300.

[0195] In this way, the receiving unit 301 switches which of the legacy receiving unit 301X and the LVSTL receiving unit 301Y generates the DQ signal according to the type of the signal DQ sent by the sending unit 202. In order to perform the switching, the low level and high level of the enable signals INEN1 and INEN2 are adjusted. In other words, the receiving unit 301 has two receiving methods, and which transmission method is selected is determined according to the type of the signal DQ.

[0196] The output signal LVSTL_OUT2 when the LVSTL receiving unit 301Y is used is a signal based on the signal LVSTL_IN2 and therefore has a smaller amplitude than the output signal Legacy_OUT2 (a signal based on the signal Legacy_IN2) when the legacy receiving unit 301X is used.

[0197] Next, the circuit structure of the receiving unit 201 will be described. Fig.14 This is a circuit diagram showing a configuration example of the receiving unit 201 of the semiconductor storage device 200 according to the first embodiment. Fig.14 express Figure 5 The detailed circuit structure of the receiving unit 201 is described above. As described above, the receiving unit 201 performs operations related to the reception of the signal DQ based on the enable signals INEN1 and INEN2. The receiving unit 201 has the same structure and function as the receiving unit 301.

[0198] The receiving section 201 receives the signal Legacy_IN1 or the signal LVSTL_IN1 transmitted from the transmitting section 302. When the transmitting section 302 transmits the signal Legacy_IN1, the enable signal generating circuit 204 transmits the high-level enable signal INEN1 and the low-level enable signal INEN2 to the receiving section 201. In addition, when the transmitting section 302 transmits the signal LVSTL_IN1, the enable signal generating circuit 204 transmits the low-level enable signal INEN1 and the high-level enable signal INEN2 to the receiving section 201.

[0199] The receiving unit 201 includes a legacy receiving unit 201X, an LVSTL receiving unit 201Y, and a selector 201C. The receiving unit 201 can select to use the legacy receiving unit 201X or the LVSTL receiving unit 201Y based on the type of the signal received from the transmitting unit 302. Specifically, when the transmitting unit 302 transmits the signal Legacy_IN1, the receiving unit 201 uses the legacy receiving unit 201X to receive the signal Legacy_IN1. In addition, when the transmitting unit 302 transmits the signal LVSTL_IN1, the receiving unit 201 uses the LVSTL receiving unit 201Y to receive the signal LVSTL_IN1.

[0200] The legacy receiving section 201X includes a differential amplifier circuit 201A. The differential amplifier circuit 201A receives a signal Legacy_IN1 from a first input terminal. A reference voltage VREFq1 is applied to a second input terminal of the differential amplifier circuit 201A. The differential amplifier circuit 201A receives an enable signal INEN1 from an enable signal generating circuit 204. When the enable signal INEN1 is at a high level, the differential amplifier circuit 201A becomes enabled. The differential amplifier circuit 201A differentially amplifies the received signal Legacy_IN1 and the reference voltage VREFq1 to generate a signal Legacy_OUT1. The output terminal of the differential amplifier circuit 201A sends the signal Legacy_OUT1 to the selector 201C. The details of the differential amplifier circuit 201A are described below.

[0201] The LVSTL receiving section 201Y includes a differential amplifier circuit 201B. The differential amplifier circuit 201B receives a signal LVSTL_IN1 from a first input terminal. A reference voltage VREFq2 is applied to a second input terminal of the differential amplifier circuit 201B. The differential amplifier circuit 201B receives an enable signal INEN2 from an enable signal generating circuit 204. When the enable signal INEN2 is at a high level, the differential amplifier circuit 201B becomes enabled. The differential amplifier circuit 201B differentially amplifies the received signal LVSTL_IN1 and the reference voltage VREFq2 to generate a signal LVSTL_OUT1. The output terminal of the differential amplifier circuit 201B sends the signal LVSTL_OUT1 to the selector 201C. The details of the differential amplifier circuit 201B are described below.

[0202] The selector 201C receives the signal Legacy_OUT1 and the signal LVSTL_OUT1. The selector 201C receives the enable signals INEN1 and INEN2 from the enable signal generating circuit 204. When the enable signal INEN1 is at a high level, the selector 201C outputs the received signal Legacy_OUT1 to the latch circuit 206. When the enable signal INEN2 is at a high level, the selector 201C outputs the received signal LVSTL_OUT1 to the latch circuit 206.

[0203] In this way, the receiving unit 201 switches to receive the DQ signal with either the legacy receiving unit 201X or the LVSTL receiving unit 201Y according to the type of the signal DQ sent by the transmitting unit 302. To perform the switching, the low level and high level of the enable signals INEN1 and INEN2 are adjusted. That is, the receiving unit 201 has two receiving methods, and which receiving method is selected is determined according to the type of the signal DQ.

[0204] The output signal LVSTL_OUT1 when the LVSTL receiving unit 201Y is used is a signal based on the signal LVSTL_IN1, and therefore has a smaller amplitude than the output signal Legacy_OUT1 (a signal based on the signal Legacy_IN1) when the legacy receiving unit 201X is used. The receiving units 212 to 214, 221, 306, and 307 have the same configuration and function as the receiving units 201 and 301, and therefore their description is omitted.

[0205] Fig.14 The circuit diagrams of the receiving unit 301 and the receiving unit 201 shown in FIG. 1 are examples of the configuration. Therefore, the receiving unit 301 and the receiving unit 201 only need to have the same Fig.14 Here, the receiving unit of the semiconductor memory device 200 of the first embodiment has functions including having two receiving methods and determining which receiving method to select according to the type of the signal DQ.

[0206] Fig.15 This is a circuit diagram showing a configuration example of the differential amplifier circuit 201A of the receiving unit 201 according to the first embodiment. Fig.15 express Fig.14 The detailed circuit structure of the differential amplifier circuit 201A is shown below. Fig.13 The differential amplifier circuits 301A and 301B, and Fig.14 The differential amplifier circuit 201B has the same structure and function as the differential amplifier circuit 201A. Therefore, only the differential amplifier circuit 201A will be described below as a representative example.

[0207] As described above, the differential amplifier circuit 201A differentially amplifies the signal Legacy_IN1 and the reference voltage VREFq1 based on the enable signal INEN1, and outputs the signal as the signal Legacy_OUT1. The differential amplifier circuit 201A includes: PMOS transistors 201a, 201b, 201c and 201d, NMOS transistors 201e, 201f and 201g, and an inverter circuit group 201h. The differential amplifier circuit 201A may further include a logic circuit such as a NAND gate and an inverter as long as the same signal logic is obtained.

[0208] The first terminals of the PMOS transistors 201a and 201b are electrically connected to a node of a power supply voltage VCCq. The control terminals of the PMOS transistors 201a and 201b are connected to an enable signal generating circuit 204 to receive an enable signal INEN1.

[0209] The second terminals of the PMOS transistors 201a and 201b are connected to the first terminals of the PMOS transistors 201c and 201d, respectively. The control terminal of the PMOS transistor 201c is connected to the control terminal of the PMOS transistor 201d. The control terminals of the PMOS transistors 201c and 201d are connected to the second terminal of the PMOS transistor 201c. The second terminal of the PMOS transistor 201c is connected to the first terminal of the NMOS transistor 201e. The second terminal of the PMOS transistor 201d is connected to the first terminal of the NMOS transistor 201f. The reference voltage generating circuit 205 is connected to the control terminal of the NMOS transistor 201e, and the reference voltage VREFq1 is applied thereto. The control terminal of the NMOS transistor 201f is connected to the node DQI, and receives the signal Legacy_IN1.

[0210] The second terminals of the NMOS transistors 201e and 201f are connected to the first terminal of the NMOS transistor 201g. A bias voltage Vbias is applied to the control terminal of the NMOS transistor 201g. The bias voltage Vbias is a voltage that turns on the NMOS transistor 201g. The second terminal of the NMOS transistor 201g is connected to a node of the ground voltage VSSq. The second terminal of the PMOS transistor 201d and the first terminal of the NMOS transistor 201f are connected to the input terminal of the inverter circuit group 201h. The output terminal of the inverter circuit group 201h is connected to the latch circuit 206, and the signal Legacy_OUT1 is sent.

[0211] The differential amplifier circuit 201A is enabled by receiving the high-level enable signal INEN1, and differentially amplifies the signal Legacy_IN1 and the reference voltage VREFq1. The inverter circuit group 201h shapes the waveform of the differentially amplified signal and outputs the signal Legacy_OUT1.

[0212] exist Fig.16 Except for Fig.13 and Fig.14 Specific examples of applicable structures other than the structure. Fig.16 1 is a circuit diagram showing a configuration example of a receiving unit of the semiconductor storage device 200 according to the first embodiment. Fig.14 As described above, the receiving unit 201 has the same structure and function as the receiving unit 301. Therefore, only the receiving unit 201 will be described below as a representative example.

[0213] exist Fig.16 An example of the structure of the receiving unit 201 is shown in FIG. Fig.16 The receiving unit 201 shown is for Fig.14The receiving unit 1201 is distinguished from the receiving unit 201 and is referred to as the receiving unit 1201. Hereinafter, the receiving unit 1201 will be mainly described with respect to the differences from the receiving unit 201.

[0214] The receiving unit 1201 has two receiving methods similar to the receiving unit 201, and the receiving method is selected based on the type of the received signal DQ. The selection of the receiving method is based on the level of the enable signal INEN1 or INEN2. Here, the signal Legacy_IN1 output from the receiving unit 1201 based on the enable signal INEN1 is referred to as the signal Legacy_OUT1. The signal LVSTL_IN1 output from the receiving unit 1201 based on the enable signal INEN2 is referred to as the signal LVSTL_OUT1.

[0215] The receiving section 1201 receives the signal Legacy_IN1 or the signal LVSTL_IN1 transmitted from the transmitting section 302. When the transmitting section 302 transmits the signal Legacy_IN1, the enable signal generating circuit 204 transmits the high-level enable signal INEN1 and the low-level enable signal INEN2 to the receiving section 201. When the transmitting section 302 transmits the signal LVSTL_IN1, the enable signal generating circuit 204 transmits the low-level enable signal INEN1 and the high-level enable signal INEN2 to the receiving section 201.

[0216] The receiving unit 1201 includes a differential amplifier circuit 1201A and a selector 1201B. Since the differential amplifier circuit 1201A has the same structure and function as the differential amplifier circuit 201A, the details are omitted. The selector 1201B receives a reference voltage VREFq1 and a reference voltage VREFq2. The selector 1201B receives enable signals INEN1 and INEN2 from the enable signal generating circuit 204. When the enable signal INEN1 is at a high level, the selector 1201B outputs the received reference voltage VREFq1 to the second input terminal of the differential amplifier circuit 1201A. When the enable signal INEN2 is at a high level, the selector 1201B outputs the received reference voltage VREFq2 to the second input terminal of the differential amplifier circuit 1201A.

[0217] The differential amplifier circuit 1201A receives the signal Legacy_IN1 or the signal LVSTL_IN1 from the first input terminal. The reference voltage VREFq1 or the reference voltage VREFq2 is applied to the second input terminal of the differential amplifier circuit 1201A. The differential amplifier circuit 1201A receives the enable signals INEN1 and INEN2 from the enable signal generating circuit 204.

[0218] When the differential amplifier circuit 1201A receives the signal Legacy_IN1, the enable signal INEN1 is at a high level and the enable signal INEN2 is at a low level. When the enable signal INEN1 is at a high level, the reference voltage VREFq1 is applied to the second input terminal of the differential amplifier circuit 1201A. At this time, the differential amplifier circuit 1201A differentially amplifies the received signal Legacy_IN1 and the reference voltage VREFq1 to generate a signal Legacy_OUT1. The output terminal of the differential amplifier circuit 1201A sends the signal Legacy_OUT1 to the latch circuit 206.

[0219] When the differential amplifier circuit 1201A receives the signal LVSTL_IN1, the enable signal INEN2 is at a high level and the enable signal INEN1 is at a low level. When the enable signal INEN2 is at a high level, the reference voltage VREFq2 is applied to the second input terminal of the differential amplifier circuit 1201A. At this time, the differential amplifier circuit 1201A differentially amplifies the received signal LVSTL_IN1 and the reference voltage VREFq2 to generate a signal LVSTL_OUT1. The output terminal of the differential amplifier circuit 1201A sends the signal LVSTL_OUT1 to the latch circuit 206.

[0220] In this way, the receiving unit 1201 switches between the signal Legacy_OUT1 and the signal LVSTL_OUT1 according to the type of the signal DQ sent by the transmitting unit 302. To perform the switching, the low level and high level of the enable signals INEN1 and INEN2 are adjusted. In other words, the receiving unit 201 has two receiving methods, and which receiving method is selected is determined according to the type of the signal DQ.

[0221] Since the output signal LVSTL_OUT1 is a signal based on the signal LVSTL_IN1 , it has a smaller amplitude than the output signal Legacy_OUT1 which is a signal based on the signal Legacy_IN1 .

[0222] The receiving unit 201 has two differential amplifier circuits, and the differential amplifier circuit 201A is used when the signal Legacy_IN1 is received, and the differential amplifier circuit 201B is used when the signal LVSTL_IN1 is received. In this regard, the receiving unit 1201 can simplify the components by using the differential amplifier circuit 1201A in common when the signal Legacy_IN1 is received and when the signal LVSTL_IN1 is received. Since the enable signal INEN1 is high when the receiving unit 201 receives the signal Legacy_IN1, and the enable signal INEN2 is high when the signal LVSTL_IN1 is received, the reference voltage to be used can be selected. Since the reference voltage can be selected according to the enable signal INEN, the receiving unit 1201 can use the differential amplifier circuit 1201A in common when the signal Legacy_IN1 is received and when the signal LVSTL_IN1 is received. In this way, since some components can be removed, the circuit area of ​​the receiving unit 1201 can be smaller than that of the receiving unit 201 .

[0223] Fig.17 2 is a circuit diagram showing a configuration example of the receiving unit 201 , the latch circuit 206 , and the differential amplifier circuit 207 of the semiconductor memory device 200 according to the first embodiment. Fig.17 express Figure 6 The detailed circuit structure of the latch circuit 206 and the differential amplifier circuit 207 is shown in the figure. As described above, the latch circuit 206 stores the signal DQ received from the receiving unit 201. The latch circuit 206 transmits the signal DQ to the transmitting unit 202. In addition, the differential amplifier circuit 207 controls the latch circuit 206 based on the signals DQS and DQSn received from the receiving units 212 and 213.

[0224] First, a configuration example of the differential amplifier circuit 207 is described. The differential amplifier circuit 207 includes a first differential amplifier circuit 207A and a second differential amplifier circuit 207B. The differential amplifier circuit 207, the first differential amplifier circuit 207A, and the second differential amplifier circuit 207B may have a logic circuit such as a NAND gate, an inverter, etc. as long as they obtain the same signal logic. Fig.17 structure.

[0225] The first differential amplifier circuit 207A differentially amplifies the signal DQS and the reference voltage VREF, and outputs the signal as the signal DQSi to the latch circuit 206. The reference voltage VREF is a voltage that serves as a reference for the signal DQS.

[0226] The first differential amplifier circuit 207A includes PMOS transistors 207a and 207b, NMOS transistors 207c, 207d and 207e, and an inverter circuit group 207f. The first differential amplifier circuit 207A may further include logic circuits such as NAND gates and inverters as long as the same signal logic is obtained.

[0227] The first terminals of the PMOS transistors 207a and 207b are electrically connected to a node of a power supply voltage VCCq. The control terminal of the PMOS transistor 207a is connected to the control terminal of the PMOS transistor 207b. The control terminals of the PMOS transistors 207a and 207b are connected to the second terminal of the PMOS transistor 207a. The second terminal of the PMOS transistor 207a is connected to the first terminal of the NMOS transistor 207c. The second terminal of the PMOS transistor 207b is connected to the first terminal of the NMOS transistor 207d. A reference voltage VREF is applied to the control terminal of the NMOS transistor 207c. The control terminal of the NMOS transistor 207d is connected to the receiving unit 212 to receive the signal DQS.

[0228] The second terminals of the NMOS transistors 207c and 207d are connected to the first terminal of the NMOS transistor 207e. A bias voltage Vbias is applied to the control terminal of the NMOS transistor 207e. The bias voltage Vbias is a voltage that turns on the NMOS transistor 207e. The second terminal of the NMOS transistor 207e is connected to a node of a ground voltage VSSq. The second terminal of the PMOS transistor 207b and the first terminal of the NMOS transistor 207d are connected to the input terminal of the inverter circuit group 207f. The output terminal of the inverter circuit group 207f is connected to the latch circuit 206 to send a signal DQSi.

[0229] The first differential amplifier circuit 207A is enabled by the bias voltage Vbias, and differentially amplifies the signal DQS and the reference voltage VREF. The inverter circuit group 207f shapes the waveform of the differentially amplified signal and outputs the signal DQSi to the latch circuit 206.

[0230] Next, the second differential amplifier circuit 207B differentially amplifies the signal DQSn and the reference voltage VREF, and outputs the signal as the signal DQSni to the latch circuit 206. The reference voltage VREF is a voltage that serves as a reference for the signal DQSn. The second differential amplifier circuit 207B has the same structure and function as the first differential amplifier circuit 207A.

[0231] The second differential amplifier circuit 207B includes PMOS transistors 207g and 207h, NMOS transistors 207i, 207j and 207k, and an inverter circuit group 2071. The second differential amplifier circuit 207B may further include logic circuits such as NAND gates and inverters as long as they are logical circuits that obtain the same signal.

[0232] The first terminals of the PMOS transistors 207g and 207h are electrically connected to a node of a power supply voltage VCCq. The control terminal of the PMOS transistor 207g is connected to the control terminal of the PMOS transistor 207h. The control terminals of the PMOS transistors 207g and 207h are connected to the second terminal of the PMOS transistor 207g. The second terminal of the PMOS transistor 207g is connected to the first terminal of the NMOS transistor 207i. The second terminal of the PMOS transistor 207h is connected to the first terminal of the NMOS transistor 207j. A reference voltage VREF is applied to the control terminal of the NMOS transistor 207i. The control terminal of the NMOS transistor 207j is connected to the receiving unit 213 to receive the signal DQSn.

[0233] The second terminals of the NMOS transistors 207i and 207j are connected to the first terminal of the NMOS transistor 207k. A bias voltage Vbias is applied to the control terminal of the NMOS transistor 207k. The bias voltage Vbias is a voltage that turns on the NMOS transistor 207k. The second terminal of the NMOS transistor 207k is connected to a node of the ground voltage VSSq. The second terminal of the PMOS transistor 207h and the first terminal of the NMOS transistor 207j are connected to the input terminal of the inverter circuit group 207l. The output terminal of the inverter circuit group 207l is connected to the latch circuit 206 to send the signal DQSni. Here, since the signal DQSn is a signal that inverts the high level and the low level of the signal DQS, the signal DQSni is a signal that inverts the high level and the low level of the signal DQSi.

[0234] The second differential amplifier circuit 207B is enabled by the bias voltage Vbias, and differentially amplifies the signal DQSn and the reference voltage VREF. The inverter circuit group 2071 shapes the waveform of the differentially amplified signal and outputs the signal DQSni to the latch circuit 206.

[0235] Next, a configuration example of the latch circuit 206 is described. The latch circuit 206 includes inverters INV1 and INV2, and a first latch circuit L1 and a second latch circuit L2. The latch circuit 206 may have a logic circuit such as a NAND gate, an inverter, etc., as long as the same signal logic is obtained. Fig.17 structure.

[0236] The inverter INV1 includes PMOS transistors 206a and 206b, and NMOS transistors 206c and 206d. The PMOS transistors 206a and 206b, and the NMOS transistors 206c and 206d are connected in series. The first end of the PMOS transistor 206a is connected to the node of the power supply voltage VCCq. The first end of the PMOS transistor 206b is connected to the second end of the PMOS transistor 206a. The first end of the NMOS transistor 206c is connected to the second end of the PMOS transistor 206b. The first end of the NMOS transistor 206d is connected to the second end of the NMOS transistor 206c. The second end of the NMOS transistor 206d is connected to the node of the ground voltage VSSq. The second end of the PMOS transistor 206b and the first end of the NMOS transistor 206c are connected to the first latch circuit L1.

[0237] The control terminals of the PMOS transistor 206a and the NMOS transistor 206d are connected to the receiving unit 201 to receive the signal Legacy_OUT1 or the signal LVSTL_OUT1. The control terminal of the PMOS transistor 206b is connected to the output terminal of the inverter circuit group 2071 of the second differential amplifier circuit 207B to receive the signal DQSni. The control terminal of the NMOS transistor 206c is connected to the output terminal of the inverter circuit group 207f of the first differential amplifier circuit 207A to receive the signal DQSi.

[0238] The first latch circuit L1 includes an inverter 206e and a clock inverter 206f. The inverter 206e and the clock inverter 206f are cross-connected. The input terminal of the inverter 206e and the output terminal of the clock inverter 206f are connected to the output terminal of the inverter INV1. The output terminal of the inverter 206e is connected to the input terminal of the clock inverter 206f. The clock inverter 206f switches the inverter output state and the inverter output stop state according to the signals DQSi and DQSni. When the clock inverter 206f is in the inverter output state, a signal of the inverted logic level of the signal input to the input terminal is output from the output terminal. When the clock inverter 206f is in the inverter output stop state, no signal is output from the output terminal regardless of the logic level of the signal input to the input terminal.

[0239] The inverter INV2 includes PMOS transistors 206g and 206h, and NMOS transistors 206i and 206j. The PMOS transistors 206g and 206h, and the NMOS transistors 206i and 206j are connected in series. The first end of the PMOS transistor 206g is connected to the node of the power supply voltage VCCq. The first end of the PMOS transistor 206h is connected to the second end of the PMOS transistor 206g. The first end of the NMOS transistor 206i is connected to the second end of the PMOS transistor 206h. The first end of the NMOS transistor 206j is connected to the second end of the NMOS transistor 206i. The second end of the NMOS transistor 206j is connected to the node of the ground voltage VSSq. The second end of the PMOS transistor 206h and the first end of the NMOS transistor 206i are connected to the second latch circuit L2.

[0240] The control terminals of the PMOS transistor 206g and the NMOS transistor 206j are connected to the receiving unit 201 to receive the signal Legacy_OUT1 or the signal LVSTL_OUT1. The control terminal of the PMOS transistor 206h is connected to the output terminal of the inverter circuit group 207f of the first differential amplifier circuit 207A to receive the signal DQSi. The control terminal of the NMOS transistor 206i is connected to the output terminal of the inverter circuit group 207l of the second differential amplifier circuit 207B to receive the signal DQSni.

[0241] The second latch circuit L2 includes an inverter 206k and a clock inverter 206l. The inverter 206k and the clock inverter 206l are cross-connected. The input end of the inverter 206k and the output end of the clock inverter 206l are connected to the output end of the inverter INV2. The output end of the inverter 206k is connected to the input end of the clock inverter 206l. The clock inverter 206l has the same function as the clock inverter 206f.

[0242] The behavior of the latch circuit 206 when the signal DQSi is at a high level is described below. The inversion signal of the signal DQSi, that is, the signal DQSni, is at a low level. At this time, the control terminals of the NMOS transistor 206c and the PMOS transistor 206h receive the high-level signal DQSi. The control terminals of the PMOS transistor 206b and the NMOS transistor 206i receive the low-level signal DQSni. Therefore, the PMOS transistor 206b and the NMOS transistor 206c of the inverter INV1 become conductive, and the signal Legacy_OUT1 or the signal LVSTL_OUT1 received by the PMOS transistor 206b and the NMOS transistor 206c passes through the inverter INV1. The signal passing through the inverter INV1 is held by the first latch circuit L1.

[0243] In addition, the PMOS transistor 206h and the NMOS transistor 206i of the inverter INV2 are turned off, and the signal Legacy_IN1 or the signal LVSTL_OUT1 received by the PMOS transistor 206g and the NMOS transistor 206j cannot pass through the inverter INV2.

[0244] On the other hand, the behavior of the latch circuit 206 when, for example, the signal DQSi is at a low level is described. The signal DQSni, which is an inversion signal of the signal DQSi, is at a high level. At this time, the control terminals of the NMOS transistor 206c and the PMOS transistor 206h receive the low-level signal DQSi. The control terminals of the PMOS transistor 206b and the NMOS transistor 206i receive the high-level signal DQSni. Therefore, the PMOS transistor 206h and the NMOS transistor 206i of the inverter INV2 become conductive, and the signal Legacy_OUT1 or the signal LVSTL_OUT1 received by the PMOS transistor 206g and the NMOS transistor 206j passes through the inverter INV2. The signal passing through the inverter INV2 is held by the second latch circuit L2.

[0245] In addition, the PMOS transistor 206 b and the NMOS transistor 206 c of the inverter INV1 are turned off, and the signal Legacy_OUT1 or the signal LVSTL_OUT1 received by the PMOS transistor 206 a and the NMOS transistor 206 d cannot pass through the inverter INV1 .

[0246] In this way, the AND latch circuit 206 can store the signal LVSTL_OUT1 or the signal Legacy_OUT1 based on the signals DQSi and DQSni shaped by the differential amplifier circuit 207 .

[0247] [1-2] Action

[0248] The transmission and reception method and the termination method of the semiconductor storage device 200 are based on the NAND chip A 200A (described in Figure 2 However, NAND chip B 200B, NAND chip C 200C, and NAND chip D 200D also have the same sending and receiving method and termination method.

[0249] As described above, when NAND chip A 200A is selected (when NAND chip A 200A is the selected NAND chip), the terminal circuit of NAND chip A 200A can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In the first embodiment, an example of the case where the selected NAND chip is NAND chip A 200A and the terminal circuit of NAND chip A 200A is enabled is described.

[0250] Here, NAND chip A 200A and NAND chip B 200B are chips that receive chip enable signal CEn1 and transmit signal RBn1, while NAND chip C 200C and NAND chip D 200D are chips that receive chip enable signal CEn2 and transmit signal RBn2.

[0251] The termination method when the semiconductor storage device 200 and the memory controller 300 according to the first embodiment receive a DQ signal will be described. Fig.18 FIG. 2 shows a method of terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the first embodiment. Fig.18 As shown, the termination circuit 303 terminates the node DQO when the receiving section 301 receives the signal LVSTL_IN2. The termination circuit 303 does not terminate the node DQO when the receiving section 301 receives the signal Legacy_IN2.

[0252] In addition, the termination circuit 203 terminates the node DQI when the receiving section 201 receives the signal LVSTL_IN1. The termination circuit 203 does not terminate the node DQI when the receiving section 201 receives the signal Legacy_IN1.

[0253] As described so far, the semiconductor memory device 200 of the first embodiment has two methods for transmitting the signals DQ, DQS, and DQSn, and two methods for receiving the signals DQ, DQS, DQSn, REn, and RE, respectively, and which method for transmitting and receiving is selected is determined according to the type of the signal DQ. In addition, the semiconductor memory device 200 can select a termination method according to the transmission and reception method. For the termination of the node DQI, the termination circuit 203 of the NAND chip A 200A is used. Similarly, the memory controller 300 of the first embodiment has two methods for transmitting the signals DQ, DQS, DQSn, REn, and RE, respectively, and two methods for receiving the signals DQ, DQS, and DQSn, respectively, and which method for transmitting and receiving is selected is determined according to the type of the signal DQ. In addition, the memory controller 300 can select a termination method according to the transmission and reception method.

[0254] Here, as an example, the types of signal DQ include six types: instruction or address, state, parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput). The state is sent in response to the state read instruction, and is information about a specific state of the semiconductor memory device 200. The parallel state is sent in response to the parallel state read instruction, and is information about the state of each of the multiple NAND chips. Feature data (FeatureData) is information about the setting parameters inside the NAND chip. The feature data (FeatureData) as the setting parameters is sent together with the set feature (SetFeature) instruction. Below, the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the case of sending and receiving these six types of signals DQ are described.

[0255] Fig.19 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.19 Of the signals DQS and DQSn, the signal DQS is shown, but the signal DQSn is a signal of inverted logic of the signal DQS and is therefore the same as the signal DQS. Fig.19 The signal RE of the signals REn and RE is shown, but the signal REn is a signal of the inverted logic of the signal RE, and therefore is the same as the signal RE. Fig.18 As described above, in the first embodiment, in the semiconductor storage device 200, only the termination circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A 200A of the selected NAND chip are used as the termination circuit. Fig.19 As shown, when the type of signal DQ is a command or an address, the signal Legacy_IN1 is sent from the memory controller 300 as the signal DQ and received by the NAND chip A 200A and the NAND chip B 200B. In addition, the signals DQS and RE sent from the memory controller 300 are fixed to a low level.

[0256] Next, when the type of the signal DQ is the state, as the signal DQ, the signal Legacy_IN2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. Also, as the signal DQS, the signal Legacy_DQS2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. Also, as the signal RE, the signal Legacy_RE1 is transmitted from the memory controller 300 and is received by the NAND chip A 200A.

[0257] Next, when the type of the signal DQ is in the parallel state, as the signal DQ, the signal Legacy_IN2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. Also, as the signal DQS, the signal Legacy_DQS2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. Also, as the signal RE, the signal Legacy_RE1 is transmitted from the memory controller 300, and is received by the NAND chip A 200A and the NAND chip B 200B.

[0258] Next, when the type of the signal DQ is feature data (FeatureData), as the signal DQ, the signal LVSTL_IN1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuit 203 of the NAND chip A 200A terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuits 218 and 219 of the NAND chip A 200A terminate the nodes DQSI and DQSnI. In addition, the signal sent from the memory controller 300 as the signal RE is fixed to a low level.

[0259] Next, when the type of the signal DQ is data output (DataOutput), as the signal DQ, the signal LVSTL_IN2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. At this time, the termination circuit 303 of the memory controller 300 terminates the node DQO. In addition, as the signal DQS, the signal LVSTL_DQS2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. At this time, the termination circuits 312 and 313 of the memory controller 300 terminate the nodes DQS0 and DQSnO. In addition, as the signal RE, the signal LVSTL_RE1 is transmitted from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuits 220 and 222 of the NAND chip A 200A terminate the nodes REnI and REI.

[0260] Next, when the type of the signal DQ is data input (DataInput), as the signal DQ, the signal LVSTL_IN1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuit 203 of the NAND chip A 200A terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuits 218 and 219 of the NAND chip A 200A terminate the nodes DQSI and DQSnI. In addition, the signal sent from the memory controller 300 as the signal RE is fixed to a low level.

[0261] like Fig.19 As described above, the memory controller 300 and / or the semiconductor memory device 200 of the first embodiment terminates each node when the types of the signal DQ are feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of enabling the termination circuit.

[0262] Fig. 20 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment. Fig. 20 Indicates the timing at which the terminal circuit becomes enabled when the type of signal DQ is feature data (FeatureData). Fig. 20 , a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is shown. Fig. 20 In the following figures, the signals REn and DQS are indicated by solid lines, and the signals RE and DQSn are indicated by dotted lines. In addition, the oblique line portion (shaded area) in the figure indicates a "don't care" value that is not particularly defined.

[0263] At time t1, the memory controller 300 sets the signal CEn1 to a low level. As a result, the NAND chip A 200A and the NAND chip B 200B are enabled. During a period including time t2, the memory controller 300 sets the signal CLE to a high level and sends a SetFeature command D5h as a signal DQ. Accompanying the sending of the SetFeature command D5h, at time t2, the memory controller 300 sets the signal WEn to a high level.

[0264] During the period including time t3 and time t4, the memory controller 300 sets the signal ALE to a high level, and transmits the address ADD specifying the target of the SetFeature instruction as the signal DQ for, for example, two cycles. Along with the transmission of the address ADD, the memory controller 300 sets the signal WEn to a high level at time t3 and time t4. At time t5, the memory controller 300 sets the signal DQS to a low level.

[0265] During a plurality of periods including time t6, t7, t8, and t9, the memory controller 300 transmits parameters W-B0, W-B1, W-B2, and W-B3 set according to feature data (FeatureData) of the signal DQ. Along with the transmission of the parameters W-B0, W-B1, W-B2, and W-B3, the memory controller 300 sets the signal DQS to a high level at time t6, t7, t8, and t9.

[0266] At time t10, the memory controller 300 sets the signal CEn1 to a high level, thereby disabling the NAND chip A 200A and the NAND chip B 200B.

[0267] At time t5, the NAND chip A 200A enables the terminal circuits 203, 218, and 219 of the NAND chip A 200A, and at time t10, disables the terminal circuits 203, 218, and 219. That is, the terminal circuits 203, 218, and 219 terminate the nodes DQI, DQSI, and DQSnI, respectively, i.e., the time when the terminal circuits 203, 218, and 219 become enabled is between time t5 and time t10. For example, when the NAND chip A 200A receives the SetFeature command D5h and the subsequent address ADD during the period when the signal CEn1 is at a low level, the terminal circuits 203, 218, and 219 are enabled based on the signal ALE becoming a low level. Furthermore, after receiving the parameters W-B0, W-B1, W-B2, and W-B3, the NAND chip A 200A disables the termination circuits 203, 218, and 219 based on the signal CEn1 becoming a high level.

[0268] Fig.21 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment. Fig.21 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is data output (DataOutput). Fig.21 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0269] At time t1, the memory controller 300 sets the signal CEn1 to a low level. As a result, the NAND chip A 200A and the NAND chip B 200B are enabled. During a period including time t2, the memory controller 300 sets the signal CLE to a high level and sends a read command 00h as the signal DQ. Along with the sending of the read command 00h, at time t2, the memory controller 300 sets the signal WEn to a high level.

[0270] During the period including time t3 to t7, the memory controller 300 sets the signal ALE to a high level. In addition, during a plurality of periods including time t3 to t7, the memory controller 300 sends an address ADD as a signal DQ. The address ADD specifies the object of data read. Along with the sending of the address ADD, the memory controller 300 sets the signal WEn to a high level during time t3 to t7.

[0271] During a period including t8, the memory controller 300 sets the signal CLE to a high level and transmits a read execution command 30h as the signal DQ. This starts reading. With the transmission of the read execution command 30h, at time t8, the memory controller 300 sets the signal WEn to a high level.

[0272] As the reading starts, at time t9, the memory controller 300 sets the signal REn to a low level. Then, the memory controller 300 periodically sets the signal REn to a low level, and in response, the semiconductor memory device 200 outputs the read data D as the signal DQ. In parallel with the output of the read data D, the semiconductor memory device 200 periodically sets the signal DQS to a high level.

[0273] When the output of the read data is completed, at time t10, the memory controller 300 sets the signal CEn1 to a high level, thereby disabling the NAND chip A 200A and the NAND chip B 200B.

[0274] The memory controller 300 enables the termination circuits 303, 312, and 313 of the memory controller 300 at time t9, and disables the termination circuits 303, 312, and 313 at time t10. That is, the termination circuits 303, 312, and 313 terminate the nodes DQO, DQS0, and DQSnO, respectively, i.e., the termination circuits 303, 312, and 313 become enabled between time t9 and time t10. For example, the memory controller 300 sets the signal REn to a low level after the read execution instruction 30h is sent, and enables the termination circuits 303, 312, and 313. Furthermore, the memory controller 300 sets the signal CEn1 to a high level after the reception of the read data D is completed, and disables the termination circuits 303, 312, and 313.

[0275] The NAND chip A 200A enables the terminal circuits 220 and 222 at time t9, and disables the terminal circuits 220 and 222 at time t10. That is, the terminal circuits 220 and 222 of the NAND chip A 200A terminate the nodes REnI and REI, respectively, i.e., the time when the terminal circuits 220 and 222 of the NAND chip A 200A become enabled is between time t9 and time t10. For example, the NAND chip 200A enables the terminal circuits 220 and 222 based on the signal REn becoming low after receiving the read execution command 30h while the signal CEn1 is at a low level. Furthermore, the NAND chip 200A disables the terminal circuits 220 and 222 based on the signal CEn1 becoming high.

[0276] Fig. 22 This is an example of a timing chart of signals in the memory system 100 according to the first embodiment. Fig. 22 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is data input (DataInput). Fig. 22 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0277] At time t1, the memory controller 300 sets the signal CEn1 to a low level. As a result, the NAND chip A 200A and the NAND chip B 200B are enabled. During a period including time t2, the memory controller 300 sets the signal CLE to a high level and sends a write command 80h as the signal DQ. Along with the sending of the write command 80h, at time t2, the memory controller 300 sets the signal WEn to a high level.

[0278] During the period including time t3 to t7, the memory controller 300 sets the signal ALE to a high level. In addition, during multiple periods including time t3 to t7, the memory controller 300 sends the address ADD as the signal DQ. The address ADD specifies the destination of the write data. Along with the sending of the address ADD, the memory controller 300 sets the signal WEn to a high level during time t3 to t7.

[0279] At time t8, the memory controller 300 sets the signal DQS to a low level. Then, the memory controller 300 sends the write data D as the signal DQ. In parallel with the sending of the write data D, the memory controller 300 periodically sets the signal DQS to a high level. When the sending of the write data is completed, the memory controller 300 sets the signal CLE to a high level at time t9, and then sends a write execution instruction 10h as the signal DQ. The status data (status) Status Out is sent.

[0280] At time t10, the memory controller 300 sets the signal CEn1 to a high level, thereby disabling the NAND chip A 200A and the NAND chip B 200B.

[0281] At time t8, the NAND chip A 200A enables the terminal circuits 203, 218, and 219 of the NAND chip A 200A, and at time t9, disables the terminal circuits 203, 218, and 219. That is, the time when the terminal circuits 203, 218, and 219 terminate the nodes DQI, DQSI, and DQSnI, respectively, that is, the time when the terminal circuits 203, 218, and 219 become enabled is between time t8 and time t9. For example, when the NAND chip A 200A receives the write command 80h and all the addresses ADD during the period when the signal CEn1 is at a low level, the terminal circuits 203, 218, and 219 are enabled based on the signal DQS becoming a low level. Furthermore, after receiving all the write data D, the NAND chip A 200A disables the terminal circuits 203, 218, and 219 based on the signal CLE becoming a high level.

[0282] The above timing chart summarizes the timing at which the terminal circuit of the memory system 100 of the first embodiment becomes enabled. The timing at which the terminal circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A 200A are enabled is determined by the memory controller 300 based on the combination of the signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ, and an instruction is issued to the NAND chip A 200A. Therefore, a dedicated instruction or the like for enabling the terminal circuit is not used.

[0283] [1-3] Advantages (Effects)

[0284] According to the memory system 100 of the first embodiment described above, the semiconductor storage device 200 has two transmission methods and two reception methods, and the memory controller 300 has two transmission methods and two reception methods. The memory system 100 can select a more appropriate transmission and reception method based on the type of the signal DQ. In addition, a signal with a small amplitude among the received signals can be terminated. The following describes the detailed effects of the memory system 100 of the first embodiment.

[0285] In NAND, in order to speed up the data transmission through the NAND bus, it is useful to use a signal with a small amplitude to transmit data. As one of the methods, a termination method such as LVSTL can be used. However, when using a termination method such as LVSTL, a sending unit and a receiving unit that can send and receive signals with a small amplitude are required. On the other hand, there is also a requirement to use a small amplitude signal for the transmission and reception of data output (DataOutput) and the like that is transmitted and received at high speed (high frequency), but for the transmission and reception of instructions and addresses that are not transmitted and received at such high speed, a large amplitude signal is intended to be used to ensure the reliability of the signal.

[0286] In this regard, the memory system 100 of the first embodiment includes the transmitting units 202 and 302 and the receiving units 201 and 301 that can transmit and receive both the DQ signal with a large amplitude and the DQ signal with a small amplitude. As a result, the memory system 100 of the first embodiment can select to transmit and receive the signal with a large amplitude or the signal with a small amplitude according to the type of the signal DQ. Specifically, the memory system 100 transmits and receives the signal with a small amplitude in the type of signal DQ that must be transmitted and received at a high speed (high frequency) (for example, feature data (FeatureData), data output (DataOutput), and data input (DataInput)), and transmits and receives the signal with a high reliability and a large amplitude in the type of signal DQ that is not obstructed even at a low speed (low frequency) (for example, command or address, status, and parallel status).

[0287] In addition, the memory system 100 includes a transceiver that can transmit and receive signals with small amplitudes, and can use an LVSTL termination circuit. When receiving a signal with small amplitude, the memory system 100 can adjust the impedance of the node receiving the signal by enabling the LVSTL termination circuit. By enabling the LVSTL termination circuit, the memory system 100 can further reduce the amplitude of the signal and perform higher-speed transmission and reception. In addition, since the LVSTL (low voltage swing terminated logic) termination circuit can suppress the through current at the time of termination, it can suppress power consumption compared with the legacy termination circuit such as the CTT (center tapped termination) method or the POD (pseudo open drain) method.

[0288] [2] Second Embodiment

[0289] Hereinafter, a memory controller 300 and a semiconductor storage device 200 according to the second embodiment will be described.

[0290] [2-1] Composition (Structure)

[0291] As described above, the memory controller 300 of the first embodiment has two transmission methods and two reception methods, and the semiconductor storage device 200 has two transmission methods and two reception methods. In contrast, the memory controller 300 of the second embodiment has two transmission methods and one reception method, and the semiconductor storage device 200 has one transmission method and two reception methods. In other respects, the second embodiment is substantially the same as the first embodiment.

[0292] Specifically, the configurations of the transmission units 202, 215, and 216, and the reception units 301, 306, and 307 of the memory system 100 of the second embodiment are different from those of the first embodiment. The transmission units 202, 215, and 216, and the reception units 301, 306, and 307 of the second embodiment are respectively referred to as transmission units 202_B, 215_B, and 216_B, and reception units 301_B, 306_B, and 307_B to distinguish them from the transmission units 202, 215, and 216, and the reception units 301, 306, and 307 of the first embodiment. The configurations of the transmission units 302, 309 to 311, and 314, and the reception units 201, 212 to 214, and 221 of the memory system 100 of the second embodiment are the same as those of the first embodiment, and thus description thereof is omitted. Hereinafter, the differences between the memory system 100 of the second embodiment and the first embodiment will be mainly described.

[0293] [2-1-1] Circuit structure of memory system

[0294] Fig.23 It is a circuit diagram showing a configuration example of the transmission unit 202_B of the semiconductor memory device 200 according to the second embodiment. Fig.23 express Figure 6 The detailed circuit structure of the second embodiment of the transmitting unit 202 is described above. The transmitting unit 202_B controls the voltage of the node DQI based on the signal transmitted as the signal DQ, similarly to the transmitting unit 202. Hereinafter, the signal transmitted by the transmitting unit 202_B as the signal DQ is referred to as the signal IN2.

[0295] The transmission section 202_B is different from the transmission section 202 and has only one transmission method. It transmits a signal with a small amplitude regardless of the type of the received signal DQ (described below). Therefore, the enable signal received by the transmission section 202_B from the enable signal generating circuit 204 is also one type, and the signal is transmitted based on the enable signal OUTEN. Here, the signal IN2 transmitted from the transmission section 202_B based on the enable signal OUTEN is referred to as the signal LVSTL_IN2. The signal LVSTL_IN2 has a smaller amplitude than the signal Legacy_IN1 transmitted by the transmission section 302, for example.

[0296] Transmitter 202_B includes NMOS transistors 202F and 202G, AND gate 202H, inverter 202I, and NOR gate 202J. A first terminal of NMOS transistor 202F is electrically connected to a node of power supply voltage VCCq. A second terminal of NMOS transistor 202F is connected to node DQI.

[0297] The first terminal of the NMOS transistor 202G is connected to the node DQI. The second terminal of the NMOS transistor 202G is electrically connected to the node of the ground voltage VSSq. The first input terminal of the AND gate 202H receives the enable signal OUTEN from the enable signal generating circuit 204. The second input terminal of the AND gate 202H receives the signal IN2 from the latch circuit 206. The output terminal of the AND gate 202H is connected to the control terminal of the NMOS transistor 202F. The AND gate 202H sends the AND of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the NMOS transistor 202F from the output terminal.

[0298] The input terminal of the inverter 202I receives the enable signal OUTEN from the enable signal generating circuit 204. The inverter 202I sends the logic inversion of the received signal OUTEN2 from the output terminal to the first input terminal of the NOR gate 202J.

[0299] The first input terminal of the NOR gate 202J is connected to the output terminal of the inverter 202I. The second input terminal of the NOR gate 202J receives the signal IN2 from the latch circuit 206. The output terminal of the NOR gate 202J is connected to the control terminal of the NMOS transistor 202G. The NOR gate 202J sends the signal received from the first input terminal and the signal received from the second input terminal "NOR" to the control terminal of the NMOS transistor 202G from the output terminal.

[0300] Thus, the transmission unit 202_B has only one transmission method, and transmits the signal LVSTL_IN2 regardless of the type of the received signal DQ, unlike the transmission unit 202. The amplitude of the signal LVSTL_IN2 becomes smaller because the voltage VCCq is transmitted through the NMOS transistor 202F, and the transmitted voltage is lower than the voltage VCCq by the threshold voltage of the NMOS transistor 202F.

[0301] Since the transmission units 215_B and 216_B have the same configuration and function as the transmission unit 202_B, the description thereof will be omitted.

[0302] Fig.23 The circuit diagram of the transmission unit 202_B shown in FIG. 1 is an example of a configuration. Therefore, the transmission unit 202_B only needs to have Fig.23 Here, the functions of the sending unit of the memory system 100 of the second embodiment include: the memory controller 300 has two sending methods, and the semiconductor memory device 200 has one sending method; and the sending method of the memory controller 300 determines an appropriate method according to the type of the signal DQ, and the sending method of the semiconductor memory device 200 is not limited to the type of the signal DQ.

[0303] Fig.24 It is a circuit diagram showing a configuration example of the receiving unit 301_B of the semiconductor storage device 200 according to the second embodiment. Fig.24 express Figure 5 The detailed circuit structure of the receiving unit 301 is shown in FIG. 301. The receiving unit 301_B is different from the receiving unit 301 in that it has only one receiving method and receives a signal with a small amplitude regardless of the type of the received signal DQ (described below). Therefore, the receiving unit 301_B also receives one type of enable signal from the enable signal generating circuit 304 and performs operations related to the reception of the signal DQ based on the enable signal INEN.

[0304] The receiving section 301_B receives the signal LVSTL_IN2 transmitted from the transmitting section 202_B. The signal LVSTL_IN2 has a smaller amplitude than, for example, the Legacy_IN1 received by the receiving section 201 .

[0305] The receiving section 301_B includes a differential amplifier circuit 301B. The differential amplifier circuit 301B receives a signal LVSTL_IN2 from a first input terminal. A reference voltage VREFq2 is applied to a second input terminal of the differential amplifier circuit 301B.

[0306] The differential amplifier circuit 301B receives the enable signal INEN from the enable signal generating circuit 304. When the enable signal INEN is at a high level, the differential amplifier circuit 301B becomes enabled. The differential amplifier circuit 301B differentially amplifies the received signal LVSTL_IN2 and the reference voltage VREFq2, generates a signal LVSTL_OUT2, and outputs it to other elements in the memory controller 300.

[0307] Thus, the receiving unit 301_B has only one receiving method, and outputs the signal LVSTL_OUT2 regardless of the type of the received signal DQ, unlike the receiving unit 301. Since the output signal LVSTL_OUT2 is based on the signal LVSTL_IN2, it has a smaller amplitude than the output signal Legacy_OUT2 (a signal based on the signal Legacy_IN2) of the receiving unit 201, for example.

[0308] Since the receiving units 306_B and 307_B have the same configuration and function as the receiving unit 301_B, their description is omitted. Here, similarly to the signal LVSTL_IN2, the signal transmitted from the transmitting unit 215_B and received by the receiving unit 306_B is referred to as LVSTL_DQS2. The signal LVSTL_DQS2 has a smaller amplitude than, for example, the signal Legacy_DQS1 received by the receiving unit 212.

[0309] Fig.24 The circuit diagram of the receiving unit 301_B shown in FIG. 1 is an example of a configuration. Therefore, the receiving unit 301_B only needs to have Fig.24 Here, the functions of the receiving unit of the memory system 100 of the second embodiment include: the memory controller 300 has one receiving method, and the semiconductor memory device 200 has two receiving methods; the receiving method of the memory controller 300 is not limited to the type of the signal DQ; and the receiving method of the semiconductor memory device 200 selects an appropriate method according to the type of the signal DQ.

[0310] [2-2] Action

[0311] Similar to the first embodiment, in the semiconductor storage device 200 of the second embodiment, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same functions as the NAND chip A 200A (described in Figure 2The sending and receiving method and termination method are the same as those in ( ).

[0312] As described in the first embodiment, when the NAND chip A 200A is the selected NAND chip, the terminal circuit of the NAND chip A 200A can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In the second embodiment, an example of the case where the selected NAND chip is the NAND chip A 200A and the terminal circuit of the NAND chip A 200A is enabled is described.

[0313] A description will be given of a termination method when the semiconductor storage device 200 and the memory controller 300 according to the second embodiment receive a DQ signal. Fig.25 FIG. 2 shows a method of terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the second embodiment. Fig.25 As shown, the termination circuit 303 of the memory controller 300 terminates the node DQO when the receiving section 301_B receives the signal LVSTL_IN2.

[0314] In addition, similarly to the first embodiment, the termination circuit 203 of the NAND chip A 200A terminates the node DQI when the receiving unit 201 receives the signal LVSTL_IN1. The termination circuit 203 does not terminate the node DQI when the receiving unit 201 receives the signal Legacy_IN1.

[0315] The semiconductor memory device 200 of the second embodiment has one method for transmitting the signals DQ, DQS, and DQSn, and two methods for receiving the signals DQ, DQS, DQSn, REn, and RE, respectively, and which receiving method is selected is determined according to the type of the signal DQ. In addition, the semiconductor memory device 200 can select a termination method according to the transmission and reception method. For the termination of the node DQI, the termination circuit 203 of the NAND chip A 200A is used. In addition, the memory controller 300 of the second embodiment has two methods for transmitting the signals DQ, DQS, DQSn, REn, and RE, respectively, and one method for receiving the signals DQ, DQS, and DQSn, respectively, and which transmission method is selected is determined according to the type of the signal DQ. In addition, the memory controller 300 can select a termination method according to the transmission and reception method.

[0316] The following describes the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the six signals DQ of sending and receiving instructions or addresses, status, parallel status, feature data (FeatureData), data output (DataOutput), and data input (DataInput).

[0317] Fig.26 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.26 Of the signals DQS and DQSn, the signal DQS is shown, but the signal DQSn is a signal of inverted logic of the signal DQS and is therefore the same as the signal DQS. Fig.26 The signal RE of the signals REn and RE is shown, but the signal REn is a signal of the inverted logic of the signal RE, and therefore is the same as the signal RE. Fig.25 As described above, in the second embodiment, in the semiconductor memory device 200, only the termination circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A 200A of the selected NAND chip are used as termination circuits. Fig.26 As shown, when the type of signal DQ is a command or an address, the same as in the first embodiment (see Fig.19 )same.

[0318] Next, when the type of the signal DQ is the state, as the signal DQ, the signal LVSTL_IN2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. At this time, the termination circuit 303 of the memory controller 300 terminates the node DQO. In addition, as the signal DQS, the signal LVSTL_DQS2 is transmitted from the NAND chip A 200A and is received by the memory controller 300. At this time, the termination circuits 312 and 313 of the memory controller 300 terminate the nodes DQS0 and DQSnO, respectively. In addition, as the signal RE, the signal LVSTL_RE1 is transmitted from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuits 220 and 222 of the NAND chip A 200A terminate the nodes REnI and REI.

[0319] Next, when the type of the signal DQ is in the parallel state, as the signal DQ, the signal LVSTL_IN2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. At this time, the termination circuit 303 of the memory controller 300 terminates the node DQO. In addition, as the signal DQS, the signal LVSTL_DQS2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. At this time, the termination circuits 312 and 313 of the memory controller 300 terminate the nodes DQS0 and DQSnO. In addition, as the signal RE, the signal Legacy_RE1 is transmitted from the memory controller 300, and is received by the NAND chip A 200A and the NAND chip B 200B.

[0320] In addition, when the type of the signal DQ is feature data (FeatureData), data output (DataOutput), and data input (DataInput), the same as in the first embodiment (refer to Fig.19 )same.

[0321] like Fig.26 As described above, the memory controller 300 and (or) the semiconductor memory device 200 of the second embodiment terminates each node when the types of the signal DQ are state, parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of the termination circuit becoming enabled.

[0322] Fig. 27 This is an example of a timing chart of signals in the memory system 100 according to the second embodiment. Fig. 27 This shows the timing when the terminal circuit becomes enabled when the type of the signal DQ is the state and the parallel state. Since the state and the parallel state have the same timing diagram, either one is used. Fig. 27 For explanation. Fig. 27 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0323] At time t1, the memory controller 300 sets the signal CEn1 to a low level. As a result, the NAND chip A 200A and the NAND chip B 200B become enabled. During a period including time t2, the memory controller 300 sets the signal CLE to a high level and sends a status read instruction 70h or 78h as the signal DQ. The status read instructions 70h and 78h instruct the output of status data. Accompanying the sending of the status read instruction 70h or 78h, at time t2, the memory controller 300 sets the signal WEn to a high level.

[0324] At time t3, the memory controller 300 sets the signal REn to a low level and then sends the status Status Out as the signal DQ.

[0325] At time t4, the memory controller 300 sets the signal CEn1 to a high level, thereby disabling the NAND chip A 200A and the NAND chip B 200B.

[0326] First, the timing of the terminal circuit becoming enabled when the type of the signal DQ is the state is described. The memory controller 300 enables the terminal circuits 303, 312, and 313 of the memory controller 300 at time t3, and disables the terminal circuits 303, 312, and 313 at time t4. That is, the terminal circuits 303, 312, and 313 terminate the nodes DQO, DQSO, and DQSnO, respectively, that is, the time when the terminal circuits 303, 312, and 313 become enabled is between time t3 and time t4. For example, the memory controller 300 sets the signal REn to a low level after the status read instruction 70h is sent, and sets the terminal circuits 303, 312, and 313 to enable. Furthermore, the memory controller 300 sets the signal CEn1 to a high level after the reception of the status Status Out is completed, and sets the terminal circuits 303, 312, and 313 to disable.

[0327] In addition, the NAND chip A 200A enables the terminal circuits 220 and 222 of the NAND chip A 200A at time t3, and disables the terminal circuits 220 and 222 at time t4. That is, the terminal circuits 220 and 222 terminate the nodes RenI and REI, respectively, i.e., the time when the terminal circuits 220 and 222 become enabled is between time t3 and time t4.

[0328] For example, after receiving the status read command 70h while the signal CEn1 is at a low level, the NAND chip 200A enables the termination circuits 220 and 222 based on the signal REn going low. Furthermore, the NAND chip 200A disables the termination circuits 220 and 222 based on the signal CEn1 going high.

[0329] The timing diagram for the signal DQ type in the parallel state and the timing for the terminal circuit to become enabled only differs from the reference. Fig. 27 What has been described so far is the same as the status.

[0330] The timing diagram when the type of the signal DQ is feature data (FeatureData), data output (DataOutput), and data input (DataInput) and the timing when the terminal circuit becomes enabled are the same as those in the first embodiment. That is, the timing diagram when the type of the signal DQ is feature data (FeatureData) and the timing when the terminal circuit becomes enabled are the same as those in the first embodiment. Fig. 20 The signal DQ is the same as the timing diagram when the data is output (DataOutput) and the timing when the terminal circuit becomes enabled. Fig.21The signal DQ is the same as the timing diagram when data is input (DataInput) and the timing when the terminal circuit becomes enabled. Fig. 22 The timing shown is the same.

[0331] As described above, in the second embodiment, similarly to the first embodiment, the timing for enabling the termination circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A 200A is determined by the memory controller 300 based on the combination of the signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ, and an instruction is issued to the NAND chip A 200A. Therefore, a dedicated instruction or the like for enabling the termination circuit is not used.

[0332] [2-3] Advantages (Effects)

[0333] According to the memory system 100 of the second embodiment described above, compared with the memory system 100 of the first embodiment, it is possible to reduce the circuit area, reduce the capacitance parasitic on the input and output pins, and reduce the time required for control. In addition, the memory system 100 of the second embodiment can terminate the signal with a small amplitude among the received signals, similarly to the first embodiment. The detailed effects of the memory system 100 of the second embodiment are described below.

[0334] In the memory system 100 of the second embodiment, the memory controller 300 has two transmission methods and one reception method, and the semiconductor memory device 200 has one transmission method and two reception methods. Therefore, the memory system 100 of the second embodiment can simplify the configuration of the transmission unit and the reception unit compared with the first embodiment in which the memory controller 300 and the semiconductor memory device 200 each have two transmission and reception methods. By simplifying the configuration of the transmission unit and the reception unit, the memory system 100 of the second embodiment can achieve a reduction in circuit area and a reduction in parasitic capacitance on the input and output pins compared with the memory system 100 of the first embodiment.

[0335] In addition, the memory system 100 of the first embodiment uses two enable signals and two reference voltages to control which transmission and reception method is used because the memory controller 300 and the semiconductor storage device 200 respectively have two transmission and reception methods, thereby distinguishing whether to enable the terminal circuit.

[0336] In the memory system 100 of the second embodiment, the signal transmitted from the transmission unit 202_B and received by the reception unit 301_B is only one signal LVSTL_OUT2. Therefore, there are only one enable signal and one reference voltage VREFq, and the termination circuit is always enabled, which makes control easier than the first embodiment.

[0337] Furthermore, the memory system 100 of the second embodiment includes a transmitting unit 302 and a receiving unit 201 that can transmit and receive both a DQ signal with a large amplitude and a DQ signal with a small amplitude. As a result, when the memory system 100 of the second embodiment transmits a signal from the memory controller 300 to the semiconductor memory device 200, it can select to transmit and receive a signal with a large amplitude or a signal with a small amplitude according to the type of the signal DQ. Specifically, when the memory system 100 transmits a signal DQ such as a state, a parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput), it can transmit and receive a signal with a small amplitude, and when the memory system 100 transmits a signal DQ such as a command or an address, it can transmit and receive a signal with a high reliability and a large amplitude. For the transmission and reception of commands and addresses, a signal with a large amplitude can be used to ensure the reliability of the signal.

[0338] In addition, the memory system 100 of the second embodiment can use an LVSTL termination circuit by including a transceiver that can transmit and receive signals with a small amplitude, similarly to the memory system 100 of the first embodiment. Therefore, the memory system 100 of the second embodiment can further reduce the amplitude of the signal by enabling the LVSTL termination circuit, and can perform higher-speed transmission and reception. In addition, since the LVSTL termination circuit can suppress the through current at the time of termination, it can suppress power consumption compared with the legacy termination circuit such as the CTT method or the POD method.

[0339] [3] Third Embodiment

[0340] Hereinafter, a memory controller 300 and a semiconductor storage device 200 according to the third embodiment will be described.

[0341] [3-1] Composition (Structure)

[0342] As described above, the memory controller 300 of the second embodiment has two transmission methods and one receiving method, and the semiconductor storage device 200 has one transmission method and two receiving methods. In contrast, the memory controller 300 of the third embodiment has one transmission method and one receiving method, and the semiconductor storage device 200 has one transmission method and one receiving method. The third embodiment is substantially the same as the second embodiment in other respects.

[0343] Specifically, the configurations of the transmission units 302, 309 to 311, and 314, and the reception units 201, 212 to 214, and 221 of the memory system 100 of the third embodiment are different from those of the second embodiment. The transmission units 302, 309 to 311, and 314, and the reception units 201, 212 to 214, and 221 of the third embodiment are referred to as transmission units 302_C, 309_C to 311_C, and 314_C, and reception units 201_C, 212_C to 214_C, and 221_C, respectively, to distinguish them from the transmission units 302, 309 to 311, and 314, and the reception units 201, 212 to 214, and 221 of the second embodiment. The configurations of the transmission units 202, 215, and 216, and the reception units 301, 306, and 307 of the memory system 100 of the third embodiment are the same as those of the transmission units 202_B, 215_B, and 216_B, and the reception units 301_B, 306_B, and 307_B of the second embodiment, and thus description thereof is omitted. However, in order to distinguish from the second embodiment, the transmission units 202, 215, and 216, and the reception units 301, 306, and 307 of the third embodiment are referred to as transmission units 202_C, 215_C, and 216_C, and the reception units 301_C, 306_C, and 307_C, respectively. Hereinafter, the memory system 100 of the third embodiment will be mainly described with respect to the differences from the second embodiment.

[0344] [3-1-1] Circuit structure of memory system

[0345] Fig.28 It is a circuit diagram showing a configuration example of the transmission unit 302_C of the semiconductor memory device 200 according to the third embodiment. Fig.28 express Figure 5 The detailed circuit structure of the third embodiment of the transmitting unit 302 is shown in FIG. 2. Similar to the transmitting unit 302, the transmitting unit 302_C controls the voltage of the node DQO based on the signal transmitted as the signal DQ. The transmitting unit 302_C has the same structure and function as the transmitting unit 202_B. Hereinafter, the signal transmitted to the transmitting unit 302_C as the signal DQ is referred to as the signal IN1.

[0346] The transmission section 302_C is different from the transmission section 302 and has only one transmission method. It transmits a signal with a small amplitude regardless of the type of the received signal DQ (described below). Therefore, the enable signal received by the transmission section 302_C from the enable signal generating circuit 304 is also one type, and the signal is transmitted based on the enable signal OUTEN. Here, the signal IN1 transmitted from the transmission section 302_C based on the enable signal OUTEN is referred to as the signal LVSTL_IN1. The signal LVSTL_IN1 has a smaller amplitude than the Legacy_IN1 transmitted by the transmission section 302, for example.

[0347] The transmission unit 302_C includes NMOS transistors 302F and 302G, an AND gate 302H, an inverter 302I, and a NOR gate 302J. A first terminal of the NMOS transistor 302F is electrically connected to a node of a power supply voltage VCCq. A second terminal of the NMOS transistor 302F is connected to a node DQO.

[0348] The first terminal of the NMOS transistor 302G is connected to the node DQ0. The second terminal of the NMOS transistor 302G is electrically connected to the node of the ground voltage VSSq. The first input terminal of the AND gate 302H receives the enable signal OUTEN from the enable signal generating circuit 304. The second input terminal of the AND gate 302H receives the signal IN1 from other elements not shown in the memory controller 300. The output terminal of the AND gate 302H is connected to the control terminal of the NMOS transistor 302F. The AND gate 302H sends the AND of the signal received from the first input terminal and the signal received from the second input terminal to the control terminal of the NMOS transistor 302F from the output terminal.

[0349] The input terminal of the inverter 302I receives the enable signal OUTEN1 from the enable signal generating circuit 304. The inverter 302I sends the logic inversion of the received signal OUTEN1 from the output terminal to the first input terminal of the NOR gate 302J.

[0350] The first input terminal of the NOR gate 302J is connected to the output terminal of the inverter 302I. The second input terminal of the NOR gate 302J receives a signal IN1 from another element not shown in the memory controller 300. The output terminal of the NOR gate 302J is connected to the control terminal of the NMOS transistor 302G. The NOR gate 302J sends the signal received from the first input terminal and the signal received from the second input terminal "NOR" to the control terminal of the NMOS transistor 302G from the output terminal.

[0351] Thus, the transmission section 302_C has only one transmission method, and transmits the signal LVSTL_IN1 regardless of the type of the received signal DQ, unlike the transmission section 302. The amplitude of the signal LVSTL_IN1 becomes smaller because the voltage VCCq is transmitted through the NMOS transistor 302F, and the transmitted voltage is lower than the voltage VCCq by the threshold voltage of the NMOS transistor 302F.

[0352] Since the transmission units 309_C to 311_C and 314_C have the same configuration and function as the transmission unit 302_C, their description is omitted.

[0353] Fig.28 The circuit diagram of the transmission unit 302_C shown in FIG. 1 is an example of a configuration. Fig.28 Here, the functions of the transmission unit of the memory system 100 of the third embodiment include: the memory controller 300 has one transmission method, the semiconductor memory device 200 has another transmission method; and the transmission methods of the memory controller 300 and the semiconductor memory device 200 are not limited to the type of the signal DQ.

[0354] Fig.29 It is a circuit diagram showing a configuration example of a receiving unit 201_C of a semiconductor storage device 200 according to the third embodiment. Fig.29 express Figure 6 The detailed circuit structure of the receiving unit 201 is shown in FIG. 2. The receiving unit 201_C is different from the receiving unit 201 in that it has only one receiving method and receives a signal with a small amplitude regardless of the type of the received signal DQ (described below). Therefore, the receiving unit 201_C also receives one type of enable signal from the enable signal generating circuit 204 and performs operations related to the reception of the signal DQ based on the enable signal INEN.

[0355] The receiving section 201_C receives the signal LVSTL_IN1 transmitted from the transmitting section 302_C. The signal LVSTL_IN1 has a smaller amplitude than the Legacy_IN1 received by the receiving section 201 , for example.

[0356] The receiving unit 201_C includes a differential amplifier circuit 201B. The differential amplifier circuit 201B receives a signal LVSTL_IN1 from a first input terminal. A reference voltage VREFq2 is applied to a second input terminal of the differential amplifier circuit 201B.

[0357] The differential amplifier circuit 201B receives the enable signal INEN from the enable signal generating circuit 204. When the enable signal INEN is at a high level, the differential amplifier circuit 201B becomes enabled. The differential amplifier circuit 201B differentially amplifies the received signal LVSTL_IN1 and the reference voltage VREFq2, generates a signal LVSTL_OUT1, and outputs it to the latch circuit 206.

[0358] Thus, receiving unit 201_C has only one receiving method, and outputs signal LVSTL_OUT1 regardless of the type of received signal DQ, unlike receiving unit 201. Output signal LVSTL_OUT1 is based on signal LVSTL_IN1, and therefore has a smaller amplitude than output signal Legacy_OUT1 (signal based on signal Legacy_IN1) of receiving unit 201, for example.

[0359] Since the receiving units 212_C to 214_C and 221_C have the same configuration and function as the receiving unit 201_C, their description is omitted. Here, similar to the signal LVSTL_IN1, the signal transmitted from the transmitting unit 309_C and received by the receiving unit 212_C is referred to as the signal LVSTL_DQS1. The signal LVSTL_DQS1 has a smaller amplitude than, for example, the signal Legacy_DQS1 received by the receiving unit 212.

[0360] The signal transmitted from the transmission section 314_C and received by the reception section 221_C is referred to as a signal LVSTL_RE1. The signal LVSTL_RE1 has a smaller amplitude than, for example, Legacy_RE1 received by the reception section 221.

[0361] Fig.29 The circuit diagram of the receiving unit 201_C shown in FIG. 1 is an example of a configuration. Fig.29 Here, the functions of the receiving unit of the memory system 100 of the third embodiment include: the memory controller 300 has one receiving method, the semiconductor memory device 200 has one receiving method; and the receiving methods of the memory controller 300 and the semiconductor memory device 200 are not limited to the type of the signal DQ.

[0362] [3-2] Action

[0363] Similar to the first embodiment, in the semiconductor storage device 200 of the third embodiment, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same functions as the NAND chip A 200A (described in Figure 2The sending and receiving method and termination method are the same as those in ( ).

[0364] As described in the first embodiment, when the NAND chip A 200A is the selected NAND chip, the terminal circuit of the NAND chip A 200A can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In the third embodiment, an example of the case where the selected NAND chip is the NAND chip A 200A and the terminal circuit of the NAND chip A 200A is enabled is described.

[0365] A description will be given of a termination method when the semiconductor storage device 200 and the memory controller 300 according to the third embodiment receive a DQ signal. Fig.30 FIG. 2 shows a method for terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the third embodiment. Fig.30 As shown, the termination circuit 303 terminates the node DQ0 when the receiving section 301_C receives the signal LVSTL_IN2, similarly to the second embodiment.

[0366] In addition, the termination circuit 203 terminates the node DQI when the receiving section 201_C receives the signal LVSTL_IN1.

[0367] The semiconductor memory device 200 of the third embodiment has one method for transmitting each of the signals DQ, DQS, and DQSn, and one method for receiving each of the signals DQ, DQS, DQSn, REn, and RE. The transmission and reception method is not limited to the type of the signal DQ, and a signal with a small amplitude is always transmitted and received. In addition, in the semiconductor memory device 200, when the receiving unit 201_C receives a signal, the termination circuit 203 of the NAND chip A 200A always terminates the node DQI.

[0368] In addition, the memory controller 300 of the third embodiment has one method for transmitting each of the signals DQ, DQS, DQSn, REn, and RE, and one method for receiving each of the signals DQ, DQS, and DQSn. The transmission and reception method is not limited to the type of the signal DQ, and a signal with a small amplitude is always transmitted and received. In addition, when the receiving unit 301_C in the memory controller 300 receives a signal, the termination circuit 303 always terminates the node DQO.

[0369] The following describes the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the six signals DQ of sending and receiving instructions or addresses, status, parallel status, feature data (FeatureData), data output (DataOutput), and data input (DataInput).

[0370] Fig.31 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.31 The signal DQS is shown in the figure, and the signal DQSn is a signal of the inverted logic of the signal DQS, and is therefore the same as the signal DQS. Fig.31 The signal RE of the signals REn and RE is shown, and the signal REn is a signal of the inverted logic of the signal RE, and is therefore the same as the signal RE. Fig.30 As described above, in the third embodiment, in the semiconductor storage device 200, only the termination circuit of the NAND chip A 200A of the selected NAND chip is used as the termination circuit. Fig.31 As shown, when the type of signal DQ is a command or an address, as signal DQ, signal LVSTL_IN1 is sent from memory controller 300 and received by NAND chip A 200A and NAND chip B 200B. At this time, the termination circuit 203 of NAND chip A 200A terminates node DQI. In addition, signals DQS and RE sent from memory controller 300 are fixed to a low level.

[0371] When the type of the signal DQ is state, the same as the second embodiment (refer to Fig.26 )same.

[0372] Next, when the type of the signal DQ is in the parallel state, as the signal DQ, the signal LVSTL_IN2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. At this time, the termination circuit 303 of the memory controller 300 terminates the node DQO. In addition, as the signal DQS, the signal LVSTL_DQS2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. At this time, the termination circuits 312 and 313 of the memory controller 300 terminate the nodes DQS0 and DQSnO. In addition, as the signal RE, the signal LVSTL_RE1 is transmitted from the memory controller 300, and is received by the NAND chip A 200A and the NAND chip B 200B. At this time, the termination circuits 220 and 222 of the NAND chip A 200A terminate the nodes REnI and REI.

[0373] In addition, when the type of the signal DQ is feature data (FeatureData), data output (DataOutput), and data input (DataInput), the same as in the first embodiment (refer to Fig.19 )same.

[0374] like Fig.31 As described above, the memory controller 300 and (or) the semiconductor memory device 200 of the third embodiment terminates each node when the type of the signal DQ is command or address, state, parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of the termination circuit becoming enabled.

[0375] Fig.32 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment. Fig.32 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is command, address, or data input (DataInput). Fig.32 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ. Fig.32 The data writing is taken as an example. When the type of the signal DQ is command or address and data input (DataInput), the timing diagram is the same as the data input (DataInput) of the first embodiment ( Fig. 22 ) is the same, but the timing at which the terminal circuit becomes enabled is different from that at the time of data input (DataInput) in the first embodiment. Fig.32 Only the timing at which the terminal circuit becomes enabled when the type of signal DQ is command or address and data input (DataInput) is described.

[0376] At time t1, the NAND chip A 200A enables the terminal circuits 203, 218, and 219 of the NAND chip A 200A, and at time t10, disables the terminal circuits 203, 218, and 219. That is, the terminal circuits 203, 218, and 219 terminate the nodes DQI, DQSI, and DQSnI, respectively, i.e., the time when the terminal circuits 203, 218, and 219 become enabled is between time t1 and time t10. This is because in the third embodiment, since the signal transmitted and received is one type, the terminal circuit can always be enabled during the period when the memory controller 300 enables the NAND chip A 200A for the purpose of communicating with the NAND chip A 200A. For example, the NAND chip A 200A enables the terminal circuits 203, 218, and 219 based on the signal CEn1 becoming a low level. Furthermore, the NAND chip A 200A disables the termination circuits 203, 218, and 219 based on the signal CEn1 becoming a high level.

[0377] The timing diagram when the types of the signal DQ are state, parallel state, feature data (FeatureData), and data output (DataOutput) is the same as that of the second embodiment, but the timing when the terminal circuit becomes enabled is different from that of the second embodiment. Therefore, the following only describes the timing when the types of the signal DQ are state, parallel state, feature data (FeatureData), and data output (DataOutput).

[0378] Fig.33 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment. Fig.33 This shows the timing when the terminal circuit becomes enabled when the type of the signal DQ is the state and parallel state. Fig. 27 same.

[0379] The memory controller 300 enables the terminal circuits 303, 312, and 313 of the memory controller 300 at time t3, and disables the terminal circuits 303, 312, and 313 at time t4. That is, the terminal circuits 303, 312, and 313 terminate the nodes DQO, DQSO, and DQSnO, respectively, i.e., the time when the terminal circuits 303, 312, and 313 become enabled is between time t3 and time t4. For example, the memory controller 300 sets the signal REn to a low level after the status read instruction 70h or 78h is sent, and enables the terminal circuits 303, 312, and 313. Furthermore, the memory controller 300 sets the signal CEn1 to a high level after the status Status Out is received, and disables the terminal circuits 303, 312, and 313.

[0380] At time t3, the NAND chip A 200A enables the terminal circuits 220 and 222 of the NAND chip A 200A, and at time t4, disables the terminal circuits 220 and 222. That is, the terminal circuits 220 and 222 terminate the nodes REnI and REI, respectively, that is, the time when the terminal circuits 220 and 222 become enabled is between time t3 and time t4. For example, when the signal CEn1 is at a low level, the NAND chip 200A enables the terminal circuits 220 and 222 based on the signal REn becoming a low level after receiving the status read instruction 70h or 78h. Furthermore, after the NAND chip 200A completes the sending of the status Status Out, the terminal circuits 220 and 222 are disabled based on the signal CEn1 becoming a high level. In addition, as shown in reference Fig.32As described above, the termination circuit 203 of the NAND chip A 200A terminates the node DQI during the entire period including the period of transmission of the command (status read command 70h or 78h), that is, from time t1 to time t3.

[0381] Fig.34 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment. Fig.34 This is the timing when the terminal circuit becomes enabled when the type of signal DQ is feature data (FeatureData). Fig. 20 same.

[0382] At time t5, the NAND chip A 200A enables the termination circuits 203, 218, and 219 of the NAND chip A 200A, and at time t10, disables the termination circuits 203, 218, and 219. That is, the termination circuits 203, 218, and 219 terminate the nodes DQI, DQSI, and DQSnI, respectively, i.e., the termination circuits 203, 218, and 219 become enabled between time t5 and time t10. For example, when the NAND chip A 200A receives the SetFeature command D5h and the subsequent address ADD, the termination circuits 203, 218, and 219 are enabled based on the signal ALE becoming a low level. Furthermore, after receiving the parameters W-B0, W-B1, W-B2, and W-B3, the NAND chip A 200A disables the termination circuits 203, 218, and 219 based on the signal CEn1 becoming a high level. In addition, as referenced Fig.32 As described above, the termination circuit 203 of the NAND chip A 200A terminates the node DQI during the entire period including the period of sending the set feature (SetFeature) command D5h and the address ADD, that is, from time t1 to time t5.

[0383] Fig.35 This is an example of a timing chart of signals in the memory system 100 according to the third embodiment. Fig.35 This shows the timing when the terminal circuit becomes enabled when the type of signal DQ is data output (DataOutput). Fig.21 same.

[0384] The memory controller 300 enables the termination circuits 303, 312, and 313 of the memory controller 300 at time t9, and disables the termination circuits 303, 312, and 313 at time t10. That is, the termination circuits 303, 312, and 313 terminate the nodes DQO, DQS0, and DQSnO, respectively, i.e., the termination circuits 303, 312, and 313 become enabled between time t9 and time t10. For example, the memory controller 300 sets the signal REn to a low level after the read execution instruction 30h is sent, and enables the termination circuits 303, 312, and 313. Furthermore, the memory controller 300 sets the signal CEn1 to a high level after the reception of the read data D is completed, and disables the termination circuits 303, 312, and 313.

[0385] At time t9, the NAND chip A 200A enables the terminal circuits 220 and 222, and at time t10, disables the terminal circuits 220 and 222. That is, the terminal circuits 220 and 222 terminate the nodes REnI and REI, respectively, i.e., the time when the terminal circuits 220 and 222 become enabled is between time t9 and time t10. For example, when the signal CEn1 is at a low level, the NAND chip 200A enables the terminal circuits 220 and 222 based on the signal REn becoming a low level after receiving the read execution instruction 30h. Furthermore, the NAND chip 200A disables the terminal circuits 220 and 222 based on the signal CEn1 becoming a high level. In addition, as shown in FIG. Fig.32 As described above, during the entire period including the period of sending the read command 00h, the address ADD, and the read execution command 30h, that is, from time t1 to time t9, the termination circuit 203 of the NAND chip A200A terminates the node DQI.

[0386] As described above, similarly to the first and second embodiments, in the third embodiment, the timing for enabling the termination circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A200A is determined by the memory controller 300 based on the combination of the signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ, and instructs the NAND chip A200A. Therefore, a dedicated instruction or the like for enabling the termination circuits is not used.

[0387] [3-3] Advantages (Effects)

[0388] According to the memory system 100 of the third embodiment described above, compared with the memory system 100 of the second embodiment, the effects of reducing the circuit area, reducing the capacitance parasitic on the input and output pins, and reducing the time required for control can be further improved. In addition, the memory system 100 of the third embodiment can terminate the signal with a small amplitude among the received signals, similarly to the second embodiment. The detailed effects of the memory system 100 of the third embodiment are described below.

[0389] In the memory system 100 of the third embodiment, the memory controller 300 has one transmission method and one reception method, and the semiconductor memory device 200 has one transmission method and one reception method. Therefore, the memory system 100 of the third embodiment can simplify the configuration of the transmission unit and the reception unit compared with the second embodiment. By simplifying the configuration of the transmission unit and the reception unit, the memory system 100 of the third embodiment can reduce the circuit area and reduce the capacitance parasitic on the input and output pins compared with the memory system 100 of the second embodiment.

[0390] In addition, the memory system 100 of the second embodiment uses two enable signals and two reference voltages to distinguish whether to enable the terminal circuit in order to control which transmission and reception method is used respectively because the transmission unit 302 has two transmission methods and the reception unit 201 has a reception method.

[0391] In the memory system 100 of the third embodiment, the signal transmitted from the transmission section 302_C and received by the reception section 201_C is only one signal LVSTL_OUT1, and the signal transmitted from the transmission section 202_C and received by the reception section 301_C is only one signal LVSTL_OUT2. Therefore, since the memory system 100 of the third embodiment has only one enable signal and one reference voltage VREFq, and the termination circuit is always enabled, it is easier to control than the second embodiment.

[0392] Furthermore, the memory system 100 of the third embodiment transmits and receives only DQ signals with small amplitudes. Therefore, the memory system 100 of the third embodiment is suitable for high-speed transmission and reception.

[0393] In addition, the memory system 100 of the third embodiment includes a transceiver that can transmit and receive signals with small amplitude, similarly to the memory systems 100 of the first and second embodiments, and can use an LVSTL termination circuit. Therefore, the memory system 100 of the second embodiment can further reduce the amplitude of the signal by enabling the LVSTL termination circuit, and can perform higher-speed transmission and reception. In addition, since the LVSTL termination circuit can suppress the through current at the time of termination, it can suppress power consumption compared to the legacy termination circuit such as the CTT method or the POD method. Since the memory system 100 of the third embodiment uses the LVSTL termination circuit that consumes less power, the termination circuit can be enabled for a long time.

[0394] [4] Fourth Embodiment

[0395] Hereinafter, a memory controller 300 and a semiconductor storage device 200 according to the fourth embodiment will be described.

[0396] [4-1] Composition (Structure)

[0397] The memory controller 300 and the semiconductor storage device 200 according to the fourth embodiment have the same structure as those of the first embodiment except for the following point: That is, the memory controller 300 according to the fourth embodiment does not include the termination circuit 303 .

[0398] The memory system 100 of the fourth embodiment is further different from the first embodiment in the termination method of the wiring of the semiconductor memory device 200. The fourth embodiment is the same as the first embodiment in other respects. Hereinafter, the memory system 100 of the fourth embodiment will be mainly described in terms of the differences from the first embodiment.

[0399] In the first embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203 of the NAND chip A 200A is used. In contrast, in the fourth embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203 of the NAND chip C 200C is used. The termination circuit 203 of the NAND chip C 200C is sometimes referred to as the termination circuit 203_C below in order to distinguish it from the termination circuit 203 of the NAND chip A 200A. Similarly, the termination circuits 218 to 220 and 222 of the NAND chip C 200C are sometimes referred to as the termination circuits 218_C to 220_C and 222_C below in order to distinguish it from the termination circuits 218 to 220 and 222 of the NAND chip A 200A. In the fourth embodiment, when terminating the nodes DQSI, DQSnI, REnI, and REI for communication between the memory controller 300 and the NAND chip A 200A, the termination circuits 218_C to 220_C and 222_C are used respectively.

[0400] The terminal circuit 203_C has the same structure and function as the terminal circuit 203 of the NAND chip A 200A. The fourth embodiment is the same as the first embodiment except for the points described here. For example, the transmission units 202, 215, 216, 302, 309 to 311 and 314, and the reception units 201, 212 to 214, 221, 301, 306 and 307 of the fourth embodiment have the same structure and function as those of the first embodiment.

[0401] [4-2] Action

[0402] Similar to the first embodiment, in the semiconductor storage device 200 of the fourth embodiment, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same functions as the NAND chip A 200A (described in Figure 2 The sending and receiving method and termination method are the same as those in ( ).

[0403] As described in the first embodiment, when the NAND chip A 200A is the selected NAND chip, the terminal circuit of the NAND chip A 200A may be enabled, and the terminal circuit of the non-selected NAND chip may be enabled. In the fourth embodiment, an example is described in which the selected NAND chip is the NAND chip A 200A, and the terminal circuits 203_C, 218_C to 220_C, and (or) 222_C of the non-selected NAND chip, i.e., the NAND chip C 200C, are enabled.

[0404] A description will be given of a termination method when the semiconductor storage device 200 and the memory controller 300 according to the fourth embodiment receive a DQ signal. Fig.36 FIG. 4 shows a method for terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the fourth embodiment. Fig.36 As shown, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI when the receiving section 201 receives the signal LVSTL_IN1 and when the receiving section 301 receives the signal LVSTL_IN2. The termination circuit 203_C does not terminate the node DQI when the receiving section 201 receives the signal Legacy_IN1 and when the receiving section 301 receives the signal Legacy_IN2.

[0405] The semiconductor memory device 200 of the fourth embodiment has two methods of transmitting signals DQ, DQS, and DQSn, and two methods of receiving signals DQ, DQS, DQSn, REn, and RE, similarly to the first embodiment. Which method of transmitting and receiving is selected is determined according to the type of the signal DQ. In addition, the semiconductor memory device 200 can select a termination method according to the transmission and reception method. For the termination of the node DQI, the termination circuit 203_C of the NAND chip C 200C is used. Similarly, the memory controller 300 of the fourth embodiment has two methods of transmitting signals DQ, DQS, DQSn, REn, and RE, similarly to the first embodiment. Which method of transmitting and receiving is selected is determined according to the type of the signal DQ. In addition, the memory controller 300 can select a termination method according to the transmission and reception method.

[0406] The following describes the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the six types of signals DQ, namely, sending and receiving instructions or addresses, status, parallel status, setting features (SetFeature), data output (DataOutput), and data input (DataInput).

[0407] Fig.37 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.37 Of the signals DQS and DQSn, the signal DQS is shown, but the signal DQSn is a signal of inverted logic of the signal DQS and is therefore the same as the signal DQS. Fig.37 The signal RE is shown for the signal REn and the signal RE, but the signal REn is a signal of the inverted logic of the signal RE, and therefore is the same as the signal RE. Fig.36As described above, in the fourth embodiment, only the termination circuits 203_C, 218_C, 219_C, 220, and (or) 222_C of the NAND chip C 200C which is a non-selected NAND chip are used as termination circuits. Fig.37 As shown, when the type of the signal DQ is a command or an address, when it is a state, and when it is a parallel state, it is different from the first embodiment (refer to Fig.19 )same.

[0408] Next, when the type of the signal DQ is feature data (FeatureData), as the signal DQ, the signal LVSTL_IN1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the termination circuits 218_C and 219_C of the NAND chip C 200C terminate the nodes DQSI and DQSnI.

[0409] Next, when the type of the signal DQ is data output (DataOutput), as the signal DQ, the signal LVSTL_IN2 is sent from the NAND chip A 200A and received by the memory controller 300. At this time, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS2 is sent from the NAND chip A 200A and received by the memory controller 300. At this time, the termination circuits 218_C and 219_C of the NAND chip C 200C terminate the nodes DQSI and DQSnI. Thus, unlike the first embodiment, when the memory controller 300 receives the signal, the termination circuit of the memory controller 300 does not terminate the wiring, and the termination circuits 203_C, 218_C, 219_C, 220 and (or) 222_C of the NAND chip C 200C terminate the wiring. In addition, as the signal RE, the signal LVSTL_RE1 is transmitted from the memory controller 300 to the NAND chip A 200A. At this time, the termination circuits 220_C and 222_C of the NAND chip C 200C terminate the nodes REnI and REI, respectively.

[0410] Next, when the type of the signal DQ is data input (DataInput), the signal LVSTL_IN1 is sent from the memory controller 300 to the NAND chip A 200A as the signal DQ. At this time, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS1 is sent from the memory controller 300 to the NAND chip A 200A. At this time, the termination circuits 218_C and 219_C of the NAND chip C 200C terminate the nodes DQSI and DQSnI.

[0411] like Fig.37 As described above, the memory controller 300 and / or the semiconductor memory device 200 of the fourth embodiment terminates each node when the types of the signal DQ are feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of enabling the termination circuit.

[0412] Fig.38 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment. Fig.38 Indicates the timing at which the terminal circuit becomes enabled when the type of signal DQ is feature data (FeatureData). Fig.38 In, with Fig. 20 Similarly, timing diagrams of signals CEn1 , CEn2 , CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ are shown.

[0413] During the period from time t2 to time t9, the timing diagram of the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is the same as that of the first embodiment. Fig. 20 Regarding the signal CEn2, the following mainly describes the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ during the period from time ta to time td and from time te to time th.

[0414] As described above, the memory system 100 of the first to third embodiments does not use a dedicated instruction or the like to enable the termination circuits 203, 218, 219, 220, and (or) 222 of the NAND chip A 200A. In contrast, the memory system 100 of the fourth embodiment uses a dedicated instruction to determine the timing for enabling the termination circuits 203_C, 218_C, 219_C, 220, and (or) 222_C of the NAND chip C 200C.

[0415] Specifically, the memory controller 300 controls the timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C by sending the ODT command 95h, address ADD, and ODT end command 9Bh in the signal DQ and controlling the signal CEn2.

[0416] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period including time tb and tc, the memory controller 300 sets the signal CLE to a high level, and sends the ODT instruction 95h and the address ADD as the signal DQ. The ODT instruction 95h enables the terminal circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip 200 specified by the address ADD during the period when the NAND chip 200 becomes enabled. In addition, the ODT instruction 95h instructs the target NAND chip 200 to enable the terminal circuits 203, 218, and 219 of the NAND chip 200. In the case of the fourth embodiment, the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C specified by the address ADD are enabled while the signal CEn2 is at a low level. With the transmission of the ODT command 95h and the address ADD, the memory controller 300 sets the signal WEn to a high level at times tb and tc.

[0417] At time td, the memory controller 300 sets the signal CEn1 to a low level and sets the signal CEn2 to a high level, thereby enabling the NAND chip A 200A and the NAND chip B 200B, and disabling the NAND chip C 200C and the NAND chip D 200D.

[0418] During the period from time t5 to time te, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D are enabled. At time te, the memory controller 300 sets the signals CEn1 and CEn2 to a high level. As a result, the NAND chip A 200A, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D are disabled.

[0419] During the period from time tf to time th, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D are enabled. At time tg, the memory controller 300 sends an ODT end instruction 9Bh as a signal DQ. The ODT end instruction 9Bh is an instruction indicating the end of enabling the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C while the signal CEn2 is at a low level. During the period from sending the ODT command 95h and the address ADD to sending the ODT end command 9Bh, the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C are enabled during the period when the signal CEn2 is at a low level, that is, during the period between time t5 and time te, and between time tf and time tg. With the sending of the ODT end command 9Bh, at time tg, the memory controller 300 sets the signal WEn to a high level.

[0420] At time th, the memory controller 300 sets the signal CEn2 to a high level, thereby disabling the NAND chip C 200C and the NAND chip D 200D.

[0421] In this way, the memory controller 300 controls the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT command 95h, the address ADD, and the ODT end command 9Bh in the signal DQ and controlling the signal CEn2. Based on the instruction of the memory controller 300, the NAND chip C 200C enables the termination circuits 203_C, 218_C, and 219_C of the NAND chip C 200C at time t5, and disables the termination circuits 203_C, 218_C, and 219_C at time te. That is, the termination circuits 203_C, 218_C and 219_C terminate the nodes DQI, DQSI and DQSnI respectively, that is, the time when the termination circuits 203_C, 218_C and 219_C become enabled is between the time t5 and the time te.

[0422] Similarly, between time tf and time tg, based on the instruction of the memory controller 300, the NAND chip C200C enables the termination circuits 203_C, 218_C, and 219_C of the NAND chip C200C. However, the conditions for enabling the termination circuits are unintentionally satisfied only until the ODT end instruction 9Bh becomes effective, and as a result, the termination circuits are enabled. That is, the termination of the nodes DQI, DQSI, and DQSnI is unintentionally performed, and the termination between time tf and time tg may not be performed.

[0423] Fig.39 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment. Fig.39 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is data output (DataOutput). Fig.39 In, with Fig.21 Similarly, timing diagrams of signals CEn1 , CEn2 , CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ are shown.

[0424] During the period from time t2 to time t9, the timing diagram of the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is the same as that of the first embodiment. Fig.21 Regarding the signal CEn2, the following mainly describes the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ during the period from time ta to time td and from time te to time th.

[0425] exist Fig.39 In, with Fig.38 Similarly, a dedicated instruction is used to determine the timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C. Specifically, the memory controller 300 controls the timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ, and controlling the signal CEn2. The ODT instruction 97h is the same as the ODT instruction 95h, and is an instruction to enable the terminal circuits of the chip specified by the address ADD during the period when the chip is enabled. In addition, the ODT command 97h instructs the target NAND chip 200 to enable the termination circuits 203, 218, 219, 220, and 222 of the NAND chip 200.

[0426] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period including time tb and tc, the memory controller 300 sets the signal CLE to a high level and sends the ODT instruction 97h and the address ADD as the signal DQ. As a result, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C specified by the address ADD become enabled during the period when the signal CEn2 is at a low level. Along with the sending of the ODT instruction 97h and the address ADD, at time tb and tc, the memory controller 300 sets the signal WEn to a high level.

[0427] At time td, the memory controller 300 sets the signal CEn1 to a low level and sets the signal CEn2 to a high level, thereby enabling the NAND chip A 200A and the NAND chip B 200B, and disabling the NAND chip C 200C and the NAND chip D 200D.

[0428] During the period from time t9 to time te, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D are enabled. At time te, the memory controller 300 sets the signals CEn1 and CEn2 to a high level. As a result, the NAND chip A 200A, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D are disabled.

[0429] During the period from time tf to time th, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. At time tg, the memory controller 300 sends an ODT end instruction 9Bh as a signal DQ. According to the ODT end instruction 9Bh, the memory controller 300 sets the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C to be disabled. Along with the sending of the ODT end instruction 9Bh, at time tg, the memory controller 300 sets the signal WEn to a high level.

[0430] At time th, the memory controller 300 sets the signal CEn2 to a high level, thereby disabling the NAND chip C 200C and the NAND chip D 200D.

[0431] In this way, the memory controller 300 controls the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C by sending the ODT command 97h, address ADD, and ODT end command 9Bh in the signal DQ and controlling the signal CEn2.

[0432] In addition, based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C to 220_C and 222_C of the NAND chip C 200C at time t9, and disables the terminal circuits 203_C, 218_C to 220_C and 222_C at time te. That is, the terminal circuits 203_C, 218_C to 220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI, respectively, that is, the time when the terminal circuits 203_C, 218_C to 220_C and 222_C become enabled is between time t9 and time te.

[0433] Similarly, between time tf and time tg, based on the instruction of the memory controller 300, the NAND chip C200C enables the termination circuits 203_C, 218_C to 220_C, and 222_C of the NAND chip C200C. However, the conditions for enabling the termination circuits are unintentionally satisfied only until the ODT end instruction 9Bh becomes effective, and as a result, the termination circuits are enabled. That is, the termination of the nodes DQI, DQSI, DQSnI, REnI, and REI is unintentionally performed, and the termination between time tf and time tg may not be performed.

[0434] Fig.40 This is an example of a timing chart of signals in the memory system 100 according to the fourth embodiment. Fig.40 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is data input (DataInput). Fig.40 In, with Fig. 22 Similarly, timing diagrams of signals CEn1 , CEn2 , CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ are shown.

[0435] During the period from time t2 to time t9, the timing diagram of the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is the same as that of the first embodiment. Fig. 22Regarding the signal CEn2, the following mainly describes the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ during the period from time ta to time td and from time te to time th.

[0436] exist Fig.40 In, with Fig.38 Similarly, a dedicated command is used to determine the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C.

[0437] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period including time tb and tc, the memory controller 300 sets the signal CLE to a high level and sends the ODT instruction 95h and the address ADD as the signal DQ. As a result, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C specified by the address ADD become enabled during the period when the signal CEn2 is at a low level. Along with the sending of the ODT instruction 95h and the address ADD, at time tb and tc, the memory controller 300 sets the signal WEn to a high level.

[0438] At time td, the memory controller 300 sets the signal CEn1 to a low level and sets the signal CEn2 to a high level, thereby enabling the NAND chip A 200A and the NAND chip B 200B, and disabling the NAND chip C 200C and the NAND chip D 200D.

[0439] During the period from time t8 to time t9, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D are enabled. At time t9, the memory controller 300 sets the signal CEn2 to a high level. As a result, the NAND chip C 200C and the NAND chip D 200D are disabled. At time te, the memory controller 300 sets the signal CEn1 to a high level. As a result, the NAND chip A 200A and the NAND chip B 200B are disabled.

[0440] During the period from time tf to time th, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. At time tg, the memory controller 300 sends an ODT end instruction 9Bh as a signal DQ. According to the ODT end instruction 9Bh, the memory controller 300 sets the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C to be disabled. Along with the sending of the ODT end instruction 9Bh, at time tg, the memory controller 300 sets the signal WEn to a high level.

[0441] At time th, the memory controller 300 sets the signal CEn2 to a high level, thereby disabling the NAND chip C 200C and the NAND chip D 200D.

[0442] Based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C and 219_C of the NAND chip C 200C at time t8, and disables the terminal circuits 203_C, 218_C and 219_C at time t9. That is, the terminal circuits 203_C, 218_C and 219_C terminate the nodes DQI, DQSI and DQSnI, that is, the time when the terminal circuits 203_C, 218_C and 219_C become enabled is between time t8 and time t9.

[0443] Similarly, between time tf and time tg, based on the instruction of the memory controller 300, the NAND chip C200C enables the termination circuits 203_C, 218_C, and 219_C of the NAND chip C200C. However, the conditions for enabling the termination circuits are unintentionally satisfied only until the ODT end instruction 9Bh becomes effective, and as a result, the termination circuits are enabled. That is, the termination of the nodes DQI, DQSI, and DQSnI is unintentionally performed, and the termination between time tf and time tg may not be performed.

[0444] Based on the above timing chart, the timing of enabling the terminal circuit of the memory system 100 of the fourth embodiment is summarized. The timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C is controlled by the memory controller 300 by sending the ODT instruction 95h or 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ, and controlling the signal CEn2. That is, a dedicated instruction for enabling the terminal circuit is used.

[0445] [4-3] Advantages (Effects)

[0446] The memory system 100 according to the fourth embodiment described above includes the transmission units 202 and 302 and the reception units 201 and 301 in the same manner as in the first embodiment. Therefore, the same effects as in the first embodiment are obtained.

[0447] According to the memory system 100 of the fourth embodiment, unlike the first embodiment, a termination circuit of a non-selected NAND chip is used when terminating wiring in the semiconductor memory device 200. If a termination circuit of a non-selected NAND chip is used for the termination circuit for terminating wiring, reflection of a signal when it is conducted in the wiring can be further reduced compared to the case where a termination circuit of a selected NAND chip is used.

[0448] Therefore, the memory system 100 according to the fourth embodiment may have higher impedance conformity of the wiring when the wiring is terminated than the memory system 100 according to the first embodiment, and the characteristics of the received signal may be further improved.

[0449] In the fourth embodiment, an example is shown in which only the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C are used when terminating the wiring, but the terminal circuits of other NAND chips may be used in combination. For example, when terminating the node DQI, the terminal circuit 203 of the NAND chip A 200A may be used simultaneously for termination, instead of using only the terminal circuit 203_C of the NAND chip C 200C.

[0450] [5] Fifth embodiment

[0451] Hereinafter, a memory controller 300 and a semiconductor storage device 200 according to the fifth embodiment will be described.

[0452] [5-1] Composition (Structure)

[0453] The memory controller 300 and the semiconductor storage device 200 according to the fifth embodiment have the same structure as those of the second embodiment except for the following point: That is, the memory controller 300 according to the fifth embodiment does not include the termination circuit 303 .

[0454] The memory system 100 of the fifth embodiment is further different from the second embodiment in the termination method of the wiring of the semiconductor memory device 200. The fifth embodiment is the same as the second embodiment in other respects. Hereinafter, the memory system 100 of the fifth embodiment will be mainly described with respect to the differences from the second embodiment.

[0455] In the second embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203 of the NAND chip A 200A is used. In contrast, in the fifth embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203_C of the NAND chip C 200C is used similarly to the fourth embodiment. Similarly, in the fifth embodiment, when the nodes DQSI, DQSnI, REnI, and REI are terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuits 218_C to 220_C and 222_C are used.

[0456] For example, the transmitters 202_B, 215_B, 216_B, 302, 309 to 311, and 314, and the receivers 201, 212 to 214, 221, 301_B, 306_B, and 307_B of the fifth embodiment have the same structure and function as those of the second embodiment.

[0457] [5-2] Action

[0458] Similar to the first embodiment, in the semiconductor storage device 200 of the fifth embodiment, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same functions as the NAND chip A 200A (described in Figure 2 The sending and receiving method and termination method are the same as those in ( ).

[0459] As described in the first embodiment, when NAND chip A 200A is the selected NAND chip, the terminal circuit of NAND chip A 200A can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In the fifth embodiment, an example of a case where the selected NAND chip is NAND chip A 200A and the terminal circuit of NAND chip C 200C, which is the non-selected NAND chip, is enabled is described.

[0460] A description will be given of a termination method when the semiconductor storage device 200 and the memory controller 300 according to the fifth embodiment receive a DQ signal. Fig.41 FIG. 5 shows a method of terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the fifth embodiment. Fig.41As shown, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI when the receiving section 201 receives the signal LVSTL_IN1 and when the receiving section 301_B receives the signal LVSTL_IN2. The termination circuit 203_C does not terminate the node DQI when the receiving section 201 receives the signal Legacy_IN1.

[0461] The semiconductor memory device 200 of the fifth embodiment has one method for transmitting the signals DQ, DQS, and DQSn, and two methods for receiving the signals DQ, DQS, DQSn, REn, and RE, respectively, as in the second embodiment, and determines which receiving method is selected according to the type of the signal DQ. In addition, the semiconductor memory device 200 can select a termination method according to the transmission and reception method. For the termination of the node DQI, the termination circuit 203_C of the NAND chip C 200C is used. In addition, the memory controller 300 of the fifth embodiment has two methods for transmitting the signals DQ, DQS, DQSn, REn, and RE, respectively, as in the second embodiment, and has one method for receiving the signals DQ, DQS, and DQSn, respectively, and determines which transmission method is selected according to the type of the signal DQ. In addition, the memory controller 300 can select a termination method according to the transmission and reception method.

[0462] The following describes the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the six signals DQ of sending and receiving instructions or addresses, status, parallel status, feature data (FeatureData), data output (DataOutput), and data input (DataInput).

[0463] Fig.42 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.42 Of the signals DQS and DQSn, the signal DQS is shown, but the signal DQSn is a signal of inverted logic of the signal DQS and is therefore the same as the signal DQS. Fig.42 The signal RE is shown for the signal REn and the signal RE, but the signal REn is a signal of the inverted logic of the signal RE, and therefore is the same as the signal RE. Fig.41 As described above, in the fifth embodiment, only the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C which is a non-selected NAND chip are used as termination circuits. Fig.42 As shown, when the type of the signal DQ is a command or an address, the same as in the second embodiment (refer to Fig.26 )same.

[0464] Next, when the type of the signal DQ is the state, as the signal DQ, the signal LVSTL_IN2 is sent from the NAND chip A 200A and is received by the memory controller 300. At this time, the terminal circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS2 is sent from the NAND chip A 200A and is received by the memory controller 300. At this time, the terminal circuits 218_C and 219_C of the NAND chip C 200C terminate the nodes DQSI and DQSnI. In addition, as the signal RE, the signal LVSTL_RE1 is sent from the memory controller 300 and is received by the NAND chip A 200A. At this time, the terminal circuits 220_C and 222_C of the NAND chip C 200C terminate the nodes REnI and REI.

[0465] Next, when the type of the signal DQ is in the parallel state, as the signal DQ, the signal LVSTL_IN2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. At this time, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, as the signal DQS, the signal LVSTL_DQS2 is transmitted from the NAND chip A 200A and the NAND chip B 200B, and is received by the memory controller 300. In this case, the termination circuits 218_C and 219_C of the NAND chip C 200C terminate the nodes DQSI and DQSnI. In addition, as the signal RE, the signal LVSTL_RE1 is transmitted from the memory controller 300, and is received by the NAND chip A 200A and the NAND chip B 200B. At this time, the termination circuits 220_C and 222_C of the NAND chip C 200C terminate the nodes REnI and REI.

[0466] In addition, when the type of the signal DQ is feature data (FeatureData), data output (DataOutput), and data input (DataInput), the same as in the fourth embodiment (refer to Fig.37 )same.

[0467] like Fig.42 As described above, the memory controller 300 and (or) the semiconductor memory device 200 of the fifth embodiment terminates each node when the types of the signal DQ are state, parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of the termination circuit becoming enabled.

[0468] Fig.43 This is an example of a timing chart of signals in the memory system 100 according to the fifth embodiment. Fig.43 This shows the timing at which the terminal circuit becomes enabled when the AND signal DQ is in the state and parallel state. Since the state and parallel state have the same timing diagram, either one is used. Fig.43 For explanation. Fig.43 In, with Fig. 27 Similarly, timing diagrams of signals CEn1 , CEn2 , CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ are shown.

[0469] During the period from time t2 to time t3, the timing diagram of the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is the same as that of the second embodiment. Fig. 27 Regarding the signal CEn2, the following mainly describes the signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ during the period from time ta to time td and from time te to time th.

[0470] The memory system 100 of the fifth embodiment uses a dedicated instruction to determine the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220 and (or) 222_C of the NAND chip C200C, similarly to the fourth embodiment. Specifically, the memory controller 300 controls the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ and controlling the signal CEn2.

[0471] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period including time tb and tc, the memory controller 300 sets the signal CLE to a high level and sends the ODT instruction 97h and the address ADD as the signal DQ. As a result, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C specified by the address ADD become enabled during the period when the signal CEn2 is at a low level. Along with the sending of the ODT instruction 97h and the address ADD, at time tb and tc, the memory controller 300 sets the signal WEn to a high level.

[0472] At time td, the memory controller 300 sets the signal CEn1 to a low level and sets the signal CEn2 to a high level, thereby enabling the NAND chip A 200A and the NAND chip B 200B, and disabling the NAND chip C 200C and the NAND chip D 200D.

[0473] During the period from time t3 to time te, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D are enabled. At time te, the memory controller 300 sets the signals CEn1 and CEn2 to a high level. As a result, the NAND chip A 200A, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D are disabled.

[0474] During the period from time tf to time th, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. At time tg, the memory controller 300 sends the ODT end instruction 9Bh as the signal DQ. During the period from sending the ODT instruction 97h and the address ADD to sending the ODT end instruction 9Bh, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C possessed by the NAND chip C 200C become enabled during the period when the signal CEn2 is at a low level, that is, between time t3 and time te, and between time tf and time tg. Accompanying the sending of the ODT end instruction 9Bh, at time tg, the memory controller 300 sets the signal WEn to a high level.

[0475] At time th, the memory controller 300 sets the signal CEn2 to a high level, thereby disabling the NAND chip C 200C and the NAND chip D 200D.

[0476] In this way, the memory controller 300 controls the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C by sending the ODT command 97h, address ADD, and ODT end command 9Bh in the signal DQ and controlling the signal CEn2.

[0477] Based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C to 220_C and 222_C of the NAND chip C 200C at time t3, and disables the terminal circuits 203_C, 218_C to 220_C and 222_C at time te. That is, the terminal circuits 203_C, 218_C to 220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI, respectively, that is, the time when the terminal circuits 203_C, 218_C to 220_C and 222_C become enabled is between time t3 and time te.

[0478] Similarly, between time tf and time tg, based on the instruction of the memory controller 300, the NAND chip C200C enables the termination circuits 203_C, 218_C to 220_C, and 222_C of the NAND chip C200C. However, the conditions for enabling the termination circuits are unintentionally satisfied only until the ODT end instruction 9Bh becomes effective, and as a result, the termination circuits are enabled. That is, the termination of the nodes DQI, DQSI, DQSnI, REnI, and REI is unintentionally performed, and the termination between time tf and time tg may not be performed.

[0479] The timing diagram for the signal DQ type in the parallel state and the timing for the terminal circuit to become enabled only differs from the reference. Fig.43 What has been described so far is the same as the status.

[0480] The timing diagram when the type of the signal DQ is feature data (FeatureData), data output (DataOutput), and data input (DataInput) and the timing when the terminal circuit becomes enabled are the same as those in the fourth embodiment. That is, the timing diagram when the type of the signal DQ is feature data (FeatureData) and the timing when the terminal circuit becomes enabled are the same as those in the fourth embodiment. Fig.38 The signal DQ is the same as the timing diagram when the data is output (DataOutput) and the timing when the terminal circuit becomes enabled. Fig.39 The signal DQ is the same as the timing diagram when data is input (DataInput) and the timing when the terminal circuit becomes enabled. Fig.40 The timing shown is the same.

[0481] Based on the above timing chart, the timing of enabling the terminal circuit of the memory system 100 of the fifth embodiment is summarized. The timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C is controlled by the memory controller 300 by sending the ODT instruction 95h or 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ, and controlling the signal CEn2. That is, a dedicated instruction for enabling the terminal circuit is used.

[0482] [5-3] Advantages (Effects)

[0483] The memory system 100 according to the fifth embodiment described above includes the transmission units 202_B and 302 and the reception units 201 and 301_B, similarly to the second embodiment. Therefore, the same effects as those of the second embodiment are obtained.

[0484] In addition, according to the memory system 100 of the fifth embodiment, unlike the second embodiment and similar to the fourth embodiment, when terminating the wiring in the semiconductor memory device 200, the termination circuit of the non-selected NAND chip is used. Therefore, compared with the memory system 100 of the second embodiment, the reflection when the signal is transmitted in the wiring can be further reduced.

[0485] In the fifth embodiment, an example is shown in which only the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C are used when terminating the wiring, but the terminal circuits of other NAND chips may be used in combination. For example, when terminating the node DQI, the terminal circuit 203 of the NAND chip A 200A may be used simultaneously for termination, instead of using only the terminal circuit 203_C of the NAND chip C 200C.

[0486] [6] Sixth Embodiment

[0487] Hereinafter, a memory controller 300 and a semiconductor storage device 200 according to the sixth embodiment will be described.

[0488] [6-1] Composition (Structure)

[0489] The memory controller 300 and the semiconductor storage device 200 according to the sixth embodiment have the same structure as those of the third embodiment except for the following point: That is, the memory controller 300 according to the sixth embodiment does not include the termination circuit 303 .

[0490] The memory system 100 of the sixth embodiment is further different from the third embodiment in the termination method of the wiring of the semiconductor memory device 200. The sixth embodiment is the same as the third embodiment in other respects. Hereinafter, the memory system 100 of the sixth embodiment will be mainly described in terms of the differences from the third embodiment.

[0491] In the third embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203 of the NAND chip A 200A is used. In contrast, in the sixth embodiment, when the node DQI is terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuit 203_C of the NAND chip C 200C is used, similarly to the fourth and fifth embodiments. Similarly, in the sixth embodiment, when the nodes DQSI, DQSnI, REnI, and REI are terminated for communication between the memory controller 300 and the NAND chip A 200A, the termination circuits 218_C to 220_C and 222_C are used.

[0492] Except for the points described here, the sixth embodiment is the same as the third embodiment. For example, the transmission units 202_C, 215_C, 216_C, 302_C, 309_C to 311_C, and 314_C, and the reception units 201_C, 212_C to 214_C, 221_C, 301_C, 306_C, and 307_C of the sixth embodiment have the same structure and function as those of the third embodiment.

[0493] [6-2] Action

[0494] Similar to the first embodiment, in the semiconductor storage device 200 of the sixth embodiment, the NAND chip B 200B, the NAND chip C 200C, and the NAND chip D 200D also have the same functions as the NAND chip A 200A (described in Figure 2 The sending and receiving method and termination method are the same as those in ( ).

[0495] As described in the first embodiment, when NAND chip A 200A is the selected NAND chip, the terminal circuit of NAND chip A 200A can be enabled, and the terminal circuit of the non-selected NAND chip can also be enabled. In the sixth embodiment, an example is described in which the terminal circuit of NAND chip C 200C, which is a non-selected NAND chip, is enabled when the selected NAND chip is NAND chip A 200A.

[0496] A description will be given of a termination method when the semiconductor storage device 200 and the memory controller 300 according to the sixth embodiment receive a DQ signal. Fig.44 FIG. 6 shows a method of terminating the signal DQ of the semiconductor memory device 200 and the memory controller 300 according to the sixth embodiment. Fig.44 As shown, the termination circuit 203_C of the NAND chip C 200C terminates the node DQI when the receiving section 201_C receives the signal LVSTL_IN1 and when the receiving section 301_C receives the signal LVSTL_IN2.

[0497] The semiconductor memory device 200 of the sixth embodiment has one method for transmitting the signals DQ, DQS, and DQSn, and one method for receiving the signals DQ, DQS, DQSn, REn, and RE, respectively, similarly to the third embodiment. The transmission and reception method is not limited to the type of the signal DQ, and a signal with a small amplitude is always transmitted and received. In addition, in the semiconductor memory device 200, when the receiving unit 201_C of the NAND chip A 200A receives a signal, the termination circuit 203_C of the NAND chip C 200C always terminates the node DQI. Similarly, the memory controller 300 of the sixth embodiment has one method for transmitting the signals DQ, DQS, DQSn, REn, and RE, and one method for receiving the signals DQ, DQS, and DQSn, respectively, similarly to the third embodiment. The transmission and reception method is not limited to the type of the signal DQ, and a signal with a small amplitude is always transmitted and received. In addition, when the receiving section 301_C receives a signal in the memory controller 300 , the termination circuit 203_C always terminates the node DQI.

[0498] The following describes the sending and receiving methods and termination methods of the signals DQ, DQS, DQSn, REn, and RE for the six signals DQ of sending and receiving instructions or addresses, status, parallel status, feature data (FeatureData), data output (DataOutput), and data input (DataInput).

[0499] Fig.45 This is an example of a method for transmitting and receiving signals DQ, DQS, and RE, and a method for terminating signals. Fig.45 Of the signals DQS and DQSn, the signal DQS is shown, but the signal DQSn is a signal of inverted logic of the signal DQS and is therefore the same as the signal DQS. Fig.45 The signal RE of the signals REn and RE is shown, but the signal REn is a signal of the inverted logic of the signal RE, and therefore is the same as the signal RE. Fig.44As described above, in the sixth embodiment, only the termination circuits 203_C, 218_C, 219_C, 220 and (or) 222_C of the NAND chip C 200C which is a non-selected NAND chip are used as termination circuits. Fig.45 As shown, when the type of the signal DQ is a command or an address, as the signal DQ, the signal LVSTL_IN1 is sent from the memory controller 300 and is received by the NAND chip A 200A and the NAND chip B 200B. At this time, the terminal circuit 203_C of the NAND chip C 200C terminates the node DQI. In addition, the nodes DQSO and DQSnO of the memory controller 300, the node of the signal REn of the output transmission unit 311, and the node of the signal RE of the output transmission unit 314 are in an electrically floating state. At this time, the terminal circuits 218_C to 220_C and 222_C of the NAND chip C 200C terminate the nodes DQSI, DQSnI, REnI, and REI, respectively. As a result, the wirings that transmit the signals DQS, DQSn, REn, and RE, respectively, are suppressed from being electrically floating.

[0500] In addition, when the types of the signal DQ are state, parallel state, and data output (DataOutput), the same as in the fifth embodiment (refer to Fig.42 )same.

[0501] When the type of the signal DQ is feature data (FeatureData), the signals DQ and DQS are the same as those in the fifth embodiment (see Fig.42 ). The node of the signal REn of the output transmission unit 311 and the node of the signal RE of the output transmission unit 314 of the memory controller 300 are in an electrically floating state. At this time, the terminal circuits 220_C and 222_C of the NAND chip C 200C terminate the nodes REnI and REI. Thus, the wiring of the transmission signals REn and RE is suppressed from being electrically floating.

[0502] When the type of the signal DQ is data input (DataInput), the signals DQ and DQS are the same as those in the fifth embodiment (refer to Fig.42 ). The node of the signal REn of the output transmission unit 311 and the node of the signal RE of the output transmission unit 314 of the memory controller 300 are in an electrically floating state. At this time, the terminal circuits 220_C and 222_C of the NAND chip C 200C terminate the nodes REnI and REI. Thus, the wiring of the transmission signals REn and RE is suppressed from being electrically floating.

[0503] like Fig.45As described above, the memory controller 300 and (or) the semiconductor memory device 200 of the sixth embodiment terminates each node when the type of the signal DQ is command or address, state, parallel state, feature data (FeatureData), data output (DataOutput), and data input (DataInput). The following describes the timing of the termination circuit becoming enabled.

[0504] Fig.46 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment. Fig.46 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is command, address, or data input (DataInput). Fig.46 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ. Fig.46 The following is an example of data writing.

[0505] The timing diagram of signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn and DQ is the same as that of the fourth embodiment. Fig.40 Again, the description is omitted. Hereinafter, the signal CEn2 is mainly described.

[0506] The memory system 100 of the sixth embodiment uses a dedicated instruction to determine the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C, similarly to the fourth and fifth embodiments. Specifically, the memory controller 300 controls the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ and controlling the signal CEn2.

[0507] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period from time ta to time th, the memory controller 300 sets the signal CEn2 to a low level. At time th, the memory controller 300 sets the signal CEn2 to a high level. As a result, the NAND chip C 200C and the NAND chip D 200D become disabled.

[0508] During the period from sending the ODT command 97h and the address ADD to sending the ODT end command 9Bh, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C become enabled while the signal CEn2 is at a low level, that is, between time tc and time tg.

[0509] In this way, the memory controller 300 controls the timing of enabling the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT command 97h, the address ADD, and the ODT end command 9Bh in the signal DQ and controlling the signal CEn2. The sixth embodiment always enables the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by always setting the signal CEn2 to a low level during at least the entire period (time td to time te) including the period during which the memory controller 300 and the NAND chip A 200A transmit and receive the signal DQ.

[0510] Specifically, based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C to 220_C and 222_C of the NAND chip C 200C at time tc, and disables the terminal circuits 203_C, 218_C to 220_C and 222_C at time tg. That is, the terminal circuits 203_C, 218_C to 220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI, respectively, i.e., the time when the terminal circuits 203_C, 218_C to 220_C and 222_C become enabled is between time tc and time tg. This is because in the sixth embodiment, the signal transmitted and received is one type, and the terminal circuit can be always enabled when the memory controller 300 enables the NAND chip A 200A for the purpose of communicating with the NAND chip A 200A.

[0511] Fig.47 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment. Fig.47 Indicates the timing at which the terminal circuit becomes enabled when the type of the signal DQ is state and parallel state. Fig.47 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0512] The timing diagram of signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn and DQ is the same as that of the fifth embodiment. Fig.43 Again, the description is omitted. Hereinafter, the signal CEn2 is mainly described.

[0513] exist Fig.47 In, with Fig.46 Similarly, a dedicated instruction is used to determine the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C. Specifically, the memory controller 300 controls the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ and controlling the signal CEn2.

[0514] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period from time ta to time th, the memory controller 300 sets the signal CEn2 to a low level. At time th, the memory controller 300 sets the signal CEn2 to a high level. As a result, the NAND chip C 200C and the NAND chip D 200D become disabled.

[0515] During the period from sending the ODT instruction 97h and the address ADD to sending the ODT end instruction 9Bh, the terminal circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C possessed by the NAND chip C200C become enabled while the signal CEn2 is at a low level, that is, between time tc and time tg.

[0516] Based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C~220_C and 222_C of the NAND chip C 200C at time tc, and disables the terminal circuits 203_C, 218_C~220_C and 222_C at time tg. That is, the terminal circuits 203_C, 218_C~220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI respectively, that is, the time when the terminal circuits 203_C, 218_C~220_C and 222_C become enabled is between time tc and time tg.

[0517] Fig.48This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment. Fig.48 Indicates the timing at which the terminal circuit becomes enabled when the type of the signal DQ is feature data (FeatureData). Fig.48 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0518] The timing diagram of signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ is the same as that of the fourth embodiment. Fig.38 Again, the description is omitted. Hereinafter, the signal CEn2 is mainly described.

[0519] At Fig.48 In, with Fig.46 Similarly, a dedicated instruction is used to determine the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C. Specifically, the memory controller 300 controls the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ and controlling the signal CEn2.

[0520] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period from time ta to time th, the memory controller 300 sets the signal CEn2 to a low level. At time th, the memory controller 300 sets the signal CEn2 to a high level. As a result, the NAND chip C 200C and the NAND chip D 200D become disabled.

[0521] During the period from sending the ODT command 97h and the address ADD to sending the ODT end command 9Bh, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C become enabled while the signal CEn2 is at a low level, that is, between time tc and time tg.

[0522] Based on the instruction of the memory controller 300, the NAND chip C 200C enables the terminal circuits 203_C, 218_C to 220_C and 222_C of the NAND chip C 200C at time tc, and disables the terminal circuits 203_C, 218_C to 220_C and 222_C at time tg. That is, the terminal circuits 203_C, 218_C to 220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI, that is, the time when the terminal circuits 203_C, 218_C to 220_ and 222_C become enabled is between time tc and time tg.

[0523] Fig.49 This is an example of a timing chart of signals of the memory system 100 according to the sixth embodiment. Fig.48 Indicates the timing when the terminal circuit becomes enabled when the type of signal DQ is data output (DataOutput). Fig.49 2 is a timing diagram of signals CEn1, CEn2, CLE, ALE, WEn, REn, RE, DQS, DQSn, and DQ.

[0524] The timing diagram of signals CEn1, CLE, ALE, WEn, REn, RE, DQS, DQSn and DQ is the same as that of the fourth embodiment. Fig.39 Again, the description is omitted. Hereinafter, the signal CEn2 is mainly described.

[0525] exist Fig.49 In, with Fig.46 Similarly, a dedicated instruction is used to determine the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C. Specifically, the memory controller 300 controls the timing to enable the termination circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C by sending the ODT instruction 97h, the address ADD, and the ODT end instruction 9Bh in the signal DQ and controlling the signal CEn2.

[0526] At time ta, the memory controller 300 sets the signal CEn2 to a low level. As a result, the NAND chip C 200C and the NAND chip D 200D become enabled. During the period from time ta to time th, the memory controller 300 sets the signal CEn2 to a low level. At time th, the memory controller 300 sets the signal CEn2 to a high level. As a result, the NAND chip C 200C and the NAND chip D 200D become disabled.

[0527] During the period from sending the ODT command 97h and the address ADD to sending the ODT end command 9Bh, the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C200C become enabled while the signal CEn2 is at a low level, that is, between time tc and time tg.

[0528] Based on the instruction of the memory controller 300, the NAND chip A 200A enables the terminal circuits 203_C, 218_C to 220_C and 222_C of the NAND chip C 200C at time tc, and disables the terminal circuits 203_C, 218_C to 220_C and 222_C at time tg. That is, the terminal circuits 203_C, 218_C to 220_C and 222_C terminate the nodes DQI, DQSI, DQSnI, REnI and REI, that is, the time when the terminal circuits 203_C, 218_C to 220_C and 222_C become enabled is between time tc and time tg.

[0529] Based on the above timing chart, the timing of enabling the terminal circuit of the memory system 100 of the sixth embodiment is summarized. The timing of enabling the terminal circuits 203_C, 218_C, 219_C, 220_C and (or) 222_C of the NAND chip C 200C is controlled by the memory controller 300 by sending the ODT command 97h, the address ADD, and the ODT end command 9Bh in the signal DQ, and controlling the signal CEn2. That is, a dedicated command for enabling the terminal circuit is used.

[0530] [6-3] Advantages (Effects)

[0531] The memory system 100 according to the sixth embodiment described above includes the transmission units 202_C and 302_C and the reception units 201_C and 301_C, similarly to the third embodiment. Therefore, the same effects as those of the third embodiment are obtained.

[0532] Furthermore, according to the memory system 100 of the sixth embodiment, unlike the third embodiment and similar to the fourth and fifth embodiments, a termination circuit of the non-selected NAND chip is used when terminating the wiring in the semiconductor memory device 200. Therefore, compared with the memory system 100 of the third embodiment, reflection when the signal is transmitted in the wiring can be further reduced.

[0533] Furthermore, according to the memory system 100 of the sixth embodiment, since the LVSTL termination circuit with low power consumption is used, the termination circuit can be enabled for a long period of time.

[0534] In the sixth embodiment, an example is shown in which only the terminal circuits 203_C, 218_C, 219_C, 220_C, and (or) 222_C of the NAND chip C 200C are used when terminating the wiring, but in practice, terminal circuits of other NAND chips may be used in combination. For example, when terminating the node DQI, the terminal circuit 203 of the NAND chip A 200A may be used simultaneously for termination, instead of using only the terminal circuit 203_C of the NAND chip C 200C.

[0535] [7] Other variations, etc.

[0536] In the first to sixth embodiments of the present invention, the memory system 100 may have other structures. For example, it may include components not shown in the figure and may be connected by wiring or the like not shown in the figure.

[0537] In this specification, "connection" means electrical connection, and does not exclude the possibility of other components being interposed therebetween. "Electrical connection" may be through an insulator as long as the electrical connection can be operated in the same manner as the electrically connected component.

[0538] The first to sixth embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. The first to sixth embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The first to sixth embodiments or their variations are included in the scope or spirit of the present invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor storage device, comprising: A first pin receiving a first signal and a second signal having a smaller amplitude than the first signal; a first receiving circuit connected to the first pin, differentially amplifying the first signal and the first voltage to output a third signal, and differentially amplifying the second signal and the second voltage to output a fourth signal having a smaller amplitude than the third signal; and The first terminal circuit is connected to the first pin, and is in a disabled state when the first pin receives the first signal, and is in an enabled state when the first pin receives the second signal. 2 . The semiconductor memory device according to claim 1 , wherein the second voltage is lower than the first voltage.

3. The semiconductor memory device according to claim 1, wherein the first termination circuit comprises: a first resistor and a first switch connected in series between the first pin and a node to which a ground voltage is supplied.

4. The semiconductor memory device according to claim 1, wherein the first signal comprises a command or an address; and The second signal includes a parameter value or write data.

5. The semiconductor memory device according to claim 1, further comprising a first transmission circuit, the first transmission circuit outputting a fifth signal and a sixth signal having a smaller amplitude than the fifth signal to the first pin; and The fifth signal includes data indicating a status; The sixth signal includes read data.

6. The semiconductor memory device according to claim 1, further comprising a first transmission circuit that outputs a fifth signal to the first pin; and The fifth signal includes data indicating a state or read data.

7. The semiconductor memory device according to claim 6, wherein an output node of the first transmission circuit is connected to a node to which a power supply voltage is supplied via an NMOS transistor.

8. The semiconductor memory device according to claim 1, further comprising: A second pin receives a fifth signal and a sixth signal having an amplitude smaller than that of the fifth signal; a second receiving circuit connected to the second pin, differentially amplifying the fifth signal and the first voltage to output a seventh signal, and differentially amplifying the sixth signal and the second voltage to output an eighth signal having a smaller amplitude than the seventh signal; a second terminal circuit connected to the second pin, which is in a disabled state when the second pin receives the fifth signal, and is in an enabled state when the second pin receives the sixth signal; A third pin receives a ninth signal and a tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin, differentially amplifying the ninth signal and the first voltage to output an eleventh signal, and differentially amplifying the tenth signal and the second voltage to output a twelfth signal having a smaller amplitude than the eleventh signal; and The third terminal circuit is connected to the third pin, and is in a disabled state when the third pin receives the ninth signal, and is in an enabled state when the third pin receives the tenth signal.

9. The semiconductor memory device according to claim 8, further comprising: A fourth pin receives a 13th signal and a 14th signal having a smaller amplitude than the 13th signal; a fourth receiving circuit connected to the fourth pin, differentially amplifying the 13th signal and the first voltage to output a 15th signal, and differentially amplifying the 14th signal and the second voltage to output a 16th signal having a smaller amplitude than the 15th signal; a fourth terminal circuit connected to the fourth pin, which becomes a disabled state when the fourth pin receives the thirteenth signal, and becomes an enabled state when the fourth pin receives the fourteenth signal; The fifth pin receives the 17th signal and the 18th signal having a smaller amplitude than the 17th signal; a fifth receiving circuit connected to the fifth pin, differentially amplifying the seventeenth signal and the first voltage to output a nineteenth signal, and differentially amplifying the eighteenth signal and the second voltage to output a twenty-second signal having a smaller amplitude than the nineteenth signal; and The fifth terminal circuit is connected to the fifth pin, and is in a disabled state when the fifth pin receives the seventeenth signal, and is in an enabled state when the fifth pin receives the eighteenth signal.

10. The semiconductor memory device according to claim 9, further comprising a first circuit and a latch circuit, wherein the first circuit is connected to the second receiving circuit and the third receiving circuit, and outputting a 21st signal and a 22nd signal based on the 7th signal and the 11th signal, or outputting the 21st signal and the 22nd signal based on the 8th signal and the 12th signal; The latch circuit stores data included in the third signal or the fourth signal based on the 21st signal and the 22nd signal. 11 . The semiconductor memory device according to claim 1 , further comprising a first chip, wherein the first chip includes the first pin, the first receiving circuit, and the first terminal circuit.

12. The semiconductor memory device according to claim 1, further comprising: A first chip, comprising the first pin and the first receiving circuit; and The second chip includes the first terminal circuit.

13. The semiconductor storage device according to claim 12, wherein the first terminal circuit becomes enabled during a period from receiving the first command as the first signal to before receiving the second command, while the second chip is receiving a signal for setting the second chip to an enabled state.

14. A memory system comprising: a first transmitting circuit that receives a first signal and outputs a second signal having a smaller amplitude than the first signal; A first pin, receiving the second signal; a first receiving circuit connected to the first pin, differentially amplifying the second signal and the first voltage, and outputting a third signal; and a first terminal circuit connected to the first pin and being enabled during a period when the first pin receives the second signal; and An output node of the first transmission circuit is connected to a node to which a power supply voltage is supplied via an NMOS transistor. 15 . The memory system according to claim 14 , wherein the first termination circuit comprises: a first resistor and a first switch connected in series between the first pin and a node to which a ground voltage is supplied. The memory system of claim 14 , wherein the first signal comprises a command or an address. The memory system according to claim 16 , wherein the first signal further includes a value of a parameter or write data.

18. The memory system according to claim 14, further comprising a second transmitting circuit, the second transmitting circuit receiving a fourth signal and outputting a fifth signal having a smaller amplitude than the fourth signal to the first pin; and The fifth signal includes data indicating a state or read data; An output node of the second transmission circuit is connected to a node to which a power supply voltage is supplied via an NMOS transistor.

19. The memory system of claim 14, further comprising: a second transmitting circuit receiving the fourth signal and outputting a fifth signal having a smaller amplitude than the fourth signal; The second pin receives the fifth signal; a second receiving circuit connected to the second pin, differentially amplifying the fifth signal and the first voltage, and outputting a sixth signal; a second terminal circuit connected to the second pin and being in an enabled state during a period when the second pin receives the fifth signal; a third transmitting circuit receiving the seventh signal and outputting an eighth signal having a smaller amplitude than the seventh signal; The third pin receives the eighth signal; a third receiving circuit connected to the third pin, differentially amplifying the eighth signal and the first voltage, and outputting a ninth signal; and The third terminal circuit is connected to the third pin and becomes enabled while the third pin receives the eighth signal.

20. The memory system of claim 19, further comprising: a fourth transmitting circuit receiving a tenth signal and outputting an eleventh signal having a smaller amplitude than the tenth signal; The fourth pin receives the eleventh signal; a fourth receiving circuit connected to the fourth pin, differentially amplifying the eleventh signal and the first voltage, and outputting a twelfth signal; a fourth terminal circuit connected to the fourth pin and being in an enabled state during a period when the fourth pin receives the eleventh signal; a fifth transmitting circuit that receives the thirteenth signal and outputs a fourteenth signal having a smaller amplitude than the thirteenth signal; The fifth pin receives the fourteenth signal; a fifth receiving circuit connected to the fifth pin, differentially amplifying the fourteenth signal and the first voltage, and outputting a fifteenth signal; and The fifth terminal circuit is connected to the fifth pin and becomes enabled while the fifth pin receives the fourteenth signal.

21. The memory system according to claim 20, further comprising a first circuit and a latch circuit, wherein the first circuit is connected to the second receiving circuit and the third receiving circuit, and Based on the sixth signal and the ninth signal, output a sixteenth signal and a seventeenth signal; The latch circuit stores data included in the third signal based on the sixteenth signal and the seventeenth signal. 22 . The memory system according to claim 14 , further comprising a first chip, wherein the first chip comprises the first pin, the first receiving circuit, and the first terminal circuit.

23. The memory system of claim 14, further comprising: A first chip, comprising the first pin and the first receiving circuit; and The second chip includes the first terminal circuit.

24. The memory system according to claim 23, wherein the first terminal circuit becomes enabled when the second chip is receiving a signal for enabling the second chip during a period from when the first command is received as the first signal to before when the second command is received.

25. The memory system of claim 14, further comprising: A memory controller, comprising the first sending circuit; and The semiconductor storage device includes the first pin and the first terminal circuit.

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