Electrode portion of semiconductor device and method for manufacturing the same

Abstract

A method of manufacturing an electrode portion of a semiconductor device includes a step of preparing a semiconductor substrate having an impurity-added region. The method also includes a step of forming a first metal layer on the impurity-added region. The method also includes a step of forming a second metal layer on the first metal layer. The method also includes a step of heating the semiconductor substrate including the first metal layer and the second metal layer. The impurity-added region contains silicon. The first metal layer contains tantalum. The second metal layer contains titanium. By the step of heating, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity-added region, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

Description

Technical Field

[0001] The exemplary embodiments of the present invention relate to the electrode portion of a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicides, formed by combining metals and silicon, are used as materials for the electrode portions of semiconductor devices. Patent Documents 1 through 9 disclose such silicides. Furthermore, Patent Document 10 discloses a method for adding boron (B) to a titanium silicide layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-527111

[0006] Patent Document 2: Japanese Patent Application Publication No. 2006-186326

[0007] Patent Document 3: Japanese Patent Application Publication No. 2000-349169

[0008] Patent Document 4: Japanese Patent Application Publication No. 9-321280

[0009] Patent Document 5: Japanese Patent Application Publication No. 9-171969

[0010] Patent Document 6: Japanese Patent Application Publication No. 5-315286

[0011] Patent Document 7: Japanese Patent Application Publication No. 3-209773

[0012] Patent Document 8: Japanese Patent Application Publication No. 5-182982

[0013] Patent Document 9: US Patent No. 7,518,921

[0014] Patent Document 10: U.S. Patent No. 5,721,175 Summary of the Invention

[0015] The technical problem that the invention aims to solve

[0016] This invention provides a technique for suppressing the increase of contact resistance in the electrode portion of a semiconductor device.

[0017] Technical solutions for solving technical problems

[0018] In one exemplary embodiment, a method for manufacturing an electrode portion of a semiconductor device is provided. The method includes the step of preparing a semiconductor substrate having impurity addition regions. The method further includes the step of forming a first metal layer on the impurity addition regions. The method further includes the step of forming a second metal layer on the first metal layer. The method further includes the step of heating the semiconductor substrate including the first and second metal layers. The impurity addition regions contain silicon. The first metal layer contains tantalum. The second metal layer contains titanium. Through the heating step described above, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity addition regions, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

[0019] Invention Effects

[0020] According to an exemplary embodiment, it is possible to suppress the increase in contact resistance in the electrode portion of a semiconductor device. Attached Figure Description

[0021] Figure 1 of (a), Figure 1 (b) Figure 1 (c) and Figure 1 (d) is a diagram illustrating the manufacturing method of the electrode portion of the semiconductor device according to the first embodiment.

[0022] Figure 2 of (a), Figure 2 (b) Figure 2 (c) and Figure 2 (d) is a diagram illustrating the manufacturing method of the electrode portion of the semiconductor device according to the second embodiment.

[0023] Figure 3 of (a), Figure 3 (b) and Figure 3 (c) is a diagram illustrating the manufacturing method of the electrode portion of the semiconductor device of the comparative example.

[0024] Figure 4 of (a), Figure 4 (b) Figure 4 (c) and Figure 4 (d) represents the depth D (nm) from the substrate surface in the comparative example and the impurity concentration Ci (cm). -3 A diagram showing the relationship between ).

[0025] Figure 5 of (a), Figure 5 (b) Figure 5 (c) Figure 5 (d) Figure 5 of (e) Figure 5 (f) and Figure 5 (g) is a diagram illustrating a first manufacturing method of a semiconductor device having an electrode portion according to an exemplary embodiment.

[0026] Figure 6 of (a), Figure 6 (b) Figure 6 (c) and Figure 6 (d) is a diagram illustrating a second manufacturing method of a semiconductor device having an electrode portion according to an exemplary embodiment.

[0027] Figure 7 (a) and Figure 7 (b) is a diagram illustrating a third manufacturing method of a semiconductor device having an electrode portion according to an exemplary embodiment. Detailed Implementation

[0028] The following describes various exemplary embodiments.

[0029] In one exemplary embodiment, a method for manufacturing an electrode portion of a semiconductor device is provided. The manufacturing method includes the step of preparing a semiconductor substrate having impurity addition regions. The manufacturing method further includes the step of forming a first metal layer on the impurity addition regions. The manufacturing method further includes the step of forming a second metal layer on the first metal layer. The manufacturing method further includes the step of heating the semiconductor substrate including the first metal layer and the second metal layer. The impurity addition regions contain silicon (Si). The first metal layer contains tantalum (Ta). The second metal layer contains titanium (Ti). Through the above-described heating step, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity addition regions, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

[0030] When titanium bonds with impurities in the impurity addition region, the impurity concentration in the impurity addition region decreases. Furthermore, when titanium bonds with impurities in the impurity addition region, a layer with high resistivity is sometimes formed. According to the method for manufacturing the electrode portion of the semiconductor device according to the above embodiment, tantalum contained in the first metal layer and the first silicide layer suppresses the diffusion of impurities contained in the impurity addition region and the bonding of impurities with titanium contained in the second metal layer. Therefore, according to this manufacturing method, the contact resistance between the impurity addition region and the first silicide layer can be reduced.

[0031] In one exemplary embodiment, a method for manufacturing an electrode portion of a semiconductor device is provided. The method includes the step of preparing a semiconductor substrate having an impurity addition region and an oxide film formed on the impurity addition region. The method further includes the step of forming a first metal layer on the impurity addition region through the oxide film. The method further includes the step of forming a second metal layer on the first metal layer. The method further includes the step of heating the semiconductor substrate including the first and second metal layers. The impurity addition region contains silicon (Si). The oxide film contains silicon dioxide (SiO2). The first metal layer contains a high-melting-point metal, which contains at least one selected from tantalum (Ta), tungsten (W), and molybdenum (Mo). The second metal layer contains titanium (Ti). Through the heating step described above, a first silicide layer containing titanium, the aforementioned high-melting-point metal, and silicon is formed on the semiconductor substrate, and a second silicide layer containing titanium and silicon is formed on the first silicide layer. Additionally, through the heating step described above, a titanium oxide layer is formed on the second silicide layer.

[0032] Similarly, the high-melting-point metals contained in the first metal layer and the first silicide layer suppress the diffusion of impurities contained in the impurity addition region and the bonding of impurities with titanium contained in the second metal layer. Therefore, the contact resistance between the impurity addition region and the first silicide layer can be reduced.

[0033] Furthermore, during the heating step described above, the oxygen contained in the oxide film combines with the titanium contained in the second metal layer to form a titanium oxide layer. As a result, the oxide film that might hinder a uniform silanization reaction between the impurity addition region and the first metal layer can be removed. Therefore, the inhomogeneity of the silanization reaction between the impurity addition region and the first metal layer is reduced.

[0034] An exemplary embodiment of a semiconductor device includes an electrode portion comprising a first silicide layer and a second silicide layer. The first silicide layer is located on an impurity addition region and contains titanium, tantalum, and silicon.

[0035] The second silicide layer is located on the first silicide layer and contains titanium and silicon.

[0036] An exemplary embodiment of a semiconductor device includes an electrode portion comprising a first silicide layer, a second silicide layer, and a titanium oxide layer. The first silicide layer is located on an impurity addition region and contains titanium, a high-melting-point metal, and silicon. The second silicide layer is located on the first silicide layer and contains titanium and silicon. The titanium oxide layer is located on the second silicide layer. The high-melting-point metal contains at least one selected from tantalum, tungsten, and molybdenum.

[0037] In one exemplary embodiment, the impurity in the impurity addition region is boron (B).

[0038] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. Furthermore, in each drawing, the same or equivalent parts are labeled with the same reference numerals, and repeated descriptions are omitted.

[0039] [First Implementation Method]

[0040] The following is for reference Figure 1 of (a), Figure 1 (b) Figure 1 (c) and Figure 1 (d) describes the manufacturing method of the electrode portion of the semiconductor device according to the first embodiment. Figure 1 of (a), Figure 1 (b) Figure 1 (c) and Figure 1 Figure (d) illustrates a method for manufacturing the electrode portion of the semiconductor device according to the first embodiment. This method includes (a) a substrate preparation step, (b) a first metal layer formation step, (c) a second metal layer formation step, and (d) a heating step. The steps (a) substrate preparation, (b) first metal layer formation, (c) second metal layer formation, and (d) heating are performed sequentially. These steps will be described below.

[0041] (a) Substrate preparation steps

[0042] In the substrate preparation step, the semiconductor substrate is prepared. For example... Figure 1 As shown in (a), the semiconductor substrate has an impurity addition region 3 (diffusion layer). The impurity addition region 3 is located on the surface side of the semiconductor substrate. The semiconductor substrate and the impurity addition region 3 contain silicon. The impurity in the impurity addition region 3 is boron. The impurity addition region 3 is formed by implanting impurity ions into the semiconductor substrate. After this ion implantation, the impurities in the impurity addition region 3 are electrically activated by heating (annealing) the semiconductor substrate. For example, the annealing temperature is 800°C and the annealing time is several tens of minutes. As another example, the annealing temperature is above 1000°C and the annealing time is a very short time (e.g., less than 1 second).

[0043] (b) Steps for forming the first metal layer

[0044] In the first metal layer formation step, such as Figure 1 As shown in (b), a first metal layer 61 is formed on the impurity addition region 3. The first metal layer 61 is formed by a method such as sputtering. The first metal layer 61 is a tantalum layer containing tantalum. The thickness of the first metal layer 61 is, for example, 2 nm to 100 nm.

[0045] (c) Step for forming the second metal layer

[0046] In the second metal layer formation step, such as Figure 1 As shown in (c), a second metal layer 62 is formed on the first metal layer 61. The second metal layer 62 is formed by a method such as sputtering. The second metal layer 62 is a titanium layer containing titanium. The thickness of the second metal layer 62 is, for example, 2 nm to 100 nm.

[0047] (d) Heating steps

[0048] In the heating step (annealing step for silaneization), the semiconductor substrate comprising the first metal layer 61 and the second metal layer 62 is heated (annealed). For example, under the first annealing condition, the annealing temperature is 650°C and the annealing time is 30 seconds. As another example, under the second annealing condition, the annealing temperature is 900°C and the annealing time is 30 seconds. The semiconductor substrate may also be annealed under the first annealing condition and then annealed under the second annealing condition.

[0049] Through this annealing, a silicide reaction occurs between the materials constituting the impurity addition region 3, the first metal layer 61, and the second metal layer 62. The silicon contained in the impurity addition region 3 is consumed during the silicide reaction. The result of the silicide reaction carried out by this annealing is as follows: Figure 1 As shown in (d), a silicide layer 9 is formed. The silicide layer 9 includes a first silicide layer 91 and a second silicide layer 92. The first silicide layer 91 is formed on the impurity addition region 3. The second silicide layer 92 is formed on the first silicide layer 91. Through this annealing, an electrode portion of a semiconductor device including the first silicide layer 91 and the second silicide layer 92 is provided.

[0050] The first silicide layer 91 is formed of a compound containing titanium, tantalum, and silicon (Ti-Ta-Si). The second silicide layer 92 is formed of a compound containing titanium and silicon (TiSi). X ) is formed. Here, "TiSi" X For example, the "X" in "" is 2.

[0051] In this embodiment, the impurity concentration at the interface between the first silicide layer 91 after the silicide reaction and the impurity addition region 3 is 1×10⁻⁶. 20 cm -3 The above. The impurities in this interface are activated impurities. Typically, the concentration of activated impurities is 1×10⁻⁶. 20 cm -3 Under the above conditions, good electrical conductivity can be obtained. To achieve good electrical conductivity after silicide formation, the impurity concentration in the activated impurity addition region 3 in "(a) Substrate Preparation Step" is set to be greater than 1×10⁻⁶. 20 cm -3 High. For example, the impurity concentration before the silicide reaction is set at a position corresponding to the interface between the first silicide layer 91 and the impurity addition region 3 after the silicide reaction, which is 5 × 10⁻⁶.20 cm -3 That's all. In addition, in the above-mentioned "(a) Substrate preparation step", the peak position of the impurity concentration in the impurity addition region 3 is set to, for example, a position 100 nm or less from the substrate surface.

[0052] <Effect 1>

[0053] In the aforementioned "(d) heating step," when titanium bonds with the impurities in the impurity addition region 3, the impurity concentration in the impurity addition region 3 decreases. Furthermore, when titanium bonds with the impurities in the impurity addition region 3, a titanium boride layer (TiB2 layer) with high resistivity is sometimes formed. The tantalum contained in the first metal layer 61 and the first silicide layer 91 suppresses the diffusion of impurities contained in the impurity addition region 3 and the bonding of impurities with titanium contained in the second metal layer 62. Therefore, according to this manufacturing method, the contact resistance between the impurity addition region 3 and the first silicide layer 91 can be reduced.

[0054] <Effect 2>

[0055] In semiconductor device manufacturing methods, after forming the silicide layer 9, the semiconductor substrate is sometimes heated at a high temperature. For example, after forming the silicide layer 9, the semiconductor substrate is heated to a temperature of 1000°C for a few seconds. As another example, after forming the silicide layer 9, the semiconductor substrate is heated to a temperature of approximately 850°C for about one hour. As yet another example, heat treatment of the semiconductor substrate at temperatures above 800°C (around 850°C) is performed, for example, in the step of forming silicon channels in a three-dimensional NAND flash memory. Such heat treatment is also performed when manufacturing a three-dimensional LSI.

[0056] The first silicide layer 91 contains tantalum, which, like the first metal layer 61, suppresses the diffusion and bonding of boron and titanium. Therefore, the increase in contact resistance is suppressed by utilizing the first silicide layer 91. Furthermore, the first silicide layer 91 provides a contact with strong resistance to thermal coagulation and high heat resistance.

[0057] [Second Implementation]

[0058] The following is for reference Figure 2 of (a), Figure 2 (b) Figure 2 (c) and Figure 2 (d) describes the manufacturing method of the electrode portion of the semiconductor device according to the second embodiment. Figure 2 of (a), Figure 2 (b) Figure 2 (c) and Figure 2Figure (d) illustrates a method for manufacturing the electrode portion of the semiconductor device according to the second embodiment. This method includes (a) a substrate preparation step, (b) a first metal layer formation step, (c) a second metal layer formation step, and (d) a heating step. The steps (a) substrate preparation, (b) first metal layer formation, (c) second metal layer formation, and (d) heating are performed sequentially. These steps will be described below.

[0059] (a) Substrate preparation steps

[0060] In the substrate preparation step, the semiconductor substrate is prepared. For example... Figure 2 As shown in (a), the semiconductor substrate has an impurity addition region 3 and an oxide film 20 formed on the impurity addition region 3. The impurity addition region 3 is located on the surface side of the semiconductor substrate. The semiconductor substrate and the impurity addition region 3 contain silicon.

[0061] The oxide film 20 contains silicon dioxide. The thickness of the oxide film 20 is approximately 1 to 2 nm. The oxide film 20 is a native oxide film. A native oxide film can be formed by exposing the exposed surface of the impurity addition region 3 to air or an oxygen atmosphere. The oxide film 20 can also be formed by cleaning or the like. In this case, the oxide film 20 is a chemical oxide. The "(a) substrate preparation step" of the second embodiment is the same as the "(a) substrate preparation step" of the first embodiment, except that the oxide film 20 is formed on the surface of the impurity addition region 3, and the various conditions are also the same as the corresponding conditions of the "(a) substrate preparation step" of the first embodiment.

[0062] (b) Steps for forming the first metal layer

[0063] In the first metal layer formation step, such as Figure 2 As shown in (b), a first metal layer 61 is formed on the impurity addition region 3, separated by an oxide film 20. The first metal layer 61 is formed by a sputtering method or the like. The first metal layer 61 is a high-melting-point metal layer containing a high-melting-point metal. The high-melting-point metal contains at least one selected from tantalum, tungsten, and molybdenum. In the second embodiment, the thickness of the first metal layer 61 can be set to be the same as the thickness of the first metal layer 61 in the first embodiment.

[0064] (c) Step for forming the second metal layer

[0065] In the second metal layer formation step, such as Figure 2As shown in (c), a second metal layer 62 is formed on the first metal layer 61. The "(c) second metal layer formation step" of the second embodiment is the same as the "(c) second metal layer formation step" of the first embodiment, and its various conditions are also the same as the corresponding conditions of the "(c) second metal layer formation step" of the first embodiment.

[0066] (d) Heating steps

[0067] In the heating step (annealing step for siliconization reaction), the semiconductor substrate including the first metal layer 61 and the second metal layer 62 is heated (annealed). The "(d) heating step" of the second embodiment is the same as the "(d) heating step" of the first embodiment, and its various conditions are also the same as the corresponding conditions of the "(d) heating step" of the first embodiment.

[0068] The result of the silanization reaction carried out by this annealing is as follows: Figure 2 As shown in (d), a silicide layer 9 is formed. The silicide layer 9 includes a first silicide layer 91 and a second silicide layer 92. This annealing provides an electrode portion for a semiconductor device including the first silicide layer 91 and the second silicide layer 92. The first silicide layer 91 is formed on the impurity addition region 3. The second silicide layer 92 is formed on the first silicide layer 91. Additionally, this annealing forms a titanium oxide layer 21 on the second silicide layer 92.

[0069] The first silicide layer 91 is formed of a compound containing titanium, a high-melting-point metal, and silicon. The second silicide layer 92 is formed of a compound containing titanium and silicon (TiSi). X ) is formed. Here, "TiSi" X The "X" in the figure is, for example, 2. The titanium oxide layer 21 is formed by the reaction of oxygen and other substances contained in the oxide film 20 with the titanium constituting the second metal layer 62. The titanium oxide layer 21 may have a composition of "TiO2". X "TiO" represents the composition formula. X The "X" in the text is, for example, 2. Furthermore, in "(d) Heating Step", sometimes... Figure 2 In the region (d) where the titanium oxide layer 21 is formed, a mixed layer of titanium oxide layer 21 and second silicide layer 92 is formed.

[0070] <Effect 1>

[0071] In the second embodiment, the high-melting-point metal produces the same effect as tantalum described above as effect 1 in the first embodiment. That is, according to the second embodiment, the contact resistance between the impurity addition region 3 and the first silicide layer 91 can be reduced.

[0072] <Effect 2>

[0073] Furthermore, in the second embodiment, as effect 2 of the second embodiment, the first silicide layer 91 containing the high-melting-point metal provides the same effect as the first silicide layer 91 described above. That is, in the second embodiment, the increase in contact resistance is also suppressed by utilizing the first silicide layer 91. In addition, by utilizing the first silicide layer 91, a contact with strong resistance to thermal coagulation and high heat resistance can be obtained.

[0074] <Effect 3>

[0075] In the above-described "(d) heating step", the oxygen contained in the oxide film 20 combines with the titanium contained in the second metal layer 62 to form a titanium oxide layer 21. As a result, the oxide film 20, which may hinder the uniform silanization reaction between the impurity addition region 3 and the first metal layer 61, is removed. Therefore, the non-uniformity of the silanization reaction between the impurity addition region 3 and the first metal layer 61 is reduced.

[0076] [Comparative Example]

[0077] Here, we will explain the comparative examples. Figure 3 of (a), Figure 3 (b) and Figure 3 Figure (c) illustrates a method for manufacturing the electrode portion of the semiconductor device of the comparative example. This method includes (a) a substrate preparation step, (b) a second metal layer formation step, and (c) a heating step. The substrate preparation step, (b) the second metal layer formation step, and (c) the heating step are performed sequentially. These steps will be described below.

[0078] (a) Substrate preparation steps

[0079] like Figure 3 As shown in (a), the “(a) substrate preparation step” of the comparative example is the same as the “(a) substrate preparation step” of the second embodiment.

[0080] (b) Steps for forming the second metal layer

[0081] The manufacturing method of the comparative example does not include the first metal layer formation step of the second embodiment. In the manufacturing method of the comparative example, as... Figure 3 As shown in (b), a second metal layer 62 is formed on the impurity addition region 3, separated from the oxide film 20. In the second metal layer formation step, as... Figure 3 As shown in (b), a second metal layer 62 is formed directly above the oxide film 20. The second metal layer 62 is formed by a method such as sputtering. The second metal layer 62 is a titanium layer containing titanium.

[0082] (c) Heating step

[0083] In the comparative example's heating step (annealing step for silanization reaction), the semiconductor substrate including the oxide film 20 and the second metal layer 62 is heated (annealed). The comparative example's "(c) heating step" is the same as the second embodiment's "(d) heating step," and its various conditions are also the same as the corresponding conditions in the second embodiment's "(d) heating step." Through this annealing, as... Figure 3 As shown in (c), a second silicide layer 92 is formed on the impurity addition region 3. Through this annealing, a titanium oxide layer 21 (TiO2) is formed on the second silicide layer 92. X Additionally, sometimes a titanium boride layer 31 (TiB2) is formed between the second silicide layer 92 and the impurity addition region 3.

[0084] <Inspection>

[0085] The following is for reference Figure 4 of (a), Figure 4 (b) Figure 4 (c) and Figure 4 (d) examines the first embodiment, the second embodiment, and the comparative example. Figure 4 of (a), Figure 4 (b) Figure 4 (c) and Figure 4 (d) represents the depth D (nm) from the substrate surface in the comparative example and the impurity concentration Ci (cm). -3 A diagram showing the relationship between ).

[0086] Figure 4 (a) represents the impurity concentration distribution after the completion of the "(a) substrate preparation step" in the comparative example above (i.e., the initial impurity concentration distribution). This initial impurity concentration distribution is... Figure 4 (b) Figure 4 (d) is also represented by a dashed line. Figure 4 (b) represents the estimated impurity concentration distribution (solid line) after the completion of the heating step ((c)) in the comparative example above. Figure 4 In (b), the first region A represents the region of the second silicide layer 92 (TiSi2). Figure 4 In (b), the second region B represents the region of the titanium boride layer 31 (TiB2). Figure 4 In (b), the third region C represents the impurity addition region 3 after silicide formation.

[0087] like Figure 4 As shown in (b), in the comparative example, the titanium boride layer 31 (TiB2) contains a high concentration of boron (impurity). Additionally, in the comparative example, as... Figure 4 As shown in (b), the impurity concentration Ci (cm³) near the boundary between the second region B and the third region C.-3 The impurity concentration decreased from the initial state.

[0088] Here, on Figure 4 The appropriateness of the inference of the impurity concentration distribution of the comparative example shown in (b) will be explained. The impurity concentration was measured, for example, using SIMS (secondary ion mass spectroscopy). Figure 4 (c) represents the impurity concentration distribution (solid line) measured by SIMS on the substrate after the heating step ((c)) of the comparative example. When analyzing from the region with higher impurity concentration near the substrate surface (high concentration region) towards the region with lower impurity concentration inside the substrate (low concentration region) using SIMS, impurity atoms contained in the high concentration region move to the low concentration region due to knock-on. Therefore, in SIMS, it is not possible to accurately measure the impurity concentration in the low concentration region generated near the boundary between the titanium boride layer 31 (second region B) and the impurity addition region 3 (third region C). However, the impurity concentration measured by SIMS from the substrate surface to the titanium boride layer 31 (second region B) is generally accurate.

[0089] Figure 4 (d) represents the impurity concentration distribution (solid line) measured by SIMS after removing the second silicide layer 92 (TiSi2) and titanium boride layer 31 (TiB2) from the substrate following the heating step ((c)) of the comparative example. The TiSi2 layer can be removed, for example, using diluted hydrofluoric acid (HF). The TiB2 layer can be removed, for example, using diluted H2O2. Since... Figure 4 The impurity concentration in (d) was measured using the SIMS method after removing the high-concentration region, thus accurately reflecting the impurity concentration in impurity addition region 3 (third region C). When comprehensively judging the above... Figure 4 The measurement results of (c) and Figure 4 When the measurement result of (d) is obtained, it can be determined that Figure 4 The estimation of the impurity concentration distribution in (b) is appropriate.

[0090] like Figure 4 As shown in (b), in the comparative example, the titanium boride layer 31 (TiB2) contains a high concentration of boron (impurity). However, the boron contained in the titanium boride layer 31 (TiB2) does not contribute to the improvement of conductivity or the reduction of contact resistance.

[0091] Additionally, in comparative examples, such as Figure 4 As shown in (b), the impurity concentration Ci (cm³) near the boundary between the second region B and the third region C. -3The impurity concentration decreased from the initial state. This is believed to be because the impurities (boron) near the boundary between the titanium boride layer 31 (second region B) and the impurity addition region 3 (third region C) were absorbed by the titanium boride layer 31 during its formation. Furthermore, in the comparative example, the impurity concentration Ci (cm³) near this boundary was... -3 Less than 1×10 20 cm -3 .

[0092] On the other hand, in the first and second embodiments described above, the impurity concentration in the impurity addition region 3 at the interface between the silicide layer 9 and the impurity addition region 3 is relatively high, at 1×10⁻⁶. 20 cm -3 Therefore, by following the first and second embodiments, contact resistance can be reduced.

[0093] [First Manufacturing Method for Semiconductor Devices]

[0094] The following is for reference Figure 5 of (a), Figure 5 (b) Figure 5 (c) Figure 5 (d) Figure 5 of (e) Figure 5 (f) and Figure 5 (g) will describe a first manufacturing method for a semiconductor device having an electrode portion according to an exemplary embodiment. Figure 5 of (a), Figure 5 (b) Figure 5 (c) Figure 5 (d) Figure 5 of (e) Figure 5 (f) and Figure 5 Figure (g) is a diagram illustrating a first manufacturing method for a semiconductor device having electrode portions according to an exemplary embodiment. This manufacturing method (the first manufacturing method) includes (a) an impurity addition region formation step, (b) an insulating film formation step, (c) a contact hole formation step, (d) a metal layer formation step, (e) a barrier metal formation step, (f) a heating step, and (g) a polishing step. The steps (a) impurity addition region formation step, (b) insulating film formation step, (c) contact hole formation step, (d) metal layer formation step, (e) barrier metal formation step, (f) heating step, and (g) polishing step are performed sequentially. These steps will be described below.

[0095] (a) Impurity Addition Region Formation Step

[0096] In the impurity addition region formation step, such as Figure 5As shown in (a), a component separation portion 2 is formed on the surface side of the semiconductor substrate 1. The semiconductor substrate 1 is formed of silicon. The component separation portion 2 is formed of silicon dioxide or the like. Next, using ion implantation, impurities are added to a region on the surface side of the semiconductor substrate 1 to form an impurity addition region 3. The impurity addition region 3 has a conductivity type opposite to that of the semiconductor substrate 1. The method for forming this impurity addition region 3 is the same as the method for forming the impurity addition region 3 in the "(a) substrate preparation step" of the first or second embodiment described above.

[0097] (b) Insulating film formation step

[0098] In the insulating film formation step, such as Figure 5 As shown in (b), an insulating film 4 (PMD: pre-metal dielectric) is formed on the impurity addition region 3. The insulating film 4 is formed of silicon dioxide or the like. The insulating film 4 can be formed using chemical vapor deposition (CVD).

[0099] (c) Contact hole formation step

[0100] In the contact hole forming step, such as Figure 5 As shown in (c), a contact hole 5 is formed. The contact hole 5 penetrates the insulating film 4. The contact hole 5 can be formed using photolithography and reactive ion etching (RIE).

[0101] (d) Metal layer formation steps

[0102] In the metal layer formation step, such as Figure 5 As shown in (d), the metal layer 6 is deposited on the surface of the insulating film 4, the inner surface of the contact hole 5, and the exposed surface of the impurity addition region 3. Furthermore, sometimes a natural oxide film with a thickness of several nm is formed on the exposed surface of the impurity addition region 3 before the metal layer 6 is deposited. The natural oxide film is made of the same material as the insulating film 4, namely silicon dioxide. This natural oxide film can also be etched using dilute hydrofluoric acid or the like before the metal layer 6 is deposited. The concentration of the dilute hydrofluoric acid is set low enough so that the thickness of the insulating film 4 does not become too thin. Alternatively, the etching time using dilute hydrofluoric acid is set short so that the thickness of the insulating film 4 does not become too thin. This metal layer formation step is the same as "(b) First metal layer formation step" and "(c) Second metal layer formation step" in the first or second embodiment described above.

[0103] (e) Barrier metal formation steps

[0104] In the barrier metal formation step, such as Figure 5As shown in (e), a barrier metal layer 7 is deposited on metal layer 6. A metal layer 8 is deposited on the barrier metal layer 7. The barrier metal layer 7 is formed of titanium nitride (TiN) or the like. The metal layer 8 is formed of a low-resistivity metal such as tungsten. The deposition methods for the barrier metal layer 7 and the metal layer 8 are CVD, atomic layer deposition (ALD), or physical vapor deposition (PVD), etc. The metal layer 8 can be formed in a manner that completely fills the contact hole 5. The barrier metal layer 7 prevents the metal layer 8 from reacting with the metal layer 6 and with the semiconductor substrate 1. When the metal layer 8 is deposited using CVD or ALD, the barrier metal layer 7 prevents impurities contained in the metal layer 8 from diffusing into the metal layer 6 or the semiconductor substrate 1.

[0105] (f) Heating step

[0106] In the heating step (annealing step for siliconization reaction), the semiconductor substrate 1 on which the above layers are formed (refer to...) Figure 5 (e) is heated (annealed). Through this annealing, the metal layer 6 reacts with the impurity addition region 3. Through this reaction, as Figure 5 As shown in (f), a silicide layer 9 is formed on the substrate surface. This heating step can be performed in a nitrogen (N2) atmosphere. This heating step can be a standalone step or it can also be used to heat the barrier metal layer 7 and the metal layer 8, etc. This heating step is the same as the "(d) heating step" in the first or second embodiment described above.

[0107] (g) Grinding step

[0108] In the grinding step, chemical mechanical polishing (CMP) and other methods are used to remove the metal layer 6, barrier metal layer 7, and metal layer 8 formed outside the contact hole 5. For example... Figure 5 As shown in (g), CMP is performed until the insulating film 4 is exposed. This forms the contact plug 10 (electrode portion). The contact plug 10 is processed into a plug shape and includes a silicide layer 9, a metal layer 6, a barrier metal layer 7, and a metal layer 8. Furthermore, the impurity addition region 3 is electrically connected to the contact plug 10.

[0109] In the first method for manufacturing a semiconductor device, the silicide layer 9 is formed in the same manner as in the manufacturing methods of the first or second embodiment described above. Therefore, using the first method for manufacturing a semiconductor device, the high resistivity of the impurity addition region 3 is suppressed. Thus, using the first method for manufacturing a semiconductor device, the contact resistance between the impurity addition region 3 and the silicide layer 9 can be reduced.

[0110] [Second Manufacturing Method for Semiconductor Devices]

[0111] The following is for reference Figure 6 of (a), Figure 6 (b) Figure 6 (c) and Figure 6 (d) will describe a second manufacturing method for a semiconductor device having an electrode portion according to an exemplary embodiment. Figure 6 of (a), Figure 6 (b) Figure 6 (c) and Figure 6 Figure (d) illustrates a second manufacturing method for a semiconductor device having electrode portions according to an exemplary embodiment. This example is an embodiment using the SALICIDE (Self-Aligned Silicide) method. This manufacturing method (the second manufacturing method) includes (a) an impurity addition region formation step, (b) a metal layer formation step, (c) a heating step, and (d) an unreacted metal removal step. The impurity addition region formation step, (b) the metal layer formation step, (c) the heating step, and (d) the unreacted metal removal step are performed sequentially. These steps will be described below.

[0112] (a) Impurity Addition Region Formation Step

[0113] In the impurity addition region formation step, such as Figure 6 As shown in (a), a component separation portion 2 is formed on the surface side of the semiconductor substrate 1. The semiconductor substrate 1 is formed of silicon. The component separation portion 2 is formed of silicon dioxide or the like. Next, impurities are added to the region on the surface side of the semiconductor substrate 1 to form an impurity addition region 3. The method for forming the impurity addition region 3 is the same as the method for forming the impurity addition region 3 in the "(a) substrate preparation step" of the first or second embodiment described above.

[0114] (b) Metal layer formation steps

[0115] In the metal layer formation step, such as Figure 6 As shown in (b), metal layer 6 is formed on impurity addition region 3. This metal layer formation step is the same as "(b) first metal layer formation step" and "(c) second metal layer formation step" in the first or second embodiment described above.

[0116] (c) Heating step

[0117] In the heating step (annealing step for silanization reaction), the semiconductor substrate 1 on which the metal layer 6 is formed is heated (annealed). Through this annealing, the metal layer 6 reacts with the impurity addition region 3. Through this reaction, such as Figure 6As shown in (c), a silicide layer 9 is formed on the surface side of the semiconductor substrate 1. On the element separation section 2, the metal layer 6 remains in an unreacted state. This heating step is the same as the heating step (d) in the first or second embodiment described above.

[0118] (d) Unreacted metal removal steps

[0119] In the unreacted metal removal step, such as Figure 6 As shown in (d), the unreacted metal layer 6 is selectively removed by cleaning with a chemical solution. The silicide layer 9 obtained by this second manufacturing method is electrically connected to the impurity addition region 3 and functions as an electrode.

[0120] In the second manufacturing method, the silicide layer 9 is formed by the manufacturing method of the first or second embodiment described above. Therefore, by using the second manufacturing method, the high resistivity of the impurity addition region 3 is suppressed. Thus, by using the second manufacturing method, the contact resistance between the impurity addition region 3 and the silicide layer 9 can be reduced.

[0121] [Third Manufacturing Method for Semiconductor Devices]

[0122] The following is for reference Figure 7 (a) and Figure 7 (b) describes a third manufacturing method for semiconductor devices. Figure 7 (a) and Figure 7 Figure (b) is a diagram illustrating a third manufacturing method for a semiconductor device having electrode portions according to an exemplary embodiment. This manufacturing method (the third manufacturing method) includes (a) an element forming step and (b) a polishing step. The (a) element forming step and (b) polishing step are performed sequentially. These steps will be described below.

[0123] (a) Component formation steps

[0124] In the component forming step, forming Figure 7 The component structure shown in (a) is as follows. That is, in the component forming step, the component separation part 103 and p are separated. - Trap 101, n - Trap 102, n + The first impurity addition region 3a, p + A second impurity addition region 3b is formed within the semiconductor substrate 1. Next, a gate insulating film 104, a gate electrode 105, and a gate sidewall 106 are formed on the semiconductor substrate 1. These formation methods can also be generally known methods. Figure 7 In the component structure shown in (a), p -The pair of first impurity addition regions 3a (n-type) within the well 101 constitute the source and drain regions of the field-effect transistor, respectively. - A pair of second impurity addition regions 3b (p-type) within the well 102 constitute the source and drain regions in the field-effect transistor, respectively.

[0125] The impurity in the n-type first impurity addition region 3a is a common n-type impurity such as As. The first impurity addition region 3a can be formed by using an n-type impurity in the "(a) substrate preparation step" of the first or second embodiment described above. The impurity in the p-type second impurity addition region 3b is boron or the like. The second impurity addition region 3b is formed using the "(a) substrate preparation step" of the first or second embodiment described above.

[0126] Next, an insulating film 107 is deposited on the semiconductor substrate 1. Then, the upper surface of the insulating film 107 is planarized by CMP or the like. Then, contact holes 5 are formed in the insulating film 107 using photolithography and RIE or the like. The contact holes 5 penetrate the insulating film 107. Then, a metal layer 6 is formed on the exposed surfaces of the first impurity addition region 3a and the second impurity addition region 3b. The steps for forming this metal layer 6 are the same as "(b) the first metal layer formation step" and "(c) the second metal layer formation step" in the first or second embodiment described above.

[0127] Next, barrier metal layer 7 is deposited on metal layer 6. Metal layer 8 is then deposited on barrier metal layer 7. Metal layer 8 is formed of a low-resistivity metal such as tungsten.

[0128] Then, a heating step (annealing step for silicide reaction) is performed. This heating step is the same as "(d) heating step" in the first or second embodiment described above. In this heating step, the semiconductor substrate 1 on which the above-described element structure is formed is heated (annealed). Through this annealing, the metal layer 6 reacts with the first impurity addition region 3a, forming a silicide layer 9a at the bottom of the contact hole 5. The silicide layer 9a comprises the two silicide layers shown in the first or second embodiment. In addition, through this annealing, the metal layer 6 reacts with the second impurity addition region 3b, forming a silicide layer 9b at the bottom of the contact hole 5. The silicide layer 9b comprises the two silicide layers (first silicide layer 91 and second silicide layer 92) shown in the first or second embodiment. The silicide layer 9a is in contact with the first impurity addition region 3a, and the silicide layer 9b is in contact with the second impurity addition region 3b.

[0129] (b) Grinding steps

[0130] In the polishing step, CMP (chemical mechanical polishing) and other methods are used to remove the metal layer 6, barrier metal layer 7, and metal layer 8 formed outside the contact hole 5. For example... Figure 7 As shown in (b), CMP is performed until the insulating film 107 is exposed. As a result, a contact plug (electrode portion) comprising a silicide layer 9a, a metal layer 6, a barrier metal layer 7, and a metal layer 8 is formed on the side of the first impurity addition region 3a. Additionally, a contact plug (electrode portion) comprising a silicide layer 9b, a metal layer 6, a barrier metal layer 7, and a metal layer 8 is formed on the side of the second impurity addition region 3b.

[0131] The silicide layers 9a and 9b are formed by the manufacturing method of the first or second embodiment described above, thus suppressing the high resistivity of the first impurity addition region 3a and the second impurity addition region 3b. Therefore, the contact resistance between the first impurity addition region 3a and the silicide layer 9a can be reduced. Furthermore, the contact resistance between the second impurity addition region 3b and the silicide layer 9b can be reduced.

[0132] The above description illustrates various exemplary embodiments, but the invention is not limited to these exemplary embodiments. Various additions, omissions, substitutions, and modifications are possible. Furthermore, elements from different embodiments can be combined to form other embodiments. Additionally, various embodiments of the present invention have been described in this specification for illustrative purposes, and it should be understood that various modifications can be made without departing from the scope and spirit of the invention. Therefore, the various embodiments disclosed in this specification are not intended to be limiting; the true scope and spirit are given by the appended claims.

[0133] Explanation of reference numerals in the attached figures

[0134] 1… Semiconductor substrate, 2… Component separation section, 3… Impurity addition region, 3a… First impurity addition region, 3b… Second impurity addition region, 4… Insulating film, 5… Contact hole, 6… Metal layer, 7… Barrier metal layer, 8… Metal layer, 9… Silice layer, 9a… Silice layer, 9b… Silice layer, 10… Contact plug, 20… Oxide film, 21… Titanium oxide layer, 31… Titanium boride layer, 61… First metal layer, 62… Second metal layer, 91… First silicide layer, 92… Second silicide layer.

Claims

1. A method for manufacturing an electrode portion of a semiconductor device, characterized in that, include: Steps for preparing a semiconductor substrate with impurity addition regions; The step of forming a first metal layer on the impurity addition region; The step of forming a second metal layer on the first metal layer; as well as The step of heating the semiconductor substrate including the first metal layer and the second metal layer. The impurity addition region contains silicon. The first metal layer contains tantalum. The second metal layer contains titanium. The heating step described above. A first silicide layer containing titanium, tantalum, and silicon is formed on the impurity addition region, and a second silicide layer containing titanium and silicon is formed on the first silicide layer. The impurity concentration at the interface between the first silicide layer and the impurity addition region is 1×10⁻⁶. 20 cm -3 above, The impurity in the impurity addition region is boron.

2. A method for manufacturing an electrode portion of a semiconductor device, characterized in that, include: The step of preparing a semiconductor substrate having an impurity addition region and an oxide film formed on the impurity addition region; The step of forming a first metal layer over the oxide film in the impurity addition region; The step of forming a second metal layer on the first metal layer; and The step of heating the semiconductor substrate including the first metal layer and the second metal layer. The impurity addition region contains silicon. The oxide film contains silicon dioxide. The first metal layer contains a high-melting-point metal, wherein the high-melting-point metal contains at least one selected from tantalum, tungsten, and molybdenum. The second metal layer contains titanium. Through the heating step, a first silicide layer containing titanium, the high-melting-point metal, and silicon is formed on the semiconductor substrate; a second silicide layer containing titanium and silicon is formed on the first silicide layer; and a titanium oxide layer is formed on the second silicide layer. The impurity concentration at the interface between the first silicide layer and the impurity addition region is 1×10⁻⁶. 20 cm -3 above, The impurity in the impurity addition region is boron.

3. A semiconductor device, characterized in that, include: Impurity addition area; A first silicide layer containing titanium, tantalum, and silicon is located on the impurity addition region; as well as A second silicide layer, located on the first silicide layer and containing titanium and silicon, The impurity concentration at the interface between the first silicide layer and the impurity addition region is 1×10⁻⁶. 20 cm -3 above, The impurity in the impurity addition region is boron.

4. A semiconductor device comprising: Impurity addition area; A first silicide layer located on the impurity addition region and containing titanium, a high-melting-point metal, and silicon; A second silicide layer located on the first silicide layer and containing titanium and silicon; as well as The titanium oxide layer located on the second silicide layer, The high-melting-point metal contains at least one selected from tantalum, tungsten, and molybdenum. The impurity concentration at the interface between the first silicide layer and the impurity addition region is 1×10⁻⁶. 20 cm -3 above, The impurity in the impurity addition region is boron.

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