MEMS piezoelectric vector hydrophone chip with double mass cantilever beam structure and preparation method thereof

Abstract

The application relates to a MEMS piezoelectric vector hydrophone chip of a double-mass cantilever structure and a preparation method thereof. The vector hydrophone chip comprises an upper mass, a lower mass, a cantilever and a 'back' shaped base support structure. One end of the cantilever is connected with the inner wall of the 'back' shaped base support structure to fix the cantilever. The other end of the cantilever is suspended. The upper mass and the lower mass are symmetrically distributed on the upper and lower sides of the suspended end of the cantilever. A piezoelectric sensing unit is located above the cantilever structure, can sense the stress change of the cantilever and convert the stress change into an electric signal to realize acceleration electric measurement. The MEMS piezoelectric vector hydrophone provided by the application increases the upper mass above the cantilever to form a symmetric double-mass structure, can obviously improve the sensitivity and directivity of the vector hydrophone, has a relatively simple preparation process, does not need a small air gap, has the advantages of a passive device, stable work, low noise and the like.

Description

Technical Field

[0001] This invention relates to the field of sensing technology, and in particular to a MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure and its fabrication method. Background Technology

[0002] Compared to scalar hydrophones, vector hydrophones can measure vector information of underwater sound fields, such as particle displacement, velocity, and acceleration, which is beneficial for the identification of long-distance, multi-target underwater. MEMS vector hydrophones enable miniaturization, low power consumption, and low cost, and are easier to array, representing an important direction for the future development of vector hydrophones. Vector hydrophones possess a natural figure-eight (also known as cosine or dipole) directivity, which can suppress isotropic noise in the environment and enable sound source localization. Therefore, directivity is a key indicator that distinguishes vector hydrophones from scalar hydrophones.

[0003] In existing technologies, vector hydrophones commonly use a cantilever beam structure with a single mass block. However, its figure-eight directional characteristic exhibits significant skewness, which no longer meets current requirements for hydrophone directivity. Research has revealed that this is primarily due to the asymmetry of the sensitive structure. Therefore, designing a MEMS piezoelectric vector hydrophone chip with good directivity and high sensitivity is an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure and a simple fabrication process, good directivity, high sensitivity, low noise, stable operation, and no need for a small air gap, along with its fabrication method. This invention proposes a symmetrical dual-mass cantilever beam structure, which significantly improves the hydrophone's directivity. Furthermore, the addition of the upper mass block also significantly enhances the device's sensitivity. However, the fabrication and installation of the upper mass block require high precision; deviations in size or position can severely reduce the hydrophone's directivity and sensitivity. This invention utilizes MEMS technology to fabricate the piezoelectric vector hydrophone chip with the upper mass block and dual-mass cantilever beam structure, and provides a detailed fabrication method that is simple and easy to implement.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution.

[0006] This invention proposes a MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure. The chip includes: an upper mass block, a lower mass block, a cantilever beam, and a U-shaped substrate support structure; wherein,

[0007] One end of the cantilever beam is connected to the inner wall of one side of the "U"-shaped base support structure to fix the cantilever beam; the other end of the cantilever beam is suspended.

[0008] The upper and lower mass blocks are symmetrically distributed on the upper and lower sides of the cantilever beam's suspended end;

[0009] The other three inner walls of the "U"-shaped base support structure, together with the upper mass block, the lower mass block, and the cantilever beam, form a U-shaped slit.

[0010] As an improvement to the above technical solution, the upper mass block and the lower mass block are etched, pasted or bonded to the same positions on the upper and lower sides of the cantilever beam; the upper mass block and the lower mass block have the same mass.

[0011] As an improvement to the above technical solution, the cantilever beam comprises, from bottom to top, a composite layer and a piezoelectric sensing unit stacked sequentially; wherein, the piezoelectric sensing unit comprises, from bottom to top, a bottom electrode, a piezoelectric layer and a top electrode stacked sequentially.

[0012] As an improvement to the above technical solution, the bottom electrode and the top electrode are aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals.

[0013] The piezoelectric layer is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film formed by at least one of these piezoelectric films and a doping element, or a composite film formed by at least two of these piezoelectric films, or a piezoelectric film or composite film with an isolation layer on its surface; the isolation layer is a silicon nitride layer, a silicon dioxide layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite film formed by at least two of these.

[0014] The doping element is vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt, or niobium, but in practical applications it is not limited to these listed elements.

[0015] As one of the improvements to the above technical solution, the "U"-shaped substrate support structure includes, from bottom to top, a silicon substrate layer and a composite layer stacked sequentially.

[0016] As an improvement to the above technical solution, the composite layer comprises, from bottom to top, a silicon layer and an insulating layer stacked sequentially.

[0017] As an improvement to the above technical solution, the material of the insulating layer is a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite layer formed from at least two of these.

[0018] This invention also proposes a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure, the method comprising the following steps:

[0019] Step 1. Prepare the substrate;

[0020] Step 2. Prepare an insulating layer on the upper surface of the silicon wafer layer and prepare a bulk silicon etching mask layer on the lower surface of the substrate.

[0021] Step 3. Deposit a bottom electrode film on the upper surface of the insulating layer and pattern it to form the bottom electrode;

[0022] Step 4. Deposit a piezoelectric layer film on the upper surface of the bottom electrode and pattern it to form a piezoelectric layer;

[0023] Step 5. Deposit a top electrode film on the upper surface of the piezoelectric layer and pattern it to form the top electrode;

[0024] Step 6. Prepare a mask for etching U-shaped slits on the front side of the substrate, and pattern the mask to expose the pattern of the U-shaped slits to be etched. Perform wet etching or dry etching on the insulating layer and silicon wafer layer respectively to form U-shaped slits.

[0025] Step 7. Pattern the bulk silicon etching mask layer to obtain the patterns required for the first and second etching cavities;

[0026] Step 8. Perform wet etching or dry etching on the bottom of the substrate to form a first etching cavity and a second etching cavity, and release the cantilever beam and the lower mass block; the first etching cavity is directly opposite the piezoelectric sensing unit, and the lower mass block is formed between the first etching cavity and the second etching cavity; the piezoelectric sensing unit is formed by a bottom electrode, a piezoelectric layer and a top electrode;

[0027] Step 9. Prepare the upper mass block and determine its installation position: Bond or paste the upper mass block to the corresponding position on the upper surface of the cantilever beam, and make the position of the upper mass block symmetrical with that of the lower mass block, and ensure that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam, so as to obtain the MEMS piezoelectric vector hydrophone chip with a double mass block cantilever beam structure.

[0028] The lower mass block is obtained by etching, pasting, or bonding.

[0029] As an improvement to the above technical solution, step 1 uses an SOI substrate or a silicon substrate as the substrate; the SOI substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer, an SOI buried oxide layer, and a base silicon layer; the silicon substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer and a base silicon layer.

[0030] The bulk silicon etching mask layer in step 2 is a hard mask composed of a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, metallic aluminum, gold, or a composite film formed of at least two of these materials, or a photoresist layer, or a composite mask layer composed of a hard mask and a photoresist layer.

[0031] When an SOI substrate is used as the substrate, in step 8, the base silicon layer and SOI buried oxide layer of the SOI substrate are subjected to wet etching or dry etching from the outside to the inside.

[0032] When a silicon substrate is used as the substrate, in step 8, the base silicon layer of the silicon substrate is subjected to wet etching or dry etching.

[0033] As an improvement to the above technical solution, in order to ensure that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam, step 9 specifically includes:

[0034] The MEMS piezoelectric vector hydrophone chip with a dual-mass block cantilever beam structure was modeled using simulation software. Based on the size and position of the lower mass block, the size and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks and the center of gravity of the cantilever beam are on the same horizontal plane.

[0035] Fabrication of the upper mass block: A mask is designed based on the optimized size of the upper mass block; a double-sided polished ordinary silicon substrate is used as the substrate, a support layer is deposited, and a thicker photoresist is coated on the surface of the support layer; the other side of the silicon substrate is patterned using a mask, and the bulk silicon is subjected to wet etching or dry etching; the photoresist and support layer are removed to obtain the upper mass block;

[0036] The upper mass block is bonded or pasted onto the optimized position on the cantilever beam, so that the position of the upper mass block is symmetrical with that of the lower mass block and the positions are directly opposite each other, ensuring that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam.

[0037] The supporting layer is made of aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride, or a composite film formed from at least two of these materials. The advantages of this invention compared to existing technologies are:

[0038] 1. Compared with the cantilever beam structure of a single mass block, the double mass block structure formed by stacking the upper and lower parts of the present invention can effectively improve the directivity and sensitivity of the hydrophone, suppress isotropic interference, and better achieve target positioning.

[0039] 2. The manufacturing process of this invention is relatively simple, the upper mass block is accurately prepared and installed, and the hydrophone chip does not require a small air gap. It also has the advantages of being passive, stable in operation and low in noise. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a MEMS piezoelectric vector hydrophone provided in an embodiment of the present invention;

[0041] Figure 2A top view of the piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a dual-mass block cantilever beam structure provided in an embodiment of the present invention;

[0042] Figure 3 A three-dimensional schematic diagram of the piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a dual-mass block cantilever beam structure provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic cross-sectional view of the SOI substrate for a piezoelectric sensing chip.

[0044] Figure 5 This is a schematic diagram of the cross-section of the chip behind the silicon dioxide layers on both sides of the SOI substrate.

[0045] Figure 6 This is a schematic cross-sectional view of the chip after the bottom electrode, piezoelectric layer, and top electrode have been deposited on the front side.

[0046] Figure 7 This is a schematic diagram of the chip cross-section after etching the U-shaped slit.

[0047] Figure 8 This is a schematic diagram of the chip cross-section after the back-side body etching mask is patterned.

[0048] Figure 9 A schematic diagram of the chip cross-section after bulk silicon etching (taking dry bulk etching as an example);

[0049] Figure 10 A schematic diagram of the chip cross-section after SOI buried oxide layer etching (taking dry bulk etching as an example);

[0050] Figure 11 This is a cross-sectional view of the piezoelectric sensor chip on an SOI silicon substrate after the mass block has been attached to the front side.

[0051] Figure 12 This is a schematic diagram of the structure of the piezoelectric sensor chip on a silicon substrate after fabrication.

[0052] Attached Figure Labels

[0053] a. Piezoelectric sensor chip b. PCB circuit board c. Package housing

[0054] 1a, upper mass block; 2a, lower mass block; 3a, cantilever beam

[0055] 4a. "U"-shaped base support structure; 5a. U-shaped slit

[0056] 1. Silicon layer 2. SOI buried oxide layer 3. Silicon substrate layer

[0057] 4. Insulating layer; 5. Bulk etching mask layer; 6. Bottom electrode

[0058] 7. Piezoelectric layer; 8. Top electrode; 9. Photoresist layer

[0059] 10. First etching cavity; 11. Second etching cavity Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] The present invention discloses a MEMS piezoelectric vector hydrophone with a dual-mass block cantilever beam structure, comprising: a plurality of piezoelectric sensing chips a, a plurality of corresponding PCB circuit boards b with impedance matching and amplification, and a package shell c; wherein each piezoelectric sensing chip a is pasted and fixed on a PCB circuit board b, and is placed perpendicular to each other along the X-axis, Y-axis and Z-axis of the package shell c, and is internally sealed.

[0062] Each piezoelectric sensing chip a includes: an upper mass block 1a, a lower mass block 2a, a cantilever beam 3a, and a U-shaped base support structure 4a; one end of the cantilever beam 3a is connected to the inner wall of the U-shaped base support structure 4a, serving to fix the cantilever beam 3a; the other end of the cantilever beam 3a is suspended; the upper mass block 1a and the lower mass block 2a are symmetrically distributed on the upper and lower sides of the suspended end of the cantilever beam 3a; the other three inner walls of the U-shaped base support structure 4a, together with the upper mass block 1a, the lower mass block 2a, and the cantilever beam 3a, form a U-shaped slit 5a; the encapsulation shell c is a metal shell such as aluminum, which can effectively shield electromagnetic interference.

[0063] The cantilever beam 3a includes an upper mass block 1a and a lower mass block 2a, which can effectively improve the directivity of the vector hydrophone.

[0064] The hydrophone operates in a frequency range below 10kHz.

[0065] On the front side of the substrate, inductively coupled plasma (ICP) etching is used to etch the composite layer at the other three ends of the cantilever beam 3a (the non-fixed end), forming a U-shaped slit 5a, which lays the foundation for the release of the cantilever beam 3a; the width of the U-shaped slit 5a is 0.01μm to 2000μm; the size of the U-shaped slit 5a determines the length and width of the cantilever beam 3a structure;

[0066] Preferably, when there is an acceleration input, the inertial force causes the "U"-shaped base support structure and the upper and lower dual mass blocks to move relative to each other, resulting in deformation of the cantilever beam. Due to the piezoelectric effect of the piezoelectric material, the piezoelectric units on the cantilever beam generate charges, thereby enabling the electrical measurement of acceleration.

[0067] Preferably, the substrate thickness can be 10–5000 μm; the SOI buried oxide layer thickness is 0.01–100 μm;

[0068] Preferably, the insulating layer 4 may be a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite layer formed from at least two of these; the thickness of the insulating layer is 0.01 to 100 μm.

[0069] Preferably, the bottom electrode and the top electrode can be aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals; the electrode thickness is 1 nm to 100 μm.

[0070] Preferably, the piezoelectric layer may be a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film formed by at least one of these piezoelectric films and a doping element, or a composite film formed by at least two of these piezoelectric films, or a piezoelectric film or composite film with an isolation layer disposed on its surface; the isolation layer may be a silicon nitride layer, a silicon dioxide layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite film formed by at least two of these; the thickness of the piezoelectric layer is 0.01–600 μm;

[0071] Preferably, the doping element is vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt, or niobium;

[0072] Preferably, the bulk etching mask may be a hard mask composed of a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, metallic aluminum, gold, or a composite layer formed of at least two of these, or a photoresist layer, or a composite mask layer composed of a hard mask and a photoresist layer; the thickness of the hard mask is 0.01 μm to 100 μm; the thickness of the photoresist is 0.01 μm to 100 μm.

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] To facilitate understanding of the embodiments of the present invention, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments.

[0075] Figure 1 This is a schematic diagram of the structure of a MEMS piezoelectric vector hydrophone provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the piezoelectric vector hydrophone includes: several piezoelectric sensing chips a, several corresponding impedance matching and amplification circuit boards b, and a package shell c; wherein, each piezoelectric sensing chip a is pasted and soldered on a PCB circuit board b, and is placed perpendicular to each other along the X-axis, Y-axis and Z-axis of the package shell c, and is internally encapsulated.

[0076] Figure 2 A top view of the piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a dual-mass block cantilever beam structure provided in an embodiment of the present invention; Figure 3 This is a three-dimensional schematic diagram of the piezoelectric sensing chip of the MEMS piezoelectric vector hydrophone with a dual-mass cantilever beam structure provided in an embodiment of the present invention; as shown. Figure 3 As shown, each piezoelectric sensing chip includes: an upper mass block 1a, a lower mass block 2a, a cantilever beam 3a, and a U-shaped substrate support structure 4a; one end of the cantilever beam 3a is connected to the inner wall of the U-shaped substrate support structure 4a, serving to fix the cantilever beam 3a; the other end of the cantilever beam 3a is suspended; the upper mass block 1a and the lower mass block 2a are symmetrically distributed on the upper and lower sides of the suspended end of the cantilever beam 3a; the other three inner walls of the U-shaped substrate support structure 4a, together with the upper mass block 1a, the lower mass block 2a, and the cantilever beam 3a, form a U-shaped slit 5a; the cantilever beam 3a includes a composite layer and a piezoelectric layer, wherein the composite layer includes a silicon layer 1 and an insulating layer 4; the piezoelectric unit includes a piezoelectric layer 7, a top electrode 8, and a bottom electrode 6; the U-shaped substrate support structure 4a includes a composite layer and a silicon substrate layer 3; the first etching cavity 10 is located below the cantilever beam 3a corresponding to the piezoelectric layer. When acceleration is input, the inertial force causes relative motion between the U-shaped base support structure 4a and the upper and lower dual mass blocks, resulting in deformation of the cantilever beam 3a. Due to the piezoelectric effect of the piezoelectric material, the piezoelectric units on the cantilever beam 3a generate charges, thereby enabling the electrical measurement of acceleration.

[0077] The sensor chip operates in the frequency range below 10kHz. Furthermore, it maintains high sensitivity even below 500Hz, making it well-suited for various applications.

[0078] The fabrication method of this MEMS piezoelectric vector hydrophone is described in detail below with reference to Examples 1-4 and the accompanying drawings.

[0079] Example 1

[0080] (1) Prepare the substrate SOI silicon wafer

[0081] The prepared SOI silicon wafer is a no-clean substrate that can be used directly for experiments. Figure 4This is a cross-sectional view of the SOI silicon wafer of the piezoelectric sensing chip, as shown below. Figure 3 As shown, the SOI silicon wafer includes: SOI silicon wafer 1, SOI buried oxide layer 2, and SOI silicon substrate layer 3; the thickness of SOI silicon wafer 1 is 50μm; the thickness of SOI buried oxide layer 2 is 3.5μm; and the thickness of SOI silicon substrate layer 3 is 100μm.

[0082] (2) Preparation of thermally oxidized silicon dioxide layer

[0083] A 10 μm thick silicon dioxide layer was prepared on the upper surface of SOI silicon wafer 1 and the lower surface of SOI silicon substrate layer 3 using a thermal oxidation furnace. The silicon dioxide layer on the upper surface of SOI silicon wafer 1 serves as insulating layer 4, and the silicon dioxide layer on the lower surface of SOI silicon substrate layer 3 serves as one of the bulk silicon etching mask layers 5. Figure 5 As shown.

[0084] (3) Fabrication of bottom electrode 6

[0085] A platinum / titanium composite layer with a platinum thickness of 0.5 μm and a titanium thickness of 0.1 μm is deposited on the upper surface of the insulating layer 4 on the front side of the SOI substrate using magnetron sputtering. Then, processes such as coating with photoresist, exposure, development, etching of the composite layer with etchant, and removal of photoresist with acetone are performed sequentially to pattern the composite layer and form the bottom electrode 6.

[0086] (4) Fabrication of piezoelectric layer 7

[0087] A 0.2 μm thick zinc oxide piezoelectric layer was prepared on the upper surface of the bottom electrode 6 by magnetron sputtering. Then, the zinc oxide piezoelectric layer was patterned by sequentially coating photoresist, exposure, development, etching the zinc oxide piezoelectric layer with a 1:10 phosphoric acid:water etchant, and removing the photoresist with acetone, thus forming the piezoelectric layer 7.

[0088] (5) The top electrode 8 was prepared using a peeling process.

[0089] Photoresist is coated on the front side of a silicon substrate. After exposure and development, the reverse pattern of the top electrode is formed on the photoresist. A platinum / titanium composite layer with a platinum thickness of 0.5 μm and a titanium thickness of 0.1 μm is deposited using magnetron sputtering. Finally, the photoresist is removed with acetone to obtain the patterned top electrode 8.

[0090] In this process, a bottom electrode 6, a piezoelectric layer 7, and a top electrode 8 are deposited on the front side of the silicon substrate to form a piezoelectric unit. A cross-sectional view of the chip is shown below. Figure 6 As shown.

[0091] (6) Formation of U-shaped slit 5a

[0092] Photoresist is coated on the front side of the SOI substrate. After exposure and development, the U-shaped slit pattern to be etched is exposed on the photoresist. ICP etching is used to etch the insulating layer 4 and the SOI silicon wafer 1 respectively, forming a U-shaped slit 5a with a width of 80 μm. The etched barrier layer is the SOI buried oxide layer 2. Figure 7 As shown.

[0093] (7) Patterning of deep silicon etching masks

[0094] A 10 μm thick silicon dioxide layer was deposited on the back surface of the thermally oxidized silicon dioxide layer on the SOI substrate using PECVD, and a 100 μm thick photoresist was coated on it. After double-sided exposure and development of the photoresist, the patterns of the first etching cavity 10 and the second etching cavity 11 to be etched were exposed on the photoresist. ICP was used to etch the silicon dioxide layer and the thermally oxidized layer under the photoresist to form the bulk silicon etching mask layer 5 for deep silicon etching, as shown below. Figure 8 As shown.

[0095] (8) Release of cantilever beam 3a and lower mass block 2a

[0096] The deep silicon of the SOI silicon substrate 3 is etched using deep reactive ion etching (DRIE). After etching, the SOI buried oxide layer 2 on the SOI silicon substrate 3 is etched using ICP, forming a first etching cavity 10 and a second etching cavity 11, releasing the cantilever beam 3a and the lower mass block 2a. The first etching cavity 10 is directly opposite the piezoelectric unit, and the lower mass block 2a is formed between the first etching cavity 10 and the second etching cavity 11. Figure 9 and Figure 10 As shown.

[0097] (9) Prepare mass block 1a

[0098] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks were on the same horizontal plane as the center of gravity of the cantilever beam. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick aluminum film was sputtered as a support film. A 20μm thick photoresist was then coated on the surface of the aluminum film. The other side of the silicon substrate was coated with photoresist, exposed, developed, and patterned. Dry etching was then performed on the bulk silicon. The photoresist was removed using acetone and ethanol. The aluminum film was removed by wet etching to obtain the upper mass block 1a.

[0099] (10) Bond the mass block 1a

[0100] The upper mass block 1a is bonded to the optimized position on the upper surface of the cantilever beam 3a, ensuring that the position of the upper mass block is symmetrical to that of the lower mass block and directly opposite it. This guarantees that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam. Figure 11 As shown.

[0101] Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip, such as... Figure 11 As shown. The operating frequency range of this sensor chip is below 10kHz.

[0102] (11) Packaging of MEMS vector hydrophones

[0103] Figure 11 This is a cross-sectional view of the fabricated piezoelectric sensor chip. After dicing the sensor chip, individual piezoelectric sensor chips a are formed, as shown below. Figure 2 As shown in the figure, several piezoelectric sensing chips a are connected and glued to corresponding PCB circuit boards b using voltage soldering and epoxy resin adhesive. They are placed perpendicularly to each other within the aluminum shell c along the X, Y, and Z axes, with leads extended out. The outer casing is then sealed with epoxy resin, polyurethane, etc., completing the fabrication of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is as follows. Figure 1 As shown.

[0104] Example 2

[0105] (1) Prepare silicon substrate

[0106] The prepared silicon substrate is a no-wash substrate that can be used directly in experiments. The silicon substrate consists of: silicon layer 1 and silicon substrate layer 3; the thickness of silicon layer 1 is 20 μm; the thickness of silicon substrate layer 3 is 300 μm.

[0107] (2) Preparation of thermally oxidized silicon dioxide layer

[0108] A 15 μm thick silicon dioxide layer is prepared on the upper surface of silicon wafer 1 and the lower surface of silicon substrate layer 3 using a thermal oxidation furnace. The silicon dioxide layer on the upper surface of silicon wafer 1 serves as insulating layer 4, and the silicon dioxide layer on the lower surface of silicon substrate layer 3 serves as one of the bulk etching composite mask layers.

[0109] (3) Fabrication of bottom electrode 6

[0110] A platinum / titanium composite layer with a platinum thickness of 0.4 μm and a titanium thickness of 0.2 μm is deposited on the upper surface of the insulating layer 4 on the front side of the silicon substrate using magnetron sputtering. Then, processes such as coating with photoresist, exposure, development, etching of the composite layer with etchant, and removal of photoresist with acetone are performed sequentially to pattern the composite layer and form the bottom electrode 6.

[0111] (4) Fabrication of piezoelectric layer 7

[0112] A 10 μm thick organic film layer was prepared on the upper surface of the bottom electrode 6 using the sol-gel method. Then, the organic film layer was patterned by sequentially performing processes such as coating with photoresist, exposure, development, etching with etchant, and removal of photoresist with acetone, thus forming the piezoelectric layer 7.

[0113] (5) The top electrode 8 was prepared using a peeling process.

[0114] Photoresist is coated on the front side of a silicon substrate. After exposure and development, the reverse pattern of the top electrode is formed on the photoresist. A platinum / titanium composite layer with a platinum thickness of 0.5 μm and a titanium thickness of 0.1 μm is deposited using magnetron sputtering. Finally, the photoresist is removed with acetone to obtain the patterned top electrode 8.

[0115] Among them, a bottom electrode 6, a piezoelectric layer 7, and a top electrode 8 are deposited on the front side of the silicon substrate to form a piezoelectric unit.

[0116] (6) Formation of U-shaped slit 5a

[0117] Photoresist is coated on the front side of the SOI substrate. After exposure and development, the U-shaped slit pattern to be etched is exposed on the photoresist. The insulating layer 4 and silicon wafer 1 are etched by ICP etching method to form a U-shaped slit 5a with a width of 60μm.

[0118] (7) Patterning of deep silicon etching masks

[0119] A 100μm thick photoresist 9 is coated on the surface of the bulk silicon etching mask layer 5 on the back of the silicon substrate to form a composite mask layer for deep silicon etching. After exposure and development, the desired patterns of the first etching cavity 10 and the second etching cavity 11 are obtained.

[0120] (8) Release of cantilever beam 3a and lower mass block 2a

[0121] The silicon substrate 3 is etched using a wet etching method to form a first etching cavity 10 and a second etching cavity 11, releasing the cantilever beam 3a and the lower mass block 2a. The first etching cavity 10 is directly opposite the piezoelectric unit, and the lower mass block 2a is formed between the first etching cavity 10 and the second etching cavity 11.

[0122] (9) Prepare mass block 1a

[0123] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks were on the same horizontal plane as the center of gravity of the cantilever beam. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick silicon dioxide film was sputtered as a support film. A 20μm thick photoresist was then coated on the surface of the silicon dioxide film. The other side of the silicon substrate was coated with photoresist, exposed, developed, and patterned. Dry etching was then performed on the bulk silicon. The photoresist was removed using acetone and ethanol. The silicon dioxide film was then removed by dry etching to obtain the upper mass block 1a.

[0124] (10) Bond the mass block 1a

[0125] The upper mass block 1a is bonded to the optimized position on the upper surface of the cantilever beam 3a, so that the position of the upper mass block is symmetrical with that of the lower mass block and is directly opposite each other, ensuring that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam.

[0126] Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip, such as... Figure 12 As shown. The operating frequency range of this sensor chip is below 10kHz.

[0127] (11) Packaging of MEMS vector hydrophones

[0128] Figure 12 This is a cross-sectional view of the fabricated piezoelectric sensor chip. After dicing the sensor chip, individual piezoelectric sensor chips a are formed, as shown below. Figure 2 As shown in the figure, several piezoelectric sensing chips a are connected and glued to corresponding PCB circuit boards b using voltage soldering and epoxy resin adhesive. They are placed perpendicularly to each other within the aluminum shell c along the X, Y, and Z axes, with leads extended out. The outer casing is then sealed with epoxy resin, polyurethane, etc., completing the fabrication of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is as follows. Figure 1 As shown.

[0129] Example 3

[0130] (1) Prepare the substrate SOI silicon wafer

[0131] The prepared SOI silicon wafer is a no-clean substrate that can be used directly for experiments. Figure 4 This is a cross-sectional view of the SOI silicon wafer of the piezoelectric sensing chip, as shown below. Figure 4 As shown, the SOI silicon wafer includes: SOI silicon wafer 1, SOI buried oxide layer 2, and SOI silicon substrate layer 3; the thickness of SOI silicon wafer 1 is 20 μm; the thickness of SOI buried oxide layer 2 is 1 μm; and the thickness of SOI silicon substrate layer 3 is 200 μm.

[0132] (2) Preparation of thermally oxidized silicon dioxide layer

[0133] A 3μm thick silicon dioxide layer was prepared on the upper surface of SOI silicon wafer 1 and the lower surface of SOI silicon substrate layer 3 using a thermal oxidation furnace. The silicon dioxide layer on the upper surface of SOI silicon wafer 1 serves as insulating layer 4, and the silicon dioxide layer on the lower surface of SOI silicon substrate layer 3 serves as one of the bulk silicon etching mask layers 5. Figure 5 As shown.

[0134] (3) Fabrication of bottom electrode 6

[0135] A gold / chromium composite layer with a gold thickness of 0.05 μm and a chromium thickness of 0.01 μm is deposited on the upper surface of the insulating layer 4 on the front side of the SOI substrate using magnetron sputtering. Then, processes such as photoresist coating, exposure, development, etching of the composite layer with etchant, and removal of photoresist with acetone are performed sequentially to pattern the composite layer and form the bottom electrode 6.

[0136] (4) Fabrication of piezoelectric layer 7

[0137] A 1 μm thick zinc oxide piezoelectric layer was prepared on the upper surface of the bottom electrode 6 using magnetron sputtering. Then, the process of coating photoresist, exposure, development, etching the zinc oxide piezoelectric layer with etchant, and removing the photoresist with acetone was performed sequentially to pattern the zinc oxide piezoelectric layer and form the piezoelectric layer 7.

[0138] (5) The top electrode 8 was prepared using a peeling process.

[0139] Photoresist is coated on the front side of a silicon substrate. After exposure and development, the reverse pattern of the top electrode is formed on the photoresist. A gold / chromium composite layer with a gold thickness of 0.05 μm and a chromium thickness of 0.01 μm is deposited using magnetron sputtering. Finally, the photoresist is removed with acetone to obtain the patterned top electrode 8.

[0140] In this process, a bottom electrode 6, a piezoelectric layer 7, and a top electrode 8 are deposited on the front side of the silicon substrate to form a piezoelectric unit. A cross-sectional view of the chip is shown below. Figure 6 As shown.

[0141] (6) Formation of U-shaped slit 5a

[0142] Photoresist is coated on the front side of the SOI substrate. After exposure and development, the U-shaped slit pattern to be etched is exposed on the photoresist. ICP etching is used to etch the insulating layer 4 and the SOI silicon wafer 1 respectively, forming a U-shaped slit 5a with a width of 10 μm. The etched barrier layer is the SOI buried oxide layer 2. Figure 7 As shown.

[0143] (7) Patterning of deep silicon etching masks

[0144] A 30 μm thick silicon dioxide layer was deposited on the back surface of the thermally oxidized silicon dioxide layer on the SOI substrate using PECVD, and a 200 μm thick photoresist was coated on it. After double-sided exposure and development of the photoresist, the patterns of the first etching cavity 10 and the second etching cavity 11 to be etched were exposed on the photoresist. ICP was used to etch the silicon dioxide layer and the thermally oxidized layer under the photoresist to form the bulk silicon etching mask layer 5 for deep silicon etching, as shown below. Figure 8 As shown.

[0145] (8) Release of cantilever beam 3a and lower mass block 2a

[0146] The deep silicon of the SOI silicon substrate 3 is etched using deep reactive ion etching (DRIE). After etching, the SOI buried oxide layer 2 on the SOI silicon substrate 3 is etched using ICP, forming a first etching cavity 10 and a second etching cavity 11, releasing the cantilever beam 3a and the lower mass block 2a. The first etching cavity 10 is directly opposite the piezoelectric unit, and the lower mass block 2a is formed between the first etching cavity 10 and the second etching cavity 11. Figure 9 and Figure 10 As shown.

[0147] (9) Prepare mass block 1a

[0148] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks were on the same horizontal plane as the center of gravity of the cantilever beam. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick platinum and titanium film were sputtered as a composite support film. A 40μm thick photoresist was coated on the surface of the platinum / titanium composite film. The other side of the silicon substrate was coated with photoresist, exposed, developed, and patterned. The bulk silicon was then wet-etched. The photoresist was removed using acetone and ethanol. The platinum / titanium composite film was removed by wet etching to obtain upper mass block 1a.

[0149] (10) Attach the mass block 1a

[0150] The upper mass block 1a is attached to the optimized position on the upper surface of the cantilever beam 3a, ensuring that the upper mass block is symmetrical to the lower mass block vertically and directly aligned. This guarantees that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam. Figure 11 As shown.

[0151] Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip, such as... Figure 11 As shown. The operating frequency range of this sensor chip is below 10kHz.

[0152] (11) Packaging of MEMS vector hydrophones

[0153] Figure 11 This is a cross-sectional view of the fabricated piezoelectric sensor chip. After dicing the sensor chip, individual piezoelectric sensor chips a are formed, as shown below. Figure 2 As shown in the figure, several piezoelectric sensing chips a are connected and glued to corresponding PCB circuit boards b using voltage soldering and epoxy resin adhesive. They are placed perpendicularly to each other within the aluminum shell c along the X, Y, and Z axes, with leads extended out. The outer casing is then sealed with epoxy resin, polyurethane, etc., completing the fabrication of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is as follows. Figure 1 As shown.

[0154] Example 4

[0155] 1) Prepare the SOI silicon substrate

[0156] The prepared SOI silicon wafer is a no-clean substrate that can be used directly for experiments. Figure 3 This is a cross-sectional view of the SOI silicon wafer of the piezoelectric sensing chip, as shown below. Figure 4 As shown, the SOI silicon wafer includes: SOI silicon wafer 1, SOI buried oxide layer 2, and SOI silicon substrate layer 3; the thickness of SOI silicon wafer 1 is 40 μm; the thickness of SOI buried oxide layer 2 is 5.5 μm; and the thickness of SOI silicon substrate layer 3 is 400 μm.

[0157] (2) Preparation of thermally oxidized silicon dioxide layer

[0158] An 8 μm thick silicon dioxide layer was prepared on the upper surface of SOI silicon wafer 1 and the lower surface of SOI silicon substrate layer 3 using a thermal oxidation furnace. The silicon dioxide layer on the upper surface of SOI silicon wafer 1 serves as insulating layer 4, and the silicon dioxide layer on the lower surface of SOI silicon substrate layer 3 serves as one of the bulk silicon etching mask layers 5. Figure 5 As shown.

[0159] (3) Fabrication of bottom electrode 6

[0160] A platinum / titanium composite layer with a platinum thickness of 0.2 μm and a titanium thickness of 0.05 μm is deposited on the upper surface of the insulating layer 4 on the front side of the SOI substrate using magnetron sputtering. Then, processes such as coating with photoresist, exposure, development, etching of the composite layer with etchant, and removal of photoresist with acetone are performed sequentially to pattern the composite layer and form the bottom electrode 6.

[0161] (4) Fabrication of piezoelectric layer 7

[0162] A composite layer of perovskite film and zinc oxide film with a thickness of 25 μm was prepared on the upper surface of the bottom electrode 6 using the sol-gel method. Then, the perovskite film was patterned by sequentially performing processes such as coating with photoresist, exposure, development, etching with etchant, and removal of photoresist with acetone, thus forming the piezoelectric layer 7.

[0163] (5) The top electrode 8 was prepared using a peeling process.

[0164] Photoresist is coated on the front side of a silicon substrate. After exposure and development, the reverse pattern of the top electrode is formed on the photoresist. A platinum / titanium composite layer with a platinum thickness of 0.2 μm and a titanium thickness of 0.05 μm is deposited using magnetron sputtering. Finally, the photoresist is removed with acetone to obtain the patterned top electrode 8.

[0165] In this process, a bottom electrode 6, a piezoelectric layer 7, and a top electrode 8 are deposited on the front side of the silicon substrate to form a piezoelectric unit. A cross-sectional view of the chip is shown below. Figure 6 As shown.

[0166] (6) Formation of U-shaped slit 5a

[0167] Photoresist is coated on the front side of the SOI substrate. After exposure and development, the U-shaped slit pattern to be etched is exposed on the photoresist. ICP etching is used to etch the insulating layer 4 and the SOI silicon wafer 1 respectively, forming a U-shaped slit 5a with a width of 20 μm. The etched barrier layer is the SOI buried oxide layer 2. Figure 7 As shown.

[0168] (7) Patterning of deep silicon etching masks

[0169] A 15 μm thick silicon dioxide layer was deposited on the thermally oxidized silicon dioxide layer on the back side of the SOI substrate using PECVD, and a 300 μm thick photoresist was coated on it. After double-sided exposure and development of the photoresist, the patterns of the first etching cavity 10 and the second etching cavity 11 to be etched were exposed on the photoresist. ICP was used to etch the silicon dioxide layer and the thermally oxidized layer under the photoresist to form the bulk silicon etching mask layer 5 for deep silicon etching, as shown below. Figure 8 As shown.

[0170] (8) Release of cantilever beam 3a and lower mass block 2a

[0171] The deep silicon of the SOI silicon substrate 3 is etched using deep reactive ion etching (DRIE). After etching, the SOI buried oxide layer 2 on the SOI silicon substrate 3 is etched using ICP, forming a first etching cavity 10 and a second etching cavity 11, releasing the cantilever beam 3a and the lower mass block 2a. The first etching cavity 10 is directly opposite the piezoelectric unit, and the lower mass block 2a is formed between the first etching cavity 10 and the second etching cavity 11. Figure 9 and Figure 10 As shown.

[0172] (9) Prepare mass block 1a

[0173] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks were on the same horizontal plane as the center of gravity of the cantilever beam. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick platinum and titanium film were sputtered as a composite support film. A 40μm thick photoresist was coated on the surface of the platinum / titanium composite film. The other side of the silicon substrate was coated with photoresist, exposed, developed, and patterned. Dry etching was then performed on the bulk silicon. The photoresist was removed using acetone and ethanol. The platinum / titanium composite film was removed by dry etching to obtain upper mass block 1a.

[0174] (10) Attach the mass block 1a

[0175] The upper mass block 1a is attached to the optimized position on the upper surface of the cantilever beam 3a, ensuring that the upper mass block is symmetrical to the lower mass block vertically and directly aligned. This guarantees that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam. Figure 11 As shown.

[0176] Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip, such as... Figure 11 As shown. The operating frequency range of this sensor chip is below 10kHz.

[0177] (11) Packaging of MEMS vector hydrophones

[0178] Figure 11 This is a cross-sectional view of the fabricated piezoelectric sensor chip. After dicing the sensor chip, individual piezoelectric sensor chips a are formed, as shown below. Figure 2 As shown in the figure, several piezoelectric sensing chips a are connected and glued to corresponding PCB circuit boards b using voltage soldering and epoxy resin adhesive. They are placed perpendicularly to each other within the aluminum shell c along the X, Y, and Z axes, with leads extended out. The outer casing is then sealed with epoxy resin, polyurethane, etc., completing the fabrication of the MEMS vector hydrophone. The MEMS vector hydrophone structure provided in this embodiment is as follows. Figure 1 As shown.

[0179] It should be noted that the piezoelectric layer materials used in the embodiments of the present invention, such as zinc oxide film, aluminum nitride film, lead zirconate titanate piezoelectric film, PMN-PT piezoelectric film, perovskite piezoelectric film, or organic piezoelectric film and their composite film layers, are interchangeable in each embodiment.

[0180] This invention provides a MEMS piezoelectric vector hydrophone with a dual-mass cantilever beam structure. First, a composite resonant membrane consisting of a silicon layer and a thermo-oxidative layer is formed on the front side of an SOI substrate or silicon substrate. Then, a lower metal electrode, a piezoelectric layer, and an upper electrode are deposited sequentially on the composite resonant membrane. A U-shaped slit is formed on the front side of the substrate by etching the composite layer around the cantilever beam and mass blocks, laying the foundation for the release of the cantilever beam and lower mass blocks. A bulk silicon composite etching mask is deposited on the back side of the substrate to form a bulk silicon etching mask. The bulk etching mask layer on the back side of the silicon substrate is photolithographically etched and etched to form the mask pattern required for bulk etching. Bulk silicon etching releases the composite resonant membrane and the lower mass block. Finally, an upper mass block, directly opposite the lower mass block, is attached or bonded to the upper surface of the cantilever beam's suspended end, completing the fabrication of the sensor chip. The device and fabrication method of this invention have a relatively simple fabrication process, good directivity, high sensitivity, stable operation, low noise, and do not require a micro-air gap.

[0181] After dicing the sensor chip, individual piezoelectric sensing chips are formed. Several piezoelectric sensing chips are connected and glued to corresponding PCB circuit boards using voltage soldering and epoxy resin adhesive. They are placed perpendicularly to each other within the aluminum shell along the X, Y, and Z axes, with leads extended. The outer shell is then sealed with epoxy resin, polyurethane, etc., completing the fabrication of the MEMS vector hydrophone. The MEMS piezoelectric vector hydrophone structure fabricated using the method of this invention significantly improves sensitivity compared to MEMS piezoresistive hydrophones, and the fabrication process is relatively simple. Furthermore, it eliminates the need for the tiny air gap found in MEMS capacitive vector hydrophones, requires no bias voltage during operation, and is a passive device with very low noise. By adding an upper mass block above the cantilever beam, forming a symmetrical double-mass structure, the vibration amplitude of the cantilever beam can be significantly increased, allowing the piezoelectric material to generate more charge, thus significantly improving the hydrophone's sensitivity. The symmetrical double-mass structure also improves the figure-eight shape of the MEMS piezoelectric vector hydrophone, thereby enhancing the device's directivity.

[0182] The piezoelectric sensor chip provided in this embodiment of the invention consists of upper and lower dual mass blocks and a composite elastic cantilever beam formed by a piezoelectric layer and a silicon substrate layer. In a MEMS vector hydrophone, when an inertial force is applied, the piezoelectric cantilever beam deforms, causing a charge to be generated on the surface of its piezoelectric film. After being amplified by an amplifier circuit, a voltage signal is obtained, enabling electrical measurement of vector information in water.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure, the method comprising the following steps: Step 1. Prepare the substrate; Step 2. Prepare an insulating layer on the upper surface of the silicon wafer layer (4), and prepare a bulk silicon etching mask layer on the lower surface of the substrate (5). Step 3. Deposit a bottom electrode film on the upper surface of the insulating layer and pattern it to form the bottom electrode (6). Step 4. Deposit a piezoelectric layer film on the upper surface of the bottom electrode and pattern it to form a piezoelectric layer (7). Step 5. Deposit a top electrode film on the upper surface of the piezoelectric layer and pattern it to form the top electrode (8). Step 6. Prepare a mask for etching the U-shaped slit on the front side of the substrate, and pattern the mask to expose the pattern of the U-shaped slit to be etched. Perform wet etching or dry etching on the insulating layer and silicon wafer layer respectively to form the U-shaped slit (5a); the width of the U-shaped slit (5a) is 0.01μm~2000μm; the size of the U-shaped slit (5a) determines the length and width of the cantilever beam (3a) structure; Step 7. Pattern the bulk silicon etching mask layer to obtain the required patterns for the first etching cavity (10) and the second etching cavity (11); Step 8. Perform wet etching or dry etching on the bottom of the substrate to form a first etching cavity (10) and a second etching cavity (11), and release the cantilever beam (3a) and the lower mass block (2a); the first etching cavity (10) is directly opposite the piezoelectric sensing unit, and the lower mass block (2a) is formed between the first etching cavity (10) and the second etching cavity (11); the piezoelectric sensing unit is formed by a bottom electrode (6), a piezoelectric layer (7) and a top electrode (8); Step 9. Prepare the upper mass block (1a) and determine its installation position: Bond or paste the upper mass block (1a) to the corresponding position on the upper surface of the cantilever beam (3a), and make the position of the upper mass block (1a) symmetrical with that of the lower mass block (2a) and the position directly opposite each other, so as to ensure that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam, and obtain the MEMS piezoelectric vector hydrophone chip with a double mass block cantilever beam structure; The lower mass block (2a) is obtained by etching, pasting or bonding; Step 9 specifically includes: The MEMS piezoelectric vector hydrophone chip with a dual-mass block cantilever beam structure was modeled using simulation software. Based on the size and position of the lower mass block, the size and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks and the center of gravity of the cantilever beam are on the same horizontal plane. Fabrication of the upper mass block: A mask is designed based on the optimized size of the upper mass block; a double-sided polished ordinary silicon substrate is used as the substrate, a support layer is deposited, and a thicker photoresist is coated on the surface of the support layer; the other side of the silicon substrate is patterned using a mask, and the bulk silicon is subjected to wet etching or dry etching; the photoresist and support layer are removed to obtain the upper mass block; The upper mass block is bonded or pasted onto the optimized position on the cantilever beam, so that the position of the upper mass block is symmetrical with that of the lower mass block and the positions are directly opposite each other, ensuring that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam. The support layer is a film formed from any one of aluminum, gold, chromium, platinum, titanium, silicon dioxide, and silicon nitride, or a composite film formed from at least two of them. In step 1, an SOI substrate or a silicon substrate is used as the substrate; the SOI substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer, an SOI buried oxide layer, and a base silicon layer; the silicon substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer and a base silicon layer. The bulk silicon etching mask layer in step 2 is any one of the following hard masks: silicon dioxide layer, silicon nitride layer, polysilicon layer, phosphosilicate glass layer, aluminum metal, and gold, or a hard mask composed of a composite film formed of at least two of these materials, or a photoresist layer (9), or a composite mask layer composed of a hard mask and a photoresist layer (9). When an SOI substrate is used as the substrate, in step 8, the base silicon layer and SOI buried oxide layer of the SOI substrate are subjected to wet etching or dry etching from the outside to the inside. When a silicon substrate is used as the substrate, in step 8, the base silicon layer of the silicon substrate is subjected to wet etching or dry etching.

2. A MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure, characterized in that, The piezoelectric vector hydrophone chip, prepared using the method described in claim 1, comprises: an upper mass block (1a), a lower mass block (2a), a cantilever beam (3a), and a U-shaped substrate support structure (4a); wherein, One end of the cantilever beam (3a) is connected to the inner wall of one side of the "U"-shaped base support structure (4a) to fix the cantilever beam (3a); the other end of the cantilever beam (3a) is suspended. The upper mass block (1a) and the lower mass block (2a) are symmetrically distributed on the upper and lower sides of the cantilever beam (3a) at the cantilever end; The inner walls of the other three sides of the "U"-shaped base support structure (4a) together with the upper mass block (1a), the lower mass block (2a) and the cantilever beam (3a) form a U-shaped slit (5a). The upper mass block (1a) and the lower mass block (2a) are etched, pasted or bonded to the same positions on the upper and lower sides of the cantilever beam (3a) by means of etching, pasting or bonding; the upper mass block (1a) and the lower mass block (2a) have the same mass; the positions of the upper mass block and the lower mass block are directly opposite each other, ensuring that the center of gravity of the upper and lower mass blocks as a whole is on the same horizontal plane as the center of gravity of the cantilever beam; The width of the U-shaped slit (5a) is 0.01μm to 2000μm; the size of the U-shaped slit (5a) determines the length and width of the cantilever beam (3a) structure.

3. The MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure according to claim 2, characterized in that, The cantilever beam (3a) comprises, from bottom to top, a composite layer and a piezoelectric sensing unit stacked sequentially; wherein the piezoelectric sensing unit comprises, from bottom to top, a bottom electrode (6), a piezoelectric layer (7) and a top electrode (8) stacked sequentially.

4. The MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure according to claim 3, characterized in that, The bottom electrode (6) and the top electrode (8) are any one of the metal films of aluminum, molybdenum, gold, chromium, platinum and titanium, or a composite film formed of at least two of these metals; The piezoelectric layer (7) is any one of zinc oxide piezoelectric film, aluminum nitride piezoelectric film, lead zirconate titanate piezoelectric film, PMN-PT piezoelectric film, perovskite piezoelectric film, organic piezoelectric film, or a doped film formed by at least one of the piezoelectric films and a doping element, or a composite film formed by at least two of the piezoelectric films, or a piezoelectric film or composite film with an isolation layer on its surface; the isolation layer is any one of silicon nitride layer, silicon dioxide layer, polycrystalline silicon layer, phosphosilicate glass layer, or a composite film formed by at least two of the piezoelectric films.

5. The MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure according to claim 2, characterized in that, The “U”-shaped substrate support structure (4a) comprises, from bottom to top, a silicon substrate layer (3) and a composite layer stacked sequentially.

6. The MEMS piezoelectric vector hydrophone chip with a dual-mass block cantilever beam structure according to claim 3 or 5, characterized in that, The composite layer comprises, from bottom to top, a silicon layer (1) and an insulating layer (4) stacked sequentially.

7. The MEMS piezoelectric vector hydrophone chip with a dual-mass cantilever beam structure according to claim 6, characterized in that, The insulating layer (4) is made of any one of silicon dioxide, silicon nitride, polycrystalline silicon, or phosphosilicate glass, or a composite layer formed from at least two of them.

Images