A chip structure based on vertical interconnection and a preparation method thereof

Abstract

The application discloses a chip structure based on vertical interconnection and a preparation method thereof. The chip structure comprises at least two layers of circuit structures. Each layer of the circuit structure comprises a heterogeneous circuit module and an optical array. The optical array comprises a light emitting element and a light receiving element. The optical arrays of adjacent layers transmit optical signals through optical connection channels. The heterogeneous circuit modules of adjacent layers transmit electrical signals through electrical connection channels. The heterogeneous circuit modules or the optical arrays of the same layer are electrically connected. The light emitting element is used for converting optical signals into electrical signals. The light receiving element is used for converting electrical signals into optical signals. The embodiment of the application has strong anti-interference capability, can improve transmission rate and transmission capacity, and can be widely applied to the technical field of chip manufacturing.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip manufacturing technical field, and in particular to a chip structure based on vertical interconnection and a preparation method thereof. BACKGROUND

[0002] With the development of computer technology, the operation speed of data processing chip is gradually improved, but with the rise of signal frequency, the high frequency effect of signal transmission tends to be obvious, the magnetic field interference brought by high frequency signal limits the further improvement of signal rate, and the signal transmission capacity is limited. SUMMARY

[0003] Therefore, the embodiments of the present application provide a chip structure based on vertical interconnection and a preparation method thereof, which has strong anti-interference ability and can improve transmission rate and transmission capacity.

[0004] In a first aspect, the embodiments of the present application provide a chip structure based on vertical interconnection, comprising at least two layers of circuit structures, each layer of the circuit structure comprising a heterogeneous circuit module and an optical array, the optical array comprising a light emitting element and a light receiving element, the optical arrays of adjacent layers transmitting optical signals through optical connection channels, the heterogeneous circuit modules of adjacent layers transmitting electrical signals through electrical connection channels, and the heterogeneous circuit modules or the optical arrays of the same layer being electrically connected; wherein the light emitting element is used to convert optical signals into electrical signals, and the light emitting element is used to convert electrical signals into optical signals.

[0005] Optionally, the optical connection channel comprises a plurality of optical waveguides and an optical isolation layer, the optical isolation layer being arranged between the optical waveguides, and the light emitting element and the light receiving element transmitting optical signals through the optical waveguides.

[0006] Optionally, the material of the optical waveguide comprises lithium niobate.

[0007] Optionally, the material of the optical isolation layer comprises silicon dioxide.

[0008] Optionally, the light emitting element and the light receiving element connected by the optical connection channel correspond to each other, and the light emitting wavelength of the corresponding light emitting element is the same as the light receiving wavelength of the corresponding light receiving element.

[0009] Optionally, the light emitting element and the light receiving element connected by the optical connection channel correspond to each other, and the light emitting central axis of the corresponding light emitting element is on the same vertical line as the light receiving central axis of the corresponding light receiving element.

[0010] Optionally, the electrical connection channel comprises a through silicon via structure.

[0011] Optionally, the light emitting element comprises a surface emitting laser, and the light receiving element comprises a photodetector.

[0012] In a second aspect, the embodiment of the present application provides a preparation method of a chip structure based on vertical interconnection, comprising:

[0013] An optical interconnection via is prepared by etching at a position of the optical connection channel of the substrate;

[0014] A medium material is filled in the optical interconnection via to prepare an optical waveguide;

[0015] A polymer layer is deposited at a substrate interface of the optical waveguide to form a light emitting element or a light receiving element, and a cladding layer is formed on a surface of the polymer layer to prepare an optical connection channel device;

[0016] The optical connection channel device is integrated into the chip structure.

[0017] The embodiment of the present application has the following beneficial effects: in the embodiment, each circuit structure layer includes a heterogeneous circuit module and an optical array, the optical array includes a light emitting element and a light receiving element, the optical arrays of adjacent layers transmit optical signals through optical connection channels, the heterogeneous circuit modules of adjacent layers transmit electrical signals through electrical connection channels, the heterogeneous circuit modules or the optical arrays of the same layer are electrically connected, high-speed signals of adjacent layers are converted into optical signals through the optical arrays and are transmitted through the optical connection channels of vertical interconnection, and low-speed signals of adjacent layers are transmitted through the electrical connection channels, so that magnetic field interference caused by high-speed signals is reduced, anti-interference capability is enhanced, transmission rate and transmission capacity are improved, chip area is reduced, and production cost is lowered. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram of a chip structure based on vertical interconnection provided by the embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of an optical connection channel provided by the embodiment of the present application;

[0020] Figure 3 is a step flowchart of a preparation method of a chip structure based on vertical interconnection provided by the embodiment of the present application;

[0021] Figure 4 is a structural block diagram after an optical connection via is prepared on a substrate provided by the embodiment of the present application;

[0022] Figure 5 is a structural block diagram after an optical waveguide is prepared in an optical connection via provided by the embodiment of the present application;

[0023] Figure 6 is a structural block diagram after a polymer layer is deposited provided by the embodiment of the present application;

[0024] Figure 7is a structural block diagram after forming a cladding layer on a surface of a polymer layer. DETAILED DESCRIPTION

[0025] The application will be further described below in conjunction with the drawings and specific embodiments. For the step numbers in the following embodiments, they are only set for the convenience of description, and the order between the steps is not limited. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0026] In the following description, “some embodiments” are related to a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0027] In the following description, the terms “first\second\third” are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first\second\third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used in the embodiments of the application have the same meanings as those commonly understood by those skilled in the art to which the embodiments of the application belong. The terms used in the embodiments of the application are only for the purpose of describing the embodiments of the application, and are not intended to limit the application.

[0029] Before the embodiments of the application are further described in detail, the terms and phrases involved in the embodiments of the application are explained, and the terms and phrases involved in the embodiments of the application are applicable to the following explanations.

[0030] The embodiments of the application provide a chip structure based on vertical interconnection, comprising at least two layers of circuit structures, each layer of the circuit structure comprising a heterogeneous circuit module and an optical array, the optical array comprising a light emitting element and a light receiving element, the optical arrays of adjacent layers transmitting optical signals through optical connection channels, the heterogeneous circuit modules of adjacent layers transmitting electrical signals through electrical connection channels, and the heterogeneous circuit modules or the optical arrays of the same layer being electrically connected; wherein the light emitting element is used to convert optical signals into electrical signals, and the light emitting element is used to convert electrical signals into optical signals.

[0031] It should be noted that the number of circuit structure layers of the chip structure is determined according to actual application, and the embodiment is not specifically limited. The heterogeneous circuit module is a plurality of integrated modules with different structures and functions, which are packaged in one chip through three-dimensional heterogeneous integration technology, and the heterogeneous module includes but is not limited to MCU, DSP or other ICs, etc. The optical array includes a plurality of light emitting elements and light receiving elements, and the light emitting elements and the light receiving elements are arranged in an array, which can meet the parallel transmission of signals, and the number of light emitting elements and light receiving elements is determined according to actual application, and the embodiment is not specifically limited.

[0032] Referring to Figure 1 For example, the chip structure includes two layers of circuit structures, and the substrate of each layer of circuit structure includes a heterogeneous module 200 and an optical array 201. The optical arrays 201 of adjacent layers are connected through optical connection channels 202 and transmit optical signals through the optical connection channels 202. The heterogeneous modules 200 of adjacent layers are connected through electrical connection channels 203 and transmit low-speed electrical signals through the electrical connection channels 203. The high-speed electrical signal is first converted into an optical signal through a light emitting element, and then converted into an electrical signal through a light receiving element. The high-speed electrical signal is converted into an optical signal for transmission between different stacked layers.

[0033] Optionally, the optical connection channel includes a plurality of optical waveguides and an optical isolation layer, the optical isolation layer is arranged between the optical waveguides, and the light emitting element and the light receiving element transmit optical signals through the optical waveguides.

[0034] Referring to Figure 2 The optical connection channel 202 includes a plurality of optical waveguides 101 and a plurality of optical isolation layers 102, and the optical waveguides 101 are isolated by the optical isolation layers 102 to reduce crosstalk between optical signals.

[0035] Optionally, the material of the optical waveguide includes lithium niobate.

[0036] Optionally, the material of the optical isolation layer includes silicon dioxide.

[0037] It should be noted that the material of the optical waveguide includes but is not limited to lithium niobate, and the material of the optical isolation layer includes but is not limited to silicon dioxide. The material of the optical waveguide and the material of the optical isolation layer are determined according to actual application, and the embodiment is not specifically limited.

[0038] Optionally, the light emitting element and the light receiving element connected by the optical connection channel correspond one by one, and the light emitting wavelength of the corresponding light emitting element is the same as the light receiving wavelength of the corresponding light receiving element.

[0039] Referring to Figure 2The two ends of the same light waveguide 101 are a light emitting element and a light receiving element, the light emitting element and the light receiving element of the two ends of the same light waveguide 101 correspond to each other, the light emitting wavelength of the light emitting element is the same as the light receiving wavelength of the light receiving element, and the light emitting and light receiving of the same wavelength make the transmission efficiency higher.

[0040] Optionally, the light emitting element and the light receiving element connected by the optical connection channel correspond to each other, the light emitting central axis of the corresponding light emitting element is on the same vertical line as the light receiving central axis of the corresponding light receiving element.

[0041] Referring to Figure 2 The two ends of the same light waveguide 101 are a light emitting element and a light receiving element, the light emitting element and the light receiving element of the two ends of the same light waveguide 101 correspond to each other, the light emitting central axis of the light emitting element is on the same vertical line as the light receiving central axis of the light receiving element, so that the transmission signal loss in the transmission process is less.

[0042] Optionally, the electrical connection channel comprises a through-silicon via structure.

[0043] The substrate material can be silicon, and a metal material is plated on the surface of the through-silicon via structure to realize electrical conduction. The through-silicon via structure can be prepared by using existing related technologies.

[0044] Optionally, the light emitting element comprises a surface emitting laser, and the light receiving element comprises a photodetector.

[0045] The surface emitting laser is prepared on the substrate material to form the light emitting element, which is convenient and fast. The photodetector corresponds to the surface emitting laser.

[0046] The embodiment of the present application has the following beneficial effects: in the embodiment, each layer of circuit structure comprises a heterogeneous circuit module and an optical array, the optical array comprises a light emitting element and a light receiving element, the optical arrays of adjacent layers transmit optical signals through optical connection channels, the heterogeneous circuit modules of adjacent layers transmit electrical signals through electrical connection channels, the electrical connection is performed between the heterogeneous circuit modules or the optical arrays of the same layer, the high-speed signals of adjacent layers are converted into optical signals through the optical array and are transmitted through the vertically interconnected optical connection channels, the low-speed signals of adjacent layers are transmitted through the electrical connection channels, so that the magnetic field interference caused by the high-speed signals is reduced, the anti-interference ability is enhanced, the transmission rate and the transmission capacity are improved, the chip area is reduced, and the production cost is reduced.

[0047] Referring to Figure 3 The embodiment of the present application provides a preparation method of a chip structure based on vertical interconnection, comprising steps S100 to S400.

[0048] S100, at the position of the optical connection channel of the substrate, an optical interconnection via is prepared by etching.

[0049] Specifically, referring toFigure 4 The position of the optical connection via is determined on the silica substrate 301 according to the pin position of the device to be packaged, and the optical connection via 302 is obtained by laser etching.

[0050] S200, filling a medium material in the optical interconnection via to prepare an optical waveguide.

[0051] Specifically, referring to Figure 5 The lithium niobate 303 is filled in the optical connection via 302 as the optical waveguide medium by a hydrothermal synthesis method.

[0052] S300, depositing a polymer layer on the substrate interface of the optical waveguide to form a light-emitting element or a light-receiving element, and forming a cladding layer on the surface of the polymer layer to prepare an optical connection device.

[0053] Specifically, referring to Figure 6 A polymer device layer 304 is deposited on the surface of the obtained device, and a light-emitting element (surface-emitting laser) or a light-receiving element (photodetector) can be made according to the use requirement. Figure 7 The optical connection device is formed by forming a polymer upper cladding layer 305 on the surface of the obtained device by spin coating.

[0054] S400, integrating the optical connection device into a chip structure.

[0055] Specifically, the optical connection device is integrated into a heterogeneous chip by a three-dimensional integration technology.

[0056] The preparation method of the chip structure based on vertical interconnection in the embodiment can be prepared by using existing equipment and related technology, and has strong transplantability and is convenient for production.

[0057] The above is a specific description of the preferred implementation of the application, but the application is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the application. These equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A chip structure based on vertical interconnection, characterized in that, The system comprises at least two layers of circuit structure. Each layer includes a heterogeneous circuit module and an optical array. The optical array includes several light-emitting elements and light-receiving elements arranged in an array for parallel signal transmission. Optical arrays in adjacent layers transmit optical signals through optical connection channels, and heterogeneous circuit modules in adjacent layers transmit electrical signals through electrical connection channels. Heterogeneous circuit modules or optical arrays in the same layer are electrically connected. The light-receiving elements convert optical signals into electrical signals, and the light-emitting elements convert high-speed electrical signals into optical signals. High-speed signals in adjacent layers are converted into optical signals by the optical array and transmitted through vertically interconnected optical connection channels. Low-speed signals in adjacent layers are transmitted through electrical connection channels. The light-emitting elements and light-receiving elements connected by the optical connection channels correspond one-to-one, and the light-emitting central axis of the corresponding light-emitting element and the light-receiving central axis of the corresponding light-receiving element are on the same vertical line.

2. The chip structure according to claim 1, characterized in that, The optical connection channel includes several optical waveguides and an optical isolation layer. The optical isolation layer is disposed between the optical waveguides, and the light-emitting element and the light-receiving element transmit optical signals through the optical waveguides.

3. The chip structure according to claim 2, characterized in that, The material of the optical waveguide includes lithium niobate.

4. The chip structure according to claim 2, characterized in that, The material of the optical isolation layer includes silicon dioxide.

5. The chip structure according to claim 2, characterized in that, The light-emitting element and the light-receiving element connected by the optical connection channel correspond one-to-one, and the light-emitting wavelength of the corresponding light-emitting element is the same as the light-receiving wavelength of the corresponding light-receiving element.

6. The chip structure according to claim 1, characterized in that, The electrical connection channel includes a through-silicon via (TSV) structure.

7. The chip structure according to claim 1, characterized in that, The light-emitting element includes a surface-emitting laser, and the light-receiving element includes a photodetector.

8. A method for fabricating a chip structure based on vertical interconnects, characterized in that, For fabricating the vertically interconnected chip structure according to any one of claims 1-7, comprising: Optical interconnect vias are fabricated at the optical connection channel locations on the substrate by etching; An optical waveguide is fabricated by filling the optical interconnect vias with dielectric material. A polymer layer is deposited at the substrate interface of the optical waveguide to form a light-emitting element or a light-receiving element, and a cladding layer is formed on the surface of the polymer layer to prepare an optical connection channel device. The optical connection channel device is integrated into the chip structure.

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