A pixel driving circuit and control method thereof, and a display device

Abstract

The present application provides a pixel driving circuit and a control method thereof, and a display device, relating to the field of display technology. The pixel driving circuit reduces flicker of the display device at a first refresh frequency. The pixel driving circuit is configured to drive a light-emitting element to emit light under multiple frame periods of the first refresh frequency, each frame period including a refresh frame and at least one hold frame in a time sequence; the pixel driving circuit includes a bias subcircuit electrically connected to a reset signal line, a first gate signal line, a first initial signal line, a data signal line, and a first node, and configured to, when in a hold frame state, cause the first node to have a first bias electrical signal; a driving subcircuit electrically connected to the first node, a second node, and a third node, and configured to, under the control of a voltage at the second node, conduct a path between the first node and the third node, so that a current for causing the light-emitting element to emit light is generated in the path, and has a first bias process when in a hold frame state.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a control method thereof, and a display device. Background Art

[0002] With the continuous development of technology, users expect display devices to support both high refresh rates to avoid flicker and low refresh rates to reduce power consumption. However, current display devices are prone to flickering at low refresh rates, which fails to meet user requirements and results in a poor user experience. Summary of the Invention

[0003] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0004] In one aspect, a pixel driving circuit, a control method thereof, and a display device are provided. The pixel driving circuit is configured to drive a light-emitting element to emit light in multiple frame periods at a first refresh frequency, each frame period including a refresh frame and at least one hold frame in a time sequence. The pixel driving circuit includes:

[0005] a bias subcircuit electrically connected to the reset signal line, the first gate signal line, the first initial signal line, the data signal line and the first node, and configured to, when in the frame holding state, cause the first node to have a first bias electrical signal;

[0006] a driving subcircuit electrically connected to the first node, the second node, and the third node, configured to conduct a path between the first node and the third node under the control of the voltage of the second node, so that a current for causing the light-emitting element to emit light is generated in the path, and having a first bias process when in the holding frame state;

[0007] a compensation sub-circuit electrically connected to a fourth node, the third node, and the first gate signal line, and configured to conduct a path between the fourth node and the third node under the control of a gate signal of the first gate signal line;

[0008] a first reset subcircuit and a second reset subcircuit, wherein the first reset subcircuit is electrically connected to the reset signal line, the second initial signal line, and the second node, and is configured to reset the second node by an initial signal of the second initial signal line under the control of the reset signal of the reset signal line; and the second reset subcircuit is electrically connected to the reset signal line, the third initial signal line, and the anode of the light-emitting element, and is configured to reset the anode by an initial signal of the third initial signal line under the control of the reset signal of the reset signal line;

[0009] a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein the first light-emitting control subcircuit is electrically connected to a light-emitting control signal line, a voltage signal line, and the first node, and the second light-emitting control subcircuit is electrically connected to the light-emitting control signal line, the third node, and the anode, and the first light-emitting control subcircuit and the second light-emitting control subcircuit are respectively configured to transmit a current for causing the light-emitting element to emit light to the anode under control of a light-emitting control signal on the light-emitting control signal line;

[0010] The storage sub-circuit is electrically connected to the second node and the voltage signal line, and is configured to hold the electrical signal of the second node.

[0011] Optionally, the bias subcircuit is further configured to, when in the frame holding state, enable the first node to have the first bias electrical signal and the second bias electrical signal in a time sequence;

[0012] The driving sub-circuit is further configured to have the first bias process and the second bias process in time sequence when in the holding frame state.

[0013] Optionally, the first refresh frequency range includes 1-60 Hz.

[0014] Optionally, the pixel driving circuit further includes a regulating subcircuit, the regulating subcircuit being electrically connected to the second gate signal line, the second node, and the fourth node, and being configured to conduct a path between the second node and the fourth node under the control of a gate signal of the second gate signal line;

[0015] The driving sub-circuit includes a driving transistor;

[0016] The control electrode of the driving transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node.

[0017] Optionally, the bias subcircuit includes a fourth transistor and a ninth transistor;

[0018] The control electrode of the fourth transistor is electrically connected to the first gate signal line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the first node;

[0019] The ninth transistor has a control electrode electrically connected to the reset signal line, a first electrode electrically connected to the first initial signal line, and a second electrode electrically connected to the first node.

[0020] Optionally, the compensation sub-circuit includes a second transistor;

[0021] The control electrode of the second transistor is electrically connected to the first gate signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node;

[0022] The first reset sub-circuit includes a first transistor; the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the second initial signal line, and the second electrode is electrically connected to the fourth node;

[0023] The second reset sub-circuit includes a seventh transistor; a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode is electrically connected to the third initial signal line, and a second electrode is electrically connected to the fifth node;

[0024] The first light-emitting control subcircuit includes a fifth transistor; the control electrode of the fifth transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the voltage signal line, and the second electrode is electrically connected to the first node;

[0025] The second light emitting control subcircuit includes a sixth transistor; the control electrode of the sixth transistor is electrically connected to the light emitting control signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the anode.

[0026] Optionally, the regulating subcircuit includes an eighth transistor;

[0027] The control electrode of the eighth transistor is electrically connected to the second gate signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the fourth node.

[0028] Optionally, the eighth transistor comprises an oxide transistor.

[0029] On the other hand, a display device is provided, comprising the above-mentioned pixel driving circuit.

[0030] In another aspect, a control method is provided for controlling the above-mentioned pixel driving circuit, the method comprising:

[0031] In the frame holding state, a first bias electrical signal is input to the data signal line.

[0032] Optionally, the method further includes:

[0033] In the frame holding state, the first bias electrical signal is input to the data signal line and the second bias electrical signal is input to the first initial signal line in a time sequence.

[0034] In another aspect, a control method is provided for controlling the above-mentioned pixel driving circuit, the method comprising:

[0035] In the frame holding state, a first bias electrical signal is input to the first initial signal line.

[0036] Optionally, the method further includes:

[0037] In the frame holding state, the first bias electrical signal is input to the first initial signal line and the second bias electrical signal is input to the data signal line in a time sequence.

[0038] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 A schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of another pixel driving circuit provided in an embodiment of the present application;

[0042] Figure 3 A driving timing diagram of a pixel driving circuit provided in an embodiment of the present application;

[0043] Figure 4 A driving timing diagram of another pixel driving circuit provided in an embodiment of the present application;

[0044] Figure 5-Figure 11 for Figure 2 The pixel driving circuit is Figure 3 and Figure 4 Schematic diagram of the driving principle under the driving timing. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0046] In the embodiments of the present application, words such as "first", "second", "fourth", "fifth", "sixth", "seventh", and "eighth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0047] In the embodiments of the present application, the gate of a transistor is referred to as a control electrode, one of the source and drain is referred to as a first electrode, and the other is referred to as a second electrode. In the embodiments of the present application, the first electrode of all transistors is referred to as a drain, and the second electrode is referred to as a source.

[0048] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0049] The embodiment of the present application provides a pixel driving circuit and a control method thereof, and a display device. The pixel driving circuit is configured to drive a light-emitting element to emit light in a multi-frame period of a first refresh frequency, each frame period including a refresh frame and at least one hold frame in a time sequence, Figure 1 and Figure 2 As shown, the pixel driving circuit includes:

[0050] The bias sub-circuit 1 is electrically connected to the reset signal line Re_P, the first gate signal line Gn_P, the first initial signal line Vinit1, the data signal line Vdata and the first node N1, and is configured to be in a frame-holding state so that the first node N1 has a first bias electrical signal.

[0051] The driving sub-circuit 2 is electrically connected to the first node N1, the second node N2 and the third node N3, and is configured to turn on the path between the first node N1 and the third node N3 under the control of the voltage of the second node N2, so that a current for making the light-emitting element emit light is generated in the path, and has a first bias process when in a frame-holding state.

[0052] The compensation sub-circuit 3 is electrically connected to the fourth node N4, the third node N3 and the first gate signal line Gn_P, and is configured to conduct the path between the fourth node N4 and the third node N3 under the control of the gate signal of the first gate signal line Gn_P.

[0053] The first reset sub-circuit 41 and the second reset sub-circuit 42, the first reset sub-circuit 41 is electrically connected to the reset signal line Re_P, the second initial signal line Vinit2 and the second node N2, and is configured to reset the second node N2 through the initial signal of the second initial signal line Vinit2 under the control of the reset signal of the reset signal line Re_P; the second reset sub-circuit 42 is electrically connected to the reset signal line Re_P, the third initial signal line Vinit3 and the anode of the light-emitting element, and is configured to reset the anode through the initial signal of the third initial signal line Vinit3 under the control of the reset signal of the reset signal line Re_P.

[0054] A first light-emitting control subcircuit 51 and a second light-emitting control subcircuit 52, the first light-emitting control subcircuit 51 is electrically connected to the light-emitting control signal line EM, the voltage signal line VDD and the first node N1, the second light-emitting control subcircuit 52 is electrically connected to the light-emitting control signal line EM, the third node N3 and the anode, the first light-emitting control subcircuit 51 and the second light-emitting control subcircuit 52 are respectively configured to transmit the current used to make the light-emitting element emit light to the anode under the control of the light-emitting control signal of the light-emitting control signal line EM.

[0055] The storage sub-circuit 6 is electrically connected to the second node N2 and the voltage signal line VDD, and is configured to hold the electrical signal of the second node N2.

[0056] refer to Figure 1 As shown, the anode of the light emitting element can be electrically connected to the fifth node N5, and the cathode of the light emitting element can be electrically connected to the ground terminal VSS.

[0057] The above-mentioned first refresh frequency refers to a low refresh frequency. The range, driving mode, etc. of the first refresh frequency are not specifically limited here. For example, the range of the first refresh frequency may include 1-60Hz. For example, the first refresh frequency can be driven in LongV mode. Take the LongV mode as an example to illustrate that the high refresh frequency of 120Hz and the low refresh frequency of 10Hz share the gamma voltage (Gamma) drive. At this time, the charging time of the pixel driving circuit at low refresh frequency is the same as that at high refresh frequency. Specifically, at high refresh frequency, one frame time is 1 / 120s, which are all refresh frames; at low refresh frequency, the next frame time is 1 / 10s, and the time to refresh the frame within this frame is still 1 / 120s. The rest of the time is a holding frame of 11 / 120s, which now includes 1 refresh frame and 11 holding frames. The pixel driving circuit refreshes the display screen in the refresh frame and does not refresh the display screen in the holding frame, but keeps the display screen or inserts black.

[0058] The specific circuit structures of the bias subcircuit, drive subcircuit, compensation subcircuit, first reset subcircuit, second reset subcircuit, first light-emitting control subcircuit, second light-emitting control subcircuit and storage subcircuit are not limited, as long as the corresponding functions are met.

[0059] The above-mentioned first node, second node, third node, fourth node and fifth node are only defined for the convenience of describing the circuit structure. The first node, second node, third node, fourth node and fifth node are not actual circuit units.

[0060] In the pixel driver circuit provided in an embodiment of the present application, the bias subcircuit is configured to, when in a hold frame state, cause the first node N1 to have a first bias electrical signal, and the driver subcircuit to have a first bias process when in the hold frame state. This allows the bias to be added during the hold frame to reduce or eliminate the effect of the refresh frame bias on the driver subcircuit, thereby effectively reducing or eliminating the brightness unevenness caused by the difference between the refresh frame and the hold frame of the pixel driver subcircuit, and effectively improving the flicker problem of the display device using this pixel driver circuit. That is, through the mutual cooperation of the bias subcircuit, the driver subcircuit, the compensation subcircuit, the first and second reset subcircuits, the first and second light-emitting control subcircuits, and the storage subcircuit, the light-emitting element can emit light at the first refresh frequency, and flicker is reduced or eliminated.

[0061] Optionally, refer to Figure 1 and Figure 2 As shown, the bias sub-circuit 1 is further configured to, in the case of being in a frame-keeping state, cause the first node N1 to have a first bias electrical signal and a second bias electrical signal in a time sequence; the driving sub-circuit 2 is further configured to, in the case of being in a frame-keeping state, have a first bias process and a second bias process in a time sequence.

[0062] Optionally, the first refresh frequency range includes 1-60 Hz.

[0063] The first refresh frequency is not specifically limited here. For example, the first refresh frequency may be 1 Hz, 10 Hz, 20 Hz, 30 Hz, 40 Hz, 50 Hz or 60 Hz, etc.

[0064] Optionally, refer to Figure 2 As shown, the pixel driving circuit also includes a regulating sub-circuit 7, which is electrically connected to the second gate signal line Gn_N, the second node N2 and the fourth node N4, and is configured to turn on the path between the second node N2 and the fourth node N4 under the control of the gate signal of the second gate signal line Gn_N.

[0065] refer to Figure 1 and Figure 2As shown, the driving sub-circuit 2 includes a driving transistor DT; the control electrode of the driving transistor DT is electrically connected to the second node N2, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the third node N3.

[0066] Optionally, refer to Figure 1 and Figure 2 As shown, the bias sub-circuit 1 includes a fourth transistor T4 and a ninth transistor T9; the control electrode of the fourth transistor T4 is electrically connected to the first gate signal line Gn_P, the first electrode is electrically connected to the data signal line Vdata, and the second electrode is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the reset signal line Re_P, the first electrode is electrically connected to the first initial signal line Vinit1, and the second electrode is electrically connected to the first node N1.

[0067] Optionally, refer to Figure 1 and Figure 2 As shown, the compensation sub-circuit 3 includes a second transistor T2; the control electrode of the second transistor T2 is electrically connected to the first gate signal line Gn_P, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the fourth node N4.

[0068] refer to Figure 1 and Figure 2 As shown, the first reset sub-circuit 41 includes a first transistor T1; the control electrode of the first transistor T1 is electrically connected to the reset signal line Re_P, the first electrode is electrically connected to the second initial signal line Vinit2, and the second electrode is electrically connected to the fourth node N4; the second reset sub-circuit 42 includes a seventh transistor T7; the control electrode of the seventh transistor T7 is electrically connected to the reset signal line Re_P, the first electrode is electrically connected to the third initial signal line Vinit3, and the second electrode is electrically connected to the fifth node N5.

[0069] refer to Figure 1 and Figure 2 As shown, the first light-emitting control sub-circuit 51 includes a fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected to the light-emitting control signal line EM, the first electrode is electrically connected to the voltage signal line VDD, and the second electrode is electrically connected to the first node N1; the second light-emitting control sub-circuit 52 includes a sixth transistor T6; the control electrode of the sixth transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the anode.

[0070] Optionally, refer to Figure 1 and Figure 2 As shown, the storage sub-circuit 6 includes a first capacitor Cst; one end of the first capacitor Cst is electrically connected to the voltage signal line VDD, and the other end is electrically connected to the second node N2.

[0071] Optionally, refer to Figure 2As shown, the regulating sub-circuit 7 includes an eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the second gate signal line Gn_N, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the fourth node N4.

[0072] Optionally, the eighth transistor includes an oxide transistor, thereby utilizing the low leakage characteristics of the oxide transistor to effectively improve the voltage holding ratio during a long frame period.

[0073] It should be noted that it can be Figure 2 All transistors except the eighth transistor are non-oxide transistors, such as LTPS (Low Temperature Poly-silicon) transistors; or at least one of the other transistors may be an oxide transistor, which is not specifically limited here. Figure 2 All transistors in the figure are non-oxide transistors, and the specific value shall be subject to actual application.

[0074] In order to unify the manufacturing process and facilitate a simpler driving method for the subsequent circuit, the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor can all be P-type transistors, and the eighth transistor can be an N-type transistor. Of course, all of the above transistors can also be N-type transistors. In the case where the above transistors are N-type transistors, the design principle is similar to that of the present application and also falls within the scope of protection of the present application.

[0075] The above does not limit the type of transistor, which may be a thin film transistor, and the thin film transistor may be a low-temperature polysilicon thin film transistor or an oxide thin film transistor.

[0076] It should be noted that if the above pixel driving circuit is applied to an OLED display device, the above light-emitting element is an organic light-emitting element. If the above pixel driving circuit is applied to a Mini LED display device or a Micro LED display device, the above light-emitting element is a Mini LED or Micro LED.

[0077] An embodiment of the present application further provides a display device, comprising the above-mentioned pixel driving circuit.

[0078] The above-mentioned display device can be a flexible display device (also called a flexible screen) or a rigid display device (ie, a display screen that cannot be bent), which is not limited here.

[0079] The above-mentioned display device can be an OLED (Organic Light-Emitting Diode) display device, or a Micro LED display device or a Mini LED display device, as well as any product or component with display function such as televisions, digital cameras, mobile phones, tablet computers, etc. that include these display devices; the above-mentioned display device can also be used in fields such as identity recognition and medical equipment. Products that have been promoted or have good promotion prospects include security identity authentication, smart door locks, medical image acquisition, etc.

[0080] The above-mentioned display device has the advantages of being able to effectively reduce flicker at a low refresh rate, low cost, good display effect, long life, high stability, high contrast, good imaging quality, and high product quality.

[0081] An embodiment of the present application further provides a control method for the above-mentioned pixel driving circuit, the control method comprising:

[0082] S11 . While maintaining a frame state, input a first bias electrical signal to the data signal line.

[0083] Optionally, the control method further includes:

[0084] S12. While maintaining the frame state, input a first bias electrical signal to the data signal line and input a second bias electrical signal to the first initial signal line in a time sequence.

[0085] An embodiment of the present application further provides a control method for the above-mentioned pixel driving circuit, the control method comprising:

[0086] S21 . While maintaining a frame state, input a first bias electrical signal to a first initial signal line.

[0087] Optionally, the control method further includes:

[0088] S22 . While maintaining the frame state, input a first bias electrical signal to the first initial signal line and input a second bias electrical signal to the data signal line in a time sequence.

[0089] The first refresh frequency can be a low refresh frequency (for example, a refresh frequency of 10 Hz). When the pixel driving circuit works at a low refresh frequency, it can refer to Figure 3 and Figure 4 The timing shown is described in detail as follows.

[0090] In the following, the eighth transistor is an N-type oxide transistor, and the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type low-temperature polysilicon transistors. Figure 3 The timing diagram of each signal line shown in the embodiment of the present application is as follows Figure 2 The working principle of the pixel driving circuit shown in FIG. 1 at a low refresh rate (for example, a refresh rate of 10 Hz) is described in detail. Figures 5 to 11 In the figure, the transistor is turned off as indicated by the “×” mark, and the light-emitting element is not emitting light as indicated by the “×” mark.

[0091] Refresh frame:

[0092] During the reset phase of the refresh frame, Figure 3 In the t11 phase, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the first gate signal line Gn_P, the light-emitting control signal line EM, and the second gate signal line Gn_N, and low-level signals are input to the second initial signal line Vinit2, the third initial signal line Vinit3, and the reset signal line Re_P. Figure 5 As shown, the first transistor T1, the seventh transistor T7, the ninth transistor T9, and the eighth transistor T8 are all turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are all turned off. Since the seventh transistor T7 is turned on, the initial signal of the third initial signal line Vinit3 can be written into the fifth node N5 and the anode of the light-emitting transistor, and the fifth node N5 and the anode of the light-emitting transistor are reset. Since the first transistor T1 and the eighth transistor T8 are both turned on, the initial signal of the second initial signal line Vinit2 can be written into the second node N2 (the initial signal of the second initial signal line Vinit2 is usually -5v~-3v), and since the ninth transistor T9 is turned on, the initial signal of the first initial signal line Vinit1 can be written into the first node N1 (the initial signal of the first initial signal line Vinit1 is usually 5v~7v). At this time, the gate-source voltage Vgs of the driving transistor DT is Vgs=Vinit2-Vinit1, and the driving transistor DT is in the on-state bias on-bias. This is a reset bias process, that is, a strong negative voltage bias process, which can effectively eliminate the influence of the grayscale voltage of the previous frame, and significantly improve the short-term image sticking, FFR (Frist Frame ration, first frame brightness ratio) level, etc.

[0093] During the write phase of the refresh frame, that is, Figure 3 In the t12 phase, high-level signals are input to the reset signal line Re_P, the light-emitting control signal line EM, the voltage signal line VDD, the data signal line Vdata, the second gate signal line Gn_N, and the first initial signal line Vinit1, and low-level signals are input to the first gate signal line Gn_P, the second initial signal line Vinit2, and the third initial signal line Vinit3. Figure 6As shown, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the driving transistor DT are all turned on, while the first transistor T1, the seventh transistor T7, the ninth transistor T9, the fifth transistor T5, and the sixth transistor T6 are all turned off. Since the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are all turned on, the driving transistor DT is in diode connection mode, and the data signal data of the data signal line Vdata is written to the first node N1 and charges the first capacitor Cst. In the end state, the potential of the first node N1 is Vdata + Vth. At this time, the gate-source voltage Vgs of the driving transistor DT is equal to Vth (Vth is the threshold voltage of the driving transistor DT), and the driving transistor DT is in the off-bias state.

[0094] During the light-emitting phase of the refresh frame, that is, Figure 3 In the t14 phase, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the first gate signal line Gn_P, and the reset signal line Re_P, and low-level signals are input to the light-emitting control signal line EM, the second gate signal line Gn_N, the second initial signal line Vinit2, and the third initial signal line Vinit3. Figure 8 As shown, the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are all turned on, and the first transistor T1, the seventh transistor T7, the ninth transistor T9, the eighth transistor T8, the second transistor T2, and the fourth transistor T4 are all turned off. Since the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are all turned on, the current input by the voltage signal line VDD flows into the anode of the light-emitting element, thereby driving the light-emitting element to emit light.

[0095] Keep Frame:

[0096] In the first bias phase of the hold frame, i.e. Figure 3 In the t21 stage, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the reset signal line Re_P, and the light-emitting control signal line EM, and low-level signals are input to the first gate signal line Gn_P, the second gate signal line Gn_N, the second initial signal line Vinit2, and the third initial signal line Vinit3. Figure 9 As shown, the fourth transistor T4, the second transistor T2, and the driving transistor DT are all turned on, and the fifth transistor T5, the sixth transistor T6, the first transistor T1, the seventh transistor T7, the ninth transistor T9, and the eighth transistor T8 are all turned off. Since the fourth transistor T4 is turned on, the Vkeep voltage of the data signal line Vdata (reference Figure 3As shown, the voltage value of the Vkeep voltage is greater than the voltage value of the data voltage Vdata) is written to the first node N1. At this time, the first node N1 has a first bias signal, and the gate-source voltage of the driving transistor DT is Vgs=Vdata+Vth-Vkeep. This is the first bias process.

[0097] During the lighting phase of the hold frame, i.e. Figure 3 In the t23 phase, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the first gate signal line Gn_P, and the reset signal line Re_P, and low-level signals are input to the light-emitting control signal line EM, the second gate signal line Gn_N, the second initial signal line Vinit2, and the third initial signal line Vinit3. Figure 11 As shown, the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are all turned on, and the first transistor T1, the seventh transistor T7, the ninth transistor T9, the eighth transistor T8, the second transistor T2, and the fourth transistor T4 are all turned off. Since the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are all turned on, the current input by the voltage signal line VDD flows into the anode of the light-emitting element, thereby driving the light-emitting element to emit light.

[0098] It should be noted that the initial signal and the Vkeep voltage of the first initial signal line Vinit1 can be as high as possible within an appropriate range, thereby effectively improving the compatibility between different grayscales.

[0099] Figure 3 The reset signal of the middle reset signal line Re_P and the gate signal of the first gate signal line Gn_P may be high-frequency pulses.

[0100] Figure 3 The initial signal of the first initial signal line Vinit1 can be a DC signal (Direct Current, DC signal), that is, the initial signal of the first initial signal line Vinit1 can remain unchanged. At this time, the first bias stage of the hold frame is set to be a Vkeep voltage whose input voltage value of the data signal line Vdata is greater than the data voltage Vdata.

[0101] In order to simplify the driving timing, the driving timing signals of the voltage signal line VDD, the second initial signal line Vinit2, and the third initial signal line Vinit3 provided in the embodiment of the present application are only one of the cases. In practical applications, other timing driving signals can also be used. For example: Figure 3 The t14 and t23 stages shown are due to Figure 2The first transistor T1 , the second transistor T2 , and the seventh transistor T7 are all turned off, and the signals of the second initial signal line Vinit2 and the third initial signal line Vinit3 can both be at a high level or a low level.

[0102] The embodiment of the present application provides a control method, which includes a reset phase of the refresh frame, a write phase of the refresh frame, a light-emitting phase of the refresh frame, a first bias phase of the hold frame, and a light-emitting phase of the hold frame, so that the refresh frame and the hold frame both include a bias process. On the one hand, the first bias phase of the hold frame can be made equivalent to the reset bias process of the reset phase of the refresh frame, so that the working state of the driving transistor DT tends to be consistent, thereby ensuring that there is no obvious difference between the brightness of the refresh frame and the brightness of the hold frame, and there is no visual flicker. Specifically, the Vkeep voltage can be used to make the effects of the first bias phase of the hold frame and the reset bias process of the reset phase of the refresh frame on the driving transistor DT equivalent, thereby partially or completely offsetting the effect of the reset bias of the reset phase; on the other hand, the above-mentioned pixel driving circuit can be implemented to drive the light-emitting element to emit light; on the other hand, the timing is simple and easy to implement.

[0103] Optionally, refresh the frame:

[0104] In the third bias phase of the refresh frame, Figure 3 In the t13 phase, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the first gate signal line Gn_P, and the light-emitting control signal line EM, and low-level signals are input to the second gate signal line Gn_N, the second initial signal line Vinit2, the third initial signal line Vinit3, and the reset signal line Re_P. Figure 7 As shown, the first transistor T1, the seventh transistor T7, the ninth transistor T9, and the driving transistor DT are all turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned off. Since the ninth transistor T9 is turned on, the initial signal of the first initial signal line Vinit1 is written to the first node N1, and the first capacitor Cst maintains the potential of the second node N2 constant. At this time, the gate-source voltage Vgs of the driving transistor DT is equal to Vdata + Vth - Vinit1. This is the third bias process, that is, the negative bias process.

[0105] Keep Frame:

[0106] In the second bias phase of the hold frame, i.e. Figure 3In the t22 stage, high-level signals are input to the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, the first gate signal line Gn_P, and the light-emitting control signal line EM, and low-level signals are input to the second gate signal line Gn_N, the second initial signal line Vinit2, the third initial signal line Vinit3, and the reset signal line Re_P. Figure 10 As shown, the first transistor T1, the seventh transistor T7, the ninth transistor T9, and the driving transistor DT are all turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned off. Since the ninth transistor T9 is turned on, the second bias signal of the first initial signal line Vinit1 is written to the first node N1. At this time, the gate-source voltage Vgs of the driving transistor DT is equal to Vdata+Vth-Vinit1. This is the second bias process.

[0107] It should be noted that the bias voltage and bias time of the second bias stage of the hold frame can be exactly the same as the bias voltage and bias time of the third bias stage of the refresh frame, so as to ensure that the second bias process of the hold frame and the third bias process of the refresh frame are equivalent, so that the voltages of the three terminals of the driving transistor DT are unified before the OLED emits light, ensuring that the initial light-emitting states of the refresh frame and the hold frame are consistent.

[0108] An embodiment of the present application provides a control method, which includes two bias processes for both the refresh frame and the hold frame through a reset phase of the refresh frame, a write phase of the refresh frame, a second bias phase of the refresh frame, a light-emitting phase of the refresh frame, a first bias phase of the hold frame, a third bias phase of the hold frame, and a light-emitting phase of the hold frame. On the one hand, by making the first bias stage of the holding frame equivalent to the reset bias process of the reset stage of the refresh frame, and the second bias process of the holding frame equivalent to the third bias process of the refresh frame, the working state of the driving transistor DT tends to be consistent, thereby ensuring that there is no obvious difference in the brightness of the refresh frame and the brightness of the holding frame, and there is no visual flicker; specifically, the Vkeep voltage can be used to make the first bias stage of the holding frame and the reset bias process of the reset stage of the refresh frame have the same effect on the driving transistor DT, and the second bias electrical signal of the first initial signal line Vinit1 can be used to make the second bias stage of the holding frame and the third bias process of the refresh frame have the same effect on the driving transistor DT, thereby partially or completely offsetting the impact of the reset bias process and the third bias process of the refresh frame; on the other hand, the above-mentioned pixel driving circuit can be used to drive the light-emitting element to emit light; on the other hand, the timing is simple and easy to implement.

[0109] In the following, the eighth transistor is an N-type oxide transistor, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type low-temperature polysilicon transistors. Figure 4 The timing diagram of each signal line shown in the embodiment of the present application is as follows Figure 2 The working principle of the pixel driving circuit shown in FIG. 1 at a low refresh frequency (eg, a refresh frequency of 10 Hz) is introduced in detail.

[0110] Figure 2 The pixel driving circuit shown in Figure 4 The working principle under the timing diagram shown is the same as that in Figure 3 The working principle under the timing diagram shown is basically the same, and both will go through Figure 5-Figure 11 The process shown.

[0111] The difference is:

[0112] In the first bias phase of the hold frame, i.e. Figure 4 In the t21 stage, high-level signals are input to the first gate signal line Gn_P, the voltage signal line VDD, the data signal line Vdata, the first initial signal line Vinit1, and the light-emitting control signal line EM, and low-level signals are input to the reset signal line Re_P, the second gate signal line Gn_N, the second initial signal line Vinit2, and the third initial signal line Vinit3. At this time, the first transistor T1, the seventh transistor T7, the ninth transistor T9, and the driving transistor DT are all turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned off. Since the ninth transistor T9 is turned on, the Vkeep voltage of the first initial signal line Vinit1 is written into the first node N1 (reference Figure 4 As shown, the voltage value of the Vkeep voltage is greater than the voltage value of the initial voltage Vinit1), at this time the first node N1 has the first bias signal, and the gate-source voltage of the driving transistor DT is Vgs=Vdata+Vth-Vkeep, which is the first bias process.

[0113] It should be noted that the Vkeep voltage is the voltage value of the first bias signal, and the first bias signal can make the pixel driving circuit be in the first bias stage during the holding frame. Figure 3 and Figure 4 As shown, the voltage value of the Vkeep voltage is greater than the voltage value of the data voltage Vdata, and the voltage value of the Vkeep voltage is greater than the voltage value of the initial voltage Vinit1.

[0114] In the second bias phase of the hold frame, i.e. Figure 4During stage t22, high-level signals are input to the reset signal line Re_P, voltage signal line VDD, data signal line Vdata, first initial signal line Vinit1, and emission control signal line EM. Low-level signals are input to the first gate signal line Gn_P, second gate signal line Gn_N, second initial signal line Vinit2, and third initial signal line Vinit3. At this time, the fourth transistor T4, second transistor T2, and drive transistor DT are all turned on, while the fifth transistor T5, sixth transistor T6, first transistor T1, seventh transistor T7, ninth transistor T9, and eighth transistor T8 are all turned off. Because the fourth transistor T4 is turned on, the second bias signal of the data signal line Vdata is written to the first node N1. At this time, the gate-source voltage Vgs of the drive transistor DT is equal to Vdata + Vth - Vinit1. This is the second biasing process.

[0115] The other stages are the same as above Figure 3 The various stages in the process are the same and will not be described here.

[0116] An embodiment of the present application provides a control method, which includes two bias processes for both the refresh frame and the hold frame through a reset phase of the refresh frame, a write phase of the refresh frame, a second bias phase of the refresh frame, a light-emitting phase of the refresh frame, a first bias phase of the hold frame, a third bias phase of the hold frame, and a light-emitting phase of the hold frame. On the one hand, by making the first bias stage of the holding frame equivalent to the reset bias process of the reset stage of the refresh frame, and making the second bias stage of the holding frame equivalent to the third bias stage of the refresh frame, the working state of the driving transistor DT tends to be consistent, thereby ensuring that there is no obvious difference in brightness between the refresh frame and the holding frame, and there is no visual flicker; specifically, the Vkeep voltage can be used to make the effects of the first bias stage of the holding frame and the reset bias process of the reset stage of the refresh frame on the driving transistor DT equivalent, and the second bias electrical signal of the data signal line Vdata can be used to make the effects of the second bias stage of the holding frame and the third bias stage of the refresh frame on the driving transistor DT equivalent, thereby partially or completely offsetting the effect of the reset bias in the reset stage; on the other hand, the coupling effect of the data line Source line jump can be effectively weakened, and the crosstalk, noise and other defects caused by the jump of the data line Sourceline can be reduced; on the other hand, the above-mentioned pixel driving circuit can be used to drive the light-emitting element to emit light; on the other hand, the timing is simple and easy to implement.

[0117] It should be noted that Figure 4The initial signal of the first initial signal line Vinit1 can be an AC signal (Alternating Current, alternating current signal), that is, the initial signal of the first initial signal line Vinit1 can be changed. In this case, the first bias stage of the maintenance frame is set to have an input voltage value of the first initial signal line Vinit1 greater than the Vkeep voltage of the initial signal Vinit1. Of course, the initial signal of the first initial signal line Vinit1 of the refresh frame can also be set to Vinit1-1, the initial signal of the first initial signal line Vinit1 of the maintenance frame can be Vinit1-2, and the data signal of the data signal line Vdata of the maintenance frame can be Vkeep. In this case, the voltage value of Vkeep can be equal to the voltage value of Vinit1-1, and the voltage value of Vinit1-2 can be greater than the voltage value of Vinit1-1.

[0118] Figure 4 The reset signal of the middle reset signal line Re_P and the gate signal of the first gate signal line Gn_P may be high-frequency pulses.

[0119] In order to simplify the driving timing, the driving timing signals of the voltage signal line VDD, the second initial signal line Vinit2, and the third initial signal line Vinit3 provided in the embodiment of the present application are only one of the cases. In practical applications, other timing driving signals can also be used. For example: Figure 4 The t14 and t24 stages shown are due to Figure 2 The first transistor T1 , the second transistor T2 , and the seventh transistor T7 are all turned off, and the signals of the second initial signal line Vinit2 and the third initial signal line Vinit3 can both be high level or low level.

[0120] An “embodiment” as referred to herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application.

[0121] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel driving circuit, characterized in that: is configured to drive the light-emitting element to emit light in a plurality of frame periods at a first refresh frequency, each frame period including a refresh frame and at least one hold frame in a time sequence; The pixel driving circuit includes: a bias subcircuit electrically connected to the reset signal line, the first gate signal line, the first initial signal line, the data signal line and the first node, and configured to, when in the frame holding state, cause the first node to have a first bias electrical signal; a driving subcircuit electrically connected to the first node, the second node, and the third node, configured to conduct a path between the first node and the third node under the control of the voltage of the second node, so that a current for causing the light-emitting element to emit light is generated in the path, and having a first bias process when in the holding frame state; a compensation sub-circuit electrically connected to a fourth node, the third node, and the first gate signal line, and configured to conduct a path between the fourth node and the third node under the control of a gate signal of the first gate signal line; a first reset subcircuit and a second reset subcircuit, wherein the first reset subcircuit is electrically connected to the reset signal line, the second initial signal line, and the second node, and is configured to reset the second node by an initial signal of the second initial signal line under the control of the reset signal of the reset signal line; and the second reset subcircuit is electrically connected to the reset signal line, the third initial signal line, and the anode of the light-emitting element, and is configured to reset the anode by an initial signal of the third initial signal line under the control of the reset signal of the reset signal line; a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein the first light-emitting control subcircuit is electrically connected to a light-emitting control signal line, a voltage signal line, and the first node, and the second light-emitting control subcircuit is electrically connected to the light-emitting control signal line, the third node, and the anode, and the first light-emitting control subcircuit and the second light-emitting control subcircuit are respectively configured to transmit a current for causing the light-emitting element to emit light to the anode under control of a light-emitting control signal on the light-emitting control signal line; a storage sub-circuit electrically connected to the second node and the voltage signal line, and configured to hold the electrical signal of the second node; The bias subcircuit includes a fourth transistor and a ninth transistor; the fourth transistor has a control electrode electrically connected to the first gate signal line, a first electrode electrically connected to the data signal line, and a second electrode electrically connected to the first node; the ninth transistor has a control electrode electrically connected to the reset signal line, a first electrode electrically connected to the first initial signal line, and a second electrode electrically connected to the first node; The compensation sub-circuit includes a second transistor; the control electrode of the second transistor is electrically connected to the first gate signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node.

2. The pixel driving circuit according to claim 1, wherein: The bias subcircuit is further configured to, when in the frame holding state, enable the first node to have the first bias electrical signal and the second bias electrical signal in a time sequence; The driving sub-circuit is further configured to have the first bias process and the second bias process in time sequence when in the holding frame state.

3. The pixel driving circuit according to claim 1, wherein: The first refresh frequency range includes 1-60 Hz.

4. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a regulating subcircuit, the regulating subcircuit being electrically connected to the second gate signal line, the second node, and the fourth node, and being configured to conduct a path between the second node and the fourth node under the control of a gate signal of the second gate signal line; The driving sub-circuit includes a driving transistor; The control electrode of the driving transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node.

5. The pixel driving circuit according to claim 4, wherein: The first reset sub-circuit includes a first transistor; the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the second initial signal line, and the second electrode is electrically connected to the fourth node; The second reset sub-circuit includes a seventh transistor; the control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the third initial signal line, and the second electrode is electrically connected to the fifth node; The first light-emitting control subcircuit includes a fifth transistor; the control electrode of the fifth transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the voltage signal line, and the second electrode is electrically connected to the first node; The second light emitting control subcircuit includes a sixth transistor; the control electrode of the sixth transistor is electrically connected to the light emitting control signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the anode.

6. The pixel driving circuit according to claim 4, wherein: The regulating subcircuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the second gate signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the fourth node.

7. The pixel driving circuit according to claim 6, wherein: The eighth transistor includes an oxide transistor.

8. A display device, characterized in that: The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 7.

9. A control method for controlling the pixel driving circuit according to any one of claims 1 to 7, characterized in that: The method comprises: In the frame holding state, a first bias electrical signal is input to the data signal line.

10. The control method according to claim 9, characterized in that: The method further comprises: In the frame holding state, the first bias electrical signal is input to the data signal line and the second bias electrical signal is input to the first initial signal line in a time sequence.

11. A control method for controlling the pixel driving circuit according to any one of claims 1 to 7, characterized in that: The method comprises: In the frame holding state, a first bias electrical signal is input to the first initial signal line.

12. The control method according to claim 11, characterized in that: The method further comprises: In the frame holding state, the first bias electrical signal is input to the first initial signal line and the second bias electrical signal is input to the data signal line in a time sequence.

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