Dram memory cell circuit and dram memory

Abstract

This application provides a DRAM memory cell circuit and a DRAM memory. By setting up a read control component and a storage component, the storage component includes a first transistor whose gate is used to store data. The stored data is input via a write bit line. By using a design method that does not utilize independent capacitors to store data, it has a higher integration density compared to traditional memory circuit cells, greatly saving the area consumption caused by independent capacitors in traditional technologies. The drain of the first transistor is electrically connected to the read control component. When the DRAM memory cell reads data, the setting of the read control component isolates the potential difference caused by the level change of the read-in bit line, avoiding the generation of a potential difference at the gate of the first transistor and preventing the loss of data stored in the gate due to the potential difference. Compared with traditional memory cell designs, it provides a better charge isolation effect.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a DRAM memory cell circuit and a DRAM memory. Background Technology

[0002] Traditional DRAM (Dynamic Random Access Memory) cells consist of a transistor and a capacitor. However, as integration density increases, the capacitor, based on the physical characteristics of passive devices, continuously reduces its charge storage capacity as its structure shrinks, leading to excessive leakage. DRAM is about to reach the limit of its refresh rate.

[0003] Existing memory cells include structures based on dual transistors or three transistors plus capacitors. Dual transistor memory cells cannot provide good charge isolation during the data reading phase, while three transistor memory cells with capacitors have insufficient integration density. Therefore, there is an urgent need for a memory cell that can solve the above problems. Summary of the Invention

[0004] To at least address the aforementioned problems, a first aspect of the present invention provides a DRAM memory cell circuit, the DRAM memory cell circuit comprising:

[0005] A read control component is electrically connected to the read bit line, and the read bit line and write bit line are not shared.

[0006] A storage component, the storage component including a first transistor, the gate of the first transistor being used to store data;

[0007] The drain of the first transistor is electrically connected to the read control component, and the source of the first transistor is grounded.

[0008] Optionally, the DRAM memory cell circuit further includes: a write control component, which is electrically connected to the gate of the first transistor, electrically connected to the write bit line, electrically connected to the write word line, and electrically connected to the read control component.

[0009] Optionally, the read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line.

[0010] Optionally, the write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

[0011] Optionally, the read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line.

[0012] The write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

[0013] Optionally, during the data reading phase, the write word line of the DRAM memory cell circuit is in a low-level state, the read word line is in a high-level state, the read control component electrically connected to the read word line is in a conducting state, the write control component electrically connected to the write word line is in a cut-off state, and the memory component is in a reading state.

[0014] Optionally, during the data writing phase, the write word line of the DRAM memory cell circuit is in a high-level state, the read word line is in a low-level state, the write control component electrically connected to the write word line is in a conducting state, the read control component electrically connected to the read word line is in a cut-off state, and the memory component is in a writing state.

[0015] Optionally, during the preparation phase of the DRAM memory cell circuit, the write word line is in a low-level state and the read word line is in a low-level state.

[0016] Optionally, the transistors described above include indium gallium zinc oxide transistors.

[0017] A second aspect of the present invention provides a DRAM memory, comprising:

[0018] As described in the first aspect, the DRAM memory cell circuit.

[0019] The DRAM memory cell circuit and DRAM memory provided in this application embodiment include: a read control component electrically connected to a read bit line, wherein the read bit line and the write bit line are not shared; a storage component including a first transistor, wherein the gate of the first transistor is used to store data; the drain of the first transistor is electrically connected to the read control component, and the source of the first transistor is grounded. By setting the read control component and the storage component, the storage component including the first transistor, wherein the gate of the first transistor is used to store data, and the stored data is input by the write bit line, the design method of storing data without using independent capacitors has a higher integration density than traditional memory circuit cells, greatly saving the area consumption caused by independent capacitors in traditional technology. The drain of the first transistor is electrically connected to the read control component. When the DRAM memory cell reads data, the setting of the read control component isolates the potential difference caused by the level change of the read storage bit line, avoiding the generation of a potential difference at the gate of the first transistor, and preventing the loss of data stored in the gate due to the potential difference. Compared with traditional memory cell designs, it provides a better charge isolation effect. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 A schematic structural block diagram of a DRAM memory cell circuit provided for an embodiment of this application;

[0022] Figure 2 A schematic block diagram of another DRAM memory cell circuit provided in an embodiment of this application;

[0023] Figure 3 A schematic block diagram of another DRAM memory cell circuit provided in an embodiment of this application;

[0024] Figure 4 A schematic block diagram of another DRAM memory cell circuit provided in an embodiment of this application;

[0025] Figure 5 A schematic block diagram of another DRAM memory cell circuit provided for embodiments of this application. Detailed Implementation

[0026] This application provides a DRAM memory cell circuit and a DRAM memory, which solves the problems of insufficient integration density and poor charge isolation effect of traditional memory cells in the prior art.

[0027] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0029] According to a first aspect of the embodiments of this application, a DRAM memory cell circuit is provided. Figure 1 A schematic structural block diagram of a DRAM memory cell circuit provided in an embodiment of this application, such as... Figure 1 As shown, the DRAM memory cell circuit includes a read control component 100, which is electrically connected to the read bit line 200; a memory component 300, which includes a first transistor 310, the gate 311 of which is used to store data; the drain of the first transistor 310 is electrically connected to the read control component, and the source of the first transistor 310 is grounded.

[0030] In the aforementioned DRAM memory cell circuit, the memory component 300 includes the aforementioned first transistor 310. The gate capacitor inside the gate 311 of the first transistor 310 is used to store data. By eliminating the independent capacitor setting of the traditional memory cell circuit, the integration density of the memory cell is improved. The aforementioned read control component 100 is used to connect the circuit of the memory component 300 and the read bit line 200 when the aforementioned DRAM memory cell is reading data. Furthermore, by setting the aforementioned read control component 100, the voltage difference caused by the level change of the read bit line 200 is stabilized, avoiding the potential difference change between the plates of the gate capacitor inside the gate 311 of the first transistor 310 caused by the voltage difference, which would lead to leakage of the stored data inside the gate capacitor, thereby providing a better charge isolation effect.

[0031] In some examples, the DRAM memory cell circuit described above further includes: a write control component electrically connected to the gate of the first transistor, the write control component electrically connected to the write bit line, the write control component electrically connected to the write word line, and the read control component electrically connected to the read word line.

[0032] Figure 2 Another schematic block diagram of a DRAM memory cell circuit provided in the embodiments of this application, such as Figure 2 As shown, the write control component 400 is electrically connected to the gate 311 of the first transistor 310, the write control component 400 is electrically connected to the write bit line 500, the read control component is electrically connected to the read word line 600, and the write control component is electrically connected to the write word line 700.

[0033] It can be explained that in the above-mentioned DRAM memory cell circuit, the above-mentioned write control component 400 is used to connect the circuit of the above-mentioned memory component 300 and the above-mentioned write bit line 500 when data is written to the above-mentioned DRAM memory cell. The data to be stored flows into the above-mentioned memory component 300 through the above-mentioned write bit line 500. By using separate bit lines for writing data and reading data in the above-mentioned DRAM memory cell, the applicability of the embodiments of this application is improved.

[0034] It can be further explained that, through the configuration of the aforementioned read control component 100, the voltage difference caused by the level change of the aforementioned read input line 200 is stabilized, preventing the potential difference change between the plates of the gate capacitor inside the gate 311 of the aforementioned first transistor 310 due to the aforementioned voltage difference, thus avoiding leakage of the stored data inside the gate capacitor and providing a better charge isolation effect. Through the configuration of the aforementioned write control component 400, the write state of the gate capacitor inside the gate 311 of the aforementioned first transistor 310 can be controlled to be turned on or off.

[0035] In some examples, the read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line.

[0036] Figure 3 Another schematic block diagram of a DRAM memory cell circuit provided in the embodiments of this application, such as Figure 3 As shown, the read control component 100 includes a second transistor 110, the drain of the second transistor 110 is electrically connected to the read bit line 200, the source of the second transistor 110 is electrically connected to the drain of the first transistor 310, and the gate of the second transistor 110 is electrically connected to the read word line 600.

[0037] It can be explained that in the above-mentioned DRAM memory cell circuit, the second transistor 110 is used to control the on / off state of the circuit between the drain of the first transistor 310 and the read bit line 200. With the setting of the second transistor 110, when the DRAM memory cell reads data, it plays a voltage stabilizing role for the voltage difference caused by the level change of the read bit line 200, avoiding the potential difference change between the gate capacitor plates inside the gate 311 of the first transistor 310 caused by the voltage difference, which would lead to leakage of the stored data inside the gate capacitor, and providing a better charge isolation effect.

[0038] In some examples, the write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

[0039] Figure 4 A schematic block diagram of another DRAM memory cell circuit provided in the embodiments of this application, such as Figure 4 As shown, the write control component 400 includes a third transistor 410, the drain of the third transistor 410 is electrically connected to the write bit line 500, the source of the third transistor 410 is electrically connected to the gate 311 of the first transistor 310, and the gate of the third transistor 410 is electrically connected to the write word line 700.

[0040] It can be explained that in the above-mentioned DRAM memory cell circuit, the third transistor 410 is used to control the on / off state of the circuit of the gate 311 of the first transistor 310 and the write bit line 500.

[0041] In some examples, the read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line.

[0042] The write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

[0043] Figure 5 Another schematic block diagram of a DRAM memory cell circuit provided for embodiments of this application, such as... Figure 5 As shown, the read control component 100 includes a second transistor 110, the drain of the second transistor 110 is electrically connected to the read bit line 200, the source of the second transistor 110 is electrically connected to the drain of the first transistor 310, and the gate of the second transistor 110 is electrically connected to the read word line 600.

[0044] The write control component 400 includes a third transistor 410, the drain of which is electrically connected to the write bit line 500, the source of which is electrically connected to the gate 311 of the first transistor 310, and the gate of which is electrically connected to the write word line 700.

[0045] It can be explained that the read word line 600 is used to control the conduction state of the second transistor 110, the write word line 700 is used to control the conduction state of the third transistor 410, and the gate capacitor inside the gate 311 of the first transistor 310 is used to store data. By eliminating the setting of independent capacitors in traditional memory cell circuits, the integration density of memory cells is improved. The second transistor 110 is used to connect the circuit of the third transistor 410 and the read bit line 200 when the DRAM memory cell is reading data. Furthermore, the setting of the second transistor 110 plays a voltage stabilizing role for the voltage difference caused by the level change of the read bit line 200, avoiding the potential difference change between the plates of the gate capacitor inside the gate 311 of the first transistor 310 caused by the voltage difference, which would lead to leakage of the stored data inside the gate capacitor, thereby providing a better charge isolation effect.

[0046] In some examples, during the data reading phase of the DRAM memory cell circuit described above, the write word line is in a low-level state, the read word line is in a high-level state, the read control component electrically connected to the read word line is in a conducting state, the write control component electrically connected to the write word line is in a cut-off state, and the memory component is in a reading state.

[0047] It can be explained that, for example Figure 2 As shown, during the data reading phase, the read control component 100 is in the ON state, the write control component 400 is in the OFF state, and the data stored in the gate capacitor of the gate 311 of the first transistor 310 flows into the read bit line 200. During the data reading phase of the memory cell, the read control component 100 stabilizes the voltage difference caused by changes in the level of the read bit line 200, preventing potential difference changes between the gate capacitor plates inside the gate 311 of the first transistor 310 due to the voltage difference, thus avoiding leakage of the stored data inside the gate capacitor and providing better charge isolation.

[0048] In some examples, during the data writing phase of the DRAM memory cell circuit, the write word line is at a high level, the read word line is at a low level, the write control component electrically connected to the write word line is in an on state, the read control component electrically connected to the read word line is in an off state, and the memory component is in a writing state.

[0049] It can be explained that, for example Figure 2 As shown, during the data writing stage, the read control component 100 is in the off state, the write control component 400 is in the channel state, and the data to be stored on the write bit line 200 flows into the gate capacitance within the gate 311 of the third transistor 310. This embodiment utilizes the gate capacitance within the transistor's gate to store data, achieving higher integration density compared to traditional storage circuit units and significantly reducing the area consumption caused by independent capacitors in conventional technologies.

[0050] In some examples, during the preparation phase of the DRAM memory cell circuit described above, the write word line is at a low level and the read word line is at a low level.

[0051] It can be explained that, for example Figure 2 As shown, when the DRAM memory cell circuit is in the preparation stage, both the write word line 700 and the read word line 600 are in a low-level state, which can directly control the transistors connected to the word lines without resetting the level, thus improving the efficiency of the next data read and write operation.

[0052] In some examples, the transistors described above include indium gallium zinc oxide transistors.

[0053] It can be noted that the channels of the aforementioned transistors can all be made of IGZO (Indium Gallium Zinc Oxide). The embodiments of this application utilize the wide bandgap characteristic of IGZO, thereby achieving a lower charge leakage rate and extremely low leakage current when the IGZO-based transistor is in the off state, greatly improving charge retention characteristics, reducing refresh frequency, and thus achieving low power consumption. Furthermore, based on the low-temperature processing characteristics of IGZO material, the processing temperature is low, so the IGZO-based transistor is compatible with downstream processes, can meet the basic requirements of monolithic 3D integration, and can be expanded in the vertical direction, thereby increasing memory integration density.

[0054] A second aspect of this application provides a DRAM memory, comprising:

[0055] As described in the first aspect, the DRAM memory cell circuit.

[0056] The DRAM memory based on the above-mentioned DRAM memory cell circuit can provide better charge isolation during data reading, has higher integration density, and does not require frequent refresh to maintain the memory state, thereby reducing power consumption.

[0057] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0058] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A DRAM memory cell circuit, characterized in that, include: A read control component is electrically connected to the read bit line, which is not shared with the write bit line. The read control component is used to stabilize the voltage difference caused by the level change of the read bit line. A storage component, the storage component including a first transistor, the gate of the first transistor being used to store data; The drain of the first transistor is electrically connected to the read control component, and the source of the first transistor is grounded; The DRAM memory cell circuit further includes a write control component, which is electrically connected to the gate of the first transistor, the write control component is electrically connected to the write bit line, the write control component is electrically connected to the write word line, and the read control component is electrically connected to the read word line; the write control component is used to control the write state of the gate capacitance inside the gate of the first transistor to be turned on or off. During the preparation phase, the write word line and the read word line of the DRAM memory cell circuit are both in a low-level state. During the data reading phase, the write control component is in a cutoff state, and during the data writing phase, the read control component is in a cutoff state. The transistors included in the first transistor, the read control component, and the write control component are indium gallium zinc oxide transistors.

2. The DRAM memory cell circuit according to claim 1, characterized in that, Also includes: A write control component is electrically connected to the gate of the first transistor, the write control component is electrically connected to the write bit line, the write control component is electrically connected to the write word line, and the read control component is electrically connected to the read word line.

3. The DRAM memory cell circuit according to claim 2, characterized in that, The read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line.

4. The DRAM memory cell circuit according to claim 2, characterized in that, The write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

5. The DRAM memory cell circuit according to claim 2, characterized in that, The read control component includes a second transistor, the drain of which is electrically connected to the read bit line, the source of which is electrically connected to the drain of the first transistor, and the gate of which is electrically connected to the read word line. The write control component includes a third transistor, the drain of which is electrically connected to the write bit line, the source of which is electrically connected to the gate of the first transistor, and the gate of which is electrically connected to the write word line.

6. The DRAM memory cell circuit according to any one of claims 2 to 5, characterized in that, During the data reading phase, the write word line of the DRAM memory cell circuit is in a low-level state, the read word line is in a high-level state, the read control component electrically connected to the read word line is in a conducting state, the write control component electrically connected to the write word line is in a cut-off state, and the memory component is in a reading state.

7. The DRAM memory cell circuit according to any one of claims 2 to 5, characterized in that, During the data writing phase, the write word line of the DRAM memory cell circuit is in a high-level state, the read word line is in a low-level state, the write control component electrically connected to the write word line is in a conducting state, and the read control component electrically connected to the read word line is in a cut-off state, thus the memory cell is in a writing state.

8. A DRAM memory, characterized in that, include: The DRAM memory cell circuit as described in any one of claims 1 to 7.

Images