Method of forming a semiconductor structure

Abstract

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A semiconductor substrate is received, wherein the semiconductor substrate includes a gate dielectric layer and a gate layer on the gate dielectric layer. A first etching operation is performed to pattern the gate layer and expose a top surface of the gate dielectric layer. A second etching operation is performed to first variable pressure coupled plasma to etch a sidewall of the gate layer, wherein the first variable pressure coupled plasma has a first power. A third etching operation is performed to second variable pressure coupled plasma to etch the sidewall of the gate layer, wherein the second variable pressure coupled plasma has a second power, and the first power is less than the second power. By adjusting parameters on the plasma etching equipment to modify the gate profile of the gate layer, the method can avoid the gate profile of necking or bottom corner while obtaining the gate profile substantially perpendicular to the gate dielectric layer, thereby greatly reducing the critical dimension difference of the MOSFET.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of forming a semiconductor structure, and more particularly to an etching process technique. BACKGROUND

[0002] With the continuous progress of the semiconductor integrated circuit (IC) industry, manufacturers need to optimize and improve the process to produce smaller and better performing products. Metal oxide semiconductor field effect transistors (MOSFETs) have been widely used in various electronic products. In the production of metal oxide semiconductor field effect transistors, photolithography and etching processes will affect the critical dimension (CD) of the final product. However, in the etching process, the characteristics of the semiconductor material will cause the problem of critical dimension difference.

[0003] In view of the above, there is an urgent need to develop a new etching process technique to overcome the aforementioned problems. SUMMARY

[0004] The present disclosure provides a method of forming a semiconductor structure, comprising the following operations. A semiconductor substrate is received, wherein the semiconductor substrate comprises a gate dielectric layer and a gate layer on the gate dielectric layer. A first etching operation is performed to pattern the gate layer and expose a top surface of the gate dielectric layer. A second etching operation is performed to etch the sidewall of the gate layer with a first variable pressure coupled plasma, wherein the first variable pressure coupled plasma has a first power. A third etching operation is performed to etch the sidewall of the gate layer with a second variable pressure coupled plasma, wherein the second variable pressure coupled plasma has a second power, and the first power is less than the second power.

[0005] In some embodiments, the second etching operation is performed at a first bias, the first bias having a first bias power. The third etching operation is performed at a second bias, the second bias having a second bias power, wherein the first bias power is greater than the second bias power.

[0006] In some embodiments, the second etching operation is performed at a first pressure. The third etching operation is performed at a second pressure, wherein the first pressure is less than the second pressure.

[0007] In some embodiments, the etching time of the second etching operation is less than the etching time of the third etching operation.

[0008] In some embodiments, the etching gas of the second etching operation is the same as the etching gas of the third etching operation.

[0009] In some embodiments, after performing the third etching operation, the sidewall of the gate layer is substantially perpendicular to the top surface of the gate dielectric layer.

[0010] In some embodiments, after performing the third etching operation, the bottom width of the gate layer is substantially equal to the top width of the gate layer.

[0011] In some embodiments, after performing the first etching operation, the bottom width of the gate layer is substantially greater than the top width of the gate layer.

[0012] In some embodiments, after performing the second etching operation, the bottom width of the gate layer is substantially greater than the top width of the gate layer.

[0013] In some embodiments, the gate layer is a polysilicon layer, and after performing the first etching operation, the polysilicon layer is divided into an N-type doped region and a P-type doped region.

[0014] The above description will be further explained in detail by embodiments, and the technical solutions of the present disclosure will be further explained. BRIEF DESCRIPTION OF DRAWINGS

[0015] The detailed description of the present disclosure will be fully understood when read in conjunction with the accompanying drawings. It should be noted that each feature is not drawn to scale according to industry standard practice and is only for illustrative purposes. In fact, the size of each feature can be arbitrarily increased or decreased for the purpose of clear discussion.

[0016] Figure 1 A schematic view of a plasma etching apparatus according to some embodiments of the present disclosure.

[0017] Figure 2 A flowchart of a method of forming a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figures 3 to 10 Cross-sectional schematic views of a semiconductor structure at various stages of a process according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the description of the present disclosure more detailed and complete, reference can be made to the accompanying drawings and various embodiments described below, in which the same numbers represent the same or similar elements.

[0020] Numerous specific details are described in the following description in order to provide a thorough understanding. However, it will be understood by those of ordinary skill in the art that the embodiments described herein are not limited to the particularly- described details and forms unless specified otherwise. In other words, unless otherwise specified, the embodiments herein are not limited to the specifically- described details and forms. Rather, it is contemplated that the embodiments herein can be practiced with variations that are apparent to those of ordinary skill in the art. For example, it is expected that one of ordinary skill, despite possibly having a different preferred embodiment, can, using routine, routine experimentation or modifications herein, make a product or carry out a process that is different from the disclosed embodiments, yet has essentially the same function. The scope of the embodiments herein is, therefore, indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalents are intended to be embraced therein.

[0021] Although the following describes the method of the present invention using a series of operations or steps, the order in which the operations or steps are shown should not be construed as a limitation of the present invention. For example, certain operations or steps can be performed in a different order and / or concurrently with other steps. Furthermore, not all of the illustrated operations, steps and / or features need to be performed in order to achieve embodiments of the present invention. In addition, each operation or step recited herein can include a number of sub-steps or actions.

[0022] In this document, the terms "a range of values" and "from one value to another value" are used as shorthand notations for a range of values ending with the recited value. Accordingly, a stated range of values includes any value and subset thereof, just as if each number within the range is explicitly recited.

[0023] As used herein, "about," "approximately," "substantially," or "essentially" include the stated value and the average value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art, taking into account the particular quantity being measured and the particular quantity of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Further, as used herein, "about," "approximately," "substantially," or "essentially" can select an acceptable range of deviation or standard deviation depending on the measurement property, coating property, or other property, and can not apply one standard deviation to all properties.

[0024] Generally, a metal oxide semiconductor field effect transistor (MOSFET) includes a gate layer, a gate dielectric layer, a source / drain region, and a channel region. In forming a MOSFET, various techniques such as deposition, photolithography, and etching are used to form the various layers and / or regions on a semiconductor substrate. In forming the gate layer, N-type dopants (e.g., phosphorus) or P-type dopants (e.g., boron) are doped according to the actual needs to form an N-type field effect transistor (NFET) or a P-type field effect transistor (PFET).

[0025] The etching process has different etching selectivity and etching rate due to the material properties. For example, the etching rate of a gate layer doped with N-type dopants is greater than the etching rate of a gate layer doped with P-type dopants. This different etching rate causes the resulting gate layer after etching to have an undesirable "necking" or "footing" gate profile. The necking or footing profile further affects the critical dimension (CD) variation of the product.

[0026] The present disclosure provides a method of forming a semiconductor structure, which can avoid the necking or footing phenomenon of the resulting gate profile of the etching process, and thus can greatly reduce the critical dimension variation of the MOSFET. In addition, the resulting gate sidewall of the semiconductor structure of the present disclosure is substantially perpendicular to the upper surface of the gate dielectric layer.

[0027] Please refer to Figure 1 , Figure 1 A schematic diagram of a plasma etching apparatus 100 according to some embodiments of the present disclosure is shown. The plasma etching apparatus 100 includes a controller 110, a chamber 120, a radio frequency (RF) generator 130, a gas distribution system 140, a vacuum pumping system 150, a radio frequency (RF) generator 160, a support device 170, and a semiconductor structure 180. The controller 110 is electrically connected to the RF generator 130, the gas distribution system 140, the vacuum pumping system 150, and the RF generator 160, and the controller 110 can control the devices electrically connected thereto.

[0028] The chamber 120 is a chamber for etching the semiconductor structure 180. When the RF generator 130 is turned on, a transfer coupled plasma (TCP) 122 is generated in the chamber 120. In detail, the RF generator 130 can generate RF power and couple the RF power to the induction coil 134 via the impedance matcher 132, so as to ionize the etching gas in the gas distribution system 140 and generate the TCP 122 in the chamber 120. In other words, the TCP 122 can be generated by turning on the RF power of the RF generator 130. Therefore, the RF power for generating the TCP 122 can also be referred to as TCP RF power. The TCP RF power can be adjusted according to actual etching requirements. In some embodiments, the RF generator 130 can generate RF power of about 100 W to about 500 W, for example, 125 W, 150 W, 175 W, 200 W, 225 W, 250 W, 275 W, 300 W, 325 W, 350 W, 375 W, 400 W, 425 W, 450 W, or 475 W. The higher the TCP RF power, the higher the concentration of the TCP 122 in the chamber 120. It should be understood that Figure 1 The induction coil 134 is shown to be located above the gas distribution system 140, however, other locations of the induction coil 134 are also included in the present disclosure.

[0029] The gas distribution system 140 can introduce target gas, such as ionized gas (e.g., the TCP 122) of etching gas (e.g., CF4, SF6, Cl2, or HBr) into the chamber 120. The gas distribution system 140 can control the distribution of the target gas so that the target gas is uniformly dispersed in the chamber 120. The gas flow of the target gas of the gas distribution system 140 can be adjusted according to actual etching requirements.

[0030] The vacuum pumping system 150 can be used to adjust the pressure in the chamber 120, and the pressure in the chamber 120 can be adjusted according to actual etching requirements. In some embodiments, the pressure in the chamber 120 is adjusted to be about 1 mTorr to about 70 mTorr, for example, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65 mTorr.

[0031] RF generator 160 generates RF power and, via impedance matching 162 and a transmitter (not shown), generates an RF voltage that biases the support device 170 under the RF voltage through electrode 172. In other words, the bias voltage of the support device 170 can be generated by turning on the RF power of RF generator 160. Therefore, the RF voltage used to generate the RF voltage can also be referred to as bias RF power. The bias RF power can be adjusted according to the actual etching requirements. In some embodiments, RF generator 160 can generate RF power from about 100W to about 350W, for example, 125W, 150W, 175W, 200W, 225W, 250W, 275W, 300W, or 325W. The higher the bias RF power, the stronger the ability of the transformer-coupled plasma 122 within chamber 120 to bombard the semiconductor structure 180.

[0032] like Figure 1 As shown, a support device 170 and a semiconductor structure 180 are disposed in a chamber 120. The semiconductor structure 180 is disposed on the support device 170 for etching operations. Specifically, when the etching target (e.g., the semiconductor structure 180) is disposed on the support device 170, the operator sets parameters on the plasma etching apparatus 100 (including TCP RF power, bias RF power, etching gas, operating pressure, and etching time, etc.) to perform the etching operation. In some embodiments, the support device 170 may include a heating device (not shown) and / or a cooling device (not shown).

[0033] Please refer to Figures 2 to 10 . Figure 2 This is a flowchart illustrating a method 200 for forming a semiconductor structure 180 according to some embodiments of the present invention. Method 200 includes operations 210 to 240. Figures 3 to 10 This is a cross-sectional schematic diagram of a semiconductor structure 180 at various stages of the manufacturing process, illustrating some embodiments of the present invention.

[0034] Please refer to Figure 3The semiconductor structure 180 includes a semiconductor substrate 310 and various layers disposed on the semiconductor substrate 310, such as a gate dielectric layer 320, a gate layer 330, and a masking layer 340. The various layers on the semiconductor substrate 310 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or spin coating, other suitable deposition processes, or any combination of the foregoing.

[0035] The semiconductor substrate 310 can be or include, for example, a bulk monocrystalline silicon substrate, a silicon on insulator (SOI) substrate, or some other suitable semiconductor substrate.

[0036] The gate dielectric layer 320 is disposed on the semiconductor substrate 310. The gate dielectric layer 320 can be formed of one or more suitable gate dielectric layer materials, such as silicon oxide, silicon nitride, or other low dielectric constant materials. The gate dielectric layer 320 can be formed by thermal oxidation, CVD, PVD, PECVD, ALD, PEALD, or spin coating, other suitable deposition processes. In some embodiments, the gate dielectric layer 320 has a thickness of about 2 nm to about 5 nm, such as 3 or 4 nm.

[0037] The gate layer 330 is disposed on the gate dielectric layer 320. The gate layer 330 includes a first gate layer 332, a second gate layer 334, and a third gate layer 336, where the second gate layer 334 is disposed on the first gate layer 332, and the third gate layer 336 is disposed on the second gate layer 334. In some embodiments, the first gate layer 332 is a polysilicon layer. The first gate layer 332 includes an N-type doped region doped with N-type dopants and / or a P-type doped region doped with P-type dopants. The N-type dopants can be, for example, a Group V element such as arsenic or phosphorus. The P-type dopants can be, for example, a Group III element such as boron or gallium. It will be appreciated that, Figure 3The first gate layer 332 is shown as a single layer of polysilicon, however, N-type and / or P-type dopants can be doped into the first gate layer 332 as desired. For example, the left first gate layer 332 is doped with N-type dopants, while the right first gate layer 332 is doped with P-type dopants. In some embodiments, the second gate layer 334 is a titanium nitride layer. In some embodiments, the third gate layer 336 is a metal layer. The third gate layer 336 can include tungsten, titanium, tantalum, or a combination thereof. The first gate layer 332, the second gate layer 334, and the third gate layer 336 can be formed by CVD, PVD, PECVD, ALD, PEALD, spin coating, or other suitable deposition processes.

[0038] A mask layer 340 is disposed on the gate layer 330. The mask layer 340 includes a first mask layer 342 and a second mask layer 344, where the second mask layer 344 is disposed on the first mask layer 342. In some embodiments, the first mask layer 342 is a nitride layer. In some embodiments, the second mask layer 344 is an oxide layer. The first mask layer 342 and the second mask layer 344 can be formed by CVD, PVD, PECVD, ALD, PEALD, or spin coating, or other suitable deposition processes.

[0039] Referring to Figure 4 The mask layer 340 of the semiconductor structure 180 is patterned to form a patterned mask layer 340a. The patterned mask layer 340a can be formed by a photolithography and etching process. For example, a layer of photoresist is coated on the mask layer 340 and a mask having a pattern is disposed on the photoresist. After exposure and development, the pattern of the mask is transferred to the photoresist, and then the patterned photoresist is used as an etching mask to etch the mask layer 340, thereby forming the patterned mask layer 340a. In some embodiments, the width of the left patterned mask layer 340a is substantially equal to the width of the right patterned mask layer 340a.

[0040] Referring to Figure 5 The third gate layer 336 of the semiconductor structure 180 is patterned to form a patterned third gate layer 336a using the patterned mask layer 340a as an etching mask. Then referring to Figure 6 The second gate layer 334 of the semiconductor structure 180 is also patterned to form a patterned second gate layer 334a using the patterned mask layer 340a as an etching mask.

[0041] Referring to Figure 2 and Figures 7 to 9The first gate layer 332 is etched (i.e., patterned). Etching the first gate layer 332 includes a first etching operation 700, a second etching operation 800, and a third etching operation 900. The first etching operation 700 can also be called main etching (ME) or soft landing (SL). The second etching operation 800 can also be called soft landing-over etching (SLOE). The third etching operation 900 can also be called over etching (OE). Please refer to the following description for a detailed description of each etching operation.

[0042] Please refer to the following at the same time Figure 2 and Figure 7 In operation 220, a first etching operation 700 is performed to pattern the first gate layer 332 and expose the top surface S of the gate dielectric layer 320. Specifically, the semiconductor structure 180 is disposed in the chamber 120 of the plasma etching apparatus 100 and mounted on a support device 170. Parameters on the plasma etching apparatus 100 are set to perform the first etching operation 700. More specifically, the first etching operation 700 etches the first gate layer 332, dividing it into an N-type doped region NR (i.e., the first gate layer n-332a) and a P-type doped region PR (i.e., the first gate layer p-332a). It should be noted that the doping of the first gate layer 332 occurs during the formation of... Figure 3 The semiconductor structure was already doped at 180°, therefore, after performing the first etching operation 700°, a structure like this will be formed. Figure 7 The N-type doped region NR is on the left, and the P-type doped region PR is on the right. It is worth noting that because the etching rate of the first gate layer n-332a in the N-type doped region NR is greater than the etching rate of the first gate layer p-332a in the P-type doped region PR, more material remains in the first gate layer p-332a than in the first gate layer n-332a. Furthermore, since the terminal signal is detected simultaneously during the first etching operation 700, the gate dielectric layer 320 can be used as an etching stop layer. In some embodiments, the vertical etching rate of the first etching operation 700 is greater than the lateral etching rate. In some embodiments, the first etching operation 700 substantially does not etch the gate dielectric layer 320.

[0043] In some embodiments, the TCP RF power of the first etching operation 700 is about 350 W to about 400 W, for example, 355 W, 360 W, 365 W, 370 W, 375 W, 380 W, 385 W, 390 W, or 395 W. In some embodiments, the bias RF power of the first etching operation 700 is about 150 W to about 200, for example, 155 W, 160 W, 165 W, 170 W, 175 W, 180 W, 185 W, 190 W, or 195 W. In some embodiments, the etching gas of the first etching operation 700 comprises Cl2and HBr. In some embodiments, the operation pressure of the first etching operation 700 is about 2 mTorr to about 10 mTorr, for example, 3, 4, 5, 6, 7, 8, 9 mTorr.

[0044] Please continue to refer to Figure 7 After performing the first etching operation 700, a structure as shown in FIG. 7B is formed. Figure 7 The N-type doped region NR on the left side and the P-type doped region PR on the right side. The first gate layer n-332a of the N-type doped region NR has a gate profile gradually widening from top to bottom, the first gate layer n-332a has a top width W N1 and a bottom width W N2 , the bottom width W N2 is greater than the top width W N1 . The first gate layer p-332a of the P-type doped region PR has a width gradually widening from top to bottom, the first gate layer p-332a has a top width W P1 and a bottom width W P2 , the bottom width W P2 is greater than the top width W P1 . In detail, in the case that the width of the mask layer 340a on the left side is substantially equal to the width of the mask layer 340a on the right side, since the first etching operation 700 uses the mask layer 340a as an etching mask, the top width W N1 of the first gate layer n-332a is substantially equal to the top width W P1 of the first gate layer p-332a. It should be noted that since the dopants in the first gate layers 332 have different material properties, the etching rate of the first gate layer n-332a is greater than the etching rate of the first gate layer p-332a, thus the bottom width W N2 of the first gate layer n-332a is substantially smaller than the bottom width W P2 of the first gate layer p-332a.

[0045] Please continue to refer to Figure 1 , Figure 2 and Figure 8In operation 230, a second etching operation 800 is performed to etch the sidewalls n-SW of the first gate layer n-332a and to etch the sidewalls p-SW of the first gate layer p-332a with the first variable pressure coupled plasma 122A. In some embodiments, the second etching operation 800 has a lateral etch rate much greater than a vertical etch rate. In some embodiments, the second etching operation 800 uses HBr as the etching gas, and because HBr has a high selectivity ratio to the first gate layers p-332a, n-332a and the gate dielectric layer 320, the second etching operation 800 does not substantially etch the gate dielectric layer 320. In some embodiments, the etching gas used in the second etching operation 800 is different from the etching gas used in the second etching operation 700.

[0046] In some embodiments, the TCP RF power of the second etching operation 800 is about 150 W to about 200 W, such as 160 W, 165 W, 170 W, 175 W, 180 W, 185 W, 195 W. In some embodiments, the bias RF power of the second etching operation 800 is about 250 W to about 300 W, such as 255 W, 260 W, 265 W, 270 W, 275 W, 280 W, 285 W, 290 W, 295 W. It should be noted that the higher the bias RF power, Figure 1 the stronger the bombardment capability of the variable pressure coupled plasma 122 in the chamber 120 to the semiconductor structure 180. In some embodiments, the etching gas of the second etching operation 800 includes HBr. In some embodiments, the operation pressure of the second etching operation 800 is about 10 mTorr to about 75 mTorr, such as about 20 mTorr to about 70 mTorr or about 30 mTorr to about 65 mTorr. In some embodiments, the etching time of the second etching operation 800 is about 5 seconds to about 10 seconds, such as 6, 7, 8, or 9 seconds.

[0047] Please continue to refer to Figure 7 and Figure 8 After the second etching operation 800 is performed, the bottom width W N3 of the first gate layer n-332b is less than the bottom width W N2 of the first gate layer n-332a. P3 The bottom width W P2 of the first gate layer p-332b is less than the bottom width W N3 of the first gate layer p-332a. P3 .

[0048] Please continue to refer to Figure 1 , Figure 2and Figure 9 In operation 240, a third etching operation 900 is performed to etch the sidewalls n-SW of the first gate layer n-332b and to etch the sidewalls p-SW of the first gate layer p-332b with the second variable pressure coupled plasma 122B. In some embodiments, the first variable pressure coupled plasma 122A of the second etching operation 800 has a first power, and the second variable pressure coupled plasma 122B of the third etching operation 900 has a second power, where the first power is less than the second power. In some embodiments, the third etching operation 900 has a lateral etch rate that is much greater than a vertical etch rate, as compared to the first etching operation 700. In some embodiments, the third etching operation 900 uses HBr as the etching gas, and because HBr has a high selectivity ratio to the first gate layer p-332b, n-332b, and the gate dielectric layer 320, the third etching operation 900 does not substantially etch the gate dielectric layer 320. It is noted that the difference between the first variable pressure coupled plasma 122A and the second variable pressure coupled plasma 122B is the concentration of the variable pressure coupled plasma. The higher the TCP RF power, the higher the concentration of the variable pressure coupled plasma 122 in the chamber 120.

[0049] In some embodiments, the TCP RF power of the third etching operation 900 is about 350 W to about 400 W, such as 355 W, 360 W, 365 W, 370 W, 375 W, 380 W, 385 W, 390 W, or 395 W. In some embodiments, the bias RF power of the third etching operation 900 is about 150 W to about 200 W, such as 155 W, 160 W, 165 W, 170 W, 175 W, 180 W, 185 W, 190 W, or 195 W. In some embodiments, the etching gas of the third etching operation 900 includes HBr. In some embodiments, the operating pressure of the third etching operation 900 is about 50 mTorr to about 90 mTorr, such as about 55, 60, 65, 70, 75, 80, or 85 mTorr. In some embodiments, the etching time of the third etching operation 900 is about 10 seconds to about 25 seconds, such as 12, 15, 18, 20, 22, or 24 seconds.

[0050] In some embodiments, the second etching operation 800 is performed under a first bias voltage having a first bias power; the third etching operation 900 is performed under a second bias voltage having a second bias power, wherein the first bias power is greater than the second bias power. In some embodiments, the second etching operation 800 is performed under a first pressure, and the third etching operation 900 is performed under a second pressure, wherein the first pressure is less than the second pressure. In some embodiments, the etching time for performing the second etching operation 800 is less than the etching time for performing the third etching operation 900. In some embodiments, the etching gas used to perform the second etching operation 800 is the same as the etching gas used to perform the third etching operation 900.

[0051] Please continue to refer to Figure 9 After performing the third etch operation 900, the bottom width W of the first gate layer n-332c N4 The bottom width W is smaller than that of the first gate layer n-332b N3 The bottom width W of the first gate layer p-332c P4 The bottom width W of the first gate layer p-332b is smaller than that of the second gate layer. P3 It is worth noting that the third etching operation 900 modifies the gate profiles of the first gate layer n-332b and the first gate layer p-332b laterally by adjusting the parameters on the plasma etching apparatus 100, thereby increasing the bottom width W of the first gate layer n-332c. N4 Essentially equal to the bottom width W of the first gate layer p-332c P4 In some embodiments, the bottom width W of the first gate layer n-332c N4 Essentially equal to the top width W of the first gate layer n-332c N1 In some embodiments, the bottom width W of the first gate layer p-332c P4 Essentially equal to the top width W of the first gate layer p-332c P1 In some embodiments, the sidewall n-SW of the first gate layer n-332c is substantially perpendicular to the top surface S of the gate dielectric layer 320. In some embodiments, the sidewall p-SW of the first gate layer p-332c is substantially perpendicular to the top surface S of the gate dielectric layer 320.

[0052] Please refer to Figure 10 An ion implantation operation is performed to form source / drain regions 1000 in the semiconductor substrate 310. Specifically, the source / drain regions 1000 are formed on both sides of the N-type doped region NR and the P-type doped region PR, thereby forming... Figure 10 The left side shows an N-type field-effect transistor (NFET), and the right side shows a P-type field-effect transistor (PFET). Because... Figure 9The N-type doped region NR and the P-type doped region PR of the formed semiconductor structure 180 have substantially the same width, and thus, the critical dimensions of the N-type field effect transistor and the P-type field effect transistor are similar.

[0053] In summary, the present application provides a method of forming a semiconductor structure by adjusting parameters on a plasma etching apparatus to modify the gate profile of a gate layer, so that necking or bottom corner gate profiles can be avoided, while substantially vertical gate profiles to the gate dielectric layer are obtained, thereby substantially reducing the critical dimension difference of MOSFETs.

[0054] Although the present application has been disclosed in terms of embodiments thereof, it is not intended to limit the present application thereto, and various modifications and alterations are possible without departing from the spirit and scope of the present application, and the scope of protection of the present application is defined by the scope of claims and their equivalents.

[0055] [SYMBOL DESCRIPTION]

[0056] 100: plasma etching apparatus

[0057] 110: controller

[0058] 120: chamber

[0059] 122, 122A, 122B: transformer coupled plasma (TCP)

[0060] 130: radio frequency (RF) generator

[0061] 132: impedance matcher

[0062] 134: induction coil

[0063] 140: gas distribution system

[0064] 150: vacuum pumping system

[0065] 160: radio frequency (RF) generator

[0066] 162: impedance matcher

[0067] 170: support device

[0068] 172: electrode

[0069] 180: semiconductor structure

[0070] 200: method

[0071] 210: operation

[0072] 220: operation

[0073] 230: operation

[0074] 240: operation

[0075] 310: semiconductor substrate

[0076] 320: gate dielectric layer

[0077] 330: gate layer

[0078] 332: first gate layer

[0079] 334, 334a: second gate layer

[0080] 336, 336a: third gate layer

[0081] 340, 340a: mask layer

[0082] 342, 342a: first mask layer

[0083] 344, 344a: second mask layer

[0084] 700: first etch operation

[0085] 800: second etch operation

[0086] 900: third etch operation

[0087] 1000: source / drain region

[0088] n-332a, n-332b, n-332c: first gate layer

[0089] n-SW: sidewall

[0090] p-332a, p-332b, p-332c: first gate layer

[0091] p-SW: sidewall

[0092] NR: N-type doped region

[0093] PR: P-type doped region

[0094] S: top surface

[0095] W N1 : top width

[0096] W N2 ,W N3 ,W N4 : bottom width

[0097] W P1 : top width

[0098] W P2 ,WP3 W P4 : bottom width.

Claims

1. A method of forming a semiconductor structure, comprising: Comprising: receiving a semiconductor substrate, wherein the semiconductor substrate comprises a gate dielectric layer and a gate layer on the gate dielectric layer; performing a first etching operation to pattern the gate layer and expose a top surface of the gate dielectric layer; performing a second etching operation to first variable pressure coupled plasma etch a sidewall of the gate layer under a first bias, wherein the first variable pressure coupled plasma has a first power and the first bias has a first bias power; and performing a third etching operation to second variable pressure coupled plasma etch the sidewall of the gate layer under a second bias, wherein the second variable pressure coupled plasma has a second power, the first power is less than the second power, the second bias has a second bias power, and the first bias power is greater than the second bias power.

2. The method of claim 1, wherein: the second etching operation is performed under a first pressure; and the third etching operation is performed under a second pressure, wherein the first pressure is less than the second pressure.

3. The method of claim 1, wherein an etching time of performing the second etching operation is less than an etching time of performing the third etching operation.

4. The method of claim 1, wherein an etching gas of performing the second etching operation is the same as an etching gas of performing the third etching operation.

5. The method of claim 1, wherein after performing the third etching operation, the sidewall of the gate layer is perpendicular to the top surface of the gate dielectric layer.

6. The method of claim 1, wherein after performing the third etching operation, a bottom width of the gate layer is equal to a top width of the gate layer.

7. The method of claim 1, wherein after performing the first etching operation, a bottom width of the gate layer is greater than a top width of the gate layer.

8. The method of claim 1, wherein after performing the second etching operation, a bottom width of the gate layer is greater than a top width of the gate layer.

9. The method of claim 1, wherein the gate layer is a polysilicon layer, and after performing the first etching operation, the polysilicon layer is separated into an N-type doped region and a P-type doped region.

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