Highly robust anti-static surge substrate-type ESD / TVS diode structure and method

Abstract

The present invention discloses a highly robust anti-static surge substrate-type ESD / TVS diode structure and method. This ESD / TVS diode structure comprises an emitter junction optimization filling slot disposed beneath the surface metal and contacts, in contact with and electrically connected to the semiconductor single crystal substrate. Below the emitter junction optimization filling slot is an emitter junction optimization diffusion disposed within the semiconductor single crystal substrate and in contact with the emitter junction optimization filling slot. A collector junction optimization filling slot extends from the surface of the semiconductor single crystal substrate, and a collector junction optimization diffusion is disposed within the semiconductor single crystal substrate below the collector junction optimization filling slot. A lateral suppression filling slot extends from the surface of the semiconductor single crystal substrate, and a lateral suppression diffusion is disposed within the semiconductor single crystal substrate below the lateral suppression filling slot. Using this invention, a punch-through TVS / ESD product that meets high-end requirements can be fabricated on a semiconductor substrate without an epitaxial substrate.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a highly robust anti-static surge substrate-type ESD / TVS tube structure and method. Background Art

[0002] A transient voltage suppressor (TVS) diode is a voltage-limiting overvoltage protection device (TVS) that limits excessive voltage to a safe range at speeds of hundreds of nanoseconds, thereby protecting subsequent circuits. Its key feature is that under reverse application conditions, when subjected to a high-energy pulse, its operating impedance instantly drops to an extremely low on-state value, allowing high current to flow while simultaneously clamping the voltage to a predetermined level, effectively protecting the precision components in electronic circuits.

[0003] In the consumer electronics sector, consumer-grade TVS / ESD protection devices, which combine both anti-static and surge protection, can be used to prevent overvoltages caused by static electricity, surges, mitigate interference, and absorb surge power. TVS / ESD devices are widely used in various fields, including mobile terminals (mobile phones and wearable devices), computer systems, communications equipment, automotive electronics, household appliances, electric lighting, and instrumentation. They are currently the most widely used overvoltage protection device and are indispensable in consumer electronics. They are mass-produced and used as ideal protection devices for consumer electronics.

[0004] The vast consumer electronics market has always fostered enormous demand for TVS / ESD devices. In 2021, the global TVS (including ESD) market was estimated at 21.7 billion yuan. The top five TVS manufacturers were Littelfuse, Nexperia, ON Semiconductor, Semtech, and Vishay. These five manufacturers collectively accounted for approximately 35.7% of the global market share.

[0005] Faced with such huge demand, on the one hand, various high-end TVS / ESD products with low parasitic capacitance that can meet high-end needs have been developed. On the other hand, reducing TVS / ESD production costs and exploring new low-cost TVS / ESD structures and manufacturing methods to meet advanced needs have also become research contents with good social and economic value.

[0006] Traditional high-end TVS / ESD devices are typically fabricated using epitaxial semiconductor substrates. Utilizing the steep change in doping concentration in the epitaxial layer, the resulting vertical transistor structure achieves high current injection capability, high breakdown voltage, low parasitic capacitance, and low on-resistance, resulting in high-end TVS / ESD products with high current flow capacity, high withstand voltage, low capacitance, and a narrow discharge window. However, the cost of epitaxial semiconductor substrates is at least four times higher than that of non-epitaxial substrates. Given the near-astronomical volume of TVS / ESD shipments, the ability to fabricate high-end TVS / ESD products that meet these requirements, such as high current flow capacity, high withstand voltage, low capacitance, and a narrow discharge window, on non-epitaxial semiconductor substrates, would be of immense economic value. Summary of the Invention

[0007] In response to the above-mentioned problems existing in the prior art, the present invention provides a highly robust anti-static surge substrate-type ESD / TVS tube structure and method, including preparing a typical structure of a TVS / ESD with high current passing capability, relatively high withstand voltage, low capacitance value, and narrow discharge window on a semiconductor substrate without an epitaxial substrate, as well as an implementation method for preparing the structure.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A highly robust anti-static surge substrate-type ESD / TVS tube structure includes a semiconductor single crystal substrate of a first type semiconductor, a deep diffusion well of a second type semiconductor formed in the semiconductor single crystal substrate, an emitter region injection or diffusion of the first type semiconductor formed in the deep diffusion well, a surface metal and contact formed on the surface of the ESD / TVS tube structure, a bottom metal and contact formed on the back side, an emitter junction optimization filling groove in contact with and electrically connected to the semiconductor single crystal substrate is provided below the surface metal and contact, a diffusion range of the emitter region injection or diffusion structurally encompasses the emitter junction optimization filling groove, an emitter junction optimization diffusion located in the semiconductor single crystal substrate and in contact with the emitter junction optimization filling groove is provided at the bottom of the emitter junction optimization filling groove, and a depth of the emitter junction optimization diffusion is equal to Or it is greater than the depth of injection or diffusion in the emitter region, a collector junction optimization filling groove is extended on the surface of the semiconductor single crystal substrate, a collector junction optimization diffusion is provided in the semiconductor single crystal substrate below the collector junction optimization filling groove, the collector junction optimization diffusion is in contact with the collector junction optimization filling groove, the collector junction optimization diffusion is distributed on the peripheral side of the deep diffusion well, the collector junction optimization filling groove is structurally in contact with the surface but not electrically connected to the surface, a lateral inhibition filling groove is extended on the surface of the semiconductor single crystal substrate, the lateral inhibition filling groove is structurally in contact with the surface but not electrically connected to the surface, a lateral inhibition diffusion is provided in the semiconductor single crystal substrate below the lateral inhibition filling groove, the lateral inhibition diffusion is in contact with the lateral inhibition filling groove, the lateral inhibition diffusion is not in contact with the deep diffusion well and the collector junction optimization diffusion and is separated by a predetermined distance.

[0010] Furthermore, the doping concentration of the semiconductor single crystal substrate is 5e18cm -3 to 1e20cm -3 The doping concentration of the deep diffusion well is 5e16cm -3 to 5e17cm -3 The doping concentration of the emitter region injected or diffused is 5e16cm -3 to 1e20cm -3 The doping concentration of the emitter junction optimization diffusion is 1e18cm -3 to 1e19cm -3 The doping concentration of the collector junction optimization diffusion is 5e16cm -3 to 1e18cm -3 The doping concentration of the lateral diffusion suppression is 5e16cm -3 to 5e19cm -3 .

[0011] Furthermore, the collector junction optimization diffusion does not penetrate deep into the deep diffusion well and does not connect with the emitter region injection or diffusion.

[0012] Furthermore, each independent collector junction is optimized for diffusion to form a continuous distribution.

[0013] Furthermore, the surface metal and contact are surface metal after deposition and etching, which are injected or diffused with the emitter junction optimization filling groove and part of the emitter area to form an ohmic contact to constitute one terminal of the ESD / TVS tube structure, and the bottom metal and contact constitute the other terminal of the ESD / TVS tube structure.

[0014] A method for preparing a highly robust anti-static surge substrate-type ESD / TVS tube structure comprises the following steps:

[0015] S1: SiO2 is formed on the surface as a diffusion mask, and then the selective diffusion patterns of S2 and S3 are formed by etching;

[0016] S2: Performing selective diffusion in the semiconductor single crystal substrate, and forming a deep diffusion well of the second type semiconductor through multiple diffusions at 800 to 1050 degrees;

[0017] S3: Performing selective diffusion in the deep diffusion well, and forming an emitter region of the first type semiconductor through multiple diffusions at 800 to 950 degrees;

[0018] S4: using etching or grooving process to form emitter junction optimized diffusion depth controlled grooving, collector junction optimized diffusion morphology controlled grooving, and lateral inhibition depth controlled grooving;

[0019] S5: while maintaining the surface SiO2 diffusion mask, depositing a diffusion source at the bottom of the emitter junction optimized diffusion depth control groove to form a conductive dielectric filling, and depositing a diffusion source at the bottom of the collector junction optimized diffusion morphology control groove and the lateral inhibition depth control groove to form a non-conductive dielectric filling, the diffusion source deposited at the bottom of the groove is filled with a diffusion source of the first type semiconductor, and the conductive medium is filled with a diffusion source of the second type semiconductor;

[0020] S6: After annealing and impurity activation, different diffusion regions are formed around the bottoms of the emitter junction optimized diffusion depth control groove, the collector junction optimized diffusion morphology control groove, and the lateral inhibition depth control groove, namely, the emitter junction optimized diffusion, the collector junction optimized diffusion, and the lateral inhibition diffusion;

[0021] S7: remove the surface SiO2 diffusion mask, fill the emitter junction optimized filling groove with conductive dielectric, and fill the collector junction optimized filling groove and lateral inhibition filling groove with non-conductive dielectric;

[0022] S8: Surface metal and contact are formed on the surface, and the emitter junction is optimized to fill the groove and inject or diffuse into part of the emitter area to form an ohmic contact to form one terminal of the ESD / TVS. A back metal structure located under the substrate is formed on the back to form another terminal of the ESD / TVS. At this point, a complete ESD / TVS tube structure is formed.

[0023] Furthermore, the groove bottom diffusion source filling and the conductive medium filling are only filled at the bottom of the emitter junction optimized diffusion depth control groove, the collector junction optimized diffusion morphology control groove, and the lateral inhibition depth control groove without filling the entire groove.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The present invention can produce a punch-through TVS / ESD product that meets high-end needs on a semiconductor substrate without an epitaxial substrate, without the need for an epitaxial semiconductor substrate, thereby greatly reducing the process limitations and production costs of high-end punch-through TVS / ESD.

[0026] 2. Since all parasitic PN junctions and parasitic NPN or PNP structures of the ESD / TVS tube structure of the present invention are inside the single crystal silicon, it has good robustness under multiple repeated shocks and is fully suitable for actual TVS / ESD usage scenarios.

[0027] 3. In the present invention: First, the emission enhancement mechanism on the emitter side improves the injection efficiency of its emitter-base region, effectively improving the current injection capability, making the present invention have a stronger current discharge capability; second, the enhancement induction mechanism on the collector side induces the current to diffuse laterally, so that the on-resistance of the present invention is reduced, and a narrow discharge window is provided. At the same time, the improvement of the concentration distribution between the base region and the collector also improves the current discharge capability; third, due to the optimization effect of the emission enhancement mechanism on the emitter side and the enhancement induction mechanism on the collector side, the base region concentration can be further reduced, making the present invention have a higher breakdown voltage and low parasitic capacitance; fourth, the non-connected lateral suppression mechanism suppresses the lateral diffusion of the electric field at a certain distance, avoiding lateral premature breakdown and maintaining a high withstand voltage of the entire device. As a result, a high-end TVS / ESD product that can meet the requirements of high current passing capability, high withstand voltage, low capacitance value, and narrow discharge window is prepared on a semiconductor substrate without an epitaxial substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the substrate-type ESD / TVS tube structure under traditional technology;

[0029] Figure 2 Schematic diagram of the substrate-type ESD / TVS tube structure in the embodiment;

[0030] Figure 3 Schematic diagram of process 1 of the method for preparing a substrate-type ESD / TVS tube structure in the embodiment;

[0031] Figure 4 Schematic diagram of process 2 of the method for preparing a substrate-type ESD / TVS tube structure in an embodiment;

[0032] Figure 5 Schematic diagram of process 3 of the method for preparing the substrate-type ESD / TVS tube structure in the embodiment;

[0033] Figure 6 Schematic diagram of process 4 of the method for preparing the substrate-type ESD / TVS tube structure in the embodiment;

[0034] Figure 7 Schematic diagram of process 5 of the method for preparing the substrate-type ESD / TVS tube structure in the embodiment;

[0035] Figure 8 Schematic diagram of process six of the method for preparing a substrate-type ESD / TVS tube structure in the embodiment;

[0036] Figure 9 Schematic diagram of internal doping of substrate-type ESD / TVS tube of the present invention;

[0037] Figure 10 This is one of the schematic diagrams of the principle of the substrate-type ESD / TVS tube of the present invention;

[0038] Figure 11 This is the second schematic diagram of the principle of the substrate type ESD / TVS tube of the present invention;

[0039] Figure 12 This is the third schematic diagram of the principle of the substrate-type ESD / TVS tube of the present invention;

[0040] Figure 13 A schematic diagram of an embodiment of a style that can be adopted by the present invention;

[0041] Figure 14 This is a schematic diagram of another embodiment that can be adopted by the present invention.

[0042] Markings in the figure: 001-semiconductor single crystal substrate; 002-deep diffusion well; 003-emitter region injection or diffusion; 004-emitter junction optimization diffusion; 005-emitter junction optimization filling groove; 006-collector junction optimization diffusion; 007-collector junction optimization filling groove; 008-lateral inhibition diffusion; 009-lateral inhibition filling groove; 010-surface metal and contact; 011-bottom metal and contact; 012-emitter junction optimization diffusion depth control groove; 013-collector junction optimization diffusion morphology control groove; 014-lateral inhibition depth control groove; 015-groove bottom diffusion source filling ;016-conductive dielectric filling; 017-non-conductive dielectric filling; 020-style one emitter junction optimization filling groove; 021-style one emitter region injection or diffusion; 022-style one deep diffusion well; 023-style one lateral suppression filling groove; 024-style one collector junction optimization filling groove; 025-style one unit cell area definition; 030-style two emitter junction optimization filling groove; 031-style two emitter region injection or diffusion; 032-style two deep diffusion well; 033-style two lateral suppression filling groove; 034-style two collector junction optimization filling groove; 035-style two unit cell area definition. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] Please refer to the figures, the present invention provides several embodiments of the technical solutions based on the present invention.

[0045] Figure 1 A schematic diagram of the structure of a substrate-type ESD / TVS tube provided by an embodiment of the present invention that relies on traditional technology is shown below. Figure 1 The device is fabricated using a single crystal substrate rather than an epitaxial wafer process. Substrate-based TVS diodes based on traditional processes can be constructed using a PN junction diode structure or an NPN or PNP transistor structure in the vertical direction. The NPN or PNP transistor structure exhibits punch-through characteristics, and its charge injection effect provides improved current discharge capability, enabling sufficient ESD surge protection in a smaller area and controlling parasitic capacitance, surpassing the PN junction diode structure in various aspects.

[0046] Figure 1The non-epitaxial single crystal substrate has a good cost advantage. The entire substrate-type ESD / TVS tube structure, which relies on traditional processes, consists of forming a second-type semiconductor deep diffusion well 002 in a first-type semiconductor single crystal substrate 001. The first-type semiconductor emitter region is implanted or diffused 003 in the second-type semiconductor deep diffusion well 002. Surface metal and contacts 010 and bottom metal and contacts 011 are formed on the surface and back, respectively, ultimately forming a vertical transistor structure. However, the substrate-type ESD / TVS tube structure under traditional processes has the following problems: First, in order to ensure the on-resistance, the concentration of the semiconductor single crystal substrate 001 is high, while the concentration of the deep diffusion well 002 cannot be too low for the injection efficiency, and the concentration derivative of the concentration boundary between the deep diffusion well 002 and the semiconductor single crystal substrate 001 is high, which makes it difficult to improve the withstand voltage of the entire device; Second, the concentration derivative of the PN junction boundary formed by the emitter region injection or diffusion 003 and the deep diffusion well 002 is low, resulting in low emitter injection efficiency and low current passing capacity per unit area. If the polysilicon emitter method is used to improve the emitter injection efficiency, it is difficult to meet the robustness requirements of multiple repeated electrostatic surges; Third, the vertical width of the base region of the deep diffusion well 002 under the emitter region injection or diffusion 003 is difficult to control. Low-energy ion implantation will make the base region too wide to form a transistor structure, while high-energy ion implantation will be too expensive to meet the process conditions and cause lattice damage. Therefore, most of the non-epitaxial single crystal substrates on the market are PN junction diode structures without back-punch characteristics, while high-end ESD / TVS with back-punch characteristics are basically prepared on epitaxial substrates.

[0047] The present invention prepares a typical TVS / ESD structure with high current carrying capacity, high withstand voltage, low capacitance and narrow discharge window on a semiconductor substrate without an epitaxial substrate, and provides an implementation method for preparing the typical TVS / ESD structure.

[0048] Figure 2-8 It is a bilaterally symmetrical structure. In order to make the description and illustration beautiful, concise and direct, the structural logo is only marked on the left side, and the right side is a symmetrical structure that is exactly the same as the logo on the left.

[0049] Figure 2 Schematic diagram of the structure of a novel highly robust and low-cost substrate-type ESD / TVS tube provided by an embodiment of the present invention. Figure 2The non-epitaxial single crystal substrate has a good cost advantage. A deep diffusion well 002 of a second type semiconductor is formed in a semiconductor single crystal substrate 001 of the first semiconductor type, and a first type semiconductor emitter region injection or diffusion 003 is formed in the second type semiconductor deep diffusion well 002. Surface metal and contact 010 and bottom metal and contact 011 are formed on the surface and back, respectively. In addition, the emitter junction optimization filling groove 005 is a physical structure, which is in contact with the semiconductor single crystal substrate 001 below the surface metal and contact 010 and is electrically connected; the emitter junction optimization diffusion 004 is a specific doping region, which is in the single crystal substrate below the emitter junction optimization filling groove 005 and is in contact with the emitter junction optimization filling groove 005. The emitter junction optimization diffusion 004 and the emitter junction optimization filling groove 005 are collectively referred to as an emission enhancement mechanism; the collector junction optimization filling groove 007 is a physical structure, which extends to the surface of the single crystal substrate; the collector junction optimization diffusion 006 is a specific doping region. The doped region is in the single crystal substrate below the collector junction optimization filling groove 007 and is in contact with the collector junction optimization filling groove 007. The collector junction optimization diffusion 006 and the collector junction optimization filling groove 007 are collectively referred to as an enhancement induction mechanism; the lateral inhibition filling groove 009 is a physical structure extending to the surface of the single crystal substrate; the lateral inhibition diffusion 008 is a specific doped region, in the single crystal substrate below the lateral inhibition filling groove 009 and is in contact with the lateral inhibition filling groove 009. The lateral inhibition diffusion 008 and the lateral inhibition filling groove 009 are collectively referred to as a non-connected lateral inhibition mechanism.

[0050] The following combination Figure 2 , specifically stating the specific structural features of the present invention:

[0051] 1) In order to ensure low on-resistance, the semiconductor single crystal substrate 001 adopts a low resistivity single crystal substrate of the first type semiconductor with a doping concentration of 5e18cm -3 to 1e20cm -3 within the range.

[0052] 2) The deep diffusion well 002 is deep from the surface (5-7 microns in this embodiment) and is formed using a low-cost well diffusion process, but it is not ruled out that a high-energy ion implantation process that is costly and prone to lattice damage may be used. Through the impurity compensation effect, the deep diffusion well 002 is a second-type semiconductor. In this embodiment, due to the optimization design mentioned later, the doping concentration can be designed to be as low as 5e16cm -3 to 5e17cm -3 range, and the doping concentration derivative can be designed to be low, the PN junction formed by the deep diffusion well 002 and the emitter region injection or diffusion 003 is closer to a graded junction.

[0053] 3) A first-type semiconductor emitter region injection or diffusion 003 is formed in the second-type semiconductor deep diffusion well 002. The emitter region injection or diffusion 003 is formed using a low-cost diffusion process. The diffusion range of the emitter region injection or diffusion 003 must structurally encompass the emitter junction optimization filling trench 005. In this embodiment, the doping concentration and doping concentration derivative restrictions of the emitter region injection or diffusion 003 are relatively loose, with a doping concentration range of 5e16cm -3 to 1e20cm -3 There is no special requirement for the doping concentration derivative of the emitter region injection or diffusion 003. In the case of meeting the restriction conditions, it is not excluded to use the injection method to form the emitter region injection or diffusion 003.

[0054] 4) The emitter junction optimized diffusion 004 is a first type of semiconductor doping formed by impurity diffusion or injection and then diffusion. The two can be selected according to the actual process conditions. The depth of the emitter junction optimized diffusion 004 is equal to or greater than the emitter region injection or diffusion 003. The doping concentration range of the emitter junction optimized diffusion 004 is 1e18cm -3 to 1e19cm -3 It is obviously much higher than the injection or diffusion 003 in the emission region.

[0055] 5) The emitter junction optimization filling trench 005 is contained within the emitter region implant or diffusion 003, providing both structural and electrical contact with the surface metal and contact 010. Its depth is determined by the trenching process and can be easily and precisely controlled. The depth-to-width ratio of the trench used to form the emitter junction optimization filling trench 005 is not specifically limited and is easily achieved in practical processes.

[0056] 6) The collector junction optimized diffusion 006 is a second type of semiconductor doping formed by impurity diffusion or injection and diffusion. It is distributed around the deep diffusion well 002 and cannot penetrate deep into the deep diffusion well 002 or even contact the emitter region injection or diffusion 003. The design tries to make each independent collector junction optimized diffusion 006 form a continuous distribution. The doping concentration range of the collector junction optimized diffusion 006 is 5e16cm -3 to 1e18cm -3 The doping concentration derivative is high, and the PN junction formed with the semiconductor single crystal substrate 001 is more inclined to an abrupt junction.

[0057] 7) The collector junction optimization filling trench 007 structurally contacts the surface but is not electrically connected to it. Its depth is determined by the trenching, making it easy to precisely control. The depth of the collector junction optimization filling trench 007 can be kept as uniform as possible while maintaining the distribution characteristics of the collector junction optimization diffusion 006 described above. The number of trenches and their aspect ratio can be adjusted based on actual conditions. A uniform trench depth and a reduced number of trenches and aspect ratio can further reduce process complexity.

[0058] 8) Lateral suppression diffusion 008 is a second type of semiconductor doping formed by impurity diffusion or injection and diffusion. It is not in contact with the deep diffusion well 002 and the collector junction optimization diffusion 006 and is separated by a certain distance (6.5 microns in this embodiment). In design, the distribution of each independent lateral suppression diffusion 008 does not need to be continuous. The doping concentration of lateral suppression diffusion 008 is loose and ranges from 5e16cm -3 to 5e19cm -3 between.

[0059] 9) The lateral inhibition filling groove 009 structurally contacts the surface but is not electrically connected to it. Its depth is determined by the groove, making it easy to precisely control. The depth of the lateral inhibition filling groove 009 can be kept as uniform as possible while maintaining the distribution characteristics of the lateral inhibition diffusion 008 described above. The number of grooves and their aspect ratio can be adjusted based on actual conditions. A uniform groove depth and a reduced number of grooves and aspect ratio can further reduce process complexity.

[0060] 10) Surface metal and contact 010 is the deposited and etched surface metal. It forms an ohmic contact with the emitter junction optimization filling trench 005 and a portion of the emitter region implanted or diffused 003, forming one terminal of the ESD / TVS. To achieve a better ohmic contact, additional metallization techniques such as, but not limited to, silicon alloys are employed. Bottom metal and contact 011 constitute the other terminal of the ESD / TVS. Nickel or a nickel-aluminum alloy is used to form the back metal structure beneath the substrate.

[0061] In this embodiment, a silicon device process is provided. The first type semiconductor refers to an N-type semiconductor doped with phosphorus or arsenic, and the second type semiconductor refers to a P-type semiconductor doped with boron. Interchanging the first and second semiconductor types, or using aluminum or phosphorus to implement the main principles, features, and design concepts of the present invention in other processes, such as SiC, is also within the scope of protection of the present invention.

[0062] Figure 3-8 This embodiment provides a novel, highly robust, low-cost, substrate-based ESD / TVS diode structure and its preparation method, along with a schematic process flow diagram. This embodiment highlights the key preparation steps of the present invention. Variations in the process details that do not alter the characteristics of the present invention in actual implementation do not limit the scope of the present invention.

[0063] The following combination Figure 3 - Figure 8 The preparation process of the present invention is specifically described in detail in the following examples:

[0064] S1: Clean the low-resistivity single crystal substrate (either homemade or purchased) and create alignment marks. Oxidation or deposition is used to form a SiO2 diffusion mask on the surface, which is then etched to form the selective diffusion patterns for S2 and S3.

[0065] S2: Arsenic is used as the diffusion source for selective diffusion in the semiconductor single crystal substrate 001. After multiple diffusions at 800 to 1050 degrees, a second type semiconductor deep diffusion well 002 is formed. Multiple diffusions can achieve a good diffusion depth and relatively uniform doping uniformity. Considering the cost and effect, this embodiment adopts a three-diffusion method with a non-constant diffusion source. Under the impurity compensation effect, a doping concentration of 5e16cm is formed at a depth of 5-7 microns from the surface. -3 to 5e17cm -3 Range of deep diffusion well 002.

[0066] S3: Boron is selectively diffused in the deep diffusion well 002, and after multiple diffusions at 800 to 950 degrees, the first type semiconductor emitter region is formed by injection or diffusion 003. The diffusion range of the emitter region injection or diffusion 003 must structurally include the emitter junction and optimize the filling groove 005. The doping concentration range is 5e16cm -3 to 1e20cm -3 So far, the formation Figure 3 The basic vertical transistor structure is shown.

[0067] S4: Use low-cost isotropic etching or ICP grooving process to form Figure 4 The grooves of different depths shown include emitter junction optimized diffusion depth controlled grooves 012, collector junction optimized diffusion morphology controlled grooves 013, and lateral suppression depth controlled grooves 014. The groove depths of emitter junction optimized diffusion depth controlled grooves 012 and collector junction optimized diffusion morphology controlled grooves 013 are precisely controlled by the etching time, and the groove depth precision requirements of lateral suppression depth controlled grooves 014 are lower than those of emitter junction optimized diffusion depth controlled grooves 012 and collector junction optimized diffusion morphology controlled grooves 013. The depths of emitter junction optimized diffusion depth controlled grooves 012, collector junction optimized diffusion morphology controlled grooves 013, and lateral suppression depth controlled grooves 014 can be unified as much as possible to further reduce costs while ensuring the distribution characteristics of subsequent diffusion areas, and the number of grooves and aspect ratio can be adjusted according to actual conditions. Uniform groove depth and reduced number of grooves and aspect ratio can further reduce process difficulty. After one or more grooves are completed, it is formed Figure 4 The structure shown.

[0068] S5: While maintaining the surface SiO2 diffusion mask, a diffusion source is deposited at the bottom of the emitter junction optimized diffusion depth control groove 012, the collector junction optimized diffusion morphology control groove 013, and the lateral suppression depth control groove 014, including the groove bottom diffusion source filling 015 and the conductive medium filling 016. The groove bottom diffusion source filling 015 is the diffusion source of the first type semiconductor, and the conductive medium filling 016 is the diffusion source of the second type semiconductor. Figure 5 As shown, the trench bottom diffusion source filling 015 and the conductive dielectric filling 016 are only filled at the bottom of the emitter junction optimized diffusion depth control trench 012, the collector junction optimized diffusion morphology control trench 013, and the lateral inhibition depth control trench 014, but do not fill the entire trench. Optionally, this step can also be replaced by ion implantation of an impurity at a corresponding dose at the bottom instead of depositing the diffusion source.

[0069] S6: After annealing and impurity activation at 850 degrees for 110 minutes, different diffusion regions are formed around the bottoms of the emitter junction optimized diffusion depth control groove 012, the collector junction optimized diffusion morphology control groove 013, and the lateral inhibition depth control groove 014, including emitter junction optimized diffusion 004, collector junction optimized diffusion 006, and lateral inhibition diffusion 008. The depth of the emitter junction optimized diffusion 004 is equal to or slightly greater than the depth of the emitter region injection or diffusion 003. The doping concentration of the emitter junction optimized diffusion 004 is in the range of 1e18cm -3 to 1e19cm -3 Since there is basically no long-distance diffusion process, the doping concentration derivative is significantly higher than that of the emitter region injection or diffusion 003. The collector junction optimized diffusion 006 is designed to form a continuous area as much as possible through process design. It is distributed around the side of the deep diffusion well 002 and cannot penetrate deep into the deep diffusion well 002 or even contact the emitter region injection or diffusion 003. The doping concentration range of the collector junction optimized diffusion 006 is 5e16cm -3 to 1e18cm -3 Because there is basically no long-distance diffusion process, the doping concentration derivative is high, and the PN junction formed with the semiconductor single crystal substrate 001 is more inclined to an abrupt junction. The lateral suppression diffusion 008 and the collector junction optimization diffusion 006 do not contact each other and are separated by a certain distance (6.5 microns in this embodiment). In terms of design, the distribution of each independent lateral suppression diffusion 008 does not need to be continuous. At this point, the formation Figure 6 Various slotting and diffusion structures are shown.

[0070] S7: Remove the surface SiO2 diffusion mask, as shown in Figure 7The positions shown are filled with a non-conductive dielectric filler 017 and a conductive dielectric filler 016, respectively. In this embodiment, SiO2 is used to ensure interface integrity, while the conductive dielectric filler 016 is considered a diffusion source for the second-type semiconductor. It is also possible to use a composite layer of SiO2 and polysilicon as the non-conductive dielectric filler 017 to laterally suppress the high aspect ratio of the depth-controlled trench 014.

[0071] S8: Aluminum with a thickness of 2 microns is deposited on the surface and etched to form 010 surface metal and contact, which forms an ohmic contact with the emitter junction optimization filling groove 005 and the injection or diffusion 003 of part of the emitter area to form a terminal of the ESD / TVS. In order to achieve a better ohmic contact effect, additional metal alloy technology is used but not limited to. Nickel or nickel-aluminum alloy is used but not limited to form a back metal structure located under the substrate on the back side to form another terminal of the ESD / TVS. At this point, the Figure 8 The complete ESD / TVS structure shown in the figure then undergoes passivation, dicing, packaging, testing and other post-processing to obtain the final ESD / TVS product.

[0072] The above steps complete the novel, highly robust, low-cost, substrate-based ESD / TVS diode structure and its preparation method proposed in this invention. As can be seen from the reference preparation methods provided in the examples, the present invention can be easily integrated with standard SiC processes without excessive additional steps and costs, offering the advantages of easy integration, low cost, and simple preparation.

[0073] Figure 9 This is a schematic diagram of the internal doping of the novel high-robustness, low-cost substrate-type ESD / TVS tube of the present invention, used to further illustrate the design ideas and principles related to the emission enhancement mechanism composed of the emitter junction optimized diffusion 004 and the emitter junction optimized filling groove 005. Figure 9 It shows Figure 2The doping concentration profile data for the novel, highly robust, low-cost, substrate-based ESD / TVS diode structure of the present invention is shown, centered vertically from top to bottom. Compared to the doping concentration of conventional single-crystal ESD / TVS diodes, the novel single-crystal ESD / TVS diode disclosed herein exhibits a higher concentration at a normalized depth of 0.4° on the emitter side of the emitter-base junction, due to the emission enhancement mechanism formed by the emitter junction optimized diffusion 004 and the emitter junction optimized filling groove 005. Simultaneously, the junction barrier region is narrower, significantly improving emitter injection efficiency. Furthermore, because the present invention utilizes slotting to control the diffusion depth, unlike conventional single-crystal ESD / TVS diodes that solely utilize a high-peak-concentration deep diffusion well 002 to advance the diffusion depth, the base concentration at a normalized depth of 0.6° is lower, further facilitating minority carrier sweeping from the emitter into the collector. This results in higher injection efficiency and improves the withstand voltage of the base-collector junction, thereby increasing the withstand voltage of the device as a whole.

[0074] Figure 10 - Figure 12 This is a schematic diagram of the principle of the novel high-robustness, low-cost substrate-type ESD / TVS tube of the present invention, used to further illustrate the design ideas and principles related to the enhanced induction mechanism composed of the collector junction optimized diffusion 006 and the collector junction optimized filling groove 007 of the present invention, and the design ideas and principles related to the non-connected lateral suppression mechanism composed of the lateral suppression diffusion 008 and the lateral suppression filling groove 009. Figure 10 for Figure 2 The upper left part is an enlarged schematic diagram of the main structure, including the semiconductor single crystal substrate 001, deep diffusion well 002, emitter region injection or diffusion 003, emitter junction optimization diffusion 004, emitter junction optimization filling groove 005, collector junction optimization diffusion 006, collector junction optimization filling groove 007, lateral inhibition diffusion 008, lateral inhibition filling groove 009, surface metal and contact 010 and Figure 2 The structures expressed are consistent.

[0075] Figure 11 for Figure 10The enlarged image in the upper right corner illustrates the design concept and principle of the enhanced induction mechanism comprised of the collector junction optimized diffusion 006 and the collector junction optimized filling groove 007. The solid arrow in the figure indicates the direction of current density. On the one hand, the deep diffusion well 002 in the novel single-crystal ESD / TVS disclosed in the present invention has a lower concentration than conventional structures, making it more conducive to minority carriers being swept from the emitter into the collector. On the other hand, the presence of the collector junction optimized diffusion 006 narrows the lateral width of the base region, allowing more current to be injected into the deep diffusion well 002 from a lateral position and then into the semiconductor single crystal substrate 001. In other words, the enhanced induction mechanism changes the flow of all current from the emitter directly downward to the base collector, causing a large portion of the current to be injected into the base at a certain lateral angle before reaching the collector. As a result, on the one hand, the emitter junction area increases, further improving the emission efficiency; on the other hand, the current channel expands wider, resulting in the beneficial effects of reduced on-resistance and a narrower discharge window.

[0076] Figure 12 for Figure 10 The enlargement of the upper left part is used to illustrate the design ideas and principles related to the non-connected lateral suppression mechanism of the present invention, which is composed of a lateral suppression diffusion 008 and a lateral suppression filling groove 009. Due to the design of the above-mentioned enhanced induction mechanism, there is an obvious lateral current diffusion phenomenon in the structure of the present invention, and the lateral electric field is also relatively high. Various ordinary terminal structures such as field limiting rings lose their traditional effect when suppressing larger lateral diffusion currents. In conjunction with the present invention, the depth of the lateral suppression diffusion 008 is controlled by the lateral suppression filling groove 009, and a non-connected lateral suppression mechanism structure is formed at a deeper position. The dark thick curve expresses the depletion region boundary. It can be seen that the optimized depletion region boundary horizontal line extends through the non-connected lateral suppression mechanism, achieving the effect of modulating the lateral electric field distribution. Therefore, the present invention does not suffer from premature breakdown in the lateral direction while having a large lateral diffusion current, suppresses excessive diffusion of lateral current, and maintains the withstand voltage of the device.

[0077] use Figures 9-12 The design concept and structural principle of the present invention are within the scope of protection and claims of the present invention. The use of different process details or non-substantial changes to the process structure will not affect the scope of protection and claims of the present invention.

[0078] Figure 13-14 Schematic diagrams of two possible embodiments of the present invention. Figure 13 The circular primitive cell design pattern of the present invention is implemented. In the circular primitive cell design pattern, the pattern-emitter junction optimization filling groove 020, the pattern-emitter region injection or diffusion 021, the pattern-deep diffusion well 022, the pattern-lateral suppression filling groove 023, the pattern-collector junction optimization filling groove 024, the pattern-cell region definition 025 are arranged in the form of concentric circles as shown in FIG. Figure 13 The advantage of this style is that it does not require special terminal design at the beginning and end. The disadvantage is that the chip area utilization is low. It is generally used in traditional vertical power devices.

[0079] Figure 14 In the cell design pattern, the second emitter junction optimization filling groove 030, the second emitter region injection or diffusion 031, the second deep diffusion well 032, the second lateral suppression filling groove 033, the second collector junction optimization filling groove 034, and the second cell region definition 035 are in the form of interdigitation. Figure 13 The advantage of this arrangement is that the number of interdigital fingers can be flexibly increased or modified, and the chip area utilization is high. It is generally used in traditional vertical power devices. The disadvantage is that special terminal designs are required at the beginning and end. It is recommended to use the lateral diffusion suppression 008 and lateral suppression filling groove 009 structure as the terminal structure to surround the beginning and end of all interdigital fingers.

[0080] In summary, the present invention is different from TVS / ESD devices prepared on a semiconductor substrate with epitaxial growth (similar to the epitaxial TVS disclosed in patent CN102290337B). The present invention can prepare a punch-through TVS / ESD product that can meet high-end needs without an epitaxial substrate; all parasitic PN junctions and their parasitic NPN or PNP structures are inside the single crystal silicon, rather than like polycrystalline silicon transistors (similar to the polycrystalline silicon transistors disclosed in patent CN102129992B) where a polycrystalline silicon-single crystal silicon interface ( This interface is prone to degradation under high current and high temperature conditions, and can maintain good performance under repeated impacts of multiple electrostatic surges; its unique structure: first, the emission enhancement mechanism on the emitter side improves the injection efficiency of its emitter-base region; second, the enhancement induction mechanism on the collector side induces the current to diffuse laterally, while improving the concentration distribution of the base region-collector; third, due to the existence of the emission enhancement mechanism on the emitter side and the enhancement induction mechanism on the collector side, the base region concentration can be further reduced; fourth, the non-connected lateral suppression mechanism suppresses the lateral diffusion of the electric field at a certain distance.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A highly robust anti-static surge substrate-type ESD / TVS tube structure, comprising a semiconductor single crystal substrate of a first type semiconductor, a deep diffusion well of a second type semiconductor formed in the semiconductor single crystal substrate, an emitter region of the first type semiconductor injected or diffused in the deep diffusion well, a surface metal and contact formed on the surface of the ESD / TVS tube structure, and a bottom metal and contact formed on the back surface, characterized in that: An emitter junction optimization filling groove is provided under the surface metal and the contact, and is in contact with and electrically connected to the semiconductor single crystal substrate. The diffusion range of the emitter region injection or diffusion structurally includes the emitter junction optimization filling groove. An emitter junction optimization diffusion is provided at the lower part of the emitter junction optimization filling groove, which is located in the semiconductor single crystal substrate and in contact with the emitter junction optimization filling groove. The depth of the emitter junction optimization diffusion is equal to or greater than the depth of the emitter region injection or diffusion. A collector junction optimization filling groove is extended from the surface of the semiconductor single crystal substrate. A collector junction optimization diffusion is provided in the semiconductor single crystal substrate at the lower part of the collector junction optimization filling groove. The optimized diffusion contacts the collector junction optimized filling groove, the collector junction optimized diffusion is distributed around the deep diffusion well, the collector junction optimized filling groove is structurally in contact with the surface but not electrically connected to the surface, a lateral inhibition filling groove extends from the surface of the semiconductor single crystal substrate, the lateral inhibition filling groove is structurally in contact with the surface but not electrically connected to the surface, a lateral inhibition diffusion is provided in the semiconductor single crystal substrate below the lateral inhibition filling groove, the lateral inhibition diffusion contacts the lateral inhibition filling groove, the lateral inhibition diffusion does not contact the deep diffusion well and the collector junction optimized diffusion and is separated by a predetermined distance; the doping concentration of the semiconductor single crystal substrate is 5e18cm -3 to 1e20cm -3 The doping concentration of the deep diffusion well is 5e16cm -3 to 5e17cm -3 The doping concentration of the emitter region injected or diffused is 5e16cm -3 to 1e20cm -3 The doping concentration of the emitter junction optimization diffusion is 1e18cm -3 to 1e19cm -3 The doping concentration of the collector junction optimization diffusion is 5e16cm -3 to 1e18cm -3 The doping concentration of the lateral diffusion suppression is 5e16cm -3 to 5e19cm -3 .

2. The highly robust anti-static surge substrate-type ESD / TVS tube structure according to claim 1, characterized in that: The collector junction optimization diffusion does not penetrate deep into the deep diffusion well and does not connect with the emitter region injection or diffusion.

3. The highly robust anti-static surge substrate type ESD / TVS tube structure according to claim 1 or 2, characterized in that: Each independent collector junction is optimized for diffusion to form a continuous distribution.

4. The highly robust anti-static surge substrate type ESD / TVS tube structure according to claim 1, characterized in that: The surface metal and contact are surface metal after deposition and etching, and are injected or diffused with the emitter junction optimization filling groove and part of the emitter area to form an ohmic contact to constitute one terminal of the ESD / TVS tube structure, and the bottom metal and contact constitute the other terminal of the ESD / TVS tube structure.

5. A method for preparing a highly robust anti-static surge substrate type ESD / TVS tube structure, characterized in that: The steps include: S1: SiO2 is formed on the surface as a diffusion mask, and then the selective diffusion patterns of S2 and S3 are formed by etching; S2: Performing selective diffusion in the semiconductor single crystal substrate, and forming a deep diffusion well of the second type semiconductor through multiple diffusions at 800 to 1050 degrees; S3: Performing selective diffusion in the deep diffusion well, and forming an emitter region of the first type semiconductor through multiple diffusions at 800 to 950 degrees; S4: using etching or grooving process to form emitter junction optimized diffusion depth controlled grooving, collector junction optimized diffusion morphology controlled grooving, and lateral inhibition depth controlled grooving; S5: while maintaining the surface SiO2 diffusion mask, depositing a diffusion source at the bottom of the emitter junction optimized diffusion depth control groove to form a conductive dielectric filling, and depositing a diffusion source at the bottom of the collector junction optimized diffusion morphology control groove and the lateral inhibition depth control groove to form a non-conductive dielectric filling, the diffusion source deposited at the bottom of the groove is filled with a diffusion source of the first type semiconductor, and the conductive dielectric filling is filled with a diffusion source of the second type semiconductor; S6: After annealing and impurity activation, different diffusion regions are formed around the bottoms of the emitter junction optimized diffusion depth control groove, the collector junction optimized diffusion morphology control groove, and the lateral inhibition depth control groove, namely, the emitter junction optimized diffusion, the collector junction optimized diffusion, and the lateral inhibition diffusion; S7: remove the surface SiO2 diffusion mask, fill the emitter junction optimized filling groove with conductive dielectric, and fill the collector junction optimized filling groove and lateral inhibition filling groove with non-conductive dielectric; S8: Surface metal and contact are formed on the surface, and the emitter junction is optimized to fill the groove and inject or diffuse into part of the emitter area to form an ohmic contact to form one terminal of the ESD / TVS. A back metal structure located under the substrate is formed on the back to form another terminal of the ESD / TVS. At this point, a complete ESD / TVS tube structure is formed.

6. The method for preparing a highly robust anti-static surge substrate type ESD / TVS tube structure according to claim 5, characterized in that: The bottom deposition diffusion source filling and conductive medium filling of the groove are only filled at the bottom of the emitter junction optimized diffusion depth control groove, the collector junction optimized diffusion morphology control groove, and the lateral inhibition depth control groove without filling the entire groove.

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