IP Packet Forwarding Method, Device, Electronic Device and Storage Medium

Abstract

The present application provides an IP packet forwarding method, apparatus, electronic device, and storage medium. Among them, the IP packet forwarding method includes: receiving a target packet, where the target packet is one of an IPv4 packet and an IPv6 packet; determining a five-tuple of the target packet; querying a session table of the target packet in a session table storage area of the FPGA based on the five-tuple of the target packet; and forwarding the target packet based on the session table of the target packet. The present application can at least improve the forwarding speed of packets to meet the requirements of the increasingly developing Internet technology for network speed.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to an IP message forwarding method, device, electronic device and storage medium. Background Art

[0002] With the rapid global development of Internet technology, network equipment is becoming increasingly widespread. The IPV4 protocol no longer fully meets the needs of Internet development, and the IPV6 protocol is gaining increasing popularity. Due to its limited address space and poor security, IPV4 no longer fully meets the needs of Internet development. IPV6 defines a 128-bit address space, providing a vast address space. However, due to the widespread use and maturity of IPV4, IPV4 and IPV6 will coexist on the Internet for a long time.

[0003] On the other hand, both IPv4 and IPv6 packets typically need to pass through an intermediate device, where they are processed and then forwarded to the corresponding server. Currently, packet forwarding relies primarily on the CPU installed in the intermediate device. However, the CPU's speed in forwarding IPv4 and IPv6 packets is slow, failing to meet the network speed requirements of the rapidly developing Internet. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide an IP message forwarding method, device, electronic device and storage medium to increase the forwarding speed of messages to meet the network speed requirements of the growing development of Internet technology.

[0005] In a first aspect, the present invention provides an IP message forwarding method, which is applied to an FPGA and includes:

[0006] Receive a target message, where the target message is one of an IPv4 message and an IPv6 message;

[0007] Determining the quintuple of the target message;

[0008] Querying a session table of the target message in a session table storage area of the FPGA based on the quintuple of the target message;

[0009] The target message is forwarded based on the session table of the target message.

[0010] In the first aspect of the present application, by receiving IPV4 messages and IPV6 messages, the five-tuple of the message can be determined, and then the five-tuple of the message can be determined, so that the session table of the message can be queried in the session table storage area of the FPGA based on the five-tuple of the message, and finally the target message can be forwarded based on the session table of the message.

[0011] Compared with the prior art, the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has a higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0012] In the first aspect of the present application, as an optional implementation manner, the session table storage area of the FPGA includes a plurality of storage blocks. Each storage block is mapped to a hash address, and each storage block stores one or two session tables with hash address conflicts, where the data length of the hash address is 24 bits.

[0013] In the above optional implementation manner, since each storage block stores one or two session tables with hash address conflicts and each storage block is mapped to a hash address, the session table stored in the storage block can be read through the hash address. At the same time, by designing the data length of the hash address to be 24 bits, the storage space in the storage area can be saved, so as to store more data.

[0014] In the first aspect of the present application, as an optional implementation manner, querying the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet includes:

[0015] Calculating a forward JHASH value based on the five-tuple of the target packet, where the data length of the forward JHASH value is 32 bits;

[0016] Taking the lower 24 bits of the forward JHASH value as the lookup table address, and determining whether there is a hash address equal to the lookup table address in the session table storage area of the FPGA;

[0017] When there is a hash address equal to the lookup table address in the session table storage area of the FPGA, the session table mapped by the hash address is used as the session table of the target packet.

[0018] In the above optional implementation manner, a forward JHASH value can be calculated based on the five-tuple of the target packet, where the data length of the forward JHASH value is 32 bits. Then, the lower 24 bits of the forward JHASH value can be used as the lookup table address, and then it can be determined whether there is a hash address equal to the lookup table address in the session table storage area of the FPGA. Thus, when there is a hash address equal to the lookup table address in the session table storage area of the FPGA, the session table mapped by the hash address is used as the session table of the target packet, and finally the session table required by the packet is read from the storage area of the FPGA.

[0019] In the first aspect of the present application, as an alternative embodiment, the storage block further stores IP address conversion information, and before forwarding the target packet based on the session table of the target packet, the method further includes:

[0020] Determine whether the target packet needs to perform address conversion based on the session table of the target packet;

[0021] When the target packet needs to perform address conversion, replace the destination IP address of the target packet based on the IP address conversion information.

[0022] In the above alternative embodiment, based on the session table of the target packet, it can be determined whether the target packet needs to perform address conversion. Furthermore, when the target packet needs to perform address conversion, the destination IP address of the target packet can be replaced based on the IP address conversion information.

[0023] In the first aspect of the present application, as an alternative embodiment, when the target packet is an IPV4 packet, the session table of the target packet stores the source IP address and the destination IP address, where the data lengths of the source IP address and the destination IP address are both 32 bits;

[0024] And when the target packet is an IPV4 packet, the session table of the target packet stores the first information, the second information, and the third information, where the first information is the high 8-bit data in the forward JHASH value, the second information is the reverse JHASH value generated based on the five-tuple of the target packet, and the third information is the forward CRC32 value generated based on the five-tuple of the target packet. The data lengths of the second information and the third information are both 32 bits.

[0025] In the above alternative embodiment, by designing the data lengths of the source IP address and the destination IP address to be both 32 bits, the data lengths of the second information and the third information to be 32 bits, and the data length of the first information to be 8 bits, the occupied space of the session table can be reduced, thereby saving the storage space of the FPGA and enabling the storage space of the FPGA to store more data.

[0026] In the first aspect of the present application, as an alternative embodiment, the method further includes:

[0027] When the storage block stores two session tables with hash address conflicts, determine the session table of the target packet based on the source IP address and the destination IP address;

[0028] Alternatively, determine a session table of the target packet based on the first information, the second information, and the third information.

[0029] In the above optional implementation, when there are two session tables with hash address conflicts stored in the storage block, the session table of the target packet can be further determined based on the source IP address and the destination IP address; or the session table of the target packet can be further determined based on the first information, the second information, and the third information.

[0030] In a first aspect of the present application, as an optional implementation, the method further includes:

[0031] When the session table storage area of the FPGA does not have the session table of the target packet, send the target packet to the CPU, so that the CPU constructs the session table of the target packet based on the middle layer and the forward JHASH value, the reverse JHASH value, and the forward CRC32 value in the target packet, and the CPU writes the session table of the target packet into the session table storage area of the FPGA through the upper-layer application.

[0032] In the above optional implementation, when the session table storage area of the FPGA does not have the session table of the target packet, by sending the target packet to the CPU, the CPU can construct the session table of the target packet based on the middle layer and the forward JHASH value, the reverse JHASH value, and the forward CRC32 value carried in the target packet, and the CPU writes the session table of the target packet into the session table storage area of the FPGA through the upper-layer application.

[0033] In a second aspect, the present invention provides an IP packet forwarding device, which is applied in an FPGA. The device includes:

[0034] A receiving module, configured to receive a target packet, where the target packet is one of an IPV4 packet and an IPV6 packet;

[0035] A determining module, configured to determine a five-tuple of the target packet;

[0036] A querying module, configured to query the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet;

[0037] A forwarding module, configured to forward the target packet based on the session table of the target packet.

[0038] The device according to the second aspect of the present application can receive IPv4 packets and IPv6 packets, and then can determine the five-tuple of the packets, and then can determine the five-tuple of the packets, so as to be able to query the session table of the packets in the session table storage area of the FPGA based on the five-tuple of the packets, and finally can forward the target packet based on the session table of the packets.

[0039] Compared with the prior art, the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0040] In a third aspect, the present invention provides an electronic device, including:

[0041] a processor; and

[0042] a memory configured to store machine-readable instructions, and the instructions, when executed by the processor, execute the IP packet forwarding method according to any one of the foregoing embodiments.

[0043] The electronic device according to the third aspect of the present application can receive IPv4 packets and IPv6 packets by executing the IP packet forwarding method, and then can determine the five-tuple of the packets, and then can determine the five-tuple of the packets, so as to be able to query the session table of the packets in the session table storage area of the FPGA based on the five-tuple of the packets, and finally can forward the target packet based on the session table of the packets.

[0044] Compared with the prior art, the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0045] In a fourth aspect, the present invention provides a storage medium storing a computer program, and the computer program is executed by a processor to execute the IP packet forwarding method according to any one of the foregoing embodiments.

[0046] The storage medium according to the fourth aspect of the present application can receive IPv4 packets and IPv6 packets by executing the IP packet forwarding method, and then can determine the five-tuple of the packets, and then can determine the five-tuple of the packets, so as to be able to query the session table of the packets in the session table storage area of the FPGA based on the five-tuple of the packets, and finally can forward the target packet based on the session table of the packets.

[0047] Compared with the prior art, the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better. Brief Description of the Drawings

[0048] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0049] Figure 1 is a schematic flowchart of a method for forwarding IP packets disclosed in an embodiment of the present application;

[0050] Figure 2 is a schematic diagram of the storage structure of a storage block disclosed in an embodiment of the present application;

[0051] Figure 3 is a schematic diagram of a session table disclosed in an embodiment of the present application;

[0052] Figure 4 is a schematic diagram of the structure of an IP packet forwarding device disclosed in an embodiment of the present application;

[0053] Figure 5 is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application. Detailed Embodiments

[0054] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application.

[0055] Embodiment 1

[0056] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a method for forwarding IP packets disclosed in an embodiment of the present application. Among them, the method of the embodiment of the present application is applied to an FPGA. As Figure 1 shown, the method of the embodiment of the present application includes the following steps:

[0057] 101. Receive a target packet, where the target packet is one of an IPv4 packet and an IPv6 packet;

[0058] 102. Determine the five-tuple of the target packet;

[0059] 103. Query the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet;

[0060] 104. Forward the target packet based on the session table of the target packet.

[0061] In the embodiments of the present application, by receiving IPv4 packets and IPv6 packets, it is possible to determine the five-tuple of the packets, and then it is possible to determine the five-tuple of the packets, so that it is possible to query the session table of the packets in the session table storage area of the FPGA based on the five-tuple of the packets, and finally it is possible to forward the target packet based on the session table of the packet.

[0062] Compared with the prior art, in the embodiments of the present application, through the FPGA and the session table in the FPGA, hardware forwarding of packets can be achieved. Among them, hardware forwarding has a higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0063] In the embodiments of the present application, specifically, by using an FPGA (Field Programmable Gate Array) to execute the method of the embodiments of the present application, the advantage of the fast speed of the FPGA in processing single tasks can be utilized to improve the speed and efficiency of packet forwarding. At the same time, by using the FPGA to execute the method of the embodiments of the present application, the CPU (central processing unit) does not need additional calculations, so that the overhead of the CPU can be reduced.

[0064] In the embodiments of the present application, the FPGA can be set in various network devices such as switches, routers, and firewalls. Among them, when a switch, router, or firewall receives a target packet, it transmits it to the FPGA. In the embodiments of the present application, for step 101, the target packet refers to a packet that needs to be forwarded and processed. Among them, the target packet can be an IPv4 packet or an IPv6 packet. An IPv4 packet refers to a packet that uses Internet Protocol version 4, and an IPv6 packet refers to a packet that uses Internet Protocol version 6.

[0065] In the embodiments of the present application, for step 102, the five-tuple of the target packet refers to the source IP address, source port, destination IP address, destination port, and transport layer protocol in the target packet.

[0066] In the embodiments of the present application, for step 103, the session table storage area of the FPGA pre-stores the session tables of several flows. Among them, when the FPGA receives the first packet of a flow, it can construct the session table of the packet through the CPU and write the session table into the session table storage area of the FPGA, so as to complete the forwarding process of subsequent packets through the session table corresponding to the flow. Among them, during the existence of the session, the five-tuple of the packet will not change. Therefore, based on the five-tuple of the target packet, the session table of the target packet can be queried in the session table storage area of the FPGA.

[0067] In the embodiments of the present application, for step 104, in some scenarios, a message needs to pass through a gateway device to detect the message through the gateway device, so as to determine whether there is an attack behavior in the message. On the other hand, usually when the gateway device determines that there is no attack behavior in the message, it needs to forward the message to the corresponding application server so that the application server can normally respond to the message.

[0068] In the embodiments of the present application, as an alternative implementation, the session table storage area of the FPGA includes several storage blocks. Specifically, please refer to Figure 2 , Figure 2 which is a schematic diagram of the storage structure of a storage block disclosed in the embodiments of the present application. As Figure 2 shown, the storage block is mapped to a hash address. For example, in Figure 2 , the storage block is mapped to the hash address "hash_addr[23:0]".

[0069] Furthermore, as Figure 2 shown, the capacity of the storage area in the embodiments of the present application is 4G Bytes. Among them, 4GBytes is divided into several storage blocks, and the capacity of each storage block is 64bytes * 4.

[0070] Furthermore, as Figure 2 shown, each storage block has 4 storage strips, and the index addresses of the 4 storage strips include first address information. Among them, the first address information of the 4 storage strips is the same. For example, the 4 storage strips have the same hash address "hash_addr[23:0]". In addition, the index address of each storage strip also includes second address information. Among them, the second address information of the 4 storage strips is arranged continuously. For example, as Figure 2 shown, the second address information of the 4 storage strips is successively "2’b00", "2’b01", "2’b10", "2’b11". In this way, the 4 storage strips can be distinguished through the second address information. On the other hand, since the addresses of the 4 storage strips are arranged continuously, when reading the contents of the 4 storage strips in a storage block, it has a higher reading efficiency.

[0071] In the embodiments of the present application, each storage block stores one or two session tables with hash address conflicts. For example, as Figure 2 shown, the storage block stores two session tables with hash address conflicts.

[0072] In the embodiments of the present application, the data length of the hash address of each storage block is 24 bits.

[0073] In the above optional implementation, since the storage block stores the session table with one or two hash address conflicts, and each storage block is mapped to a hash address, the session table stored in the storage block can be read through the hash address. At the same time, by designing the data length of the hash address to be 24 bits, the storage space in the storage area can be saved, so as to store more data.

[0074] In an embodiment of the present application, as an optional implementation, step 103: Query the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet, including the following sub-steps:

[0075] Calculate the forward JHASH value based on the five-tuple of the target packet, where the data length of the forward JHASH value is 32 bits;

[0076] Take the lower 24 bits of the forward JHASH value as the table lookup address, and determine whether there is a hash address equal to the table lookup address in the session table storage area of the FPGA;

[0077] When there is a hash address equal to the table lookup address in the session table storage area of the FPGA, use the session table mapped by the hash address as the session table of the target packet.

[0078] In the above optional implementation, the forward JHASH value can be calculated based on the five-tuple of the target packet, where the data length of the forward JHASH value is 32 bits. Then, the lower 24 bits of the forward JHASH value can be used as the table lookup address, and further determine whether there is a hash address equal to the table lookup address in the session table storage area of the FPGA. Thus, when there is a hash address equal to the table lookup address in the session table storage area of the FPGA, use the session table mapped by the hash address as the session table of the target packet, and finally read the session table required by the packet from the storage area of the FPGA.

[0079] In the above optional implementation, for how to calculate the forward JHASH value based on the five-tuple of the target packet, please refer to the prior art, and the present application will not elaborate on this.

[0080] In an embodiment of the present application, as an optional implementation, the storage block also stores IP address conversion information. For example, as Figure 2 shown, after each session table, there is IP address conversion information connected, and the IP address information that needs to be replaced for the connection of NAT46 or NAT64 forwarding. Based on this, correspondingly, before step 104: Forward the target packet based on the session table of the target packet, the method of the embodiment of the present application further includes the following steps:

[0081] Judge whether the target packet needs to perform address conversion based on the session table of the target packet;

[0082] When the target packet needs to perform address conversion, replace the destination IP address of the target packet based on the IP address conversion information.

[0083] In the above optional implementation manner, based on the session table of the target packet, it can be determined whether the target packet needs to perform address conversion. Furthermore, when the target packet needs to perform address conversion, the destination IP address of the target packet can be replaced based on the IP address conversion information.

[0084] In the above optional implementation manner, specifically, there is a flag bit in the session table of the target packet. If the value of the flag bit is 1, it indicates that the target packet needs to perform address conversion. At this time, the destination IP address in the target packet can be replaced with the available IP address conversion information. In the above optional implementation manner, specifically, the IP address conversion information can be an IPV4 address, and the destination IP address in the target packet can be an IPV6 address. That is, through the above optional implementation manner, the IPV4 address can be converted into an IPV6 address. Correspondingly, the IP address conversion information can be an IPV6 address, and the destination IP address in the target packet can be an IPV4 address, thereby realizing the conversion of the IPV6 address into an IPV4 address.

[0085] In the above optional implementation manner, specifically, both the IP address conversion information and the destination IP address in the target packet can be IPV4 addresses or both can be IPV6 addresses.

[0086] In the embodiment of the present application, as an optional implementation manner, please refer to Figure 3 , Figure 3 which is a schematic diagram of a session table disclosed in the embodiment of the present application. As Figure 3 shown, when the target packet is an IPV4 packet, the session table of the target packet stores the source IP address and the destination IP address. Among them, the data lengths of both the source IP address and the destination IP address are 32 bits. Correspondingly, when the target packet is an IPV4 packet, the session table of the target packet stores the first information, the second information, and the third information. The first information is the high 8-bit data in the forward JHASH value, the second information is the reverse JHASH value generated based on the five-tuple of the target packet, and the third information is the forward CRC32 value generated based on the five-tuple of the target packet. The data lengths of both the second information and the third information are 32 bits.

[0087] In the above optional embodiment, by designing the data lengths of the source IP address and the destination IP address to be both 32 bits, the data lengths of the second information and the third information to be 32 bits, and the data length of the first information to be 8 bits, the occupied space of the session table can be reduced, thereby saving the storage space of the FPGA and enabling the FPGA's storage space to store more data.

[0088] In an embodiment of the present application, as an optional embodiment, the method of the present application example further includes the following steps:

[0089] When there are two session tables with hash address conflicts stored in the storage block, determine the session table of the target packet based on the source IP address and the destination IP address;

[0090] Or, determine the session table of the target packet based on the first information, the second information, and the third information.

[0091] In the above optional embodiment, when there are two session tables with hash address conflicts stored in the storage block, the session table of the target packet can be further determined based on the source IP address and the destination IP address; or the session table of the target packet can be further determined based on the first information, the second information, and the third information.

[0092] In the above optional embodiment, specifically, if two session tables with the same hash address are matched, it is necessary to further determine which session table is the session table of the target packet based on the content of the session table. At this time, if the target packet is an IPV4 packet, the session table stores the 32-bit destination IP address and the 32-bit source IP address. Therefore, through the 32-bit destination IP address and the 32-bit source IP address, two session tables with hash address conflicts can be further distinguished.

[0093] Furthermore, since the source IP address and the destination IP address in an IPV6 packet are both 128-bit data, if the source IP address and the destination IP address in an IPV6 packet are stored in the session table, compared with the source IP address and the destination IP address in an IPV4 packet, the session table corresponding to the IPV6 packet occupies too much storage space. Therefore, it is necessary to compress the information used to further distinguish the conflicting session tables. In this optional embodiment, the first information, the second information, and the third information with smaller data lengths are used to replace the source IP address and the destination IP address in the IPV6 packet. Among them, the data length of the first information is 8 bits, the data length of the second information is 32 bits, and the data length of the third information is 32 bits, totaling only 72 bits. Compared with the 256-bit storage space occupied by the source IP address and the destination IP address in the IPV6 packet, the storage space occupied by this optional embodiment is smaller.

[0094] In an embodiment of the present application, as an alternative implementation, the method of the embodiment of the present application further includes the following steps:

[0095] When the session table of the target packet does not exist in the session table storage area of the FPGA, the target packet is sent to the CPU, so that the CPU constructs the session table of the target packet based on the forward JHASH value, reverse JHASH value, and forward CRC32 value in the middle layer and the target packet, and the CPU writes the session table of the target packet into the session table storage area of the FPGA through the upper-layer application.

[0096] In the above alternative implementation, when the session table of the target packet does not exist in the session table storage area of the FPGA, by sending the target packet to the CPU, the CPU can construct the session table of the target packet based on the forward JHASH value, reverse JHASH value, and forward CRC32 value carried in the middle layer and the target packet, and the CPU writes the session table of the target packet into the session table storage area of the FPGA through the upper-layer application.

[0097] In the above alternative implementation, specifically, before sending the target packet to the CPU, the FPGA is further configured to reconstruct the target packet so that the target packet carries the forward JHASH value, reverse JHASH value, and forward CRC32 value.

[0098] In the above alternative implementation, specifically, after receiving the reconstructed target packet, the CPU drives the middle layer, so that the middle layer extracts the forward JHASH value, reverse JHASH value, and forward CRC32 value from the reconstructed target packet, and sends the forward JHASH value, reverse JHASH value, and forward CRC32 value to the upper-layer application. Then, the upper-layer application constructs the session table based on the forward JHASH value, reverse JHASH value, forward CRC32 value, five-tuple, and forwarding information, and writes the session table into the storage area of the FPGA through the software and hardware interaction interface.

[0099] In the above alternative implementation, specifically, the middle layer refers to the Hardware Abstract Layer (HAL) or the Board Support Package. Correspondingly, the upper-layer application refers to the application software.

[0100] Embodiment 2

[0101] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of an IP packet forwarding device disclosed in an embodiment of the present application. Among them, the device of the embodiment of the present application is applied in the FPGA. As shown in Figure 2 , the device of the embodiment of the present application includes the following functional modules:

[0102] A receiving module 201, configured to receive a target packet, where the target packet is one of an IPv4 packet and an IPv6 packet;

[0103] A determining module 202, configured to determine the five-tuple of the target packet;

[0104] A querying module 203, configured to query the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet;

[0105] A forwarding module 204, configured to forward the target packet based on the session table of the target packet.

[0106] The device according to the embodiment of the present application can receive an IPv4 packet and an IPv6 packet, and then can determine the five-tuple of the packet, and then can determine the five-tuple of the packet, so that the session table of the packet can be queried in the session table storage area of the FPGA based on the five-tuple of the packet, and finally the target packet can be forwarded based on the session table of the packet.

[0107] Compared with the prior art, the embodiment of the present application can implement hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has a higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding of the present application is better.

[0108] It should be noted that for other detailed descriptions of the device according to the embodiment of the present application, please refer to the relevant descriptions in Embodiment 1 of the present application, and the embodiment of the present application will not elaborate on this.

[0109] Embodiment 3

[0110] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of an electronic device disclosed in the embodiment of the present application. As Figure 5 shown, the electronic device according to the embodiment of the present application includes:

[0111] A processor 301; and

[0112] A memory 302, configured to store machine-readable instructions, and when the instructions are executed by the processor 301, execute the IP packet forwarding method according to any one of the foregoing embodiments.

[0113] The electronic device according to the embodiment of the present application can execute the IP packet forwarding method, and then can receive an IPv4 packet and an IPv6 packet, and then can determine the five-tuple of the packet, and then can determine the five-tuple of the packet, so that the session table of the packet can be queried in the session table storage area of the FPGA based on the five-tuple of the packet, and finally the target packet can be forwarded based on the session table of the packet.

[0114] Compared with the prior art, the embodiment of the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has a higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0115] Embodiment 4

[0116] The embodiment of the present application provides a storage medium storing a computer program, and the computer program is executed by a processor to perform the IP packet forwarding method according to any one of the foregoing embodiments.

[0117] The storage medium of the embodiment of the present application can receive IPv4 packets and IPv6 packets by executing the IP packet forwarding method, and can then determine the five-tuple of the packets, and can further determine the five-tuple of the packets, so as to be able to query the session table of the packets in the session table storage area of the FPGA based on the five-tuple of the packets, and finally be able to forward the target packets based on the session table of the packets.

[0118] Compared with the prior art, the embodiment of the present application can achieve hardware forwarding of packets through the FPGA and the session table in the FPGA. Among them, hardware forwarding has a higher forwarding speed and forwarding efficiency. Therefore, the performance of IP packet forwarding in the present application is better.

[0119] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, and the indirect coupling or communication connection of the devices or units may be in an electrical, mechanical or other form.

[0120] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] Furthermore, in each embodiment of the present application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0122] It should be noted that if a function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0123] In this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0124] The above are only embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An IP packet forwarding method, characterized in that, The method is applied to an FPGA, and the method includes: Receiving a target packet, where the target packet is one of an IPv4 packet and an IPv6 packet; Determining a five-tuple of the target packet; Querying a session table of the target packet in a session table storage area of the FPGA based on the five-tuple of the target packet; Forwarding the target packet based on the session table of the target packet; Moreover, the session table storage area of the FPGA includes several storage blocks, each storage block is mapped to a hash address, and each storage block stores one or two session tables with hash address conflicts. Wherein, the data length of the hash address is 24 bits, each storage block has 4 storage entries, and the storage entry stores second information for distinguishing two session tables with hash address conflicts, and the second information is a reverse JHASH value generated by reversing the five-tuple of the target packet.

2. The method according to claim 1, wherein The querying the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet includes: Calculating a forward JHASH value based on the five-tuple of the target packet, where the data length of the forward JHASH value is 32 bits; Taking the lower 24 bits of the forward JHASH value as a lookup table address, and determining whether there is a hash address equal to the lookup table address in the session table storage area of the FPGA; When there is a hash address equal to the lookup table address in the session table storage area of the FPGA, using the session table mapped to the hash address as the session table of the target packet.

3. The method according to claim 2, characterized in that, The storage block also stores IP address conversion information, and before forwarding the target packet based on the session table of the target packet, the method further includes: Judging whether the target packet needs to perform address conversion based on the session table of the target packet; When the target packet needs to perform address conversion, replacing the destination IP address of the target packet based on the IP address conversion information.

4. The method according to claim 2, wherein When the target packet is an IPv4 packet, the session table of the target packet stores a source IP address and a destination IP address, where the data lengths of the source IP address and the destination IP address are both 32 bits; Moreover, when the target packet is an IPv4 packet, the session table of the target packet also stores first information and third information, where the first information is the high 8-bit data in the forward JHASH value, and the third information is a forward CRC32 value generated based on the five-tuple of the target packet, and the data lengths of the second information and the third information are both 32 bits.

5. The method according to claim 4, characterized in that The method further includes: When the storage block stores two session tables with hash address conflicts, determining the session table of the target packet based on the source IP address and the destination IP address; Or, determining the session table of the target packet based on the first information, the second information, and the third information.

6. The method according to claim 4, wherein The method further includes: When the session table of the target packet does not exist in the session table storage area of the FPGA, the target packet is sent to the CPU, so that the CPU constructs the session table of the target packet based on the middle layer and the forward JHASH value, the reverse JHASH value, and the forward CRC32 value carried in the target packet, and the CPU writes the session table of the target packet into the session table storage area of the FPGA through driving the upper-layer application.

7. An IP packet forwarding device, characterized in that, The device is applied to the FPGA, and the device includes: A receiving module, configured to receive a target packet, where the target packet is one of an IPV4 packet and an IPV6 packet; A determining module, configured to determine the five-tuple of the target packet; A querying module, configured to query the session table of the target packet in the session table storage area of the FPGA based on the five-tuple of the target packet; A forwarding module, configured to forward the target packet based on the session table of the target packet; Moreover, the session table storage area of the FPGA includes several storage blocks, each storage block is mapped to a hash address, each storage block stores one or two session tables with hash address conflicts, where the data length of the hash address is 24 bits, each storage block has 4 storage entries, and the storage entries store second information for differentiating two session tables with hash address conflicts, and the second information is the reverse JHASH value generated by reversing the five-tuple of the target packet.

8. An electronic device, characterized in that, Including: A processor; And A memory, configured to store machine-readable instructions, and when the instructions are executed by the processor, execute the IP packet forwarding method according to any one of claims 1-6.

9. A storage medium, characterized in that, The storage medium stores a computer program, and the computer program is executed by the processor to perform the IP packet forwarding method according to any one of claims 1-6.

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