Coincidence detection circuit and detection method for DTOF image sensor

Abstract

The present invention discloses a coincidence detection circuit and detection method for a DTOF image sensor, comprising a refreshable delay unit, a D flip-flop, and an AND logic gate circuit. The control end of the refreshable delay unit is connected to the reference clock output end of a delay-locked loop (DLPL), the signal output end of the refreshable delay unit is connected to the reset end of the D flip-flop, the output end of the D flip-flop is connected to the second input end of the refreshable delay unit in a feedback manner, and the output end of the D flip-flop is connected to the second input end of the AND logic gate via an inverter; a pulse signal stream is connected to the first input end of the refreshable delay unit, the clock sequence input end of the D flip-flop, and the first input end of the AND logic gate. This solution can improve the pass rate of the system's optical signal pulses while maintaining the pass rate of the ambient light noise signal, thereby improving the system's signal-to-noise ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of TOF image sensors and circuits, and in particular to a coincidence detection circuit and a detection method for a DTOF image sensor. Background Art

[0002] Image sensors have always been a hot topic in human research. With the development of contemporary science and technology, people have higher and higher requirements for traditional 2D image sensors. Not only do they expect higher resolution, faster speed, and larger dynamic range, but they also hope to obtain depth information of objects. However, two-dimensional imaging technology can no longer meet human needs, so three-dimensional imaging technology came into being.

[0003] A DTOF image sensor is a new type of 3D image sensor capable of high-precision, multi-point distance imaging at long distances, enabling 3D surface reconstruction of objects. It typically consists of a single-photon avalanche diode (SPAD) pixel array, a pixel front-end circuit, a time-to-digital converter (TDC), a timing control circuit, and some peripheral circuits. The pixel front-end circuit includes a quenching circuit, a monostable circuit, and a coincidence detection circuit. The coincidence detection circuit primarily utilizes the temporal correlation of infrared laser signals to suppress interference from ambient light sources, thereby improving the signal-to-noise ratio and enhancing maximum distance and accuracy.

[0004] Photon coincidence detection techniques, such as photon coincidence detection, adaptive sensitivity adjustment, smart accumulation, and active gating, can also suppress ambient light noise. However, compared to these techniques, photon coincidence detection is more effective and widely used. Mainstream coincidence detection circuits mostly use monostable circuits and different logic tree circuits to achieve different levels of coincidence detection. The current development direction of coincidence detection circuits is to more effectively suppress background light, preserve the system's optical signal, and further improve the signal-to-noise ratio.

[0005] The SPAD macro pixel consists of a small pixel containing 4 SPADs. Each pixel can work independently with the quenching circuit. When a light signal enters the SPAD pixel, it will cause the avalanche of the pixel PN junction and generate a pulse. After a period of reset (called dead time), the SPAD can continue to work. Therefore, in one working cycle of the system, the SPAD can be triggered multiple times.

[0006] The mechanism of the coincidence detection circuit is to use the time correlation between the reflected light signals of multiple SPADs at the same point on the target, while the triggers caused by ambient light do not have time correlation. Therefore, on the time axis, only the time corresponding to the distance between the object and the SPAD sensor (denoted as t1) has the pulse accumulation of the system laser source light signal. The rest of the time is the background light signal pulse that is randomly distributed with time. Therefore, the pulse density at t1 is largely greater than the pulse density at the rest of the time. The coincidence detection circuit can distinguish between the ambient light signal and the system light signal based on the different density of the pulses on the time axis, and set different signal pass rates according to the different pulse densities. In places where the pulses are dense on the real time axis, the signal pass rate is very high. On the contrary, in places where the pulses are sparse, the signal pass rate is low or even completely filtered out. In other words, the pass rate of the system light signal is greater than the pass rate of the ambient light, which improves the signal-to-noise ratio of the system.

[0007] The traditional coincidence detection method first sets a suitable time window (such as Figure 1 When the window signal is high, the window is opened. When the first pulse arrives, the time window is opened. If the detection level is set to 2, when the second pulse is detected in the window, the second pulse is allowed to pass (the first pulse is not passed). If the detection level is set to 3, when the third pulse is detected in the window, the third pulse is allowed to pass (although the second pulse is detected, it is blocked). And so on, the detection level can be 4, 5, 6, etc. Figure 1 The signals in the four cycles meet the detection levels of 2, 2, 3, and 4 respectively.

[0008] However, the traditional coincidence detection method uses a logic tree, which occupies a large chip area and is not conducive to high-density pixel arrangement. Therefore, it greatly limits the horizontal resolution of the DTOF sensor. In one cycle, the four SPAD pixel units of the macro pixel can generate up to four valid system light signal pulses. If a traditional coincidence detection circuit is used, these four pulses will only produce one pulse output after passing through the logic tree circuit. Although this circuit is very effective in filtering out ambient light signal pulses, it limits the throughput rate of the system light signal, greatly reducing the system's signal-to-noise ratio, and limiting the system's detection accuracy and distance.

[0009] For example, in related art, Chinese invention patent application publication number CN115498981A discloses a monostable circuit comprising: a monostable main circuit and a shielded time window circuit; wherein the monostable main circuit is configured to receive the input signal of the monostable circuit, feedback of the output signal of the monostable circuit, and a time window signal output by the shielded time window circuit through a NOR gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate. The time window signal is a signal that resists interference from abnormal pulses of the input signal on the output signal; the shielded time window circuit is configured to receive feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and a logic gate. However, this solution only addresses the problem of monostable circuits being falsely triggered by abnormal pulses of the input signal. Summary of the Invention

[0010] The technical problem to be solved by the present invention is how to increase the number of optical signal pulses in the system and improve the signal-to-noise ratio of the system.

[0011] The present invention solves the above technical problems through the following technical means:

[0012] A coincidence detection circuit for a DTOF image sensor is proposed. The circuit includes a refreshable delay unit, a D flip-flop, and an AND logic gate circuit. The control terminal of the refreshable delay unit is connected to the reference clock output terminal of a delay-locked loop (DLPL). The signal output terminal of the refreshable delay unit is connected to the reset terminal of the D flip-flop. The output terminal of the D flip-flop is connected to the second input terminal of the refreshable delay unit in a feedback manner. The output terminal of the D flip-flop is connected to the second input terminal of the AND logic gate via an inverter.

[0013] The pulse signal stream is connected to the first input terminal of the refreshable delay unit, the clock sequence input terminal of the D flip-flop and the first input terminal of the AND logic gate.

[0014] Furthermore, the refreshable delay unit includes a bias voltage generating circuit and an inverter cascade circuit, the input end of the bias voltage generating circuit is connected to the reference clock output end of the delay locked loop, and the output end of the bias voltage generating circuit is connected to the input end of the inverter cascade circuit; the output end of the inverter cascade circuit is connected to the reset end of the D trigger.

[0015] Furthermore, the bias voltage generating circuit includes an NMOS transistor NM1, a PMOS transistor PM1 and a PMOS transistor PM2, the reference clock output end of the delay locked loop is connected to the gate of the NMOS transistor NM1, the drain of the NMOS transistor NM1 is connected to the diode-connected PMOS transistor PM1, and the bias voltage PBIAS end of the PMOS transistor PM1 is connected to the power supply AVDD15 with a capacitor-connected PMOS transistor PM2.

[0016] Furthermore, the inverter cascade circuit includes a first-stage inverter and a third-stage inverter, wherein the first-stage inverter includes an NMOS transistor NM2, a PMOS transistor PM3, and a PMOS transistor PM4;

[0017] The bias voltage PBIAS terminal of the bias voltage generating circuit is connected to the gate of the PMOS transistor PM3, the source of the PMOS transistor PM3 is connected to the power supply, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM4, the pulse signal stream is connected to the gate of the NMOS transistor NM2, and the output terminal of the D trigger is connected to the gate of the PMOS transistor PM4;

[0018] The drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2 are connected and then connected to a three-stage inverter, and the output end of the three-stage inverter is connected to the reset end of the D flip-flop.

[0019] Furthermore, each inverter in the three-stage inverter includes an NMOS tube and a PMOS tube, the source of the PMOS tube is connected to the power supply, the gate of the PMOS tube is connected to the gate of the NMOS tube and then connected to the upper-stage inverter, and the drain of the PMOS tube is connected to the drain of the NMOS tube and then connected to the lower-stage inverter.

[0020] Furthermore, the D flip-flop adopts a TSPC type D flip-flop, and the D terminal of the D flip-flop is always at 0 potential.

[0021] In addition, the present invention also proposes a DTOF image sensor, including the coincidence detection circuit as described above, the first input end of the refreshable delay unit, the clock sequence input end of the D flip-flop and the first input end of the AND logic gate are all connected to the pulse output end of the monostable circuit, and the output end of the AND logic gate circuit is connected to the time-to-digital converter.

[0022] In addition, the present invention also proposes a control method for a coincidence detection circuit of a DTOF image sensor, the method comprising:

[0023] Utilizing the delay locked loop to control the refreshable delay unit to generate time windows corresponding to different delay times;

[0024] The refreshable delay unit receives the pulse signal stream, the high level of the pulse signal causes the refreshable delay unit to reset and the signal output terminal thereof outputs a reset signal of high potential;

[0025] The D flip-flop receives the pulse signal stream after the refreshable delay unit outputs a reset signal at a high level, and when a falling edge of the pulse signal stream arrives, the D flip-flop transmits a low level to its output terminal so that the second input terminal of the refreshable delay unit is at a low level;

[0026] After the corresponding time window has passed, the signal output terminal of the refreshable delay unit outputs a low level, so that the output terminal of the D flip-flop outputs a high level;

[0027] During the duration of the single low level output of the D flip-flop, the low level controls the AND logic gate to be turned on via the inverter, so that the pulse signal flow is output through the AND logic gate.

[0028] Furthermore, the method further comprises:

[0029] During the duration of the single low-level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, each node of the refreshable delay unit is reset to the initial state at the start of the time window, until the output of the D flip-flop is reset to a high level after another time window from the start of the next pulse;

[0030] Outside the duration of the low level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, the refreshable delay unit regenerates a time window.

[0031] Furthermore, the method of controlling the refreshable delay unit by using the delay locked loop to generate time windows corresponding to different delay times includes:

[0032] The bias voltage generating circuit generates a bias voltage based on a control signal generated by the delay locked loop;

[0033] The bias voltage is copied to the inverter cascade circuit to control the delay size of the first-stage inverter;

[0034] The gate of the PMOS transistor PM4 in the inverter cascade circuit serves as the second input terminal of the refreshable delay unit. When receiving a falling edge of the current, the PMOS transistor PM4 is turned on, and the copied current slowly charges the output node of the first-stage inverter. After a corresponding time window, the output is a low level through the three-stage inverter.

[0035] The gate of the NMOS tube NM2 in the inverter cascade circuit serves as the first input end of the refreshable delay unit. When receiving the rising edge of the pulse signal stream, the output node of the first-stage inverter is quickly discharged, and after reset, a high level is output through the three-stage inverter.

[0036] The advantages of the present invention are:

[0037] (1) The refreshable delay unit in the present invention generates a fixed delay signal when a pulse in the pulse signal stream arrives. This delay is called a time window. When the first pulse arrives, the output terminal Vout_D of the D flip-flop changes from high potential 1 to low potential 0 and then to high potential 1. The duration of low level 0 is a fixed delay, which is the time window. During the time period when the time window is open, the low level 0 signal of the D flip-flop is converted to high level 1 through an inverter, so that the second input terminal signal of the AND logic gate is 1, and the AND logic gate is turned on. During this period, the pulse signal stream can be output through the output terminal of the AND logic gate. Since the first pulse is a falling edge trigger at the input terminal of the D flip-flop, when it reaches the input of the AND logic gate, the AND logic gate has not yet been turned on. When the time window is opened, it itself has been extinguished. Therefore, the pulses in the newly opened window cannot pass through. Only the next pulse that arrives within the time window when the previous pulse is opened can pass through. Therefore, this solution can improve the pass rate of the system's optical signal pulses, while the pass rate of the ambient light noise signal remains unchanged, thereby improving the system's signal-to-noise ratio. The improvement of the system's signal-to-noise ratio helps to increase the system's maximum detectable distance and also helps to improve the system's detection accuracy at a certain distance.

[0038] (2) The output signal of the delayed phase-locked loop can be used to precisely control the delay of the refreshable delay unit, giving it excellent PVT characteristics.

[0039] (3) By adjusting the size of the time window, the level of compliance detection can be more conveniently changed, and it can be applied under different levels of ambient light signal intensity.

[0040] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a schematic diagram of the traditional coincidence detection function mentioned in the background technology section of the present invention;

[0042] Figure 2 1 is a schematic structural diagram of a coincidence detection circuit for a DTOF image sensor according to an embodiment of the present invention;

[0043] Figure 31 is a timing diagram of key operating signals of a coincidence detection circuit for a DTOF image sensor according to an embodiment of the present invention;

[0044] Figure 4 1 is a schematic structural diagram of a refreshable delay unit according to an embodiment of the present invention;

[0045] Figure 5 1 is a flow chart of a control method for a coincidence detection circuit of a DTOF image sensor proposed in one embodiment of the present invention. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] like Figure 2 As shown, the first embodiment of the present invention provides a coincidence detection circuit for a DTOF image sensor, the circuit comprising: a refreshable delay unit, a D flip-flop, and an AND logic gate circuit, wherein the control end of the refreshable delay unit is connected to the reference clock output end of a delay-locked loop, the signal output end of the refreshable delay unit is connected to the reset end of the D flip-flop, the output end of the D flip-flop is connected to the second input end of the refreshable delay unit in a feedback manner, and the output end of the D flip-flop is connected to the second input end of the AND logic gate via an inverter;

[0048] The pulse signal stream is connected to the first input terminal of the refreshable delay unit, the clock sequence input terminal of the D flip-flop and the first input terminal of the AND logic gate.

[0049] It should be noted that in this embodiment, the pulse signal stream Vpulse_in input to the refreshable delay unit, D flip-flop, and AND logic gate is a pulse signal stream with the same pulse width after being processed by a monostable circuit; these pulse signal streams belong to the four SPAD sub-pixels in a macro pixel (the pulse signal pulses of all SPAD pixels have a pulse width of 300ps after passing through the monostable circuit). This pulse signal stream is connected to the first input terminal Vin_n of the refreshable delay unit, the clock sequence input terminal CLK of the D flip-flop, and the first input terminal Vin1 of the AND logic gate; the delay of the refreshable delay unit can be controlled by the VCT signal output by the delay-locked loop DLL, corresponding to time windows with different delay times.

[0050] The output terminal Vout_refresh of the refreshable delay unit is connected to the RESET input terminal of the TSPC type D flip-flop. The output terminal Vout_D of the TSPC type D flip-flop is connected to the Vin_p input terminal of the refreshable delay unit in a feedback manner. The Vout_D signal is connected to the Vin1 input terminal of the AND logic gate after passing through an inverter. Finally, the output Vpulse_out of the AND logic gate is used as the output of this module for use by the subsequent TDC circuit.

[0051] The refreshable delay unit generates a fixed delay signal when a pulse signal P1 arrives. This delay is called the time window t1. When the next pulse signal P2 arrives within this time window t1, the delay starts again. When the pulse signal P2 arrives outside this time window, similar to the pulse signal P1, the pulse signal P2 also generates a fixed delay signal.

[0052] The D flip-flop uses a TSPC-type D flip-flop. When a falling edge is detected at the clock sequence input terminal CLK of the D flip-flop and the reset terminal RESET signal is high, that is, 1, the D terminal signal is transmitted to the output terminal, and the D terminal of the D flip-flop is always at 0 potential. When the RESET terminal receives the reset signal 0, its output port is reset to 1. When the AND logic gate receives a signal of 1 at the first input terminal vin1, it is in the open state, allowing the second input terminal Vin2 signal to be output to Vout. Otherwise, the AND logic gate is closed, the Vin2 signal is blocked, and the signal at the Vin2 port is extinguished.

[0053] The high level of the pulse current signal Vpulse_in causes the refreshable delay unit to quickly reset. After the reset, its output Vout_refresh is 1. This signal does not reset the D flip-flop. At the same time, the pulse signal Vpulse_in is also connected to the CLK input terminal of the D flip-flop. When the falling edge of the pulse signal Vpulse_in arrives (before the falling edge of the Vpulse_in signal arrives, the Vout_refresh signal has been reset to 1), the D flip-flop transmits a 0 potential to its Vout_D terminal. The Vout_D signal causes the Vin_p of the refreshable delay unit to be a low potential of 0. After a certain fixed delay (window time t1), the refreshable delay unit output Vout_refresh is 0, causing the D flip-flop output Vout_D to be reset to 1.

[0054] Therefore, when the first pulse arrives, the output terminal Vout_D of the D flip-flop changes from high level 1 to low level 0 and then to high level 1. The duration of low level 0 is a fixed delay, which is the window time t1. During this window time, if a second pulse arrives (such as Figure 3In the second cycle), the second pulse can quickly reset each node of the refreshable delay unit to the initial state of the window start timing, thereby restarting the timing until the D flip-flop output is reset to 1 after another window time t1 from the second pulse. The total time t2 of the time window opening is equal to the new window time t1 opened by the second pulse plus the time t3 from the second pulse to the first pulse. Therefore, the second pulse arriving within the time window opened by the first pulse realizes the refresh of the time window. Similarly, if the third pulse arrives within the time window opened by the second pulse, it will continue to refresh the time window. If the subsequent pulse is outside the time window, a new time window will be opened as the first pulse did.

[0055] During the open time window, the D flip-flop's low-level 0 signal is converted to a high-level 1 through an inverter, causing one input, Vin2, of the AND logic gate to be 1, turning the AND logic gate on. During this time, the Vpulse_in pulse can pass through the AND logic gate and reach the Vpulse_out output. Since the first pulse that opens the time window is falling-edge-triggered at the D flip-flop input, it reaches the AND logic gate before it is open. By the time the time window opens, it has already extinguished itself, and pulses in the newly opened window cannot pass through. Only the next pulse arriving within the previous pulse's open time window can pass. Therefore, if there are four closely spaced pulses, this system can allow the last three of the four pulses to pass. This solution allows more of the system light signal to pass at the time the system light signal arrives. At other times when background light triggers a pulse, this solution performs similarly to a conventional detection method with a compliance level of 2, ultimately improving the signal-to-noise ratio.

[0056] In one embodiment, if Figure 4 As shown, the refreshable delay unit includes a bias voltage generating circuit and an inverter cascade circuit, the input end of the bias voltage generating circuit is connected to the reference clock output end of the delay locked loop, and the output end of the bias voltage generating circuit is connected to the input end of the inverter cascade circuit; the output end of the inverter cascade circuit is connected to the reset end of the D trigger.

[0057] In one embodiment, the bias voltage generating circuit includes an NMOS transistor NM1, a PMOS transistor PM1, and a PMOS transistor PM2. The reference clock output terminal of the delay-locked loop is connected to the gate of the NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the diode-connected PMOS transistor PM1. The bias voltage PBIAS terminal of the PMOS transistor PM1 is connected to the power supply AVDD15 via the capacitor-connected PMOS transistor PM2.

[0058] In one embodiment, the inverter cascade circuit includes a first-stage inverter and a third-stage inverter, wherein the first-stage inverter includes an NMOS transistor NM2, a PMOS transistor PM3, and a PMOS transistor PM4;

[0059] The bias voltage PBIAS terminal of the bias voltage generating circuit is connected to the gate of the PMOS transistor PM3, the source of the PMOS transistor PM3 is connected to the power supply, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM4, the pulse signal stream is connected to the gate of the NMOS transistor NM2, and the output terminal of the D trigger is connected to the gate of the PMOS transistor PM4;

[0060] The drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2 are connected and then connected to a three-stage inverter, and the output end of the three-stage inverter is connected to the reset end of the D flip-flop.

[0061] In one embodiment, each inverter in the three-stage inverter includes an NMOS transistor and a PMOS transistor, the source of the PMOS transistor is connected to a power supply, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and then connected to the upper-stage inverter, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor and then connected to the lower-stage inverter.

[0062] Specifically, if Figure 4 As shown, the three-stage inverter includes NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, and PMOS transistors PM5, PMOS transistors PM6, and PMOS transistors PM7; wherein the source of the PMOS transistor PM5 is connected to a power supply, the gate of the PMOS transistor PM5 is connected to the gate of the NMOS transistor NM3 and then connected to an upper-stage inverter, and the drain of the PMOS transistor PM5 is connected to the drain of the NMOS transistor NM3 and then connected to a lower-stage inverter; the source of the PMOS transistor PM6 is connected to a power supply, the gate of the PMOS transistor PM56 is connected to the gate of the NMOS transistor NM4 and then connected to an upper-stage inverter, and the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM4 and then connected to a lower-stage inverter; the source of the PMOS transistor PM7 is connected to a power supply, the gate of the PMOS transistor PM7 is connected to the gate of the NMOS transistor NM5 and then connected to an upper-stage inverter, and the drain of the PMOS transistor PM7 is connected to the drain of the NMOS transistor NM5 and then connected to a lower-stage inverter.

[0063] Specifically, the working principle of the refreshable delay unit is as follows: the DLL_vctl signal output by the delay phase-locked loop is connected to the gate of the NMOS tube NM1 to control the circuit current. The drain of the NM1 tube is connected to a diode-connected PMOS tube PM1, through which a bias voltage PBIAS is generated. At the same time, a capacitor-connected PMOS tube PM2 is connected between the PBIAS terminal and the power supply AVDD15.

[0064] By applying PBIAS to the gate of the PMOS transistor PM3 in the cascaded inverter circuit, this current is copied to the branch containing PM3. The source of the PMOS transistor PM3 is connected to the power supply AVDD15, and the drain of PM3 is connected to the source of the first-stage inverter PM4. The copied current is used to control the delay of the first-stage inverter. The gate of the first-stage inverter NM2 is connected to the signal Vin_n, and PM4 is connected to the signal Vin_p. Subsequently, three consecutive inverters are connected after the first-stage inverter (these three inverters do not have PMOS transistors to control the current), and the final output is the Vout_refresh voltage signal.

[0065] When Vin_p encounters a falling edge, PMOS transistor PM4 turns on, replicating the current to slowly charge the output node of the first-stage inverter, thereby controlling the falling edge to produce a precise delay. After a period t1 (this time is mainly determined by the charging time of the first-stage node), Vout_refresh output is 0. When Vin_n receives a rising edge, NMOS transistor NM2 turns on and begins to rapidly discharge the output node of the first-stage inverter, achieving a quick reset effect on the circuit. After the reset, Vout_refresh output is 1.

[0066] If a second pulse arrives within the time window of the previous pulse (within this time window, the first-level node is still charging and has not reached the flip threshold of the next-level inverter, so the module output Vout_refresh is temporarily 1), all nodes of this module will be restored to the state at the beginning of charging, thereby clearing the charged power. Charging will start again after the second pulse, and it will still take t1 time for the Vout_refresh output to be 0, thereby achieving the refresh of the delay due to the pulse arriving within the window.

[0067] It should be noted that by adjusting the input reference clock frequency of the DLL and adjusting the window time size with an appropriate amplitude, corresponding optimization processing can be performed for ambient light of different intensities to achieve the maximum signal-to-noise ratio, further improving the detection distance and accuracy of the system.

[0068] In addition, the second embodiment of the present invention also proposes a DTOF image sensor, including the coincidence detection circuit as described in the first embodiment above, the first input end of the refreshable delay unit, the clock sequence input end of the D flip-flop and the first input end of the AND logic gate are all connected to the pulse output end of the monostable circuit, and the output end of the AND logic gate circuit is connected to the time-to-digital converter.

[0069] It should be noted that the DTOF image sensor of the present invention adopts the coincidence detection circuit proposed in the above-mentioned first embodiment. The technical features and technical effects thereof are referred to in the above-mentioned first embodiment, and are not repeated here.

[0070] In addition, if Figure 5 As shown, the third embodiment of the present invention provides a control method for a coincidence detection circuit of a DTOF image sensor, the method comprising the following steps:

[0071] S10, using the delay locked loop to control the refreshable delay unit to generate time windows corresponding to different delay times;

[0072] S20, the refreshable delay unit receives the pulse signal stream, the high level of the pulse signal resets the refreshable delay unit and the signal output terminal thereof outputs a reset signal at a high level;

[0073] S30, the D flip-flop receives the pulse signal stream after the refreshable delay unit outputs the reset signal at a high level, and when the falling edge of the pulse signal stream arrives, the D flip-flop transmits a low level to its output terminal so that the second input terminal of the refreshable delay unit is at a low level;

[0074] S40, after a corresponding time window has passed, the signal output terminal of the refreshable delay unit outputs a low level, so that the output terminal of the D flip-flop outputs a high level;

[0075] S50. During the duration of the single low level output of the D flip-flop, the low level controls the AND logic gate to be turned on via the inverter, so that the pulse signal stream is output through the AND logic gate.

[0076] In this embodiment, during the time window when the time window is open, the low-level 0 signal of the D flip-flop is converted to a high-level 1 through an inverter, causing one input, Vin2, of the AND logic gate to be 1, turning the AND logic gate on. During this time, the Vpulse_in pulse can pass through the AND logic gate to reach the Vpulse_out terminal for output. Since the first pulse that opens the time window is triggered by a falling edge at the input of the D flip-flop, when it reaches the input of the AND logic gate, the AND logic gate has not yet opened. By the time the time window opens, it has already extinguished itself. Therefore, pulses in the newly opened window cannot pass through. Only the next pulse that arrives within the time window of the previous pulse can pass through. Therefore, if there are four pulses that are very close to each other, this system can allow the last three of the four pulses to pass. At the time when the system light signal arrives, this solution allows more system light signals to pass. At other times when the background light triggers the pulse, this solution has a similar effect to the traditional detection method with a normal compliance level of 2, ultimately improving the signal-to-noise ratio.

[0077] In one embodiment, the method further comprises the following steps:

[0078] During the duration of the single low-level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, each node of the refreshable delay unit is reset to the initial state at the start of the time window, until the output of the D flip-flop is reset to a high level after another time window from the start of the next pulse;

[0079] Outside the duration of the low level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, the refreshable delay unit regenerates a time window.

[0080] In one embodiment, the step S10 of controlling the refreshable delay unit by using the delay locked loop to generate time windows corresponding to different delay times includes:

[0081] The bias voltage generating circuit generates a bias voltage based on a control signal generated by the delay locked loop;

[0082] The bias voltage is copied to the inverter cascade circuit to control the delay size of the first-stage inverter;

[0083] The gate of the PMOS transistor PM4 in the inverter cascade circuit serves as the second input terminal of the refreshable delay unit. When receiving a falling edge of the current, the PMOS transistor PM4 is turned on, and the copied current slowly charges the output node of the first-stage inverter. After a corresponding time window, the output is a low level through the three-stage inverter.

[0084] The gate of the NMOS tube NM2 in the inverter cascade circuit serves as the first input end of the refreshable delay unit. When receiving the rising edge of the pulse signal stream, the output node of the first-stage inverter is quickly discharged, and after reset, a high level is output through the three-stage inverter.

[0085] This embodiment can adjust the input reference clock frequency of the DLL and the size of the window time with an appropriate amplitude, so that corresponding optimization processing can be performed for ambient light of different intensities to achieve the maximum signal-to-noise ratio, further improving the detection distance and accuracy of the system.

[0086] It should be noted that the control method of the coincidence detection circuit of the DTOF image sensor described in the present invention corresponds to the coincidence detection circuit proposed in the first embodiment above. The technical features and technical effects thereof can be found in the first embodiment above, and will not be repeated here.

[0087] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0089] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A coincidence detection circuit for a DTOF image sensor, characterized in that: The circuit includes: a refreshable delay unit, a D flip-flop, and an AND logic gate circuit, wherein the control end of the refreshable delay unit is connected to the reference clock output end of the delay locked loop, the signal output end of the refreshable delay unit is connected to the reset end of the D flip-flop, the output end of the D flip-flop is connected to the second input end of the refreshable delay unit in a feedback manner, and the output end of the D flip-flop is connected to the second input end of the AND logic gate via an inverter; The pulse signal stream is connected to the first input terminal of the refreshable delay unit, the clock sequence input terminal of the D flip-flop and the first input terminal of the AND logic gate.

2. The coincidence detection circuit for a DTOF image sensor according to claim 1, wherein: The refreshable delay unit includes a bias voltage generating circuit and an inverter cascade circuit, the input end of the bias voltage generating circuit is connected to the reference clock output end of the delay locked loop, and the output end of the bias voltage generating circuit is connected to the input end of the inverter cascade circuit; the output end of the inverter cascade circuit is connected to the reset end of the D flip-flop.

3. The coincidence detection circuit for a DTOF image sensor according to claim 2, wherein: The bias voltage generating circuit includes an NMOS transistor NM1, a PMOS transistor PM1 and a PMOS transistor PM2. The reference clock output end of the delay-locked loop is connected to the gate of the NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the diode-connected PMOS transistor PM1. The bias voltage PBIAS end of the PMOS transistor PM1 is connected to the power supply AVDD15 with a capacitor-connected PMOS transistor PM2.

4. The coincidence detection circuit for a DTOF image sensor according to claim 2, wherein: The inverter cascade circuit includes a first-stage inverter and a third-stage inverter, wherein the first-stage inverter includes an NMOS transistor NM2, a PMOS transistor PM3, and a PMOS transistor PM4; The bias voltage PBIAS terminal of the bias voltage generating circuit is connected to the gate of the PMOS transistor PM3, the source of the PMOS transistor PM3 is connected to the power supply, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM4, the pulse signal stream is connected to the gate of the NMOS transistor NM2, and the output terminal of the D trigger is connected to the gate of the PMOS transistor PM4; The drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2 are connected and then connected to a three-stage inverter, and the output end of the three-stage inverter is connected to the reset end of the D flip-flop.

5. The coincidence detection circuit for a DTOF image sensor according to claim 4, wherein: Each inverter in the three-stage inverter includes an NMOS tube and a PMOS tube. The source of the PMOS tube is connected to the power supply, the gate of the PMOS tube is connected to the gate of the NMOS tube and then connected to the upper inverter, and the drain of the PMOS tube is connected to the drain of the NMOS tube and then connected to the lower inverter.

6. The coincidence detection circuit for a DTOF image sensor according to claim 1, wherein: The D flip-flop adopts a TSPC type D flip-flop, and the D terminal of the D flip-flop is always at 0 potential.

7. A DTOF image sensor, characterized in that: The coincidence detection circuit comprises the coincidence detection circuit according to any one of claims 1 to 6, wherein the first input terminal of the refreshable delay unit, the clock sequence input terminal of the D flip-flop, and the first input terminal of the AND logic gate are all connected to the pulse output terminal of the monostable circuit, and the output terminal of the AND logic gate circuit is connected to a time-to-digital converter.

8. A control method for a coincidence detection circuit of a DTOF image sensor according to any one of claims 1 to 6, characterized in that: The method comprises: Utilizing the delay locked loop to control the refreshable delay unit to generate time windows corresponding to different delay times; The refreshable delay unit receives the pulse signal stream, the high level of the pulse signal causes the refreshable delay unit to reset and the signal output terminal thereof outputs a reset signal of high potential; The D flip-flop receives the pulse signal stream after the refreshable delay unit outputs a reset signal at a high level, and when a falling edge of the pulse signal stream arrives, the D flip-flop transmits a low level to its output terminal so that the second input terminal of the refreshable delay unit is at a low level; After the corresponding time window has passed, the signal output terminal of the refreshable delay unit outputs a low level, so that the output terminal of the D flip-flop outputs a high level; During the duration of the single low level output of the D flip-flop, the low level controls the AND logic gate to be turned on via the inverter, so that the pulse signal flow is output through the AND logic gate.

9. The control method for a coincidence detection circuit of a DTOF image sensor according to claim 8, wherein: The method further comprises: During the duration of the single low-level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, each node of the refreshable delay unit is reset to the initial state at the start of the time window, until the output of the D flip-flop is reset to a high level after another time window from the start of the next pulse; Outside the duration of the low level output of the D flip-flop, when the refreshable delay unit receives the next pulse signal stream, the refreshable delay unit regenerates a time window.

10. The control method for a coincidence detection circuit of a DTOF image sensor according to claim 8, wherein: The method of using the delay locked loop to control the refreshable delay unit to generate time windows corresponding to different delay times includes: The bias voltage generating circuit generates a bias voltage based on a control signal generated by the delay locked loop; The bias voltage is copied to the inverter cascade circuit to control the delay size of the first-stage inverter; The gate of the PMOS transistor PM4 in the inverter cascade circuit serves as the second input terminal of the refreshable delay unit. When receiving a falling edge of the current, the PMOS transistor PM4 is turned on, and the copied current slowly charges the output node of the first-stage inverter. After a corresponding time window, the output is a low level through the three-stage inverter. The gate of the NMOS tube NM2 in the inverter cascade circuit serves as the first input end of the refreshable delay unit. When receiving the rising edge of the pulse signal stream, the output node of the first-stage inverter is quickly discharged, and after reset, a high level is output through the three-stage inverter.

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