Coaxial perspective inspection system

Abstract

Aspects of the present disclosure provide an inspection system that can include an imaging module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam and image a first pattern located on a front side of the wafer to form a first image. The second light beam can image a second pattern located below the first pattern via quantum tunneling imaging or infrared transmission imaging to form a second image. The second light beam can have a power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate overlay values of the first pattern and the second pattern and / or calculate defects of the wafer.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims the benefit of U.S. Provisional Application No. 63 / 066,779, filed August 17, 2020, entitled “Method for Producing Overlay Results with Absolute Reference for Semiconductor Manufacturing,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to methods for manufacturing semiconductor devices, and specifically to overlay errors. Background Technology

[0004] Semiconductor manufacturing involves several different steps and processes. One typical manufacturing process is called photolithography (also known as microlithography). Photolithography uses radiation such as ultraviolet or visible light to create intricate patterns in the design of semiconductor devices. Many types of semiconductor devices, such as diodes, transistors, and integrated circuits, can be constructed using semiconductor manufacturing techniques including photolithography, etching, film deposition, surface cleaning, metallization, and more. Summary of the Invention

[0005] This disclosure provides an inspection system. For example, the inspection system may include an imaging module and processing circuitry. The imaging module can image a wafer using a first beam and a second beam coaxially aligned with the first beam. The first beam can image a first pattern located on the front side of the wafer to form a first image. The second beam can image a second pattern located below the first pattern to form a second image and has power sufficient to penetrate at least a portion of the wafer's thickness and reach the second pattern. The processing circuitry can perform image analysis on the first and second images to calculate at least one overlay value of the first and second patterns and inspect for defects in the wafer. In embodiments, the second pattern may include a radioactive or fluorescent material. In embodiments, the second pattern may include at least one of dots, lines, corners, boxes, triangles, numbers, and markings.

[0006] In one embodiment, the second pattern can be incorporated into a reference plate located beneath the wafer. For example, the reference plate can be placed on or adhered to the back side of the wafer. As another example, the reference plate can be incorporated into the substrate support of a lithography scanner or stepper. In another embodiment, the second pattern can be projected onto the surface of the wafer.

[0007] In one embodiment, the second pattern may be formed on the back side of the wafer, and the second beam may have sufficient power to penetrate the entire thickness of the wafer and reach the second pattern. In another embodiment, the second pattern may be embedded within the wafer.

[0008] In an embodiment, the second wavelength may have a longer wavelength than the first wavelength of the first beam. 10. For example, the first wavelength may be from 50 nanometers to 400 nanometers, and the second wavelength may be from 1 micrometer to 10 micrometers. As another example, the first wavelength may be 266 nanometers, and the second wavelength may be 3.6 micrometers or 3.7 micrometers.

[0009] In an embodiment, the inspection system may further include an ultraviolet (UV) light source and an infrared (IR) light source, the UV light source being configured to generate a first beam and the IR light source being configured to generate a second beam. For example, the second pattern may be imaged via quantum tunneling imaging or IR transmission imaging.

[0010] In one embodiment, the second pattern may be coaxially aligned with the wafer.

[0011] In one embodiment, the processing circuit can perform image analysis by identifying the coordinate position of the first pattern relative to the second pattern as an overlay value.

[0012] As can be understood, as manufacturing progresses on a given wafer, there can be many different materials and layers depending on the given device being produced. Therefore, each wafer may have a different profile at each stage of the process. This means that different wavelengths may be required to penetrate the wafer.

[0013] Of course, for clarity, the order in which the different steps described herein are discussed has been presented. Generally, these steps can be performed in any suitable order. Furthermore, although each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that each concept can be implemented independently of or in combination with each other. Therefore, this disclosure can be implemented and viewed in many different ways.

[0014] It should be noted that the Summary of this invention does not specify every embodiment and / or additional novel aspect of this disclosure or the claimed disclosure. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding novel points that outperform conventional techniques. For additional details and / or possible perspectives regarding this disclosure and embodiments, the reader should refer to the Detailed Description of this disclosure and the corresponding drawings, which are further discussed below. Attached Figure Description

[0015] Various embodiments of this disclosure will be described in detail by way of example with reference to the following accompanying drawings, wherein the same reference numerals refer to the same elements, and in the drawings:

[0016] Figure 1A This illustrates the industrial problems associated with overlay engraving;

[0017] Figure 1B Overlay relief implemented using exemplary reference patterns according to some embodiments of this disclosure is shown;

[0018] Figure 2 This is a functional block diagram of an exemplary imaging system according to some embodiments of this disclosure;

[0019] Figure 3 It is by Figure 2 A magnified view of a portion of a coaxially aligned beam generated by an exemplary imaging system;

[0020] Figure 4A An enlarged top view of an overlay image of a portion of a wafer according to some embodiments of this disclosure is shown, the overlay images being created by... Figure 2 The first image capturing device and the second image capturing device of the exemplary imaging system capture Figure 4B Exemplary image analysis is shown for overlay calculations using absolutely independent reference patterns, according to some embodiments of this disclosure;

[0021] Figure 5 This is a flowchart illustrating exemplary imaging methods according to some embodiments of this disclosure; and

[0022] Figure 6 This is a functional block diagram of an exemplary inspection system according to some embodiments of this disclosure. Detailed Implementation

[0023] According to this disclosure, an imaging method is provided that uses an absolutely independent reference pattern as an alignment marker to align a feature pattern with, rather than with, a previous pattern. The feature pattern may be formed on the front side of a wafer, and the reference pattern is independent of the front side of the wafer. For example, the reference pattern may be formed inside or beneath the wafer. A first beam of a first wavelength (e.g., an ultraviolet (UV) beam) may be used to image the feature pattern formed on a first side of the wafer, while a second beam of a second wavelength (e.g., an infrared (IR) beam) may be used to image the reference pattern formed inside or beneath the wafer. In embodiments, the second beam may be coaxially aligned with the first beam. When the reference pattern is formed inside or beneath the wafer, in order to image the reference pattern, the second beam must "see through" a portion or the entire thickness of the wafer. For example, the second beam may have sufficient power or intensity to penetrate a portion or the entire thickness of the wafer (depending on whether the reference pattern is formed inside or beneath the wafer) to capture an image of the reference pattern using quantum tunneling imaging, IR transmission imaging, etc. Therefore, the UV image of the feature pattern and the IR image of the reference pattern can be captured on the same optical axis and superimposed on each other. Image analysis can then be performed for exposure, inspection, alignment, or other processing. Although the UV and IR images are captured coaxially, the transfer to the image detector can be coaxial or non-coaxial. For example, the coaxially captured images can be optically separated and transferred to a separate image detector, as discussed below.

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Further, for ease of description, spatially related terms such as “top,” “bottom,” “below,” “under,” “lower,” “above,” “upper”, etc., may be used herein to describe the relationship of one element or feature as shown in the figures to other elements(s)(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially related descriptors used herein may also be interpreted accordingly.

[0025] For clarity, the order in which the different steps described herein are discussed has been presented. Generally, these steps can be performed in any suitable order. Furthermore, although each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that each concept can be implemented independently of or in combination with each other. Therefore, this disclosure can be implemented and viewed in many different ways.

[0026] Microfabrication involves forming and processing multiple films and layers on a wafer. This can include dozens or more films stacked on the wafer. Applying patterns to the wafer to obtain various films and layers requires alignment with previously formed patterns. Traditionally, this alignment is achieved by forming alignment marks and scribing on a portion of the wafer. However, the inventors have recognized that various film deposition, etching, and processing techniques sometimes cover, and even completely remove, the alignment marks. Because the alignment marks are sometimes covered or missing, errors can occur when applying subsequent patterns on the wafer. The term overlay or overlay error refers to the placement difference of a given pattern relative to a previously placed pattern. Because alignment marks are often disrupted, overlay errors can accumulate with the addition of layers, potentially leading to poor performance and device errors.

[0027] Figure 1A This paper illustrates an industrial problem related to overlay. Each arrow in this paper has a starting point (e.g., 111A, 111B, 121A, and 131A) corresponding to the position of the previous pattern and an endpoint or arrow cluster (e.g., 111A', 111N', 121N') corresponding to the position of the subsequent pattern. Therefore, each arrow represents an overlay value or overlay error when the subsequent pattern is formed above or alongside the corresponding previous pattern. For example, in process 110A, there is no grid or reference plate when the initial pattern is placed. Therefore, the starting point 111A of the first arrow may be misaligned; that is, the initial pattern may have a placement error, for example, relative to the wafer edge. Subsequent patterns then attempt to align based on the corresponding previous pattern. Figure 1AAs shown, the starting point of the subsequent arrow (e.g., 111B) overlaps with the arrow cluster of the corresponding previous arrow or the preceding arrow (e.g., 111A'). In some embodiments, degradation of the alignment marks may result in alignment errors in subsequent patterns placed using such degraded alignment marks. It should be noted that walkouts can still occur even in theoretically perfect systems. For example, if the system pattern placement tolerance is + / -4 nm, and each level references the previous level, taking the reference level as 0 error, then the first layer may deviate by +4 nm. The alignment of the second layer with the first layer may deviate by +4 nm, meaning the second layer is now deviated by +8 nm from the reference level. Throughout the manufacturing process, there are also process factors that cause or mitigate stress, which can lead to walkouts / alignment shifts even if the original alignment marks are visible, potentially increasing cumulative errors.

[0028] Furthermore, the alignment mark may be damaged in step S120 of the manufacturing process and then repositioned without a reference mark. Deterioration of the alignment mark can lead to the accumulation of alignment errors in subsequent processing. Similar to starting point 111A, the starting point 121A of the new arrow may be misaligned. Figure 1A In the example, the starting point 121A is offset from the arrow cluster 111N'. This process is performed by aligning the subsequent pattern based on the corresponding previous pattern until the alignment mark is broken again at step S130. Similarly, placement is performed without a reference mark, and the starting point 131A is offset from the arrow cluster 121N'. Figure 1A As can be seen, as the number of layers increases, overlay errors may accumulate, leading to poor manufacturing yield, device errors, etc. It should be noted that process 110A is a non-limiting example. Other processes (e.g., 110B and 110C) may have different overlay values ​​(different arrows) and / or different steps.

[0029] Figure 1B Overlay relief implemented using exemplary reference patterns according to some embodiments of this disclosure is illustrated. Utilizing the techniques herein, all patterns (e.g., patterns with a starting point 141A) placed on the front (or working) side 191 of wafer 190 are based on the same reference pattern 102. In embodiments, the reference pattern 102 may be located below the front side 191 of wafer 190. For example, the reference pattern 102 may be formed on or incorporated into the back side 192 of wafer 190. As another example, the reference pattern 102 may be incorporated into a reference board (…). Figure 1B (not shown in the image) and the reference plate can be located below wafer 190, placed on the back side 192 of wafer 190 or adhered to the back side, or combined with a substrate holder for holding wafer 190 in a photolithography scanner or stepper. Figure 1B(Not shown in the image). In other words, the reference pattern 102 is unaffected by photolithography processes such as etching, deposition, and chemical mechanical polishing, which are performed on the front side 191 of the wafer 190 to form the pattern. Therefore, the reference pattern 102 is independent of the front side 191 of the wafer 190 and will remain intact during the photolithography process of the wafer 190. Thus, the reference pattern 102 can be used and is considered absolute, or independent of any pattern formed on the front side 191 of the wafer 190, and will not be changed by the various deposition and etching steps performed on the wafer 190. In an embodiment, when a new pattern is placed, the reference pattern 102 can be compared with the wafer 190. For an initial pattern, this means that the pattern can be adapted to the reference pattern 102. For subsequent patterns, this means that one or more patterns can still be compared with the reference pattern 102 to calculate overlay correction, thereby returning to the same alignment.

[0030] For example, in process 140, reference pattern 102 can be used to align an initial pattern on the front side 191 of wafer 190. In one embodiment, reference pattern 102 can be positioned at a fixed location relative to the wafer surface, such as by embedding reference pattern 102 within wafer 190 or providing reference pattern 102 fixed to the back side 192 of wafer 190. Therefore, the starting point 141A of the first arrow is aligned with reference pattern 102, the position of which is shown as reference line 150. Subsequent patterns are also aligned using a fixed, absolutely independent reference pattern 102. A new photoresist layer can be formed for each subsequent pattern, but due to reference pattern 102, alignment marks do not need to be formed on wafer 190 and / or will not be damaged. Therefore, the arrow is centered on reference line 150, meaning that subsequent patterns are aligned with reference pattern 102. For example, alignment can be achieved by moving a mask of the pattern image or moving wafer 190 relative to a mask. Therefore, as more and more layers are formed, overlay errors are less likely to accumulate.

[0031] Figure 2 This is a functional block diagram of an exemplary imaging system 200 according to some embodiments of this disclosure. For example, the exemplary imaging system 200 may be implemented in a scanner or stepper of a lithography system. As another example, the exemplary imaging system 200 may be implemented in a resist coating tool (e.g., a CLEAN TRACK manufactured by Tokyo Electron Ltd). TM ACT TMImplemented in 12), the resist coating tool includes multiple mask-specific modules such as an advanced soft baking oven unit, an edge photoresist removal module, and a cleaning system. The exemplary imaging system 200 can coaxially align two beams of different wavelengths, focusing them onto a first pattern located on the front side of a substrate (e.g., a wafer) and a second pattern located below the first pattern, respectively, and capturing images of the first and second patterns. For example, the exemplary imaging system 200 may include a first light source 210, a second light source 220, an alignment module 230, a coaxial module 240, a first image capture device 250, and a second image capture device 260. The first image capture device 250 and the second image capture device 260 can be collectively referred to as the image capture module.

[0032] In an embodiment, the first light source 210 may be configured to generate a first incident beam of a first wavelength. For example, the first light source 210 may be a UV light source that generates a first incident beam of 50 nanometers to 400 nanometers (e.g., 266 nanometers). Figure 2 The image shown is for UV. 入射 As another example, the first light source 210 may be an Optowaves (Optowaves Ltd., Massachusetts, USA) solid-state laser, such as a pumped nanosecond laser for surface imaging.

[0033] In an embodiment, the second light source 220 may be configured to generate a second incident beam of a second wavelength. According to some aspects of this disclosure, since an absolutely independent reference pattern should be located below the pattern to be formed on the front side of the wafer, and the second incident beam is used to image the reference pattern, the second incident beam must penetrate at least a portion or even the entire thickness of the wafer, such as wafer 290.

[0034] For example, the second incident beam has power or intensity sufficient to penetrate the entire thickness of wafer 290 (e.g., 750 micrometers) to capture an image of the reference pattern using quantum tunneling imaging, IR transmission imaging, etc. As another example, the second light source 220 could be an IR source that generates a second incident beam of 1 to 10 micrometers (e.g., 3.6 or 3.7 micrometers) in... Figure 2 The image shown is IR. 入射 In an embodiment, the second light source 220 may be an IR-tunable quantum cascade laser, which is available from Pranalytica, Inc. (California, USA). According to evanescent wave theory, the light source 220 is incident on a surface between two different media (e.g., the air or liquid where the wafer 290 and the coaxial module 240 in immersion lithography are located) (e.g., the front side 391 of the wafer 290, such as...). Figure 3The intensity of the beam at the point shown will decrease exponentially perpendicular to the surface. The penetration depth at which the intensity drops to 1 / e (approximately 37%) depends particularly on the wavelength of the beam. A typical penetration depth can be a fraction of the beam wavelength, for example, 1 / 5 of the wavelength, depending on the angle of incidence of the beam with respect to the surface. Due to the second incident beam IR... 入射 The second wavelength is greater than the UV wavelength of the first incident beam. 入射 The first wavelength is much longer, so with good power control, the second incident beam IR... 入射 It can penetrate the entire thickness of a 290mm wafer.

[0035] In this embodiment, the relative positions of the first (UV) light source 210 and the second (IR) light source 220 can be calibrated periodically; this is also known as red-blue relative position calibration. For example, the relative positions of the first light source 210 and the second light source 220 can be maintained within the dynamic range of the sensor, which is several tens of times larger and therefore quite loose. However, normalization can be performed as needed by imaging stage artifacts with known relative transmission. For example, once a day, making it easy to perform any relative intensity normalization. Relative position calibration or displacement calibration caused by TIS tools is common for metrology stations. As measurements are performed, the relative positions are recalibrated in real time relative to the grid. Therefore, the exemplary imaging system 200 can always have a real-time absolute reference. Digital image capture and regression can be used.

[0036] In an embodiment, the alignment module 230 can be configured to make the second incident beam IR 入射 With the first incident beam UV 入射 Coaxial alignment. For example, alignment module 230 may include a first beam splitter that splits the first incident UV beam. 入射 The beam is divided into two parts, one of which can be transmitted, and the other can be reflected. In one embodiment, the first beam splitter can be a prism. In another embodiment, the first beam splitter can be a transparent plate (such as a glass or plastic sheet) with a partially transparent metal film (such as aluminum) coated on one side, which allows the first incident beam UV... 入射 A portion of the light is transmitted, while another portion is reflected. In the exemplary imaging system 200, the first light source 210 and the first beam splitter can be arranged such that the first incident beam UV... 入射 It is incident on the first beam splitter at a 45-degree angle.

[0037] For example, the alignment module 230 may further include a second beam splitter that splits the second incident beam IR 入射The beam splitter is divided into two parts, one of which can be reflected and the other can be transmitted. For example, the second beam splitter can be a prism. As another example, the second beam splitter can be a glass or plastic sheet coated with a thin aluminum film on one side, which allows the second incident beam to IR... 入射 Part of the light is reflected, while another part is transmitted. In the exemplary imaging system 200, the second light source 220 and the second beam splitter can be arranged such that the second incident beam IR is reflected. 入射 It is incident on the second beam splitter at a 45-degree angle.

[0038] For example, the alignment module 230 may further include a third beam splitter that allows beams of different wavelengths to be reflected or transmitted. For instance, the third beam splitter may be a transparent plate coated on one side with a dichroic material that allows a first incident beam of a first wavelength (UV) to be transmitted from the first beam splitter. 入射 The second incident beam IR of the second wavelength is reflected and allowed to be transmitted from the second beam splitter. 入射 The transmitted beam is transmitted. In an embodiment, the third beam splitter is designed and positioned such that the transmitted second incident beam IR is transmitted. 入射 With the reflected first incident beam UV 入射 Coaxial alignment, and the transmitted second incident beam IR 入射 and the reflected first incident beam UV 入射 It can propagate along the same optical path to wafer 290.

[0039] In one embodiment, the coaxial module 240 can be configured to receive the first incident beam UV reflected from the third beam splitter. 入射 Focusing on the first pattern 301 located on the front side 391 of wafer 290. Figure 3 (as shown), and the second incident beam IR transmitted from the third beam splitter. 入射 Focus is applied to the second pattern 302 (or reference pattern) located below the first pattern 301. For example, the coaxial module 240 can be designed and configured to adjust the placement tolerances (i.e., depth of focus (DOF)) of the first pattern 301 and the second pattern 302. For instance, a level sensor can be used to track the top of the first pattern 301, and the height of the first pattern 301 can be subtracted from the height of the wafer 290 to simultaneously auto-adjust the coaxially aligned first incident UV beam. 入射 DOF and second incident beam IR 入射The DOF (DoF) is negligible when using deep UV (DUV) light. At 4K resolution, the 250-micron field of view (FOV) in this paper corresponds to approximately 60 nanometers per pixel. This is sufficient resolution for measurements with a registration error of 0.1 nanometers. A light source with sufficient power or intensity can mitigate any shading of the metal layer. Although... Figure 3 An image of the physical pattern formed in wafer 290 is shown, but the image of the pattern to be formed (i.e., before exposure to activation light) can be achieved, for example, by light having a wavelength that does not activate the photoresist in the wafer.

[0040] In this embodiment, the coaxial module 240 may include 2 to 12 independent optical elements, for example, 6 optical elements. Each optical element may include sapphire, AlN, MgF, CaF, BaF, LiF, Ge, Si, etc.

[0041] First incident beam UV 入射 It can be reflected by the first pattern 301 to form a first reflected beam UV 反射 The first reflected beam UV 反射 The light can be reflected sequentially by the third beam splitter and the first beam splitter, and captured by the first image capturing device 250, which can form a corresponding first image of the first pattern 301. For example, the first image capturing device 250 can be a DataRay camera. The second incident beam IR... 入射 It can be reflected by the second pattern 302 to form a second reflected beam IR 反射 . Second reflected beam IR 反射 The image can be transmitted sequentially by a third beam splitter and a second beam splitter, and captured by a second image capturing device 260, which can form a corresponding second image of the second pattern 302. For example, the second image capturing device 260 can be a high-speed, high-definition mid-wavelength IR (MWIR) camera, such as the FLIR X8500MWIR. In embodiments, image analysis can be performed on the first and second images to calculate overlay values ​​to determine the placement of the first pattern 301. For example, image analysis can be achieved by superimposing the first image of the first pattern 301 and the second image of the second pattern 302 onto each other and identifying the coordinate position of the first pattern 301 relative to the second pattern 302. In some embodiments, image analysis can be performed in real time, allowing for real-time adjustment of the placement of the first pattern 301.

[0042] In an embodiment, the alignment module 230 may further include a first lens group and a second lens group. For example, the first lens group may include reflective and / or refractive optics that collimate the first incident light beam UV generated by the first light source 210.入射 And the collimated first incident beam UV 入射 The light is guided to the first beam splitter. As another example, the second lens group may also include reflective and / or refractive optics that collimate the second incident beam IR generated by the second light source 220. 入射 And collimated second incident beam IR 入射 Guided to the second beam splitter.

[0043] In an embodiment, the exemplary imaging system 200 may further include a third lens group 270 and a fourth lens group 280. For example, the third lens group 270 may include a first reflected UV beam. 反射 Reflective and / or refractive optics are focused onto the first image capturing device 250. As another example, the fourth lens group 280 may similarly include a second reflected beam IR. 反射 Reflective and / or refractive optics are focused onto the second image capturing device 260.

[0044] In an embodiment, the exemplary imaging system 200 may further include optics that can capture diffracted beams outside the coaxial module 240 and guide these diffracted beams to the first image capture device 250 and the second image capture device 260.

[0045] exist Figure 3 In the exemplary embodiment shown, the first pattern 301 may be included in a photomask (not shown) located on the front side 391 of the wafer 290. In an embodiment, in a contact printing system, the photomask may be positioned in direct contact with the wafer 290. In another embodiment, in a proximity printing system or a projection printing system, the photomask may be positioned away from the wafer 290.

[0046] exist Figure 3 In the exemplary embodiment shown, the second pattern 302 is located on the back surface 392 of the wafer 290, and the second incident beam IR 入射Having sufficient power to penetrate the entire thickness of wafer 290, a second image of the second pattern 302 can be captured using quantum tunneling imaging, IR transmission imaging, etc. In an embodiment, the second pattern 302 can be formed on a reference plate 310. For example, the reference plate 310 can be a nearly perfectly aligned grid plate with 20-micron by 20-micron squares, and the second pattern 302 can be a corner point of at least one of these squares. As another example, the reference plate 310 can include at least one of dots, lines, corners, boxes, numbers, markings, or any other pattern suitable for alignment purposes, and the second pattern 302 can be one of these. In an embodiment, the reference plate 310 can be adhered to the back side 392 of wafer 290. Thus, the reference plate 310 and wafer 290 can be used as a module. In another embodiment, the reference plate 310 can be incorporated into a substrate holder 320 of a lithography scanner or stepper. Although each given wafer may be placed on the substrate holder 320 in a different position or orientation compared to previous placements, this is not important. For a given new pattern to be placed or exposed, the wafer can be imaged using a reference plate 310 (e.g., a grid plate). The reference plate 310 can then provide relative reference points for identifying vectors to two or more points, based on which overlay correction adjustments in the next exposure can be calculated using vector analysis. For example, when wafer 290 (if it does not yet have a pattern) is placed over reference plate 310, wafer 290 will be coarsely pre-aligned with reference plate 310. As another example, when wafer 290 (if it already has an existing pattern) is placed over reference plate 310, the existing pattern and reference plate 310 can be coaxially aligned. In conventional lithography processes, measurement errors caused by wafer backside scratches, backside dust, and / or substrate deformation due to heat can affect overlay, but conventional overlay systems often ignore these problems. The techniques described in this paper, including independent reference plates and high spatial resolution, overcome these problems.

[0047] In an embodiment, the second pattern 302 may be formed on the back surface 392 of the wafer 290, and the second incident beam IR 入射 It also has sufficient power to penetrate the entire thickness of wafer 290 to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, etc. Other techniques may include, for example, embedding the second pattern 302 (e.g., grid lines) in wafer 290 using radioactive or fluorescent materials.

[0048] In an embodiment, a second pattern 302 may be formed on the front side 291 of wafer 290, and then a silicon and / or silicon oxide layer may be deposited on the second pattern. For example, the silicon and / or silicon oxide layer may have a thickness of 1 micrometer to 5 micrometers, such that the second pattern 302 is effectively "embedded" in wafer 290, and the pattern may be formed on the silicon and / or silicon oxide layer. Therefore, the second incident beam IR 入射 Sufficient power must be available to penetrate the silicon and / or silicon oxide layers in order to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, etc. As another example, the second pattern 302 can be formed on the back side 292 of wafer 290 before a protective layer such as silicon or silicon oxide is formed on the back side 292 of wafer 290. Therefore, the second pattern 302 can also be embedded within wafer 290. Thus, the second incident beam IR... 入射 Sufficient power must be available to penetrate the entire thickness of wafer 290 in order to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, etc. In an embodiment, the second pattern 302 can be formed on the front side of the carrier wafer before the front side of the carrier wafer is bonded to the back side of the target wafer (e.g., the back side 392 of wafer 290). Therefore, the second pattern 302 can be sandwiched between the carrier wafer and the target wafer, which together serve as a single wafer. Thus, the second incident beam IR... 入射 Sufficient power must be available to penetrate the entire thickness of the target wafer in order to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, or the like. In some embodiments, light projection may also be used. For example, the second pattern 302 may be a projected grid that is not actually present in the wafer 290, on the substrate support, or as a grid plate under the substrate support. In some embodiments, the second pattern 302 may be a combination of physical markers and light projection. For example, physical reference markers may be disposed on the outer peripheral region of the substrate support that is not covered by the wafer placed on the substrate support, and light projection may complete the reference pattern in the wafer region, thus eliminating the need for tunneling techniques.

[0049] Figure 4A An enlarged top view of an overlay image of a portion of a wafer 290 according to some embodiments of the present disclosure is shown. The overlay images are captured by a first image capture device 250 and a second image capture device 260. The portion includes a first pattern 301 and a second pattern 302. Figure 4B Exemplary image analysis is shown for overlay calculations performed on a first pattern 301 that serves as a reference pattern in an alignment process, according to some embodiments of this disclosure. Figure 4A and Figure 4BThis illustrates how an absolutely independent first pattern 301 can be used to calculate the overlay values ​​of two patterns. This can be achieved by knowing each common reference pattern in the coordinate system and using that reference pattern to understand the "position" of each pattern within that coordinate system. Once these are known, such as the distances between each layer, the vector calculations required to extract the overlay values ​​can be performed using simple vector algebra. From this perspective, this is basic coordinate geometry. It can be viewed as a mix-match overlay (MMO) with a gold tool always ready for it under the stage.

[0050] In an embodiment, the first pattern 301 (represented by point M), for example, a corner of one of the squares in a grid plate with a 20-micron by 20-micron square, can be considered absolute or wafer-independent and is used to calculate the overlay value between the second pattern 302 (represented by point N) and the third pattern 401 (represented by point P) formed after the second pattern 302 is formed. By superimposing the second pattern 302 on the first pattern 301, the coordinate difference or vector from point M of the first pattern 301 to point N of the second pattern 302 can be determined. Similarly, by superimposing the third pattern 401 onto the first pattern 301, another coordinate difference or vector from point M of the first pattern 301 to point P of the third pattern 401 can also be determined. Then, the overlay value between point N and point P can be calculated.

[0051] Furthermore, using the coordinate positions of points from the second pattern 302 (e.g., N(Wx,Wy)) and the coordinate positions of points from the third pattern 401 (e.g., P(Bx,By)), the overlay value or shift from the second pattern 302 to the third pattern 401 can be determined. This overlay value can then be used to place the third or subsequent patterns to correct the overlay relative to an independent reference pattern (e.g., the first pattern 301). In some embodiments, having a reference image that is consistent for each image comparison makes it possible to correct adjacent patterns and maintain overlay correction based on an initial line or absolute reference. Regarding concerns about the critical dimension (CD) variation effect of the resist layer, the techniques described herein can extract the coordinates of the patterns without causing a CD variation effect on the resist layer and its underlying layers (e.g., a metallic resist pattern covering most of the via pattern). The CD variation effect of the resist layer can be a problem for alignment and may be ignored by the overlay measurement team, i.e., considered negligible. The technique described in this paper is a significant improvement because the reference pattern itself indicates pattern placement far better than alignment marks that experience pattern offsets caused by CD astigmatism and Zernike. It should be noted that in some embodiments, overlaying images is not necessary. Coordinate position data can be collected from the reference plate and the working surface of the wafer, and vector analysis can then be used to determine the total offset or overlay value.

[0052] Figure 5 This is a flowchart illustrating an exemplary imaging method 500 for processing a wafer (e.g., wafer 290) according to some embodiments of this disclosure. The exemplary imaging method 500 can be applied to the exemplary imaging system 200. In various embodiments, some steps of the illustrated exemplary imaging method 500 may be performed simultaneously or in a different order than shown, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as needed.

[0053] At step S510, the first beam (e.g., the first incident beam UV) can be used. 入射 ) and a second beam (e.g., a second incident beam IR) coaxially aligned with the first beam. 入射 Image the wafer. In an embodiment, the first beam can (e.g., by capturing a first reflected UV beam) to image the wafer. 反射 The first pattern located on the front side of the wafer is imaged to form a first image, and the second beam can (e.g., by capturing a second reflected beam IR) 反射The second pattern located below the first pattern is imaged to form a second image. For example, the second beam may have sufficient power to penetrate at least a portion of the wafer's thickness and reach the second pattern. In embodiments, the second beam may have a second wavelength longer than the first wavelength of the first beam. For example, the first beam may be generated by a first light source 210, such as a UV light source, while the second beam may be generated by a second light source 220, such as an IR light source. In embodiments, the first wavelength is from 50 nanometers to 400 nanometers, for example, 266 nanometers, while the second wavelength is from 1 micrometer to 10 micrometers, for example, 3.6 micrometers or 3.7 micrometers. In embodiments, the second pattern may be imaged via quantum tunneling imaging or IR transmission imaging.

[0054] In one embodiment, the second pattern can be incorporated into a reference plate located beneath the wafer (e.g., a 20-micron by 20-micron square grid plate with sub-nanometer positioning accuracy). For example, the reference plate can be placed on or adhered to the back side of the wafer. Therefore, the second beam can have sufficient power to penetrate the entire thickness of the wafer to capture a second image of the second pattern using quantum tunneling imaging, IR transmission imaging, etc. In another embodiment, the reference plate can be incorporated into a substrate holder or chuck of a lithography scanner or stepper, and the exemplary imaging method 500 can further include a step of aligning the reference plate with the wafer prior to imaging the wafer using the first and second beams. In yet another embodiment, the second pattern can be formed on the back side of the wafer. Therefore, the second beam can have sufficient power to penetrate the entire thickness of the wafer to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, etc. In still another embodiment, the second pattern can be embedded within the wafer and is accessible through one or more layers. Therefore, the second beam can have sufficient power to penetrate a portion of the wafer's thickness to capture a second image of the second pattern 302 using quantum tunneling imaging, IR transmission imaging, or the like. For example, the second pattern may include a radioactive or fluorescent material. As another example, the second pattern may include at least one of dots, lines, corners, boxes, triangles, numbers, and markers.

[0055] At step 520, image analysis can be performed on the first and second images to calculate the overlay values ​​of the first and second patterns. For example, image analysis can be performed by identifying the coordinate position of the first pattern relative to the second pattern as the overlay value, such as... Figure 4A and Figure 4B As shown.

[0056] At step S530, the first pattern can therefore be formed on the front side of the wafer based on the overlay value. For example, the photomask of the first pattern can be moved relative to the wafer based on the overlay value so that the first pattern is aligned with the second pattern, and the resist layer formed on the front side of the wafer can be exposed to allow the first pattern to be formed in the resist layer.

[0057] In an embodiment, in a “step-by-step repeat” or “step-by-step scan” system, the first beam and the second beam, as well as the photomask, can be moved to another area of ​​the wafer, and steps S510 to S530 can be repeated to form one or more patterns in the resist layer on the front side of the wafer.

[0058] The reference pattern used for patterning in this paper can be considered absolute in one aspect and relative in another. For example, the reference pattern may maintain or preserve fixed grid lines (or points, corners, boxes, or any other suitable shape) and will not change due to various deposition and etching steps on the wafer. In an embodiment, the reference pattern may be a grid plate integrated with a stage or substrate holder. In this way, the grid plate is absolute because the same physical grid plate is used throughout the wafer fabrication process, but relative because the physical grid plate is not fixed to the wafer itself and can be moved relative to the wafer throughout the wafer fabrication process. Although each time a given wafer is placed on the stage, the given wafer may be in a different position or orientation compared to a previous placement; however, this is not important. For a given new pattern to be placed or exposed, the wafer is imaged with the reference grid. The reference grid can then provide relative reference points for identifying vectors of two or more points, based on which overlay correction adjustments in the next exposure can be calculated using vector analysis.

[0059] The exemplary imaging system 200 and exemplary imaging method 500 can be implemented as a stand-alone coaxial metrology system and method that can be operated in conjunction with a lithography tool, an integrated track coaxial metrology system and method with feedforward to a linked lithography unit, or an active coaxial metrology system and method that can be embedded in a lithography tool for real-time calibration.

[0060] Figure 6This is a functional block diagram of an exemplary inspection system 600 according to some embodiments of this disclosure. The exemplary inspection system 600 can calculate overlay values ​​of a first pattern and a second pattern associated with a wafer and inspect the wafer for defects. For example, the exemplary inspection system 600 may include an imaging module 610, such as an imaging system 200 and processing circuitry 620. In an embodiment, the imaging module 610 may image the wafer using a first beam and a second beam coaxially aligned with the first beam. The first beam images a first pattern located on the front side of the wafer to form a first image, and the second beam images a second pattern located below the first pattern to form a second image. The second beam has power sufficient to penetrate at least a portion of the wafer's thickness and reach the second pattern. For example, imaging module 610 can image wafer 290 using a first beam generated by a first light source 210 (e.g., a UV light source) and a second beam generated by a second light source 220 (e.g., an IR light source, such as an IR tunable quantum cascade laser). The first beam can image a first pattern 301 located on the front side 391 of wafer 290, and the second beam can image a second pattern 302 located below the first pattern 301 and have power sufficient to penetrate at least a portion of the thickness of wafer 290 and reach the second pattern 302. Processing circuit 620 can perform image analysis on the first image of the first pattern 301 and the second image of the second pattern 302 to calculate the overlay values ​​of the first pattern 301 and the second pattern 302.

[0061] Each wafer may have scratches, thermal effects, and jamming issues deep enough to affect overlay. Wafers may further have patterning defects, such as circuitry not being connected as designed, critical dimensions being too small / too large, or gaps that could cause short circuits. Since the second beam can pass through wafer 290, it can also see defects, and the captured second image can further include information about the defects. In an embodiment, processing circuitry 620 can further inspect wafer 290 for any defects by performing image analysis on the first image of the first pattern 301 and the second image of the second pattern 302.

[0062] The aspects disclosed herein provide an imaging method that provides an accurate and precise alignment mechanism without relying on conventional alignment marks formed on the front surface of the wafer. Instead, by referencing a pattern or grid within / below the wafer, a reliable reference pattern can be repeatedly accessed for precise and accurate registration and alignment of subsequent patterns. The techniques described herein eliminate the need for conventional overlay marks. These novel paradigms for overlay can improve silicon area utilization without the need for erasure, loss of footprint, or complex scribing designs, and without the complex integration of alignment marks. The exemplary reference patterns disclosed herein will not be affected and erased by the adverse processes of fabricating devices rather than fabricating alignment marks, as is the case in conventional methods. Overlay placement accuracy can now also be measured from the first layer where the second pattern resides, because the reference pattern is now not only near perfect every time, but is always hidden directly beneath the stage.

[0063] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein may be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional construction are indicated by similar reference numerals, and therefore any redundant descriptions may be omitted.

[0064] Various techniques have been described as multiple discontinuous operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations must be performed in sequence. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in an order different from the order of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0065] As used herein, “substrate” or “target substrate” generally refers to the object being processed according to this disclosure. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, photomask), or a layer on or overlaid on a base substrate structure (such as a thin film). Therefore, a substrate is not limited to any particular base structure, underlayer, or overlay, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0066] Those skilled in the art will also understand that many changes can be made to the operation of the techniques explained above while still achieving the same purpose of this disclosure. The scope of this disclosure is intended to cover such changes. Therefore, the foregoing description of embodiments of this disclosure is not intended to be limiting. Rather, any limitations on embodiments of this disclosure are provided in the appended claims.

Claims

1. An inspection system, comprising: An imaging module configured to image a wafer using a first beam and a second beam coaxially aligned with the first beam, the first beam imaging a first pattern located on the front side of the wafer to form a first image, and the second beam imaging a second pattern located in or beneath the wafer to form a second image, the second beam having power sufficient to penetrate at least a portion of the thickness of the wafer and reach the second pattern, the wafer comprising silicon; and The processing circuit is configured to perform image analysis on the first image and the second image to calculate at least one of the overlay values ​​of the first pattern and the second pattern and to check for defects in the wafer. The first beam and the second beam are generated simultaneously by separate light sources.

2. The inspection system as claimed in claim 1, wherein, The second pattern is incorporated into a reference plate located beneath the wafer.

3. The inspection system as described in claim 2, wherein, The reference plate is placed on or attached to the back of the wafer.

4. The inspection system as described in claim 2, wherein, The reference board is integrated into the substrate support of a photolithography scanner or stepper.

5. The inspection system as claimed in claim 1, wherein, The second pattern is formed on the back side of the wafer, and the second beam has sufficient power to penetrate the entire thickness of the wafer and reach the second pattern.

6. The inspection system as claimed in claim 1, wherein, The second pattern is embedded within the wafer.

7. The inspection system as claimed in claim 1, wherein, The second pattern includes radioactive or fluorescent materials.

8. The inspection system as claimed in claim 1, wherein, The second pattern includes at least one of dots, lines, corners, boxes, triangles, numbers, and marks.

9. The inspection system as claimed in claim 1, wherein, The second beam has a longer wavelength than the first wavelength of the first beam.

10. The inspection system as claimed in claim 9, wherein, The first wavelength is 50 nanometers to 400 nanometers, and the second wavelength is 1 micrometer to 10 micrometers.

11. The inspection system of claim 10, wherein, The first wavelength is 266 nanometers, and the second wavelength is 3.6 micrometers or 3.7 micrometers.

12. The inspection system of claim 9, further comprising an ultraviolet (UV) light source and an infrared (IR) light source, the UV light source being configured to generate the first beam and the IR light source being configured to generate the second beam.

13. The inspection system of claim 12, wherein, The second pattern was imaged via quantum tunneling imaging or IR transmission imaging.

14. The inspection system as claimed in claim 1, wherein, The second pattern is coaxially aligned with the wafer.

15. The inspection system as claimed in claim 1, wherein, The processing circuit performs the image analysis by identifying the coordinate position of the first pattern relative to the second pattern as the overlay value.

16. The inspection system as claimed in claim 1, wherein, The second pattern is projected onto the surface of the wafer.

17. An inspection system, comprising: An imaging module configured to image a wafer using a first beam and a second beam coaxially aligned with the first beam, the first beam imaging a first pattern on the front side of the wafer to form a first image, the second beam imaging a second pattern below the first pattern to form a second image, the second beam having power sufficient to penetrate at least a portion of the thickness of the wafer and reach the second pattern. as well as The processing circuit is configured to perform image analysis on the first image and the second image to calculate at least one of the overlay values ​​of the first pattern and the second pattern and to check for defects in the wafer. The second beam has a longer wavelength than the first beam. The first beam and the second beam are generated simultaneously by separate light sources.

18. The inspection system of claim 17, wherein, The second pattern is incorporated into a reference plate located beneath the wafer.

19. The inspection system of claim 18, wherein, The reference plate is placed on or attached to the back of the wafer.

20. The inspection system of claim 18, wherein, The reference board is integrated into the substrate support of a photolithography scanner or stepper.

Images