Semiconductor memory device

Abstract

The present invention can suppress an increase in power consumption. A semiconductor memory device according to one embodiment includes: a bit line (BL); a memory cell transistor (MT) connected to the bit line; and a capacitor (CAP) connected between the memory cell transistor and the bit line.

Description

Technical Field

[0001] The embodiment relates to a semiconductor memory device. Background Art

[0002] As a semiconductor memory device capable of storing data non-volatily, a NAND flash memory is known. Further, as a semiconductor memory device capable of storing data volatily and performing high-speed data writing and reading, a DRAM (Dynamic random access memory) is known.

[0003] [Background Art Documents]

[0004] [Patent Documents]

[0005] Patent Document 1: U.S. Patent No. 7,372,730 Specification Summary of the Invention

[0006] [Problems to be Solved by the Invention]

[0007] The embodiment suppresses an increase in power consumption.

[0008] [Technical Means for Solving the Problems]

[0009] The semiconductor memory device of the embodiment includes: a first bit line; a first memory cell transistor connected to the first bit line; and a first capacitor connected between the first memory cell transistor and the first bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram for explaining the configuration of a memory system including the semiconductor memory device of the embodiment.

[0011] Figure 2 is a plan view for explaining the planar layout of the semiconductor memory device of the embodiment.

[0012] Figure 3 is a circuit diagram for explaining the configuration of a memory cell array of the semiconductor memory device of the embodiment.

[0013] Figure 4 is a potential diagram for explaining data stored in the memory cell transistor and the capacitor of the embodiment.

[0014] Figure 5 is Figure 2 a plan view of a cell region in region V of

[0015] Figure 6 is a cross-sectional view of a cell region taken along line VI-VI of Figure 5 ​

[0016] Figure 7 is a cross-sectional view of a memory cell transistor along line VII-VII of Figure 6 .

[0017] Figure 8 is a cross-sectional view of a capacitor along line VIII-VIII of Figure 6 .

[0018] Figure 9 is a cross-sectional view of a selection transistor along line IX-IX of Figure 6 .

[0019] Figure 10 is Figure 2 a plan view of a wiring area in region X of

[0020] Figure 11 is a cross-sectional view of a wiring area along line XI-XI of Figure 10 .

[0021] Figure 12 is a circuit diagram showing the configuration of a sense amplifier of a semiconductor memory device for explaining an embodiment.

[0022] Figure 13 is a timing diagram for explaining the read operation of a semiconductor memory device for an embodiment.

[0023] Figure 14 is a timing diagram for explaining the erase operation of a semiconductor memory device for an embodiment.

[0024] Figure 15 is a timing diagram for explaining the write operation of a semiconductor memory device for an embodiment.

[0025] Figure 16 is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device for an embodiment.

[0026] Figure 17 is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device for an embodiment.

[0027] Figure 18 is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device for an embodiment.

[0028] Figure 19 is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device for an embodiment.

[0029] Figure 20 is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device for an embodiment.

[0030] Figure 21 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0031] Figure 22 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0032] Figure 23 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0033] Figure 24 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0034] Figure 25 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0035] Figure 26 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0036] Figure 27 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0037] Figure 28 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0038] Figure 29 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0039] Figure 30 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0040] Figure 31 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0041] Figure 32 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0042] Figure 33 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment.

[0043] Figure 34It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to an embodiment. Detailed Embodiment

[0044] Hereinafter, the embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of the invention. The drawings are schematic or conceptual drawings, and the dimensions and ratios of each drawing are not necessarily the same as the actual dimensions and ratios. The technical idea of the present invention is not specified by the shape, structure, configuration, etc. of the components.

[0045] In addition, in the following description, components having substantially the same functions and configurations are given the same reference symbols including letters or numbers. In addition, when distinguishing between components that are referred to using the same reference symbols and have the same configuration, there are cases where letters or numbers are further appended after the reference symbols.

[0046] In addition, the component " / A" is assumed to have the same configuration as the component A and is a component paired with the component A.

[0047] 1. Embodiment

[0048] The semiconductor memory device according to the embodiment will be described.

[0049] 1.1 Configuration

[0050] First, the configuration of the semiconductor memory device according to the embodiment will be described.

[0051] 1.1.1 Overall Configuration

[0052] Figure 1 It is a block diagram for explaining the overall configuration of a memory system including the semiconductor memory device according to the embodiment. The semiconductor memory device 1 includes: a NAND flash memory that can store data non-volatily; and a DRAM (Dynamic random access memory) that can store data volatily; and is controlled by an external memory controller 2. In Figure 1 In the example of, the communication between the semiconductor memory device 1 and the memory controller 2 shows, for example, a case where the NAND interface specification is supported, but is not necessarily limited thereto. For example, the communication between the semiconductor memory device 1 and the memory controller 2 can further support the interface specification with the DRAM.

[0053] As Figure 1As shown, the semiconductor memory device 1 includes, for example, a memory cell array 10, an instruction buffer 11, an address buffer 12, a sequencer 13, a driving module 14, a row decoder module 15, and a sense amplifier module 16. The components in the semiconductor memory device 1 other than the memory cell array 10, the row decoder module 15, and the sense amplifier module 16 (the instruction buffer 11, the address buffer 12, the sequencer 13, and the driving module 14) are also referred to as the peripheral circuit PERI.

[0054] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn and / BLK0 to / BLKn (n is an integer of 1 or more), and two dummy blocks dBLK and / dBLK. The blocks BLK and / BLK are a collection of a plurality of DRAM memory cells and a plurality of NAND memory cells that can store data non-volatilely, and are used, for example, as an erasure unit of data. Hereinafter, for simplicity, there are cases where the DRAM memory cells and the NAND memory cells are collectively referred to as "memory cells". The dummy blocks dBLK and / dBLK function as reference capacitors for the blocks BLK and / BLK.

[0055] A plurality of bit lines, a plurality of word lines, and a plurality of select gate lines are provided in the memory cell array 10. Each DRAM memory cell is associated with, for example, one bit line and one select gate line. Each NAND memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0056] The instruction buffer 11 holds the instruction CMD received by the semiconductor memory device 1 from the memory controller 2. The instruction CMD includes, for example, commands for causing the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0057] The address buffer 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are respectively used for the selection of the block BLK, the word line, the select gate line, and the bit line.

[0058] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driving module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the instruction CMD held in the instruction buffer 11, and performs read operations, write operations, erase operations, etc.

[0059] The driving module 14 generates voltages used for read operations, write operations, erase operations, etc. Further, the driving module 14 applies the generated voltages to signal lines corresponding to the word lines and the selection gate lines selected based on the page address PAd held in the address buffer 12, for example.

[0060] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd held in the address buffer 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0061] In a write operation, the sense amplifier module 16 applies desired voltages to the respective bit lines according to the write data DAT received from the memory controller 2. Further, in a read operation, the sense amplifier module 16 determines the data stored in the memory cells based on the voltages of the bit lines, and transfers the determination result as read data DAT to the memory controller 2.

[0062] The semiconductor memory device 1 and the memory controller 2 described above can be configured as one semiconductor device by the above combination. As such a semiconductor device, for example, an SD TM memory card of a card, or an SSD (solid state drive) etc. can be cited.

[0063] 1.1.2 Planar layout

[0064] Next, the planar layout of the semiconductor memory device of the embodiment will be described.

[0065] In addition, in the drawings referred to below, the X-axis corresponds to the extending direction of the bit line BL, the Y-axis corresponds to the extending direction of the word line WL, and the Z-axis corresponds to the vertical direction with respect to the surface of the semiconductor substrate on which the semiconductor memory device 1 is formed.

[0066] Figure 2 is a plan view for explaining the planar layout of the semiconductor memory device of the embodiment. As Figure 2 shown, the sense amplifier module 16 is provided to extend along the Y-axis on the semiconductor substrate, and includes a plurality of sense amplifiers SA arranged along the Y-axis. The plurality of sense amplifiers SA are respectively connected to corresponding groups of bit lines BL and / BL.

[0067] The memory cell array 10 is provided so as to be divided into two regions sandwiching the sense amplifier module 16 along the X-axis. The bit line BL extends along the X-axis above one of the two regions of the memory cell array 10, and the bit line / BL extends along the X-axis above the other of the two regions of the memory cell array 10.

[0068] In the regions below the bit lines BL in two regions of the memory cell array 10, dummy blocks dBLK, block BLK0, block BLK1, …, and block BLKn are arranged in sequence in the direction away from the sense amplifier module 16 along the X-axis. In the regions below the bit lines / BL in two regions of the memory cell array 10, dummy blocks / dBLK, block / BLK0, block / BLK1, …, and block / BLKn are arranged in sequence in the direction away from the sense amplifier module 16 along the X-axis.

[0069] In addition, in the memory cell array 10, a cell region CA and a wiring region HA arranged along the Y-axis are provided. The cell region CA is a region where memory cells are provided, and the wiring region HA is a region for electrically connecting between the row decoder module 15 and the cell region CA.

[0070] The row decoder module 15 is provided to extend along the X-axis at the first end along the Y-axis of the memory cell array 10 and the sense amplifier module 16. The peripheral circuit PERI is provided to extend along the X-axis at the second end along the Y-axis of the memory cell array 10 and the sense amplifier module 16. The peripheral circuit PERI, the cell region CA of the memory cell array 10, the wiring region HA, and the row decoder module 15 are arranged in sequence along the Y-axis.

[0071] 1.1.3 Circuit Configuration of Memory Cell Array

[0072] Figure 3 It is a circuit diagram for explaining the configuration of the memory cell array of the semiconductor memory device according to the embodiment. In Figure 3 it shows one block BLK among the multiple blocks BLK included in the memory cell array 10 and the dummy block dBLK. In addition, the configurations of the block / BLK and the dummy block / BLK are the same as those of the block BLK and the dummy block dBLK respectively, so the description is omitted.

[0073] First, the configuration of the block BLK will be described.

[0074] As Figure 3 shown, the block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of memory strings MS respectively associated with the bit lines BL1, BL2, …, BLm (m is an integer of 1 or more).

[0075] Each memory string MS includes, for example, memory cell transistors MT0 to MT7, selection transistors ST1 to ST3, and a capacitor CAP. The memory cell transistor MT includes a control gate and a charge storage film, and functions as a NAND memory cell that non-volatilely stores data. The capacitor CAP has a pair of electrodes including an electrode electrically connected to the memory string MS, and functions as a DRAM memory cell that volatilely stores data. The selection transistors ST1 to ST3 are used for the selection of the string unit SU during various operations, and the selection of the memory cell transistor MT and the capacitor CAP within the string unit SU.

[0076] In each memory string MS, the memory cell transistors MT0 to MT7 are connected in series. The first end of the selection transistor ST1 is connected to the associated bit line BL, and the second end of the selection transistor ST1 is commonly connected to the electrode of the first end of the capacitor CAP and the first end of the selection transistor ST3 via the node N0. The electrode of the second end of the capacitor CAP is connected to the wiring CAPL. The second end of the selection transistor ST3 is connected to the first ends of the series-connected memory cell transistors MT0 to MT7. The first end of the selection transistor ST2 is connected to the second ends of the series-connected memory cell transistors MT0 to MT7. The second end of the selection transistor ST2 is connected to the source line SL. The wiring CAPL and the source line SL are configured to be controllable to a specific voltage (e.g., ground voltage) by being connected to a driver (not shown), for example.

[0077] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are commonly connected to the word lines WL0 to WL7, respectively. The gates of the selection transistors ST1 within the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3, respectively. The gate of the selection transistor ST2 is commonly connected to the selection gate line SGS. The gate of the selection transistor ST3 is commonly connected to the selection gate line SGM.

[0078] In addition, a set of multiple memory cell transistors MT connected to a common word line WL within one string unit SU is, for example, referred to as a cell CU. For example, the storage capacity of the cell CU including the memory cell transistors MT that each store 1-bit data is defined as "1 page of data".

[0079] Next, regarding the configuration of the dummy block dBLK, continue to use Figure 3 to describe.

[0080] The configuration of the dummy block dBLK is the same as the configuration of one string unit SU within the block BLK. The dummy block dBLK includes a plurality of dummy memory strings dMS associated with the bit lines BL1 to BLm, respectively.

[0081] Each dummy storage string dMS includes, for example, dummy storage cell transistors dMT0 to dMT7, dummy selection transistors dST1 to dST3, and a dummy capacitor dCAP. The configurations of the dummy storage cell transistors dMT, the dummy capacitor dCAP, and the dummy selection transistors dST1 to dST3 are the same as those of the storage cell transistors MT, the capacitor CAP, and the selection transistors ST1 to ST3, respectively. The dummy capacitor dCAP functions as a reference cell for determining the amount of charge stored in the capacitor CAP to be read out during a read operation.

[0082] In each dummy storage string dMS, the dummy storage cell transistors dMT0 to dMT7 are connected in series. The first end of the dummy selection transistor dST1 is connected to the associated bit line BL, and the second end of the dummy selection transistor dST1 is commonly connected, via a node dN0, to the electrode at the first end of the dummy capacitor dCAP and the first end of the dummy selection transistor dST3. The electrode at the second end of the dummy capacitor dCAP is connected to a wiring dCAPL. The second end of the dummy selection transistor dST3 is connected to the first ends of the series-connected dummy storage cell transistors dMT0 to dMT7. The first end of the dummy selection transistor dST2 is connected to the second ends of the series-connected dummy storage cell transistors dMT0 to dMT7. The second end of the dummy selection transistor dST2 is connected to the source line SL. The wiring dCAPL and the source line SL are configured, for example, to be controllable to a specific voltage (e.g., a ground voltage) by being connected to a driver (not shown).

[0083] In the same dummy block dBLK, the control gates of the dummy storage cell transistors dMT0 to dMT7 are commonly connected to dummy word lines dWL0 to dWL7, respectively. The gates of the plurality of dummy selection transistors dST1 to dST3 within the dummy block dBLK are commonly connected to dummy selection gate lines dSGD, dSGS, and dSGM, respectively.

[0084] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the memory strings MS and the dummy memory strings dMS to which the same column address is assigned in each string unit SU. The source line SL is shared, for example, among a plurality of blocks BLK and the dummy blocks dBLK.

[0085] In addition, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 of the present embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT and selection transistors ST included in each memory string MS can be designed to be any number. The number of string units SU included in each block BLK can be designed to be any number.

[0086] Next, use Figure 4The data stored in the memory cell transistor MT and the capacitor CAP will be described. As Figure 4 shown, in this embodiment, both the memory cell transistor MT and the capacitor CAP are configured to store 1 bit.

[0087] First, with reference to Figure 4 (A), the relationship between the data stored in the memory cell transistor MT and the threshold voltage will be described.

[0088] As Figure 4 (A) shows, the threshold voltage of the memory cell transistor MT varies according to the amount of charge accumulated in the charge accumulation film. Therefore, the data stored in the memory cell transistor MT is determined based on the threshold voltage. Specifically, when the threshold voltage of the memory cell transistor MT is equal to or higher than the voltage VCGR, it is determined that the data “0” is stored in the memory cell transistor MT. On the other hand, when the threshold voltage is lower than the voltage VCGR, it is determined that the data “1” is stored in the memory cell transistor MT. The voltage VCGR is the voltage used in the read operation and is also referred to as the read voltage VCGR.

[0089] Next, in Figure 4 (B), the relationship between the data stored in the capacitor CAP and the voltage of the node N0 will be described.

[0090] As Figure 4 (B) shows, the data stored in the capacitor CAP is determined based on the amount of charge (voltage) charged between a pair of electrodes. Specifically, when the voltage charged in the capacitor CAP (i.e., the voltage of the node N0 with respect to the voltage of the wiring CAPL) is equal to or higher than half of the power supply voltage VDD, that is, the voltage VDD / 2, it is determined that the data “1” is stored in the capacitor CAP. On the other hand, when the voltage of the node N0 with respect to the voltage of the wiring CAPL is less than the voltage VDD / 2, it is determined that the data “0” is stored in the capacitor CAP.

[0091] 1.1.4 Structure of the Memory Cell Array

[0092] Next, an example of the structure of the memory cell array of the semiconductor memory device according to the embodiment will be described.

[0093] In addition, hereinafter, in the plan view, shading is appropriately added for easy viewing of the figure. The shading added to the plan view is not necessarily related to the material or characteristics of the shaded components. In the cross-sectional view, for easy viewing of the figure, components such as insulating layers (interlayer insulating films), wirings, and contact parts are appropriately omitted.

[0094] 1.1.4.1 Unit Region

[0095] Figure 5 is a plan view showing the structure of a cell region of a memory cell array of a semiconductor memory device for explaining an embodiment, corresponding to region V of Figure 2 . In Figure 5 , as an example, a part of a region including a structure corresponding to string cells SU0 to SU3 and a dummy block dBLK in a block BLK0 of a cell region CA is shown. In addition, in Figure 5 , illustration is omitted. Blocks / BLK and dummy blocks / dBLK have the same configuration as blocks BLK and dummy blocks dBLK, so the description thereof is omitted.

[0096] As Figure 5 shown, the cell region CA includes, for example, slits SLT and SHE, memory pillars MP, contact portions CP and LI, bit lines BL, and wiring laminate.

[0097] The plurality of slits SLT extend along the Y axis and are arranged along the X axis. The plurality of slits SHE extend along the Y axis and are arranged along the X axis between adjacent slits SLT. The width of the slit SLT is, for example, wider than the width of the slit SHE. The slits SLT and SHE each include an insulator. The slit SLT disconnects the wiring layer corresponding to the word line WL and the wiring layer corresponding to the select gate line SGD between two adjacent blocks BLK. In addition, the slit SLT disconnects the wiring layer corresponding to the word line WL, the wiring layer corresponding to the select gate line SGD, the wiring layer corresponding to the dummy word line dWL, and the wiring layer corresponding to the dummy select gate line dSGD between the adjacent block BLK0 and the dummy block dBLK. The slit SHE disconnects the wiring layer corresponding to the select gate line SGD between adjacent string cells SU.

[0098] The region delimited by the slits SLT and SHE corresponds to one string cell SU or a dummy block dBLK. String cells SU0 to SU3 are provided between adjacent slits SLT along the X axis. Moreover, the four regions delimited by the three slits SHE arranged between the slits SLT respectively correspond to the string cells SU0 to SU3.

[0099] Inside the slit SLT, a contact portion LI insulated from the wiring layers corresponding to the select gate line SGD and the word line WL is provided. The conduction path formed in the memory pillar MP is electrically connected to the source line SL via the contact portion LI.

[0100] The plurality of pillars are arranged in a staggered shape in 11 columns, for example, in the region between adjacent slits SLT along the X axis. One column of pillars is provided below each of the three slits SHE. The remaining eight columns of the 11 columns of pillars are each provided with two columns between the slits SLT and SHE, and the two columns of pillars function as memory pillars MP within one string cell SU. In the memory cell array 10,Figure 5 The layout of the 1 block BLK shown is repeatedly arranged n times along the X-axis.

[0101] In addition, a plurality of columns are arranged in a staggered pattern of two columns along the X-axis in the region between the slit SLT and the sense amplifier module 16. The two columns of columns function as memory columns MP within the dummy block dBLK.

[0102] A plurality of bit lines BL extend along the X-axis respectively and are arranged along the Y-axis. One bit line BL is arranged in a manner that overlaps with one memory column MP for each dummy block dBLK and string unit SU in a top view. The bit line BL is connected to the corresponding bit line BL via the memory column MP and the contact portion CP for each dummy block dBLK and string unit SU. The conduction path formed within the memory column MP is electrically connected to the corresponding bit line BL via the contact portion CP.

[0103] In addition, the planar layout of the memory cell array 10 described above is merely an example and is not limited thereto. For example, the number of slits SHE arranged between adjacent slits SLT can be designed to be any number. The number of string units SU between adjacent slits SLT varies based on the number of slits SHE. The number and configuration of the memory columns MP can be designed to be any number and configuration. The number of bit lines BL overlapping with each memory column MP can be designed to be any number.

[0104] Figure 6 is a cross-sectional view along the Figure 5 VI-VI line, showing an example of the cross-sectional structure of the memory cell array 10 in the cell region CA. As Figure 6 shown, the memory cell array 10 includes conductor layers 21 to 27 above the semiconductor substrate 20.

[0105] Specifically, above the semiconductor substrate 20, a conductor layer 21 is provided with an insulator layer (not shown) interposed therebetween. The conductor layer 21 is used as the select gate line SGS.

[0106] Above the conductor layer 21, a plurality of layers ( Figure 6 in the example of 8 layers) of an insulator layer (not shown) and a conductor layer 22 are alternately stacked. For example, a plurality of conductor layers 22 are sequentially used as word lines WL0 to WL7 from the side of the semiconductor substrate 20.

[0107] Above the topmost conductor layer 22, a conductor layer 23 is provided with an insulator layer (not shown) interposed therebetween. For example, the conductor layer 23 is used as the select gate line SGM.

[0108] Above the conductor layer 23, a plurality of layers ( Figure 6In the example of [number of layers], there are [number of layers] (e.g., in the case of 3 layers). For example, a plurality of conductive layers 23 are electrically connected to each other and used as one wiring CAPL.

[0109] The interval along the Z-axis between the conductive layer 23 and the lowermost conductive layer 24 can be greater than the intervals along the Z-axis between the adjacent conductive layers 21 and 22, between two adjacent conductive layers 22, and between the adjacent conductive layers 22 and 23.

[0110] Above the uppermost conductive layer 24, a conductive layer 25 is provided with an insulating layer (not shown) interposed therebetween. The conductive layer 25 is used as a select gate line SGD.

[0111] The conductive layers 21 to 25 are formed, for example, in a plate shape extending along the XY plane and contain tungsten (W).

[0112] Above the conductive layer 25, a conductive layer 27 is provided with an insulating layer (not shown) interposed therebetween. For example, the conductive layer 27 is used as a bit line BL. The conductive layer 27 contains copper (Cu), for example.

[0113] The memory pillar MP is provided to extend in the Z direction and reaches below the upper surface of the semiconductor substrate 20 through the conductive layers 21 to 25 at the bottom. The memory pillar MP includes a lower pillar LMP and an upper pillar UMP formed above the lower pillar LMP.

[0114] The lower pillar LMP includes, for example, a core film 30, a semiconductor film 31, a stacked film 32, and a semiconductor portion 33. Specifically, the core film 30 is provided at substantially the center of the lower pillar LMP and extends along the Z-axis. The upper end of the core film 30 is, for example, above the conductive layer 23 and below the lowermost conductive layer 24, and the lower end is, for example, below the conductive layer 21. The core film 30 contains an insulator such as silicon oxide (SiO2), for example.

[0115] The semiconductor film 31 contains, for example, polysilicon and covers the bottom surface and side surfaces of the core film 30. The lower end of the semiconductor film 31 is in contact with the semiconductor substrate 20, and the upper end of the semiconductor film 31 is above the conductive layer 23 and below the lowermost conductive layer 24. The semiconductor film 31 includes a cylindrical portion formed to surround the side surface of the core film 30.

[0116] The stacked film 32 covers the side surface of the semiconductor film 31. Details of the configuration of the stacked film 32 will be described later.

[0117] The semiconductor portion 33 covers the upper surface of the core film 30 and contacts the portion of the semiconductor film 31 that is above the core film 30. The semiconductor portion 33 has a cylindrical shape that reaches the upper end of the lower column LMP. The semiconductor portion 33 electrically connects the lower column LMP and the upper column UMP. For example, by containing n+-type impurities such as arsenic (As) or phosphorus (P), an increase in the resistance value is suppressed.

[0118] The upper column UMP includes, for example, a core film 40, a semiconductor film 41, an insulator film 42, a conductor film 43, an insulator film 44, and a semiconductor portion 45. Specifically, the core film 40 is disposed at approximately the center of the upper column UMP and extends along the Z-axis. The upper end of the core film 40 is, for example, located above the conductor layer 25, and the lower end is, for example, located below the lowermost conductor layer 24. The core film 40 contains, for example, an insulator such as silicon dioxide (SiO2).

[0119] The semiconductor film 41 contains, for example, polysilicon and covers the bottom surface and the side surface of the core film 40. The lower end of the semiconductor film 41 contacts the semiconductor portion 33 of the lower column LMP. The upper end of the semiconductor film 41 is located in a layer above the conductor layer 25. The semiconductor film 41 includes a cylindrical portion formed so as to surround the side surface of the core film 40.

[0120] The insulator film 42 contains a material having a dielectric constant higher than that of the stacked film 32 or the insulator film 44 (for example, a High-κ material such as ZrTiOx), and covers a part of the side surface of the semiconductor film 41. The upper end of the insulator film 42 is located between the uppermost conductor layer 24 and the conductor layer 25, and the lower end of the insulator film 42 is located between the lowermost conductor layer 24 and the lower end of the semiconductor film 41.

[0121] The conductor film 43 includes a metal material and covers the side surface of the insulator film 42. The upper end of the conductor film 43 is located between the uppermost conductor layer 24 and the conductor layer 25, and the lower end of the conductor film 43 is located between the lowermost conductor layer 24 and the upper end of the lower column LMP. That is, the conductor film 43 electrically connects the plurality of conductor layers 24.

[0122] The insulator film 44 contains an oxide of silicon nitride (SiN) and is disposed in a cylindrical shape between the conductor layer 25 and the semiconductor film 41. The insulator film 44 is provided together with the conductor layer 25 between interlayer insulating films (not shown) that sandwich the conductor layer 25 along the Z-axis. Therefore, the upper end and the lower end of the insulator film 44 are aligned with the upper end and the lower end of the conductor layer 25, respectively.

[0123] The semiconductor portion 45 covers the upper surface of the core film 40 and contacts the portion of the semiconductor film 41 that is above the core film 40. The semiconductor portion 45 is, for example, cylindrical and reaches the upper end of the upper column UMP.

[0124] On the semiconductor film 41 within the memory pillar MP and on the upper surface of the semiconductor portion 45, a conductor layer 26 is provided that functions as a columnar contact portion CP. The conductor layer 26 contains, for example, tungsten (W). The upper surface of the conductor layer 26 is in contact with and electrically connected to a corresponding one of the conductor layers 27 (bit lines BL).

[0125] The insulator layer 50 is formed, for example, in a plate shape along the YZ plane and functions as a slit SLT that divides the conductor layers 21 - 25 along the X axis. By means of the insulator layer 50, the conductor layers 21 - 25 are divided, for example, between two adjacent blocks BLK or between an adjacent block BLK and a dummy block dBLK. The upper end of the insulator layer 50 is located between the conductor layer 25 and the conductor layer 27, and the lower end of the insulator layer 50 is located, for example, below the upper surface of the semiconductor substrate 20. The insulator layer 50 contains, for example, an insulator such as silicon dioxide (SiO2).

[0126] The conductor layer 51 is formed, for example, in a plate shape along the YZ plane between the insulator layer 50 and the conductor layers 21 - 25 and functions as a contact portion LI that connects the semiconductor substrate 20 and the source line SL (not shown). The conductor layer 51 contains, for example, polysilicon.

[0127] The insulator layer 52 is formed, for example, in a plate shape along the YZ plane and functions as a slit SHE that divides the conductor layer 25 along the X axis. By means of the insulator layer 52, the conductor layer 25 is divided, for example, between two adjacent string units SU. The upper end of the insulator layer 52 is located between the conductor layer 25 and the conductor layer 27, and the lower end of the insulator layer 52 is located, for example, between the conductor layer 25 and the uppermost conductor layer 24. The insulator layer 52 contains, for example, an insulator such as silicon dioxide (SiO2).

[0128] Next, the cross-sectional structure of the memory pillar MP along the XY plane will be described with reference to Figure 7 、 Figure 8 、and Figure 9 for illustration.

[0129] Figure 7 is a cross-sectional view along the VII-VII line of Figure 6 showing an example of the cross-sectional structure of the portion of the lower pillar LMP that intersects the conductor layer 22.

[0130] As Figure 7 shown, a core film 30 is provided at the central portion of the lower pillar LMP, the semiconductor film 31 surrounds the side surface of the core film 30, and the stacked film 32 surrounds the side surface of the semiconductor film 31. The stacked film 32 contains, for example, a channel insulating film 32a, a charge storage film 32b, and a block insulating film 32c.

[0131] The channel insulating film 32a surrounds the side surface of the semiconductor film 31, the charge storage film 32b surrounds the side surface of the channel insulating film 32a, and the block insulating film 32c surrounds the side surface of the charge storage film 32b. The conductor layer 22 surrounds the side surface of the block insulating film 32c. The channel insulating film 32a and the block insulating film 32c each contain, for example, silicon oxide (SiO2), and the charge storage film 32b contains, for example, silicon nitride (SiN).

[0132] By being configured as described above, the portion of the lower pillar LMP that intersects the conductor layer 22 can function as a memory cell transistor MT. Similarly, the portions of the lower pillar LMP that intersect the conductor layers 21 and 23 can function as select transistors ST2 and ST3, respectively. That is, the semiconductor film 31 is used as the current path (channel) of each of the memory cell transistor MT and the select transistors ST2 and ST3 in the lower pillar LMP.

[0133] Figure 8 is a cross-sectional view along Figure 6 the VIII-VIII line, showing an example of the cross-sectional structure of the portion of the upper pillar UMP that intersects the conductor layer 24.

[0134] As Figure 8 shown, a core film 40 is provided at the center of the upper pillar UMP, the semiconductor film 41 surrounds the side surface of the core film 40, the insulator film 42 surrounds the side surface of the semiconductor film 41, and the conductor film 43 surrounds the side surface of the insulator film 42. The conductor layer 24 surrounds the side surface of the conductor film 43.

[0135] By being configured as described above, the portion of the upper pillar UMP that intersects the conductor layer 24 can function as a capacitor CAP. That is, the portion of the semiconductor film 41 that intersects the conductor layer 24 is used as one of the pair of electrodes (node N0) of the capacitor CAP. In addition, the conductor film 43 and the plurality of conductor layers 24 are used as the other electrode (wiring CAPL) of the pair of electrodes of the capacitor CAP. As a result, compared with the case where the capacitor is formed by a single layer of the conductor layer 24, the electrode area of the capacitor can be increased. In addition, by using a High-κ material in the insulator film 42, the dielectric constant between the electrodes can be increased. Therefore, the capacitor CAP can be designed to have a capacitance of a size that can be used as a DRAM.

[0136] Figure 9 is a cross-sectional view along Figure 6 the IX-IX line, showing an example of the cross-sectional structure of the portion of the upper pillar UMP that intersects the conductor layer 25.

[0137] As Figure 9As shown, a core film 40 is provided at the center of the upper column UMP, a semiconductor film 41 surrounds the side surface of the core film 40, an insulator film 42 surrounds the side surface of the semiconductor film 41, and an insulator film 44 surrounds the side surface of the semiconductor film 41. A conductor layer 25 surrounds the side surface of the insulator film 44.

[0138] With the above configuration, the portion of the upper column UMP that intersects the conductor layer 25 can function as a select transistor ST1. That is, the portion of the semiconductor film 41 that intersects the conductor layer 25 is used as the current path of the select transistor ST1 (i.e., between the bit line BL and the lower column LMP).

[0139] 1.1.4.2 Wiring Area

[0140] Figure 10 It is a plan view for explaining the structure of the wiring area of the memory cell array of the semiconductor memory device of the embodiment, corresponding to the area X in Figure 2 In Figure 10 As an example, a part of the area containing the structure corresponding to the block BLK0 in the wiring area HA is shown. In addition, in Figure 10 The illustration is omitted. The block / BLK, the dummy block dBLK, and / dBLK have the same configuration as the block BLK, so the description is omitted.

[0141] As in Figure 10 As shown, the wiring area HA includes, for example, slits SLT and SHE, contact portions LI and CC, and a wiring laminate.

[0142] The wiring layers SGD, CAPL, SGM, WL7 to WL0, and SGS that make up the wiring laminate are sequentially arranged in a stepped manner in the direction away from the cell area CA along the Y axis. That is, in a top view, the lower the wiring layer of SGD, CAPL, SGM, WL7 to WL0, and SGS, the longer it is along the Y axis, and it has a stepped area that does not overlap with the upper wiring layer.

[0143] Moreover, contact portions CC are provided in the stepped areas corresponding to the wiring layers. Specifically, in a top view, the contact portions CC_SGD0 to CC_SGD3 are respectively provided in the stepped areas of the select gate lines SGD0 to SGD3. The contact portion CC_CAPL is provided in the stepped area of the wiring CAPL. The contact portion CC_SGM is provided in the stepped area of the select gate line SGM. The contact portions CC_WL7 to CC_WL0 are respectively provided in the stepped areas of the word lines WL7 to WL0. The contact portion CC_SGS is provided in the stepped area of the select gate line SGS.

[0144] In addition, as described above, the wiring CAPL is composed of a plurality of conductor layers 24. For example, the plurality of conductor layers 24 have the same length along the Y-axis, so the ends along the Y-axis are aligned. Further, at the ends of the plurality of conductor layers 24 along the Y-axis, a structure JCT_CAPL for electrically connecting the plurality of conductor layers 24 is provided.

[0145] In addition, the planar layout of the wiring region HA described above is merely an example and is not limited thereto. For example, the number of steps of the stepped shape of the wiring layer can be arbitrarily designed. In addition to the step difference along the Y-axis, a step difference along the X-axis can also be provided. Further, in the wiring region HA, it is not limited to the contact portion CC, and a columnar structure body penetrating the stepped wiring layer along the Z-axis can also be provided. The columnar structure body has, for example, the same structure as the storage column MP and has a function of supporting the stepped structure body in the manufacturing process of the storage cell array 10 described later.

[0146] Figure 11 is a cross-sectional view taken along the XI-XI line of Figure 10 showing an example of the cross-sectional structure of the storage cell array 10 in the wiring region HA. As Figure 11 shown, the conductor layers 21 to 25 extend along the Y-axis and reach the wiring region HA.

[0147] In the wiring region HA, on the upper surface of the conductor layer 21, a conductor film 61 that functions as a contact portion CC_SGS is provided. On the upper surfaces of the plurality of conductor layers 22, a plurality of conductor films 62 that function as CC_WL0 to CC_WL7 in sequence from the lower layer are provided. On the upper surface of the conductor layer 23, a conductor film 63 that functions as a contact portion CC_SGM is provided. On the upper surface of the lowermost conductor layer 24, a conductor film 64 that functions as a contact portion CC_CAPL is provided. The conductor film 64 is connected, for example, to the upper surface of the upper conductor layer 24 and is electrically connected to all the conductor layers 24 through the conductor film 66. On the upper surface of the conductor layer 25, a conductor film 65 that functions as a contact portion CC_SGD is provided. The conductor films 61 to 65 contain tungsten (W), for example, and have a columnar shape extending along the Z-axis.

[0148] At the ends of the plurality of conductor layers 24, a conductor film 66 that functions as a structure JCT_CAPL is provided. The conductor film 66 contains tungsten (W), for example, and has a plate-like shape extending along the XZ plane and is in contact with the plurality of conductor layers 24 respectively.

[0149] 1.1.5 Sense Amplifier

[0150] Next, the configuration of the sense amplifier of the semiconductor memory device according to the embodiment will be described.

[0151] Figure 12 This is a circuit diagram showing the configuration of a sense amplifier of a semiconductor memory device according to an embodiment. In Figure 12 it shows Figure 2 the circuit configuration of one sense amplifier SA connected to one pair of bit lines BL and / BL in the sense amplifier module 16 shown.

[0152] As Figure 12 shown, the sense amplifier SA includes transistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, and Tr7. Transistors Tr1, Tr3, and Tr5 are, for example, p-type MOS (Metal Oxide Semiconductor) transistors, and transistors Tr2, Tr4, Tr6, and Tr7 are n-type MOS transistors.

[0153] Transistor Tr1 includes a first end connected to node N1, a second end connected to node N3, and a gate connected to node N2. Transistor Tr2 includes a first end connected to node N1, a second end connected to node N4, and a gate connected to node N2.

[0154] Transistor Tr3 includes a first end connected to node N2, a second end connected to node N3, and a gate connected to node N1. Transistor Tr4 includes a first end connected to node N2, a second end connected to node N4, and a gate connected to node N1.

[0155] Transistor Tr5 includes a first end to which a power supply voltage VDD is applied, a second end connected to node N3, and a gate supplied with a signal ENn. Transistor Tr6 includes a first end connected to node N4, a second end to which a voltage VSS is applied, and a gate supplied with a signal EN. The signal ENn is an inverted signal of the signal EN. The voltage VSS is a ground voltage, for example, 0V.

[0156] Transistor Tr7 includes a first end connected to node N1, a second end connected to node N2, and a gate supplied with a signal EQ.

[0157] In the sense amplifier SA configured as described above, the bit line BL is connected via node N1, and the bit line / BL is connected via node N2. Thus, in one sense amplifier SA, a dummy memory string dMS and a plurality of memory strings MS are connected in parallel via the bit line BL, and a dummy memory string / dMS and a plurality of memory strings / MS are connected in parallel via the bit line / BL.

[0158] 1.2 Operation

[0159] Next, the operation of the semiconductor memory device according to the embodiment will be described.

[0160] In addition, in the following description, the storage cell transistors MT (NAND storage cells) and capacitors CAP (DRAM storage cells) that are the objects of operation are respectively referred to as selected storage cell transistors MT and selected capacitors CAP, and the storage cell transistors MT other than the selected storage cell transistors MT and the capacitors CAP other than the selected capacitors CAP are referred to as non-selected storage cell transistors MT and non-selected capacitors CAP. The word line WL connected to the selected storage cell transistor MT is referred to as the selected word line WLsel, and the word line WL other than the selected word line WLsel is referred to as the non-selected word line WLusel. The string unit SU including the selected storage cell transistor MT and the selected capacitor CAP is referred to as the selected string unit SU, and the string unit SU other than the selected string unit SU is referred to as the non-selected string unit SU.

[0161] 1.2.1 Read Operation

[0162] For the read operation of the semiconductor memory device of the embodiment, the Figure 13 shown timing chart is used for explanation. Figure 13 This shows the case of reading data from the selected storage cell transistor MT connected to the group of a certain bit line BL and the selected word line WLsel.

[0163] First, the operation of transferring data from the selected storage cell transistor MT to the selected capacitor CAP will be described. In the read operation of the present embodiment, by transferring data from the selected storage cell transistor MT to the selected capacitor CAP, the data stored in the selected capacitor CAP is destroyed.

[0164] As Figure 13 shown, until time t1, a voltage VSS is applied to the bit line BL and / BL, the selection gate lines SGD, SGM, and SGS, the wiring CAPL, the contact portion LI, and all the word lines WL. In addition, a voltage VSS is applied to the channel of the memory string MS (selected memory string MS) including the selected storage cell transistor MT and the selected capacitor CAP.

[0165] At time t1, the operation of transferring the data stored in the selected storage cell transistor MT to the selected capacitor CAP starts. Specifically, the row decoder module 15 applies a voltage Vsg to the selection gate lines SGS and SGM, and applies a voltage VDD to the source line SL via the contact portion LI. The voltage Vsg is, for example, a voltage that turns on each of the selection transistors ST1 to ST3. As a result, the selection transistors ST2 and ST3 become conductive.

[0166] In addition, the row decoder module 15 applies a voltage VCGR to the selected word line WLsel and a voltage VREAD to the non-selected word line WLusel. The voltage VREAD is a voltage that turns on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT.

[0167] When the threshold voltage of the selected memory cell transistor MT is less than the voltage VCGR (i.e., when the selected memory cell transistor MT stores data "1"), all the memory cell transistors MT in the selected memory string MS become conductive. Therefore, the voltage VDD of the source line SL is transmitted to the node N0 through the channels of the memory cell transistors MT and the selection transistor ST3 in the selected memory string MS. As a result, the node N0 becomes a voltage of VDD / 2 or higher, and the data "1" of the selected memory cell MT is transmitted to the selection capacitor CAP.

[0168] On the other hand, when the threshold voltage of the selected memory cell transistor MT is equal to or higher than the voltage VCGR (i.e., when the selected memory cell MT stores data "0"), the selected memory cell transistor MT becomes non-conductive. Therefore, the voltage VDD of the source line SL is not transmitted in the channel in the memory string MS closer to the capacitor CAP than the selected memory cell transistor MT. As a result, the voltage of the node N0 remains at the voltage VSS (less than VDD / 2), and the data "0" of the selected memory cell transistor MT is transmitted to the selection capacitor CAP.

[0169] At time t2, the voltage VSS is applied to the bit lines BL and / BL, the selected gate lines SGD, SGM, and SGS, the wiring CAPL, the contact portion LI, and all the word lines WL. Along with this, the voltage VSS is applied to the channel of the selected memory string MS. Thus, the period of transmitting the data of the selected memory cell transistor MT to the selection capacitor CAP ends.

[0170] Next, the operation of reading the data in the selection capacitor CAP into the sense amplifier module 16 will be described.

[0171] At time t3, the sense amplifier SA in the sense amplifier module 16 applies a voltage VDD / 2 to the corresponding bit lines BL and / BL. Specifically, for example, the sequencer 13 supplies a signal ENn of "L" level, a signal EN of "H" level, and a signal EQ of "H" level, turning on the transistors Tr5 to Tr7 in the sense amplifier SA. As a result, the voltages of the bit lines BL and / BL are made equal to the intermediate voltage between the voltage VDD and the voltage VSS (= VDD / 2). In addition, Figure 13The illustration is omitted. At time t3, the row decoder module 15 applies a voltage Vsg to the dummy selection gate line / dSGD corresponding to the dummy block / dBLK. As a result, the dummy selection transistor / dST1 corresponding to the dummy block / dBLK becomes conductive, and the dummy capacitor / dCAP is charged to the voltage VDD / 2.

[0172] At time t4, the row decoder module 15 applies a voltage Vsg to the selection gate line SGD corresponding to the selected string unit SU, and continues to apply a voltage VSS to the selection gate line SGD corresponding to the non-selected string unit SU. As a result, the selection transistor ST1 corresponding to the selected string unit SU becomes conductive.

[0173] At time t5, the sequencer 13 supplies a signal EQ of "L" level, turning off the transistor Tr7 in the sense amplifier SA. As a result, the voltages of the bit lines BL and / BL change based on the magnitude relationship of the charge amounts between the selection capacitor CAP and the dummy capacitor / dCAP.

[0174] When the voltage at the node N0 of the capacitor CAP is equal to or higher than the voltage VDD / 2 (i.e., when the capacitor CAP stores data "1"), the voltage of the bit line BL slightly rises from the voltage VDD / 2. The sense amplifier SA amplifies the voltage difference between the bit lines BL and / BL, and applies voltages VDD and VSS to the bit lines BL and / BL, respectively. As a result, the sense amplifier module 16 senses that the voltage of the bit line BL is equal to or higher than the voltage VDD / 2, and can read the data "1" from the selection capacitor CAP.

[0175] On the other hand, when the voltage at the node N0 of the capacitor CAP is less than the voltage VDD / 2 (i.e., when the capacitor CAP stores data "0"), the voltage of the bit line BL slightly drops from the voltage VDD / 2. The sense amplifier SA amplifies the voltage difference between the bit lines BL and / BL, and applies voltages VSS and VDD to the bit lines BL and / BL, respectively. As a result, the sense amplifier module 16 senses that the voltage of the bit line BL is less than the voltage VDD / 2, and can read the data "1" from the selection capacitor CAP.

[0176] At time t6, the row decoder module 15 applies a voltage VSS to the selection gate line SGD corresponding to the selected string unit SU, turning off the selection transistor ST1.

[0177] At time t7, the sense amplifier module 16 applies a voltage VSS to the bit line BL.

[0178] By operating as described above, the read operation from the selection capacitor CAP is completed.

[0179] In addition, the charge stored in the capacitor CAP leaks over time. Therefore, when the data "1" is stored in the capacitor CAP, in order to maintain the node N0 at a voltage equal to or higher than VDD / 2, a refresh operation is periodically performed. The refresh operation is the same as the read operation for selecting the capacitor CAP ( Figure 13 the operation from time t3 to time t7 in

[0180] 1.2.2 Erase Operation

[0181] Next, the erase operation of the semiconductor memory device according to the embodiment will be described using the Figure 14 timing diagram shown. Figure 14 This shows the case where data is erased from the selected memory cell transistor MT connected to the group of a certain bit line BL and the selected word line WLsel. In addition, even during the execution of the erase operation, data is stored in the selected capacitor CAP.

[0182] As Figure 14 shown, until time t11, a voltage VSS is applied to the bit line BL and / BL, the selected gate lines SGD, SGM, and SGS, the wiring CAPL, the contact portion LI, and all the word lines WL. Along with this, a voltage VSS is applied to the channel on the memory cell transistor MT side of the selected memory string MS that is closer to the selected transistor ST3 than the selected transistor ST3. On the other hand, at the node N0, a voltage corresponding to the data stored in the selected capacitor CAP is charged (a voltage equal to or higher than VDD / 2 when the data "1" is stored, and a voltage VSS when the data "0" is stored).

[0183] At time t11, the row decoder module 15 applies a voltage VERA to the contact portion LI. The voltage VERA is a high voltage used to extract the charge accumulated in the memory cell transistor MT. In addition, the row decoder module 15 continuously applies a voltage VSS and Va to the selected word line WLsel and the selected gate line SGM, respectively, and sets the non-selected word line WLusel and the selected gate line SGS to a floating state. The voltage Va is a constant voltage used to make the gate-source voltage of the selected transistor ST3 less than the voltage VERA, suppressing the charge accumulated in the selected transistor ST3 from being extracted during the erase operation. As a result, the gate-source voltage of the selected memory cell transistor MT selectively becomes the voltage VERA, and the data stored in the selected memory cell transistor MT is erased.

[0184] At time t17, the row decoder module 15 applies a voltage VSS to the contact portion LI, the selected gate lines SGM and SGS, and all the word lines WL.

[0185] By operating as described above, the erasing operation ends.

[0186] In addition, the period required for the erasing operation can be made variable with respect to the interval of the refresh operation periodically performed on the capacitor CAP. Therefore, in the example of Figure 14 , the case where the refresh operation is performed during the periods t12 to t16 between the times t11 and t17 is shown. The refresh operations at the times t12 to t16 are the same as the refresh operations at the times t3 to t7 described in Figure 13 , and thus the description thereof is omitted. Accordingly, even during the execution of the erasing operation, the voltage of the node N0 storing the data "1" can be maintained at VDD / 2 or higher.

[0187] 1.2.3 Write operation

[0188] Next, the write operation of the semiconductor memory device according to the embodiment will be described using the Figure 15 shown timing chart. Figure 15 The case where data is written to the selected memory cell transistor MT connected to the pair of a certain bit line BL and the selected word line WLsel is shown.

[0189] First, the operation of writing data to the selected capacitor CAP via the bit line BL will be described.

[0190] As Figure 15 shown, until the time t21, the voltage VSS is applied to the bit line BL and / BL, the selection gate lines SGD, SGM, and SGS, the wiring CAPL, the contact portion LI, and all the word lines WL. Along with this, the voltage VSS is applied to the channel of the selected memory string MS.

[0191] At the time t21, the sense amplifier module 16 applies the voltage VDD to the bit line BL of the selected capacitor CAP to which the predetermined write data "1" is to be connected, and applies the voltage VSS to the bit line BL of the selected capacitor CAP to which the predetermined write data "0" is to be connected.

[0192] In addition, the row decoder module 15 applies the voltage Vsg to the selection gate line SGD corresponding to the selected string unit SU, and applies the voltage VSS to the selection gate line SGD corresponding to the non-selected string unit SU. As a result, only the selection gate line SGD corresponding to the selected string unit SU becomes conductive, and the voltage applied to the bit line BL is transmitted to the node N0. That is, the voltage VDD is transmitted to the node N0 of the selected capacitor CAP for which the predetermined write data "1" is to be connected, and the voltage VSS is transmitted to the node N0 of the selected capacitor CAP for which the predetermined write data "0" is to be connected.

[0193] At time t22, the sense amplifier module 16 applies voltage VSS to the bit line BL, and the row decoder module 15 applies voltage VSS to the select gate SGD.

[0194] By operating as described above, data is written to the select capacitor CAP.

[0195] Next, the operation of transferring the data written to the select capacitor CAP to the select memory cell transistor MT will be described.

[0196] During the time period from t23 to t28, a refresh operation of the data stored in the select capacitor CAP is performed. That is, at Figure 15 times t23, t24, t25, t27, and t28 in Figure 13 the same operations as those at times t3, t4, t5, t6, and t7 in

[0197] are performed. As a result, the voltage of the node N0 of the select capacitor CAP storing the data "1" approaches the voltage VDD.

[0198] In addition, at time t26 between time t25 when the voltage of the node N0 is refreshed and time t27, the row decoder module 15 applies voltage Vsg to the select gate line SGM, and applies voltages VPGM and VPASS to the select word line WLsel and the non-select word line WLusel, respectively. The voltage VPASS is a voltage that turns on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT and suppresses the increase in the threshold voltage of the memory cell transistor MT. The voltage VPGM is a voltage higher than the voltage VPASS that increases the threshold voltage of the memory cell transistor MT.

[0199] As a result, in the memory string MS where the voltage VDD is applied to the node N0 (where the data "1" is stored in the select capacitor CAP), the voltage VDD is transferred to the channel on the memory cell transistor MT side. Therefore, the voltage (VPGM - VDD) is applied to the select memory cell transistor MT. As a result, the threshold voltage of the select memory cell transistor MT does not increase, and as a result, the data "1" is written to the select memory cell transistor MT.

[0200] Thereafter, at time t27, the row decoder module 15 applies the voltage VPASS to the selected word line WLsel and applies the voltage VSS to the selected gate line SGD.

[0201] At time t29 after time t28, the row decoder module 15 applies the voltage Vsg to the selected gate line SGS, turning on the selected transistor ST2. As a result, the channel is electrically connected to the source line SL, and the electrons in the channel are drawn toward the source line SL side.

[0202] At time t30, the row decoder module 15 applies the voltage VSS to the selected gate line SGS.

[0203] By operating as described above, the writing operation is completed.

[0204] 1.3 Manufacturing Method

[0205] Next, an example of a series of manufacturing steps from forming the laminate on the semiconductor substrate 20 to forming the slit SHE in the semiconductor memory device of the embodiment will be described. Figure 16 , Figure 17 , Figures 19 to 22 , Figure 24 , Figure 25 , and Figure 31 Shows an example of a cross-sectional structure of a structure including a structure corresponding to the wiring region HA of the memory cell array 10 in the manufacturing steps of the semiconductor memory device of the embodiment. Figure 18 , Figure 23 , Figures 26 to 30 , and Figures 32 to 34 Shows an example of a cross-sectional structure of a structure including a structure corresponding to the cell region CA of the memory cell array 10 in the manufacturing steps of the semiconductor memory device of the embodiment.

[0206] First, as Figure 16 shown, an insulator layer 71 and a sacrificial material 72 are laminated on the upper surface of the semiconductor substrate 20 over the cell region CA and the wiring region HA. On the upper surface of the sacrificial material 72, a plurality of layers ( Figure 16 in the example of 8 layers) of the insulator layer 71 and the sacrificial material 73 are alternately laminated. On the upper surface of the uppermost sacrificial material 73, an insulator layer 71 and a sacrificial material 74 are laminated. On the upper surface of the sacrificial material 74, an insulator layer 71 is laminated. The insulator layer 71 contains, for example, silicon oxide (SiO2), and the sacrificial materials 72 to 74 contain, for example, silicon nitride (SiN).

[0207] Next, as Figure 17As shown, in the wiring region HA, a mask (not shown) is provided on the upper surface of the uppermost insulator layer 71, and a pattern is formed on the mask by lithography. Thereafter, the following steps are repeated in sequence: anisotropic etching of the laminated structure of the sacrificial materials 72 to 74 and the insulator layer 71 based on the obtained pattern, and removal of a part of the mask pattern by thinning it. Thus, etching can be performed in such a manner that the portion corresponding to the wiring region HA in the laminated structure becomes stepped along the Y axis. The anisotropic etching in this step is, for example, RIE (Reactive Ion Etching). Thereafter, the stepped structure is buried by the insulator layer 75 up to the position of the uppermost insulator layer 71. The insulator layer 75 contains, for example, silicon oxide (SiO2).

[0208] Next, as Figure 18 shown, in the cell region CA, a lower pillar LMP is formed. Specifically, for example, by lithography and anisotropic etching, a hole is formed that passes through the insulator layer 71 and the sacrificial materials 72 to 74 and reaches the semiconductor substrate 20. Next, a laminated film 32 is formed by sequentially forming a block insulating film 32c, a charge storage film 32b, and a channel insulating film 32a in the hole. Then, after removing the laminated film 32 at the bottom of the hole by anisotropic etching, a semiconductor film 31 and a core film 30 are sequentially formed, and the hole is filled. The anisotropic etching in this step is, for example, RIE. Thereafter, the core film 30 is removed to a specific depth from the upper end of the hole, and a semiconductor portion 33 is formed in the space where a part of the core film 30 has been removed. In the semiconductor portion 33, for example, n+-type impurities are doped. Thus, the lower pillar LMP is formed.

[0209] Next, as Figure 19 shown, over the cell region CA and the wiring region HA, a plurality of layers ( Figure 19 in the example, three layers) of the insulator layer 76 and the sacrificial material 77 are alternately laminated on the upper surfaces of the insulator layers 71 and 75. An insulator layer 76 is laminated on the upper surface of the uppermost sacrificial material 77. The insulator layer 76 contains, for example, silicon oxide (SiO2), and the sacrificial material 77 contains, for example, silicon nitride (SiN).

[0210] Next, as Figure 20 shown, in the wiring region HA, a mask (not shown) is provided on the upper surface of the uppermost insulator layer 76, and a pattern is formed on the mask by lithography. Thereafter, anisotropic etching of the laminated structure of the sacrificial material 77 and the insulator layer 76 is performed based on the obtained pattern. Thus, in the wiring region HA, a part of the insulator layer 71 and the insulator layer 75 are exposed. In addition, at the end along the Y axis of the laminated structure of the sacrificial material 77 and the insulator layer 76, each of the plurality of layers of the sacrificial material 77 is exposed. The anisotropic etching in this step is, for example, RIE.

[0211] Next, as Figure 21 shown, after the sacrificial material 78 is disposed comprehensively, the sacrificial material 78 is patterned using lithography and anisotropic etching. Thus, the sacrificial material 78 is removed except for the portion along the Y-axis end of the stacked structure covering the sacrificial material 77 and the insulator layer 76 (i.e., the plate-like portion along the XZ plane). The sacrificial material 78 contains, for example, silicon nitride (SiN).

[0212] Next, as Figure 22 shown, an insulator layer 79 is formed in such a manner as to fill the portion of the stacked structure of the sacrificial material 77 and the insulator layer 76 removed by the steps Figure 20 shown. The insulator layer 79 contains, for example, silicon dioxide (SiO2). The sacrificial material 78 and the insulator layer 79 are removed, for example, by CMP (Chemical Mechanical Polishing) for the portion above the uppermost insulator layer 76.

[0213] Next, as Figure 23 shown, in the cell region CA, a part of the upper pillar UMP is formed. Specifically, for example, using lithography and anisotropic etching, a hole is formed that passes through the lowermost sacrificial material 77 and reaches the lowermost insulator layer 76. Additionally, it is desirable that the semiconductor portion 33 of the lower pillar LMP is not exposed at the bottom of the hole. Next, a conductor film 43 is formed in the hole. After removing the conductor film 43 at the bottom of the hole using anisotropic etching, an insulator film 42 is formed. Then, using anisotropic etching, the insulator film 42 at the bottom of the hole is further removed to expose the semiconductor portion 33 of the lower pillar LMP. The anisotropic etching in this step is, for example, RIE. Thereafter, a sacrificial material 80 is formed and the hole is filled. The sacrificial material 80 contains, for example, amorphous silicon.

[0214] In addition, in the above example, the case where the semiconductor portion 33 is exposed at the timing of removing a part of the insulator film 42 has been described, but it is not limited thereto. The timing at which the semiconductor portion 33 is exposed is arbitrary as long as the condition that the conductor film 43 does not contact the semiconductor portion 33 is satisfied.

[0215] Next, as Figure 24 shown, the insulator layer 81 and the sacrificial material 82 are alternately stacked on the upper surfaces of the insulator layers 76 and 79 and the sacrificial material 78 throughout the cell region CA and the wiring region HA. The insulator layer 81 is stacked on the upper surface of the uppermost sacrificial material 82. The insulator layer 81 contains, for example, silicon dioxide (SiO2), and the sacrificial material 82 contains, for example, silicon nitride (SiN).

[0216] Next, as Figure 25As shown, in the wiring region HA, a mask (not shown) is provided on the upper surface of the uppermost insulator layer 81, and a pattern is formed on the mask using lithography. Thereafter, anisotropic etching is performed on the stacked structure of the sacrificial material 82 and the insulator layer 81 based on the obtained pattern. As a result, in the wiring region HA, a part of the insulator layer 76, the insulator layer 79, and the sacrificial material 78 are exposed. The anisotropic etching in this step is, for example, RIE. Thereafter, the removed portions of the stacked structure of the sacrificial material 82 and the insulator layer 81 are filled with the insulator layer 83 up to the position of the uppermost insulator layer 81. The insulator layer 81 contains, for example, silicon oxide (SiO2).

[0217] Next, as Figure 26 shown, in the cell region CA, a hole H1 is formed above a part of the upper pillar UMP formed by the steps Figure 23 shown. The hole H1 passes through, for example, the sacrificial material 82 and reaches the lowermost insulator layer 81. As a result, the sacrificial material 82 is exposed within the hole H1. Next, an oxidation treatment is performed on the sacrificial material 82 exposed within the hole H1 to form an insulator film 44.

[0218] Next, as Figure 27 shown, after removing the insulator layer 81 at the bottom of the hole H1 to expose the sacrificial material 80, the sacrificial material 80 is selectively removed. As a result, a hole H2 is formed in which the semiconductor portion 33 is exposed at the bottom.

[0219] Next, as Figure 28 shown, a semiconductor film 41 and a core film 40 are sequentially formed within the hole H2, and the hole H2 is filled. Thereafter, the core film 40 is removed to a specific depth from the upper end of the hole H2, and a semiconductor portion 45 is formed in the space where a part of the core film 40 has been removed. As a result, the upper pillar UMP is formed.

[0220] Next, as Figure 29 shown, in the cell region CA, a hole H3 is formed in a region corresponding to the slit SLT and the contact portion LI. The hole H3 divides the sacrificial materials 72 to 74, 77, and 82. The lower end of the hole H3 reaches, for example, the semiconductor substrate 20. As a result, the sacrificial materials 72 to 74, 77, and 82 are exposed within the hole H3.

[0221] Next, as Figure 30 and Figure 31As shown, throughout the cell region CA and the wiring region HA, the sacrificial materials 72 to 74, 77, and 82 are respectively replaced with the conductor layers 21 to 25, and the sacrificial material 78 is replaced with the conductor film 66. Specifically, via the hole H3, the sacrificial materials 72 to 74, 77, and 82 are selectively removed, for example, by wet etching. Also, for the sacrificial material 78 exposed in the wiring region HA after the removal of the sacrificial material 77, it is also selectively removed simultaneously by the wet etching. Then, in the space where the sacrificial materials 72 to 74, 77, 78, and 82 have been removed, the conductor layers 21 to 23, 24, the conductor film 66, and the conductor layer 25 are provided via the hole H3.

[0222] Next, as Figure 32 shown, an insulator layer 50 is formed in the hole H2. Next, after removing the insulator layer 50 at the bottom of the hole H2, the semiconductor substrate 20 is exposed again. Then, a conductor layer 51 is formed in the hole H2 where the semiconductor substrate 20 is exposed again, and the hole H2 is filled.

[0223] Next, as Figure 33 shown, in the cell region CA, after forming the insulator layer 84 on the upper surface, a hole H4 is formed in the region corresponding to the slit SHE. The hole H4 divides the conductor layer 25, and the lower end of the hole H4 reaches, for example, the lowermost insulator layer 81.

[0224] Next, as Figure 34 shown, an insulator layer 52 is formed in the hole H4, and the hole H4 is filled.

[0225] According to the above steps, a series of manufacturing steps from the formation of the laminate on the semiconductor substrate 20 to the formation of the slit SHE are completed.

[0226] 1.4 Effects of this Embodiment

[0227] According to the embodiment, the memory string MS includes: a memory cell transistor MT connected to the bit line BL and functioning as a NAND memory cell; and a capacitor CAP connected between the bit line BL and the memory cell transistor MT and functioning as a DRAM memory cell. Thus, in one semiconductor memory device 1, access can be made to both the NAND memory cell and the DRAM memory cell via the same bit line BL. Therefore, compared with the case where the NAND memory cell and the DRAM memory cell are provided in different semiconductor memory devices, the transfer frequency of data from the DRAM memory cell to the NAND memory cell can be increased, and further, the storage capacity required for the DRAM memory cell in the memory system can be reduced. Therefore, the power required for the refresh operation of the DRAM memory cell can be reduced, and an increase in power consumption can be suppressed.

[0228] In addition, on the semiconductor substrate 20, DRAM memory cells are disposed above the NAND memory cells. Thus, the area occupied by the DRAM memory cells can be shared with the NAND memory cells within the memory system. Therefore, the constraint on the area requirement for the memory system can be alleviated.

[0229] In addition, the memory cell array 10 is divided into two regions sandwiching the sense amplifier module 16. The sense amplifiers SA within the sense amplifier module 16 are connected to the two regions of the memory cell array 10 via bit lines BL and / BL, respectively. Thus, the sense amplifier SA can read the data of the memory string MS connected to the bit line BL by comparing it with the dummy memory string / dMS connected to the bit line / BL.

[0230] Specifically, after setting the bit lines BL and / BL to the voltage VDD / 2, the sense amplifier SA turns on the selection transistor ST1 that selects the memory string MS. Thus, when the voltage of the selection capacitor CAP is charged to VDD / 2 or higher, the voltage of the bit line BL is higher than that of the bit line / BL, and when the voltage of the selection capacitor CAP is charged to less than VDD / 2, the voltage of the bit line BL is lower than that of the bit line / BL. Therefore, the sense amplifier SA can determine the data based on the voltage difference between the bit line BL and the bit line / BL.

[0231] In addition, in order to accurately sense the voltage change of the bit line BL or / BL during the read operation, it is desirable that the capacitance of the capacitor CAP is about 10% or more of the capacitances of the bit lines BL and / BL. That is, it is desirable to increase the capacitance of the capacitor CAP as much as possible and decrease the capacitance of the bit line BL as much as possible.

[0232] According to this embodiment, in the insulator film 42 used for the capacitor CAP, a High-κ material is used. Thus, the dielectric constant of the insulator film 42 can be made higher than the dielectric constants of the stacked film 32 used for the memory cell transistor MT and the insulator film 44 used for the selection transistor ST1. Therefore, for example, even when the film thickness of the insulator film 42 is the same as those of the stacked film 32 and the insulator film 44, a capacitance sufficient to function as a DRAM memory cell can be given to the capacitor CAP.

[0233] In addition, a plurality of conductive layers 24 are stacked along the Z axis. Thus, the area of the electrode of the capacitor CAP can be increased. Therefore, compared with the case where the conductive layer 24 is a single layer, the capacitance of the capacitor CAP can be increased. In addition, the plurality of conductive layers 24 are commonly connected via the conductive films 43 and 66. Thus, the plurality of conductive layers 24 can be regarded as one electrode.

[0234] 2. Others

[0235] In addition, in the above-described embodiment, the case where the memory cell array 10, the peripheral circuit PERI, the row decoder module 15, and the sense amplifier module 16 are arranged along the X-axis or the Y-axis in a plan view has been described, but it is not limited thereto. For example, the peripheral circuit PERI, the row decoder module 15, and the sense amplifier module 16 may also be provided between the memory cell array 10 and the semiconductor substrate 20.

[0236] In addition, in the above-described embodiment, the case where the dummy block dBLK is provided between the plurality of blocks BLK0 to BLKn and the sense amplifier module 16 has been described, but it is not limited thereto. For example, the dummy block dBLK may also be arranged in such a manner that the plurality of blocks BLK0 to BLKn are interposed therebetween and the sense amplifier module 16.

[0237] In addition, in the above-described embodiment, the case where the selection gate line SGM is commonly connected to the gates of all the selection transistors ST3 in the same block BLK has been described, but it is not limited thereto. For example, the selection gate line SGM may also be individually provided corresponding to each of the string units SU0 to SU3 in the same block BLK, similarly to the selection gate SGD.

[0238] Several embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The embodiments and their variations are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor memory device, comprising: A first bit line; A first memory cell transistor, connected to the first bit line; A first capacitor, connected between the first memory cell transistor and the first bit line; A first selection transistor, serially connecting between the first memory cell transistor and the first bit line; And A second selection transistor, serially connecting between the first selection transistor and the first bit line; and The first capacitor has a first end connected between the first selection transistor and the second selection transistor.

2. The semiconductor memory device according to claim 1, further comprising a second memory cell transistor serially connecting between the first memory cell transistor and the first selection transistor.

3. The semiconductor memory device according to claim 1, further comprising: A second bit line; A third memory cell transistor, connected to the second bit line; A second capacitor, having a first end connected between the third memory cell transistor and the second bit line; and A sense amplifier, connected between the first bit line and the second bit line.

4. The semiconductor memory device according to claim 3, wherein the sense amplifier is configured to determine data based on a voltage difference between the second bit line and the first bit line.

5. The semiconductor memory device according to claim 4, wherein the data is data stored in the first capacitor.

6. The semiconductor memory device according to claim 4, wherein the data is data stored in the first memory cell transistor.

7. The semiconductor memory device according to claim 3, wherein the sense amplifier includes: A first transistor, including a first end connected to the first bit line, a second end connected to a first node, and a gate connected to the second bit line; A second transistor, including a first end connected to the first bit line, a second end connected to a second node, and a gate connected to the second bit line; A third transistor, including a first end connected to the second bit line, a second end connected to the first node, and a gate connected to the first bit line; And A fourth transistor, including a first end connected to the second bit line, a second end connected to the second node, and a gate connected to the first bit line.

8. The semiconductor memory device according to claim 7, wherein the sense amplifier includes: A fifth transistor, including a first end connected to the first node, and a second end applied with a first voltage; A sixth transistor, including a first end connected to the second node, and a second end applied with a second voltage lower than the first voltage; and A seventh transistor, including a first end connected to the first bit line, and a second end connected to the second bit line.

9. The semiconductor memory device according to claim 8, wherein the sense amplifier is configured to determine data according to whether the voltage of the first bit line is equal to or higher than an intermediate voltage between the first voltage and the second voltage.

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