Heterogeneous integrated digitally controlled delay chip and method of manufacturing the same

Abstract

The application is suitable for the field of integrated circuit technology, and provides a heterogeneous integrated digital delay chip and a preparation method thereof.The heterogeneous integrated digital delay chip comprises an upper chip and a lower chip;the upper chip is a silicon-based MEMS chip, and the upper chip is provided with a delay circuit and a reference circuit;the lower chip is a GaAs chip, and the lower chip is provided with a switch circuit and a driving circuit;the upper chip and the lower chip are connected, and the upper chip is located directly above the lower chip.The application reduces the size of the digital delay chip and reduces power consumption.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to heterogeneous integrated numerical control delay chip and its fabrication method. Background Technology

[0002] Traditional numerically controlled delay chips are two-dimensional planar topologies designed using gallium arsenide (GaAs) technology. Internally, the chip consists of LC delay cells, switching networks, and other components. Due to the Q-factor limitations of LC delay cells in GaAs technology, delay chips exhibit high insertion loss and large area when the delay value is large and the number of bits is high. In the radio frequency (RF) front-end, this characteristic of GaAs restricts system performance. In the receiver link, it limits system noise; in the transmitter link, it increases power consumption. Summary of the Invention

[0003] To overcome the technical problems of large size and high power consumption of numerical control delay chips in related technologies, this application provides a heterogeneous integrated numerical control delay chip and its fabrication method.

[0004] This application is achieved through the following technical solution:

[0005] In a first aspect, embodiments of this application provide a heterogeneous integrated numerical control delay chip, comprising: an upper-layer chip and a lower-layer chip;

[0006] The upper-layer chip is a silicon-based MEMS chip, which contains delay circuits and reference circuits.

[0007] The lower-level chip is a GaAs chip, and the lower-level chip contains switching circuits and driving circuits;

[0008] The upper-layer chip is connected to the lower-layer chip, with the upper-layer chip located directly above the lower-layer chip.

[0009] In conjunction with the first aspect, in some possible implementations, the upper-layer chip is a single-layer silicon-based MEMS chip or a double-layer silicon-based MEMS chip. The double-layer silicon-based MEMS chip is provided with a double-layer silicon-based substrate, and the single-layer silicon-based MEMS chip is provided with a single-layer silicon-based substrate.

[0010] In conjunction with the first aspect, in some possible implementations, the silicon substrate thickness of a single-layer silicon-based MEMS chip is 390-410um, and the silicon substrate thickness of a double-layer silicon-based MEMS chip is 780-820um.

[0011] In conjunction with the first aspect, in some possible implementations, the GaAs chip has a gallium arsenide substrate thickness of 70 μm.

[0012] In conjunction with the first aspect, in some possible implementations, the driving circuit is a positive voltage driving circuit or a TTL level conversion circuit.

[0013] In conjunction with the first aspect, in some possible implementations, the upper-layer chip and the lower-layer chip are connected by gold-to-gold bonding, thermo-bonding, or wire bonding.

[0014] In conjunction with the first aspect, in some possible implementations, the upper-layer chip and the lower-layer chip are connected via through-holes.

[0015] Secondly, embodiments of this application provide a method for fabricating a heterogeneous integrated numerically controlled delay chip, including:

[0016] An upper-layer chip with a delay circuit and a reference circuit is fabricated; the upper-layer chip is a silicon-based MEMS chip.

[0017] A lower-level chip with switching circuits and driving circuits is fabricated. The lower-level chip is a GaAs chip.

[0018] By connecting the upper-layer chip and the lower-layer chip, a heterogeneous integrated CNC delay chip is obtained. The upper surface of the upper-layer chip is the upper surface of the heterogeneous integrated CNC delay chip, and the lower surface of the lower-layer chip is the lower surface of the heterogeneous integrated CNC delay chip. In conjunction with the second aspect, in some possible implementations, connecting the upper-layer chip and the lower-layer chip to obtain the heterogeneous integrated CNC delay chip includes: the upper-layer chip and the lower-layer chip are connected by gold-to-gold bonding, thermoforming bonding, or wire bonding.

[0019] In conjunction with the second aspect, some possible implementations involve connecting the upper-layer chip and the lower-layer chip to obtain a heterogeneous integrated numerical control delay chip, including connecting the upper-layer chip and the lower-layer chip through a via.

[0020] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0021] The beneficial effects of the embodiments in this application compared with the prior art are:

[0022] This application disperses the space-consuming circuits by placing the delay circuit and reference circuit in the CNC delay chip on the upper layer chip and the switching circuit and drive circuit in the CNC delay chip on the lower layer chip. This reduces the planar area occupied by each circuit and the size of the CNC delay chip. In other words, the four circuits that are set on the same plane in a traditional CNC delay chip are divided into two groups according to their functions, and the two groups of circuits are placed in two planes that are parallel in the vertical direction of the heterogeneous integrated CNC delay chip. From a top view, the size of the heterogeneous integrated CNC delay chip is smaller than that of a traditional CNC delay chip. The use of GaAs chips in the lower layer chip and silicon-based MEMS chips in the upper layer chip improves the Q value of the CNC delay chip, reduces losses, and lowers power consumption.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a heterogeneous integrated numerical control delay chip provided in an embodiment of this application;

[0026] Figure 2 This is a schematic flowchart of a method for fabricating a heterogeneous integrated numerical control delay chip according to an embodiment of this application. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0029] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0031] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0033] Traditional numerically controlled delay chips are two-dimensional planar topologies designed using gallium arsenide (GaAs) technology. Internally, the chip consists of LC delay cells, switching networks, and other components. Due to the Q-factor limitations of LC delay cells in GaAs technology, delay chips exhibit high insertion loss and large area when the delay value is large and the number of bits is high. In the radio frequency (RF) front-end, this characteristic of GaAs restricts system performance. In the receiver link, it limits system noise; in the transmitter link, it increases power consumption.

[0034] Heterogeneous integration refers to the modular integration of complex chips across different process nodes using advanced interconnect and packaging technologies. This involves dividing complex chips according to function, selecting the optimal process for chiplet design based on performance requirements, and then flexibly reassembling these chiplets. The resulting integrated chips are then integrated into a whole using advanced interconnect and packaging technologies, fully leveraging the advantages of various materials, devices, and structures.

[0035] To address the aforementioned problems, one embodiment of this application provides a heterogeneous integrated numerical control delay chip, such as... Figure 1 As shown, it includes: upper-layer chip 10 and lower-layer chip 11.

[0036] The upper-layer chip 10 is a silicon-based MEMS chip, which includes delay circuits and reference circuits. The lower-layer chip 11 is a GaAs chip, which includes switching circuits and driving circuits. The upper-layer chip 10 and the lower-layer chip 11 are connected, with the upper-layer chip 10 located directly above the lower-layer chip 11.

[0037] This application disperses the space-consuming circuits by placing the delay circuit and reference circuit in the CNC delay chip on the upper layer chip and the switching circuit and drive circuit in the CNC delay chip on the lower layer chip. This reduces the planar area occupied by each circuit and the size of the CNC delay chip. In other words, the four circuits that are set on the same plane in a traditional CNC delay chip are divided into two groups according to their functions, and the two groups of circuits are placed in two planes that are parallel in the vertical direction of the heterogeneous integrated CNC delay chip. From a top view, the size of the heterogeneous integrated CNC delay chip is smaller than that of a traditional CNC delay chip. The use of GaAs chips in the lower layer chip and silicon-based MEMS chips in the upper layer chip improves the Q value of the CNC delay chip, reduces losses, and lowers power consumption.

[0038] Specifically, the delay circuit, reference circuit, and switching circuit all have a 50Ω RF impedance.

[0039] Specifically, because the switching circuit is a broadband device, when designing delayers with the same number of bits but different requirements, only the passive circuit parts of the delay state and reference state need to be designed using silicon-based MEMS technology, which greatly shortens the design cycle. It can adjust the delay time of each bit according to the user's needs, has strong flexibility, is more practical, and improves the production efficiency of heterogeneous integrated numerical control delay chip.

[0040] For example, the upper chip 10 is a single-layer silicon-based MEMS chip or a double-layer silicon-based MEMS chip. The double-layer silicon-based MEMS chip is provided with a double-layer silicon-based substrate, and the single-layer silicon-based MEMS chip is provided with a single-layer silicon-based substrate.

[0041] Specifically, silicon-based substrates have a better Q value than gallium arsenide substrates, which will improve the Q value of CNC delay chips, reduce losses, and lower power consumption.

[0042] For example, the silicon substrate thickness of a single-layer silicon-based MEMS chip is 390-410um, and the silicon substrate thickness of a double-layer silicon-based MEMS chip is 780-820um.

[0043] For example, the GaAs chip has a gallium arsenide substrate thickness of 70 μm.

[0044] Specifically, a delay chip was designed by heterogeneously integrating GaAs chips and silicon-based MEMS chips, which improved the defect of large insertion loss in traditional GaAs chip delays.

[0045] For example, the driving circuit is a positive voltage driving circuit or a TTL level conversion circuit.

[0046] Specifically, the positive voltage drive circuit is a +5V, 0V positive voltage drive circuit.

[0047] For example, the upper chip 10 and the lower chip 11 are connected by gold-to-gold bonding, thermo-bonding, or wire bonding.

[0048] Specifically, taking gold-gold bonding as an example, Figure 1 The upper-middle layer chip 10 and the lower-middle layer chip 11 are connected by bonding point 12.

[0049] For example, the upper-layer chip 10 and the lower-layer chip 11 are connected via through-holes.

[0050] Specifically, the upper chip 10 and the lower chip 11 are connected by a through-hole, similar to the silicon via connection method. That is, the interconnection between different chips is achieved by vertically connecting the upper chip 10 and the lower chip 11 through the through-hole.

[0051] Specifically, for circuits on the same chip, such as delay circuits and reference circuits, they can be interconnected internally. For circuits on different chips, such as circuits between upper chip 10 and lower chip 11, such as switching circuits and delay circuits, they can be connected through gold-to-gold bonding points, thermo-bonding points, wire bonding points, or vias.

[0052] The aforementioned heterogeneous integrated CNC delay chip disperses the space-consuming circuits by placing the delay circuit and reference circuit in the upper chip 10 and the switching circuit and drive circuit in the lower chip 11. This reduces the planar area occupied by each circuit and decreases the size of the CNC delay chip. In other words, the four circuits that are set on the same plane in a traditional CNC delay chip are divided into two groups according to their functions, and the two groups of circuits are placed in two planes that are parallel in the vertical direction of the heterogeneous integrated CNC delay chip. From a top view, the size of the heterogeneous integrated CNC delay chip is smaller than that of a traditional CNC delay chip. The use of GaAs chips in the lower chip 11 and silicon-based MEMS chips in the upper chip 10 improves the Q value of the CNC delay chip, reduces losses, and lowers power consumption.

[0053] Specifically, in practical production and daily life, GaAs and silicon-based MEMS chip processes can be mass-produced, and chip stacking technology is mature. Furthermore, both have similar dielectric constants and coefficients of thermal expansion, making them easy to design and integrate. This heterogeneous integrated CNC delay unit has the advantages of being easy to implement, mass-producible, and having excellent performance, facilitating large-scale production and promotion.

[0054] Figure 2 This is a schematic flowchart of a method for fabricating a heterogeneous integrated numerically controlled delay chip according to an embodiment of this application, with reference to... Figure 2 The fabrication method of this heterogeneous integrated numerically controlled delay chip is described in detail below:

[0055] Step 101: Fabricate an upper-layer chip with a delay circuit and a reference circuit.

[0056] For example, the upper-layer chip is a silicon-based MEMS chip, which includes a delay circuit and a reference circuit.

[0057] Step 102: Fabricate a lower-layer chip with switching circuits and driving circuits.

[0058] For example, the lower-level chip is a GaAs chip, and the lower-level chip is equipped with switching circuits and driving circuits.

[0059] Step 103: Connect the upper-layer chip and the lower-layer chip to obtain a heterogeneous integrated CNC delay chip. The upper surface of the upper-layer chip is the upper surface of the heterogeneous integrated CNC delay chip, and the lower surface of the lower-layer chip is the lower surface of the heterogeneous integrated CNC delay chip.

[0060] For example, connecting the upper-layer chip and the lower-layer chip to obtain a heterogeneous integrated numerical control delay chip includes: the upper-layer chip and the lower-layer chip are connected by gold-to-gold bonding, thermo-bonding, or wire bonding.

[0061] For example, connecting the upper-layer chip and the lower-layer chip to obtain a heterogeneous integrated numerical control delay chip further includes connecting the upper-layer chip and the lower-layer chip through a through-hole.

[0062] The above-mentioned heterogeneous integrated numerical control delay chip fabrication method disperses the space-consuming circuits by placing the delay circuit and reference circuit in the numerical control delay chip on the upper layer chip and the switching circuit and driving circuit in the numerical control delay chip on the lower layer chip, thereby reducing the planar area occupied by each circuit and reducing the size of the numerical control delay chip. The use of GaAs chip in the lower layer chip and silicon-based MEMS chip in the upper layer chip improves the Q value of the numerical control delay chip, reduces losses, and lowers power consumption.

[0063] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0064] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A heterogeneous integrated digitally controlled delay line chip, characterized by, The application relates to a heterogeneous integrated digital delay timer chip. The upper chip is a silicon-based MEMS chip, and the upper chip is provided with a delay circuit and a reference circuit. The lower chip is a GaAs chip, and the lower chip is provided with a switch circuit and a driving circuit. The upper chip is connected with the lower chip, and the upper chip is located directly above the lower chip. The upper chip is a single-layer silicon-based MEMS chip or a double-layer silicon-based MEMS chip, the double-layer silicon-based MEMS chip is provided with a double-layer silicon-based substrate, and the single-layer silicon-based MEMS chip is provided with a single-layer silicon-based substrate; the thickness of the silicon-based substrate of the single-layer silicon-based MEMS chip is 390-410 um, the thickness of the silicon-based substrate of the double-layer silicon-based MEMS chip is 780-820 um, and the thickness of the gallium arsenide substrate of the GaAs chip is 70 um. The switch circuit is configured as a wideband device, and when the delay timer of different bits is designed, the switch circuit and the driving circuit of the lower chip are set to remain unchanged when the upper chip is redesigned. The driving circuit is a positive pressure driving circuit or a TTL level conversion circuit.

2. The heterogeneous integrated digitally controlled delay line chip of claim 1, wherein, The upper chip and the lower chip are connected through gold-gold bonding, hot-press bonding or wire bonding.

3. The heterogeneous integrated digitally controlled delay line chip of claim 1, wherein, The upper chip and the lower chip are connected through a via.

4. The heterogeneous integrated digitally controlled delay line chip of claim 1, wherein, The application relates to a heterogeneous integrated digital delay timer chip.

5. A method of fabricating a heterogeneous integrated digitally controlled delay line chip, characterized by, The application relates to a heterogeneous integrated digital delay timer chip. The upper chip is connected with the lower chip, and the upper chip is located directly above the lower chip. The upper chip is a single-layer silicon-based MEMS chip or a double-layer silicon-based MEMS chip, the double-layer silicon-based MEMS chip is provided with a double-layer silicon-based substrate, and the single-layer silicon-based MEMS chip is provided with a single-layer silicon-based substrate; the thickness of the silicon-based substrate of the single-layer silicon-based MEMS chip is 390-410 um, the thickness of the silicon-based substrate of the double-layer silicon-based MEMS chip is 780-820 um, and the thickness of the gallium arsenide substrate of the GaAs chip is 70 um. The switch circuit is configured as a wideband device, and when the delay timer of different bits is designed, the switch circuit and the driving circuit of the lower chip are set to remain unchanged when the upper chip is redesigned. The upper chip and the lower chip are connected through gold-gold bonding, hot-press bonding or wire bonding. The upper chip and the lower chip are connected through a via.

6. The method of claim 5, wherein the step of forming the plurality of digitally controlled delay lines comprises the steps of: forming a plurality of digitally controlled delay lines on the first substrate; and forming a plurality of digitally controlled delay lines on the second substrate. ​ ​ 7. The method of claim 5, wherein the step of forming the plurality of delay elements comprises the steps of: forming a plurality of delay elements on the first substrate; and forming a plurality of delay elements on the second substrate. ​ ​

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