An accelerator case analysis and monitoring device

Abstract

The present invention relates to an accelerator case analysis and monitoring device, comprising: a core board and a base board; the core board and the base board are connected via an RMC connector; the core board includes a processor and an FPGA; the base board is provided with a first number of optical fiber input interfaces and optical fiber output interfaces; the base board is also provided with a second number of BNC CMOS interfaces; the optical fiber input interface, the optical fiber output interface and the BNC CMOS interface are connected to the FPGA via the RMC connector; the processor is used to receive operation control parameters of an accelerator and send them to the FPGA; the FPGA is used to receive case information of the accelerator operation via the optical fiber input interface, generate a corresponding PWM wave signal as a trigger signal according to the case information and the operation control parameters, and output the signal via the optical fiber output interface or the BNC CMOS interface; the processor is also used to monitor the data processed by the FPGA and upload the data to a host computer.

Description

Technical Field

[0001] The present invention relates to the technical field of accelerators, and in particular to an accelerator case analysis and monitoring device. Background Art

[0002] Intermediate- and high-energy heavy ion accelerator collision experiments are a primary tool for nuclear physics research. During experiments, the intermediate- and high-energy heavy ion beams generated by the accelerator, upon bombarding fixed targets or colliding, produce a large number of secondary particles. By developing specialized large-scale experimental instruments to measure these secondary particles or their decay products, we can reconstruct nuclear reaction processes and conduct research on the properties and phase transitions of nuclear matter, as well as on the structure and interactions of atomic nuclei.

[0003] The inventors of this application discovered in their research that the above-mentioned accelerator collision experiments rely on high-precision simultaneous measurement of physical parameter information such as momentum, energy, mass and flight time of various secondary particles, which requires the integration of detectors with different functions into a dedicated large-scale experimental instrument. This type of experimental instrument often has up to 10,000 or even higher detector measurement channels and data read and write channels. At the same time, the detector is required to have a very fast response speed, reaching the level of microseconds or even nanoseconds, and needs to be able to operate with high reliability for a long time. Therefore, it is necessary to develop an electronic device that can flexibly adapt to changes in the operating conditions of accelerators in different physical experiments, and to monitor and record accelerator beam information in real time, to achieve correct analysis of slow extraction events of accelerator beams, and to provide trigger signals for different measurement channels of detectors with specific and precise delays according to the requirements of particle physics experiments. Summary of the Invention

[0004] In response to the above problems, the purpose of the present invention is to provide an accelerator event analysis and monitoring device that can be applied to large-scale experimental instruments for accelerator collision experiments. It can flexibly adapt to changes in the operating conditions of accelerators in different physical experiments, and monitor and record accelerator beam information in real time, thereby achieving correct analysis of accelerator beam slow extraction events, and realizing specific and precise time-delay trigger signals for different measurement channels of the detector according to the requirements of particle physics experiments, thereby meeting the measurement needs of particle physics experiments.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] The present application provides an accelerator case analysis and monitoring device, comprising: a core board and a base board; the core board and the base board are connected via an RMC connector;

[0007] The core board includes a processor and an FPGA connected to each other;

[0008] The base plate is provided with a first number of optical fiber input interfaces and optical fiber output interfaces; the base plate is also provided with a second number of BNC CMOS interfaces; the optical fiber input interfaces, the optical fiber output interfaces and the BNC CMOS interfaces are respectively connected to the FPGA through the RMC connector;

[0009] The processor is configured to receive the operation control parameters sent by the accelerator control system and send them to the FPGA;

[0010] The FPGA is configured to receive event information of the accelerator operation through the optical fiber input interface, generate a corresponding PWM wave signal as a trigger signal based on the event information and the operation control parameters, and output the signal through the optical fiber output interface or the BNC CMOS interface;

[0011] The processor is further configured to monitor the data of the optical fiber input interface, the optical fiber output interface, and the BNC CMOS interface processed by the FPGA, and upload the data to a host computer.

[0012] In one implementation of the present application, the core board is a single-board controller integrated with a SoC chip;

[0013] The processor includes a CPU capable of running a real-time operating system, and an EPICSIOC control program is embedded in the real-time operating system.

[0014] In one implementation of the present application, a DMA chip is also integrated on the core board, and the processor interacts with the FPGA through the DMA chip.

[0015] In one implementation of the present application, the device further includes an optical fiber communication module;

[0016] The processor transmits the data processed by the FPGA to the accelerator control system through the optical fiber communication module using the CA protocol.

[0017] In one implementation of the present application, the device further includes an aluminum alloy housing for electromagnetic shielding;

[0018] The core plate and the bottom plate are accommodated in the aluminum alloy shell.

[0019] In one implementation of the present application, the first number of optical fiber input interfaces and optical fiber output interfaces, and a portion of the BNC CMOS interfaces are led out from one end face of the aluminum alloy housing; the remaining portion of the BNC CMOS interfaces are led out from the other end face of the aluminum alloy housing.

[0020] In one implementation of the present application, the first number is 4 and the second number is 7.

[0021] In one implementation of the present application, an LED is further provided on one end face for indicating the process of the FPGA generating the PWM wave signal.

[0022] In one implementation of the present application, the baseboard is further provided with a socket connected to the core board to achieve functional expansion.

[0023] In one implementation of the present application, the model of the optical fiber input interface is AFBR-2624; the model of the optical fiber output interface is AFBR-1624; the BNC CMOS interface realizes 3.3V CMOS output and is compatible with 5V TTL input; and the power strip realizes 3.3V CMOS input and output.

[0024] Due to the adoption of the above technical solution, the present invention has the following advantages: the accelerator event analysis and monitoring device provided in the application solution of the present invention includes: a core board and a base board, wherein the core board includes a processor and an FPGA, and the base board is provided with an optical fiber input interface, an optical fiber output interface and a BNC CMOS interface; the accelerator operation control parameters can be received by the processor, and the event information of the accelerator operation can be received through the optical fiber input interface. According to the event information and the operation control parameters, the FPGA performs analysis and generates a corresponding PWM wave signal as a trigger signal, which is output through the optical fiber output interface or the BNC CMOS interface, thereby achieving the correct analysis of the accelerator slow extraction event in each physical experiment according to the accelerator operation cycle and the type of accelerated ions, and generating an accurate time delay to notify the trigger system of the physical experiment according to the physical requirements, and then generating a series of trigger signals to trigger various detectors in the physical experiment to enter the data acquisition mode, thereby meeting the measurement requirements of current particle physics implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a structural diagram of a core board and a base board of an accelerator event analysis and monitoring device provided in an embodiment of the present application;

[0026] Figure 2 Schematic diagram of the interface layout of the accelerator event analysis and monitoring device on one end face of the aluminum alloy housing in an embodiment of the present application;

[0027] Figure 3 Schematic diagram of the interface layout of the accelerator event analysis and monitoring device on the other end face of the aluminum alloy housing in an embodiment of the present application;

[0028] Figure 4This is a data flow diagram of an accelerator case analysis and monitoring device according to an embodiment of the present application;

[0029] Figure 5 This is a data flow diagram of the FPGA in the embodiment of the present application;

[0030] Figure 6 This is a schematic diagram of the host computer web monitoring interface in one embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0032] In existing technologies, the type of heavy ion beam used in each physics experiment varies, and accordingly, accelerator operating control parameters, such as operating cycle parameters, will change. Traditional event analysis systems can complete event analysis, but the generated trigger signals have a certain delay, and their operation is not flexible enough to meet the changing needs of physics experiments. The present application accordingly provides an accelerator event analysis and monitoring device, comprising: a core board and a base board; the core board and the base board are connected via an RMC connector; the core board includes a connected processor and FPGA; the base board is provided with a first number of optical fiber input interfaces and optical fiber output interfaces; the base board is also provided with a second number of BNC CMOS interfaces; the optical fiber input interface, the optical fiber output interface and the BNC CMOS interface are respectively connected to the FPGA via the RMC connector; the processor is used to receive operation control parameters sent by the accelerator control system and send them to the FPGA; the FPGA is used to receive event information of the accelerator operation through the optical fiber input interface, generate a corresponding PWM wave signal as a trigger signal according to the event information and the operation control parameters, and output it through the optical fiber output interface or the BNC CMOS interface; the processor is also used to monitor the data of the optical fiber input interface, the optical fiber output interface and the BNC CMOS interface processed by the FPGA, and upload them to the host computer. This solution flexibly adapts to changes in the operating conditions of accelerators in different physical experiments, and monitors and records accelerator beam information in real time, achieving correct analysis of slow accelerator beam extraction events, and triggering signals for different measurement channels of detectors with specific and precise time delays according to the requirements of particle physics experiments, thus meeting the measurement needs of particle physics experiments.

[0033] The accelerator event analysis and monitoring device in the solution of the present application will be described below in conjunction with more drawings in some more detailed embodiments of the present application.

[0034] like Figures 1 to 4 The accelerator parsing and monitoring device in the embodiment of the present application (referred to as the device in the embodiment of the present application) includes: a core board and a baseboard; the core board and the baseboard are connected via an RMC (Reconfigurable Input / Output Mezzanine Card) connector. The core board includes a processor and an FPGA (Field Programmable Gate Array) connected thereto; a first number of fiber optic input interfaces and fiber optic output interfaces are provided on the baseboard; a second number of BNC (Bayonet Neill-concelman) CMOS interfaces are also provided on the baseboard; the fiber optic input interface, the fiber optic output interface, and the BNC CMOS interface are respectively connected to the FPGA via RMC connectors.

[0035] More specifically, in one embodiment, the core board of the device is a single-board controller integrated with a SoC chip, such as a Zynq series SoC chip. The SoC chip includes a CPU capable of running a real-time operating system, such as an ARM processor running the Linux Real-Time operating system. The Linux Real-Time operating system is embedded with an EPICS IOC control program, enabling the ARM processor to interact with other external computer systems, such as a host computer.

[0036] The ARM processor running the Linux Real-Time operating system communicates with the FPGA via DMA (Direct Memory Access).

[0037] The device in the embodiment of the present application also includes a fiber optic communication module. The ARM processor uses the CA (Channel Access Protocol) protocol to transmit the data processed by the FPGA to the accelerator control system through the fiber optic communication module. (The accelerator control system can be a collection of one or more computers that can control the operation of the accelerator and the particle physics experiment process.) Based on optical communication, this application can achieve rapid data exchange between the processor and other computers.

[0038] In an embodiment of the present application, the device includes a housing made of aluminum alloy for effectively isolating electromagnetic interference in the environment. The core board and the base board are accommodated in the aluminum alloy housing.

[0039] Furthermore, four optical fiber input interfaces, four optical fiber output interfaces, and seven BNC CMOS interfaces are welded on the bottom plate and are led out to the outside of the aluminum alloy housing through optical fiber connectors and BNC connectors respectively.

[0040] The FPGA, through the RMC, connects high-speed DIO to the backplane, enabling communication with subsequent devices via the aforementioned optical or electrical interfaces. The aforementioned fiber optic input interface allows for optical signal input to upstream devices, while the fiber optic output interface allows for optical signal fanout. The backplane interface has seven BNC CMOS signal input and output ports for electrical input and output, capable of outputting PWM signals to meet requirements or serving as a trigger source interface. The fiber optic and electrical interfaces can be combined for use through software system configuration.

[0041] In an embodiment of the present application, the device further reserves sockets A and B on the bottom board to be connected to the core board to achieve subsequent functional expansion.

[0042] like Figure 2 As shown in FIG, 4 optical fiber input interfaces and 4 optical fiber output interfaces are led out from one end face of the aluminum alloy housing. A BNC interface is also led out from the above end face. Figure 3 As shown, the power strip and the remaining six BNC ports extend from the other end of the aluminum alloy housing. In one specific embodiment, the fiber input port is AFBR-2624; the fiber output port is AFBR-1624; the BNC CMOS port provides 3.3V CMOS output and is compatible with 5V TTL input; and the power strip provides 3.3V CMOS input and output.

[0043] The functions of the various parts of the accelerator case analysis and monitoring device in the embodiment of the present application are as follows:

[0044] The processor is used to receive the operation control parameters sent by the accelerator control system and send them to the FPGA;

[0045] FPGA, used to receive the event information of the accelerator operation through the optical fiber input interface, generate the corresponding PWM wave signal as the trigger signal according to the event information and the operation control parameters, and output it through the optical fiber output interface or BNC CMOS interface;

[0046] The processor is further used to monitor the data of the optical fiber input interface, optical fiber output interface and BNC CMOS interface processed by the FPGA, and upload the data to the host computer.

[0047] Please also refer to Figure 4 、 Figure 5 and Figure 6 , the working principle of the device in the embodiment of the present application is explained in a scenario.

[0048] The device in the embodiment of the present application is mainly used in the scenario of particle physics experiments. The device of the present invention is placed at the physical experiment site. After the on-site power supply system passes through the isolation transformer, the device is connected to a 24V DC power supply to power it.

[0049] Then, the events output by the accelerator event distribution system are connected to the optical fiber input interface of the device core board via optical fiber, and then connected to the receiving port of the physical experiment main trigger system through the BNC CMOS signal input and output port.

[0050] When the device of the embodiment of the present application is working, the accelerator control system sends the accelerator operation cycle parameters to the ARM processor of the core board running the Linux real-time embedded operating system through the CA protocol, and sends them to the FPGA part of the core board after data processing. The core board receives the accelerator event sequence and accelerator operation parameters through the optical fiber interface to complete the event analysis, and obtains a modulated signal that is synchronized with the slow extraction event and has physical significance. The modulated signal is output to the physical experiment trigger system through the BNC CMOS interface.

[0051] The ARM processor of the core board also realizes real-time monitoring of the accelerator operation cycle at the physical terminal. When the device receives the specified codeword and is in the process of generating the specified waveform, LED2 is on, and it is dark at other times. The overall system diagram of the device when working is as follows Figure 4 shown.

[0052] and Figure 5 The data flow of the FPGA is shown. The four optical inputs and seven TTL inputs form 11 external inputs. "Case Analysis" and "PWM Generation" are internally generated signals that, along with the external inputs, form 13 optional signals for the four optical outputs and seven TTL outputs.

[0053] The technical solution of the present invention can also refresh the status and update the configuration on the web page. The web setting update interface is as follows: Figure 6The left column contains refresh and update buttons. Click "Refresh Status" to display the current device settings. Click "Update Configuration" to apply the current settings and save them to disk. This means the most recent settings remain effective even after a power cycle. The right column is divided into three levels. The first level contains event code settings. The values ​​for "Period," "Delay," and "Pulse Width" are assigned by the EPICS server and cannot be modified on the web. "Input Signal" specifies the input port for parsing serial data. The second level contains output signal routing, allowing for free routing of input signals or internally generated signals. The third level contains PWM period and pulse width settings. These values ​​are assigned by the EPICS server and cannot be modified on the web. The specific meanings of the parameters on this page are as follows: "None" disables output, or disables light; "Low" indicates low output; "High" indicates high output; "Gen" indicates the output of a specified generated waveform; "PWM" indicates the output of a PWM signal; B1-B7 indicate BNC input signals; and Fi1-Fi4 indicate optical port input signals.

[0054] The technical solution of the present application achieves optoelectronic and electro-optical conversion, including four fiber input ports, four fiber output ports, and seven BNC CMOS signal input and output ports. The device can analyze specified events, and the provided firmware enables free web-based routing configuration between each port, PWM generation, and other functions. The fiber communication interface is compatible with plastic and quartz fiber networks, as well as single-mode and multimode fibers, enabling high-speed, long-distance data transmission. Fiber also has excellent insulation properties, ensuring that leakage and other issues between the event analysis device and the outside world are avoided. Furthermore, signal loss in optical fiber is less than that in coaxial cable. Optical fiber transmits only light, not electricity, and is unaffected by electromagnetic fields. Therefore, optical fiber transmission is highly resistant to electromagnetic interference and industrial interference in high-magnetic-field environments such as accelerators and superconducting spectrometers.

[0055] In summary, the accelerator event analysis and monitoring device provided in the embodiments of the present application can accurately analyze accelerator slow extraction events by acquiring accelerator operating parameters during each physics experiment based on the accelerator operating cycle and the type of accelerated ions. It also generates precise time delays based on physical requirements to notify the trigger system of the physics experiment, thereby generating a series of trigger signals to trigger various detectors in the physics experiment into data acquisition mode. The event analysis device's setting parameters are in microseconds, and its control accuracy can reach nanoseconds, which is very important for ensuring the trigger quality of physics experiments. It can fully meet the requirements of analyzing most physics experiment events, generating pulse modulation signals, and monitoring operating parameters. The present invention provides multiple optical and electrical input and output interfaces. The fiber optic interface is compatible with various different types of optical fibers. The electrical port output level and expansion strip are electrically compatible. The device's software protocols are optional, including EPICS and web. The provided firmware enables free routing configuration between each port via the web, PWM generation, and other functions, which can better meet engineering applications and can be easily integrated into large-scale physics control systems to adapt to a variety of measurement environments. The specific functions of the device can be configured according to specific needs to achieve high efficiency and high accuracy.

[0056] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0057] The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An accelerator case analysis and monitoring device, characterized in that: include: Core board and base board; the core board and the base board are connected via an RMC connector; The core board includes a processor and an FPGA connected to each other; The base plate is provided with a first number of optical fiber input interfaces and optical fiber output interfaces; the base plate is also provided with a second number of BNC CMOS interfaces; the optical fiber input interfaces, the optical fiber output interfaces and the BNC CMOS interfaces are respectively connected to the FPGA through the RMC connector; The processor is configured to receive the operation control parameters sent by the accelerator control system and send them to the FPGA; The FPGA is configured to receive event information of the accelerator operation through the optical fiber input interface, generate a corresponding PWM wave signal as a trigger signal based on the event information and the operation control parameters, and output the signal through the optical fiber output interface or the BNC CMOS interface; The processor is further configured to monitor the data of the optical fiber input interface, the optical fiber output interface, and the BNC CMOS interface processed by the FPGA, and upload the data to a host computer; The first number is 4, and the second number is 7; the BNC CMOS interface realizes 3.3V CMOS output and is compatible with 5VTTL input; The data flow of the FPGA consists of 11 external inputs with 4 optical inputs and 7 TTL inputs; the internally generated signals of the FPGA, together with the external inputs, form 13 alternative signals for selection by 4 optical outputs and 7 TTL outputs.

2. The accelerator event analysis and monitoring device according to claim 1, characterized in that: The core board is a single-board controller integrated with a SoC chip; The processor includes a CPU capable of running a real-time operating system, and an EPICS IOC control program is embedded in the real-time operating system.

3. The accelerator event analysis and monitoring device according to claim 2, characterized in that: The core board is also integrated with a DMA chip, and the processor interacts with the FPGA via the DMA chip.

4. The accelerator event analysis and monitoring device according to claim 1, characterized in that: The device also includes a fiber optic communication module; The processor transmits the data processed by the FPGA to the accelerator control system through the optical fiber communication module using the CA protocol.

5. The accelerator event analysis and monitoring device according to claim 1, characterized in that: The device also includes an aluminum alloy housing for electromagnetic shielding; The core plate and the bottom plate are accommodated in the aluminum alloy shell.

6. The accelerator event analysis and monitoring device according to claim 5, characterized in that: The first number of optical fiber input interfaces and optical fiber output interfaces, and a portion of the BNC CMOS interfaces are led out from one end face of the aluminum alloy housing; the remaining portion of the BNC CMOS interfaces are led out from the other end face of the aluminum alloy housing.

7. The accelerator event analysis and monitoring device according to claim 6, characterized in that: An LED is also provided on one end face for indicating the process of the FPGA generating the PWM wave signal.

8. The accelerator event analysis and monitoring device according to claim 1, characterized in that: The bottom plate is also provided with a socket connected to the core board to achieve function expansion.

9. The accelerator event analysis and monitoring device according to claim 8, characterized in that: The model of the optical fiber input interface is AFBR-2624; the model of the optical fiber output interface is AFBR-1624; the power strip realizes 3.3V CMOS input and output.

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