LDO without off-chip capacitor

Abstract

The application discloses a kind of LDO without slice outside capacitance, belongs to linear power supply technical field, including transconductance constant circuit Gmc, constant transconductance error amplifier AE1, first output circuit, error amplifier AE2, second output circuit, band gap reference circuit BGR, power tube Pn1 and power tube Pn2;The transconductance constant circuit Gmc is used to generate bias voltage signal;The constant transconductance error amplifier AE1 is used to generate first output signal;The error amplifier AE2 is used to generate second output signal;Band gap reference circuit BGR generates multiple independent stable outputs, provides stable reference voltage for constant transconductance error amplifier AE1 and error amplifier AE2, and then generates bias voltage through transconductance constant circuit Gmc, and constant transconductance error amplifier AE1 drives power tube Pn1 through first output circuit to output signal for analog load, and error amplifier AE2 drives power tube PN2 through second output circuit to output signal for digital load.

Description

TECHNICAL FIELD

[0001] The present application relates to a LDO without external capacitor, belonging to the technical field of linear power supply. BACKGROUND

[0002] Linear regulators and switching regulators both have their own place in today's market; systems such as desktop and notebook microprocessors require not only large current synchronized with the clock, but also low supply voltage, and these systems can fully utilize the high conversion efficiency of DC-DC converters; analog circuit modules with only analog functions cannot withstand the noise of switching regulators, but can fully utilize the advantages of low noise and low cost of linear regulators. Analog circuits are inherently more sensitive to power line noise than digital modules, which is why they need a "clean" power supply. The LDO linear regulator power supply is a loop composed of a reference voltage regulator, an error amplifier and a regulating tube, and a protection circuit; first, the output voltage is sampled through a resistor network, and then the output voltage of the regulator is adjusted through negative feedback. Based on the stable output capability, a system that obtains a stable DC output voltage. It has the advantages of fast load response, small output ripple and low noise. Under normal working conditions, the circuit load, input voltage and temperature have no effect on the output voltage of the LDO, which is related to the sampling proportional resistor. Therefore, the LDO power supply can provide a stable output voltage.

[0003] Analog circuits usually require a power supply with large current and high driving capability, while driving digital circuits requires a power supply with fast transient response and not too much current, while achieving high PSRR, large current, and dual-output LDO for analog circuits and digital implementation, which is a blank in the domestic power supply field.

[0004] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be taken as an acknowledgment or any form of suggestion that this information forms prior art that is publicly known. SUMMARY

[0005] The present application aims to overcome the deficiencies in the prior art, and provides a LDO without external capacitor, which solves the problem of poor load capacity of current LDO and the inability to realize dual-output for analog circuits and digital implementation.

[0006] To achieve the above-mentioned purpose / to solve the above-mentioned technical problems, the present application adopts the following technical solutions:

[0007] A LDO without external capacitor, comprising a transconductance constant circuit Gmc, a constant transconductance error amplifier AE1, a first output circuit, an error amplifier AE2, a second output circuit, a bandgap reference circuit BGR, a power tube Pn1 and a power tube Pn2.

[0008] The constant transconductance circuit Gmc is used to generate a bias voltage signal; the constant transconductance circuit Gmc is connected to the constant transconductance error amplifier AE1 and the error amplifier AE2 respectively.

[0009] The bandgap reference circuit BGR, the constant transconductance error amplifier AE1, the first output circuit and the power transistor Pn1 are connected in sequence.

[0010] The bandgap reference circuit BGR, error amplifier AE2, second output circuit and power transistor Pn2 are connected in sequence;

[0011] The bandgap reference circuit BGR is used to generate multiple independent outputs to provide reference voltages for the constant transconductance error amplifiers AE1 and AE2; the constant transconductance error amplifier AE1 is used to generate a first output signal, which is transmitted through the first output circuit to drive the power transistor Pn1.

[0012] The error amplifier AE2 is used to generate a second output signal, which is transmitted through the second output circuit to drive the power transistor Pn2.

[0013] Optionally, the bandgap reference circuit BGR includes a power switching switch circuit, PMOS transistors P26-P31, NMOS transistors N29-N30, resistors R3-R4, transistors PNP1 and PNP2; the sources of PMOS transistors P26-P31 are all connected to the output terminal of the switch; the gates of PMOS transistors P26-P31 are connected; the drain of PMOS transistor P26 is connected to the gate of PMOS transistor P31 and the emitter of PNP1; the drains of PMOS transistors P27, PMOS transistor P31, and PMOS transistor P32 are connected; the drain of PMOS transistor P31 is connected to the drain of NMOS transistor N29 and to the gates of PMOS transistors P26-P31; the source of NMOS transistor N29 is grounded, and the source of NMOS transistor N29 is grounded. The gate of the PMOS transistor P28 is connected to the gate of the PMOS transistor P30; the gate-drain of the PMOS transistor P30 is shorted and connected to the drain of the PMOS transistor P32; the source of the PMOS transistor P30 is grounded; the drain of the PMOS transistor P28 is connected to the gate of the PMOS transistor P32, one end of resistor R3, and one end of resistor R4; the other end of resistor R4 is grounded; the other end of resistor R3 is connected to the emitter of the transistor PNP2; the drain of the PMOS transistor P29 is connected to one end of resistor R5, and a reference voltage Vn+ is generated across resistor R5; the drain of the PMOS transistor P30 is connected to one end of resistor R6, and a reference voltage Vn1+ is generated across resistor R6; the drain of the PMOS transistor P31 is connected to one end of resistor R7, and a reference voltage Vrefx is generated across resistor R7.

[0014] Optionally, the transconductance constant circuit Gmc includes PMOS transistors P15-P19 and NMOS transistors N16-N19; PMOS transistors P15 and P16 are connected to the input signal Vin, the gate and drain of PMOS transistor P15 are shorted and connected to the gate of PMOS transistor P16 and the drain of NMOS transistor N16; the source of PMOS transistor P17 is connected to the input signal Vin, the gate of PMOS transistor P17 is connected to the control signal Pb2, and the drain of PMOS transistor P17 is connected to the source of PMOS transistors P18 and P19 respectively. The gate and drain of PMOS transistor P18 are shorted and connected to the gate of NMOS transistor N16 and the drain of NMOS transistor N18; the gate and drain of NMOS transistor N17 are shorted and connected to the gate of PMOS transistor P19 and the drain of PMOS transistor P16; the gate and drain of NMOS transistor N19 are shorted and connected to the drain of PMOS transistor P19 and the gate of NMOS transistor N18; the sources of NMOS transistors N16 to N19 are all grounded; the gate of PMOS transistor P16 is the bias signal Pb1, and the gate of NMOS transistor N18 is the bias signal Nb1.

[0015] Optionally, the constant transconductance error amplifier AE1 includes PMOS transistors P1~P14, NMOS transistors N1~N15, resistors R1 and R2; the sources of PMOS transistors P12 and P13 are connected to the drain of PMOS transistor P1, the drain of PMOS transistor P12 is connected to the drain of NMOS transistor N2, and the drain of PMOS transistor P13 is connected to the drain of NMOS transistor N3; the gate of NMOS transistor N12 is connected to Vn-, the gate of NMOS transistor N13 is connected to VN+, the sources of NMOS transistors N12 and NMOS transistor N13 are connected to the drain of NMOS transistor N1, and the drain of NMOS transistor N12 is connected to the drain of PMOS transistor P3. The drain of OS transistor N13 is connected to the drain of PMOS transistor P2; the sources of PMOS transistors P1, P2, P3, and P14 are all connected to the input signal Vin, and their gates are all connected to the same bias signal Pb1; the sources of NMOS transistors N1, N2, and N3 are all grounded, and their gates are all connected to the same bias signal Nb1; the gate and drain of NMOS transistor N8 are shorted and connected to the gate of NMOS transistor N9 and the drain of PMOS transistor P2; the gate and drain of PMOS transistor P8 are shorted and connected to the gate of PMOS transistor P9 and the drain of N2; the source of NMOS transistor N8 is connected to the source of PMOS transistor P8; the source of NMOS transistor N9 is connected to the source of PMOS transistor P9. The drain of NMOS transistor N9 is connected to the drain of PMOS transistor P4, and the drain of PMOS transistor P9 is connected to the drain of NMOS transistor N5. The gate and drain of NMOS transistor N10 are shorted and connected to the gate of NMOS transistor N11 and the drain of PMOS transistor P3. The gate and drain of PMOS transistor P10 are shorted and connected to the gate of PMOS transistor P11 and the drain of NMOS transistor N3. NMOS transistor N10 is connected to the source of PMOS transistor P10. The source of NMOS transistor N11 is connected to the source of PMOS transistor P11, and the drain of NMOS transistor N11 is connected to the drain of PMOS transistor P5. The drain of PMOS transistor P11 is connected to the drain of N4. One end of resistor R1 is connected to the drain of PMOS transistor P6, and the other end of resistor R1 is connected to the drain of NMOS transistor N6. The sources of PMOS transistors P4 and P5 are connected to the input signal Vin. The drain of PMOS transistor P4 is connected to the source of PMOS transistor P6, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P7. The gates of PMOS transistors P4 and P5 are connected together and connected to the drain of PMOS transistor P6. The gates of PMOS transistors P6 and P7 are connected together and connected to the drain of NMOS transistor N6. The source of NMOS transistor N6 is connected to the drain of NMOS transistor N4, and the source of NMOS transistor N7 is connected to the drain of N5.The gates of NMOS transistors N6 and N7 are connected to the gate of NMOS transistor N14, and the gates of NMOS transistors N4 and N5 are connected to the gate of NMOS transistor N15. One end of resistor R2 is connected to the drain of NMOS transistor N14, and the other end of resistor R2 is connected to the drain of PMOS transistor P14. The source of NMOS transistor N15 is grounded, and the drain of NMOS transistor N15 is connected to the source of NMOS transistor N14. The gate of NMOS transistor N14 is connected to the drain of PMOS transistor P14. The output terminal of the constant transconductance error amplifier AE1 is the drain of NMOS transistor N7, and the output signal is EA_O.

[0016] Optionally, the first output circuit includes a SUM circuit, an auxiliary operational amplifier AUX, and an analog load buffer Buffer1; the SUM circuit is connected to the constant transconductance error amplifier AE1 and the auxiliary operational amplifier AUX, respectively, and the analog load buffer Buffer1 is connected to the analog load buffer Buffer1 and the power transistor Pn1, respectively; the SUM circuit is used to sum the signal of the auxiliary operational amplifier AUX and the signal generated by the constant transconductance error amplifier AE1 and output it to the analog load buffer Buffer1.

[0017] Optionally, the auxiliary operational amplifier AUX includes a Pn1_sense for sensing the current of the power transistor Pn1, an operational amplifier OTA, resistors RX1 and RX2, NMOS transistors N31 and N32; one end of resistor Rx1 is connected to Vin, the other end of resistor Rx1 is connected to one end of resistor Rx2, and then connected to the inverting input of the operational amplifier OTA; the drain of Pn1_sense is connected to Vin, the gate of Pn1_sense is connected to the gate of the power transistor Pn1, and the drain of Pn1_sense is connected to resistor Rx2. The other end is connected to the drain of NMOS transistor N31; the output terminal Vx of the operational amplifier OTA is connected to the gate of NMOS transistor N31 and to the negative input terminal of the SUM circuit; the non-inverting input terminal of the operational amplifier OTA is connected to the signal Vrefx; the source of NMOS transistor N31 is grounded, and the drain of NMOS transistor N32 is connected to the drain of NMOS transistor N31; the source of NMOS transistor N32 is grounded, and the gate is connected to the bias signal Nb1; the positive input terminal of the SUM circuit is connected to the output signal EA_0 of the constant transconductance error amplifier AE1.

[0018] Optionally, the analog load buffer Buffer1 includes an NMOS transistor N20, a transistor NPN1, and a capacitor CM; the drain of the NMOS transistor N20 is connected to the collector of the transistor NPN1 and the drain of the power transistor Pn1, and is connected to the input signal Vin; the source of the NMOS transistor N20 is connected to the gate of the NPN1; the emitter of the NPN1 is connected to the gate of the Pn1; the gate of the NMOS transistor N20 is connected to the output signal SUM_OUT of the SUM circuit; the source of the power transistor Pn1 serves as the output VoutA; and the capacitor CM is connected across the gate of the NMOS transistor N20 and the output terminal of the power transistor Pn1.

[0019] Optionally, the operational amplifier OTA includes PMOS transistors P33-P35, NMOS transistor N33, and NMOS transistor N34; the source of PMOS transistor P33 is connected to the input signal Vin, the gate of PMOS transistor P33 is connected to the bias signal Pb1, and the drain of PMOS transistor P33 is connected to the source of PMOS transistor P34 and the source of PMOS transistor P35; the gate of PMOS transistor P34 is the inverting input terminal, the drain of PMOS transistor P34 is connected to the drain of NMOS transistor N33, and serves as the output terminal Vx; the gate of PMOS transistor P35 is the non-inverting input terminal; the drain of PMOS transistor P35 is connected to NMOS transistor N34 with its gate and drain shorted; and the sources of NMOS transistors N33 and NMOS transistor N34 are grounded.

[0020] Optionally, the error amplifier AE2 includes PMOS transistors P20~P23 and NMOS transistors N21~N26; the sources of PMOS transistors P20, P21, P22, and P23 are connected to the input signal Vin; the gate and drain of PMOS transistor P20 are shorted and then connected to the gate of PMOS transistor P21 and the drain of NMOS transistor N24; the drain of PMOS transistor P21 is connected to the drain of NMOS transistor N22 and serves as the output terminal, with the output signal being EA_1; the gate and drain of PMOS transistor P23 are shorted and then connected to the gate of PMOS transistor P22 and the gate of NMOS transistor N21; the drain of PMOS transistor P22 is connected to the drain of NMOS transistor N23... The drains are connected; the gate of NMOS transistor N21 is connected to the gate of NMOS transistor N22, serving as the inverting input of error amplifier AE2; the source of NMOS transistor N21 is connected to the drain of NMOS transistor N26 and the source of NMOS transistor N24; the gate of NMOS transistor N24 is connected to the gate of NMOS transistor N23, serving as the non-inverting input of error amplifier AE2; the source of NMOS transistor N23 is connected to the drain of NMOS transistor N25 and the source of NMOS transistor N23; the sources of NMOS transistors N25 and NMOS transistor N26 are grounded; the gates of NMOS transistors N25 and NMOS transistor N26 are connected to signal Nb1.

[0021] Optionally, the second output circuit includes a digital load buffer Buffer2; the digital load buffer Buffer2 includes PMOS transistors P24, PMOS transistor P25, NMOS transistor N27, and NMOS transistor N28; the source of PMOS transistor P24 is connected to the input signal Vin, and the drain of power transistor Pn2 is connected to the input signal Vin; the gate of PMOS transistor P24 is connected to the bias signal Pb1, and the drain of PMOS transistor P24 is connected to the drain of NMOS transistor N27 and the gate of power transistor Pn2; the source of NMOS transistor N27 is connected to the drain of NMOS transistor N28 and the drain of PMOS transistor P25; the gate of N27 and the gate of NMOS transistor N28 are connected to the bias signal Nb1; the drain of NMOS transistor N28 is grounded; the gate of PMOS transistor P25 is connected to the output signal EA_1 of error amplifier AE2; the source of PMOS transistor P25 is connected to the source of power transistor Pn2 as the output signal VoutD.

[0022] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0023] 1. This invention, by setting up a bandgap reference circuit BGR, generates multiple independent and stable outputs to provide stable reference voltages for constant transconductance error amplifiers AE1 and AE2. Then, a bias voltage is generated by a constant transconductance circuit Gmc. Constant transconductance error amplifier AE1 drives power transistor Pn1 through a first output circuit to output a signal for analog loads, and error amplifier AE2 drives power transistor PN2 through a second output circuit to output a signal for digital loads. This solves the problem that current LDOs have poor load-carrying capacity and cannot achieve dual-channel output for analog and digital circuits.

[0024] 2. The first output circuit of the present invention is provided with an auxiliary operational amplifier AUX. Through the operational amplifier OTA in the auxiliary operational amplifier AUX, when the gain of the power transistor Pn1 changes with the load current, the output voltage Vx of AUX will decrease as the ripple amplitude at the signal Vin increases. When the Vds of the power transistor Pn1 increases with the increase of the signal Vin, the Vds of the NMOS transistor N31 decreases, and vice versa, thereby improving the intermediate frequency PSRR.

[0025] 3. This invention sets up a constant transconductance error amplifier AE1, selects only the differential pair with larger output current as the differential pair of the input stage, and performs current-to-voltage conversion on the selected larger current signal to keep the transconductance of the amplifier input stage constant, so that the transconductance of the input stage is not affected by the input common-mode voltage, thereby improving the low-frequency PSRRS. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of an LDO without external capacitors provided in an embodiment of the present invention;

[0027] Figure 2 This is a circuit structure diagram of a bandgap reference circuit BGR for an LDO without external capacitors provided in an embodiment of the present invention;

[0028] Figure 3 This is a circuit structure diagram of a constant transconductance circuit Gmc for an LDO without external capacitors provided in an embodiment of the present invention;

[0029] Figure 4 This is a circuit diagram of a constant transconductance error amplifier AE1 with no external capacitor provided in an embodiment of the present invention;

[0030] Figure 5 This is a circuit diagram of an auxiliary operational amplifier (AUX) for an LDO without external capacitors provided in an embodiment of the present invention;

[0031] Figure 6 This is a circuit diagram of an operational amplifier OTA with no external capacitors for an LDO provided in an embodiment of the present invention;

[0032] Figure 7 This is a circuit diagram of an analog load buffer Buffer1 for an LDO without external capacitors provided in an embodiment of the present invention;

[0033] Figure 8 This is a circuit diagram of an error amplifier AE2 of an LDO without external capacitors provided in an embodiment of the present invention;

[0034] Figure 9 This is a circuit diagram of a digital load buffer Buffer2 of an LDO without external capacitors provided in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0036] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances. Example

[0038] like Figure 1 As shown, an LDO without external capacitors is characterized by comprising a constant transconductance circuit Gmc, a constant transconductance error amplifier AE1, a first output circuit, an error amplifier AE2, a second output circuit, a bandgap reference circuit BGR, and power transistors Pn1 and Pn2. The constant transconductance circuit Gmc generates a bias voltage signal and is connected to both the constant transconductance error amplifier AE1 and the error amplifier AE2. The bandgap reference circuit BGR, the constant transconductance error amplifier AE1, the first output circuit, and the power transistor Pn1 are connected in sequence. The bandgap reference circuit BGR generates multiple independent outputs to provide reference voltages for the constant transconductance error amplifiers AE1 and AE2. The constant transconductance error amplifier AE1 generates a first output signal, which is transmitted through the first output circuit to drive the power transistor Pn1. The error amplifier AE2 generates a second output signal, which is transmitted through the second output circuit to drive the power transistor Pn2.

[0039] like Figure 2As shown, the bandgap reference circuit BGR includes a power switching switch circuit, PMOS transistors P26~P31, NMOS transistors N29~N30, resistors R3~R4, transistors PNP1 and PNP2; the sources of PMOS transistors P26~P31 are all connected to the output terminal of the switch; the gates of PMOS transistors P26~P31 are connected; the drain of PMOS transistor P26 is connected to the gate of PMOS transistor P31 and the emitter of transistor PNP1; the drains of PMOS transistors P27, P31, and P32 are connected; the drain of PMOS transistor P31 is connected to the drain of NMOS transistor N29 and to the gates of PMOS transistors P26~P31; the source of NMOS transistor N29 is grounded, and the gate of NMOS transistor N29 is connected to the gate of NMOS transistor N30; the gate and drain of NMOS transistor N30 are shorted and connected to PMOS transistor P26~P31. The drain of transistor P32 is connected; the source of NMOS transistor N30 is grounded; the drain of PMOS transistor P28 is connected to the gate of PMOS transistor P32, one end of resistor R3, and one end of resistor R4; the other end of resistor R4 is grounded; the other end of resistor R3 is connected to the emitter of transistor PNP2; the drain of PMOS transistor P29 is connected to one end of resistor R5, generating a reference voltage Vn+ across resistor R5; the drain of PMOS transistor P30 is connected to one end of resistor R6, generating a reference voltage Vn1+ across resistor R6; the drain of PMOS transistor P31 is connected to one end of resistor R7, generating a reference voltage Vrefx across resistor R7; when powered on, the bandgap is powered by Vin. When there is an output signal VoutA, the Switch circuit disconnects Vin and controls VoutA to power the bandgap, reducing the noise of the bandgap reference output.

[0040] like Figure 3As shown, the constant transconductance circuit Gmc is integrated in the constant transconductance error amplifier AE1 to provide bias voltage for the constant transconductance error amplifier AE1. The constant transconductance circuit Gmc includes PMOS transistors P15~P19 and NMOS transistors N16~N19; PMOS transistors P15 and P16 are connected to the input signal Vin, the gate and drain of PMOS transistor P15 are shorted and connected to the gate of PMOS transistor P16 and the drain of NMOS transistor N16; the source of PMOS transistor P17 is connected to the input signal Vin, the gate of PMOS transistor P17 is connected to the control signal Pb2, and the drain of PMOS transistor P17 is connected to the source of PMOS transistor P17. The gate and drain of PMOS transistors P18 and P19 are connected to the source of PMOS transistors P18 and P19 respectively; the gate and drain of PMOS transistor P18 are shorted and connected to the gate of NMOS transistor N16 and the drain of NMOS transistor N18; the gate and drain of NMOS transistor N17 are shorted and connected to the gate of PMOS transistor P19 and the drain of PMOS transistor P16; the gate and drain of NMOS transistor N19 are shorted and connected to the drain of PMOS transistor P19 and the gate of NMOS transistor N18; the source of NMOS transistors N16 to N19 is grounded; the gate of PMOS transistor P16 is the bias signal Pb1, and the gate of NMOS transistor N18 is the bias signal Nb1.

[0041] like Figure 4As shown, the constant transconductance error amplifier AE1 includes PMOS transistors P1~P14, NMOS transistors N1~N15, resistors R1 and R2; the sources of PMOS transistors P12 and P13 are connected to the drain of PMOS transistor P1, the drain of PMOS transistor P12 is connected to the drain of NMOS transistor N2, and the drain of PMOS transistor P13 is connected to the drain of NMOS transistor N3; the gate of NMOS transistor N12 is connected to Vn-, the gate of NMOS transistor N13 is connected to VN+, the sources of NMOS transistors N12 and NMOS transistor N13 are connected to the drain of N1, the drain of NMOS transistor N12 is connected to the drain of PMOS transistor P3, and the drain of NMOS transistor N13 is connected to the drain of PMOS transistor P2; PMOS transistors P1, P2, ... The sources of P3 and P14 are both connected to the input signal Vin, and their gates are both connected to the same bias signal Pb1; the sources of NMOS transistors N1, N2, and N3 are all grounded, and their gates are all connected to the same bias signal Nb1; the gate-drain of NMOS transistor N8 is shorted and connected to the gate of NMOS transistor N9 and the drain of PMOS transistor P2; the gate-drain of PMOS transistor P8 is shorted and connected to the gate of PMOS transistor P9 and the drain of NMOS transistor N2; the source of NMOS transistor N8 is connected to the source of PMOS transistor P8; the source of NMOS transistor N9 is connected to the source of PMOS transistor P9; the drain of NMOS transistor N9 is connected to the drain of PMOS transistor P4; the drain of PMOS transistor P9 is connected to the drain of NMOS transistor N5; NMOS transistors The gate and drain of N10 are shorted and connected to the gate of NMOS transistor N11 and the drain of PMOS transistor P3. The gate and drain of PMOS transistor P10 are shorted and connected to the gate of PMOS transistor P11 and the drain of N3. The source of NMOS transistor N10 is connected to the source of PMOS transistor P10. The source of NMOS transistor N11 is connected to the source of PMOS transistor P11, and the drain of NMOS transistor N11 is connected to the drain of PMOS transistor P5. The drain of PMOS transistor P11 is connected to the drain of NMOS transistor N4. NMOS transistors N8~N11 and PMOS transistors P8~P11 form a maximum current selection circuit. Within the entire common-mode input voltage range, only the differential pair with the larger output current is selected as the differential pair of the input stage, ensuring constant transconductance. The error is reduced, and the square-law model is independent of the current, resulting in good process portability and thus not affecting the overall performance of the op-amp. One end of resistor R1 is connected to the drain of P6, and the other end of resistor R1 is connected to the drain of N6. The sources of PMOS transistors P4 and P5 are connected to the input signal Vin. The drain of PMOS transistor P4 is connected to the source of PMOS transistor P6, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P7. The gates of PMOS transistors P4 and P5 are connected together and then connected to the drain of PMOS transistor P6. The gates of PMOS transistors P6 and P7 are connected together and then connected to the drain of NMOS transistor N6. The source of NMOS transistor N6 is connected to the drain of N4, and the source of NMOS transistor N7 is connected to the drain of NMOS transistor N5.The gates of NMOS transistors N6 and N7 are connected to the gate of NMOS transistor N14, and the gates of NMOS transistors N4 and N5 are connected to the gate of NMOS transistor N15. PMOS transistors P4~P7 and NMOS transistors N4~N7 form the load of the constant transconductance error amplifier AE1, converting the selected larger current signal into voltage. Simultaneously, due to the high output resistance of the load, the signal is further amplified. One end of resistor R2 is connected to the drain of NMOS transistor N14. The other end is connected to the drain of PMOS transistor P14, the source of NMOS transistor N15 is grounded, the drain of NMOS transistor N15 is connected to the source of NMOS transistor N14, and the gate of NMOS transistor N14 is connected to the drain of PMOS transistor P14. The output of constant transconductance error amplifier AE1 is the drain of NMOS transistor N7, and the output signal is EA_O. Constant transconductance error amplifier AE1 keeps the transconductance of the amplifier input stage constant, so that the transconductance of the input stage is not affected by the input common-mode voltage, thus improving the low-frequency PSRRS.

[0042] The first output circuit includes a SUM circuit, an auxiliary operational amplifier AUX, and an analog load buffer Buffer1. The SUM circuit is connected to the constant transconductance error amplifier AE1 and the auxiliary operational amplifier AUX, respectively. The analog load buffer Buffer1 is connected to the analog load buffer Buffer1 and the power transistor Pn1, respectively. The SUM circuit is used to sum the signal of the auxiliary operational amplifier AUX and the signal generated by the constant transconductance error amplifier AE1 and output it to the analog load buffer Buffer1.

[0043] like Figure 5As shown, the auxiliary operational amplifier AUX includes Pn1_sense for sensing the current of power transistor Pn1, operational amplifier OTA, resistors RX1 and RX2, NMOS transistors N31 and N32; one end of resistor Rx1 is connected to Vin, the other end of resistor Rx1 is connected to one end of resistor Rx2, and then connected to the inverting input of operational amplifier OTA; the drain of Pn1_sense is connected to Vin, and the gate of Pn1_sense is connected to the gate of power transistor Pn1. The drain of ense is connected to the other end of resistor Rx2, and then to the drain of NMOS transistor N31; the output terminal Vx of operational amplifier OTA is connected to the gate of NMOS transistor N31 and the negative input terminal of the SUM circuit; the non-inverting input terminal of operational amplifier OTA is connected to signal Vrefx; the source of N31 is grounded, and the drain of NMOS transistor N32 is connected to the drain of NMOS transistor N31; the source of NMOS transistor N32 is grounded, and its gate is connected to bias signal Nb1; the positive input terminal of the SUM circuit is connected to... The output signal EA_0 of the constant transconductance error amplifier AE1 is input. The size of NMOS transistor N31 is 1 / 500 of that of power transistor Pn1. Since the length of NMOS transistor N31 is equal to that of power transistor Pn1, they have the same short-channel effect. The current density of NMOS transistor N31 and power transistor Pn1 is equal. The load effect of resistors RX1 and RX2 is minimized. The drain-source voltage Vds of NMOS transistor N31 and the drain-source voltage Vds of power transistor Pn1 are set to be equal. Therefore, NMOS transistor N3... 1. Compared to power transistor Pn1, only the area is reduced, and other aspects remain unchanged. When the gain of power transistor Pn1 changes with the load current, the AUX output voltage Vx will decrease as the ripple amplitude at Vin increases. This is because the gain of the voltage Vy from Vin to the drain of NMOS transistor N31 is negative. When the drain-source voltage Vds of power transistor Pn1 increases with Vin, the drain-source voltage Vds of NMOS transistor N31 decreases, and vice versa, thereby improving the intermediate frequency PSRR.

[0044] like Figure 6 As shown, the operational amplifier OTA includes PMOS transistors P33~P35, NMOS transistor N33, and NMOS transistor N34. The source of PMOS transistor P33 is connected to the input signal Vin, and the gate of PMOS transistor P33 is connected to the bias signal Pb1. The drain of PMOS transistor P33 is connected to the source of PMOS transistor P34 and the source of PMOS transistor P35. The gate of PMOS transistor P34 is the inverting input terminal, and the drain of PMOS transistor P34 is connected to the drain of NMOS transistor N33, serving as the output terminal Vx. The gate of PMOS transistor P35 is the non-inverting input terminal. The drain of PMOS transistor P35 is connected to NMOS transistor N34, which has its gate and drain shorted. The sources of NMOS transistors N33 and NMOS transistor N34 are grounded.

[0045] likeFigure 7 As shown, the analog load buffer Buffer1 includes an NMOS transistor N20, a transistor NPN1, and a capacitor CM. For an analog circuit load, the large current output of Pn1, capable of 5A, results in a very large area for the power transistor, leading to a very large interstage capacitance Cgs. Although the MOS transistor is a voltage-controlled device and its gate does not carry current, Cgs absorbs current during the MOS's turn-on process. If directly driven by a constant transconductance error amplifier AE1, Cgs would directly act as the load for AE1, which is a very low impedance load. This causes a significant drop in the gain of AE1. Furthermore, since AE1 is used for error voltage amplification, it cannot provide such a large input current or leakage current to turn on or off the power transistor Pn1. Therefore, using an analog load buffer... The Buffer1 circuit, without affecting the loop gain, should provide a sufficiently large current to rapidly charge and discharge capacitor Cgs, and must also ensure a sufficiently wide output voltage swing to fully turn power transistor Pn1 on or off. The drain of NMOS transistor N20 is connected to the collector of transistor NPN1 and the drain of power transistor Pn1, and is connected to the input signal Vin. The source of NMOS transistor N20 is connected to the gate of transistor NPN1, and the emitter of transistor NPN1 is connected to the gate of power transistor Pn1. The gate of NMOS transistor N20 is connected to the output signal SUM_OUT of the SUM circuit. The source of power transistor Pn1 serves as the output VoutA. Capacitor CM is connected across the gate of NMOS transistor N20 and the output of power transistor Pn1 to perform frequency compensation for the analog load buffer1 circuit.

[0046] like Figure 8As shown, the error amplifier AE2 includes PMOS transistors P20~P23 and NMOS transistors N21~N26. The sources of PMOS transistors P20, P21, P22, and P23 are connected to the input signal Vin. The gate and drain of PMOS transistor P20 are shorted and then connected to the gate of PMOS transistor P21 and the drain of NMOS transistor N24. The drain of PMOS transistor P21 is connected to the drain of NMOS transistor N22 and serves as the output terminal, with the output signal being EA_1. The gate and drain of PMOS transistor P23 are shorted and then connected to the gate of PMOS transistor P22 and the gate of NMOS transistor N21. The drain of PMOS transistor P22 is connected to the drain of NMOS transistor N23. The gates of NMOS transistors are connected; the gate of NMOS transistor N21 is connected to the gate of NMOS transistor N22, serving as the inverting input of error amplifier AE2; the source of NMOS transistor N21 is connected to the drain of NMOS transistor N26 and the source of NMOS transistor N24; the gate of NMOS transistor N24 is connected to the gate of NMOS transistor N23, serving as the non-inverting input of error amplifier AE2; the source of NMOS transistor N23 is connected to the drain of NMOS transistor N25 and the source of NMOS transistor N23; the sources of NMOS transistors N25 and NMOS transistor N26 are grounded; the gates of NMOS transistors N25 and NMOS transistor N26 are connected to signal Nb1.

[0047] like Figure 1 As shown, the source of power transistor Pn1 is also connected to resistor R8, the other end of resistor R8 is connected to resistor R9 and the inverting input terminal of constant transconductance error amplifier AE1, and the other end of resistor R9 is grounded; the source of power transistor Pn2 is also connected to resistor R10, the other end of resistor R10 is connected to resistor R11 and the inverting input terminal of error amplifier AE2, and the other end of resistor R11 is grounded.

[0048] like Figure 9As shown, the second output circuit includes a digital load buffer Buffer2; the digital load buffer Buffer2 includes PMOS transistors P24, PMOS transistor P25, NMOS transistor N27, and NMOS transistor N28; the source of PMOS transistor P24 is connected to the input signal Vin, and the drain of power transistor Pn2 is connected to the input signal Vin; the gate of PMOS transistor P24 is connected to the bias signal Pb1, and the drain of PMOS transistor P24 is connected to the drain of NMOS transistor N27 and the gate of power transistor Pn2; the source of NMOS transistor N27 is connected to the drain of NMOS transistor N28 and the drain of PMOS transistor P25; the gate of NMOS transistor N27 is connected to the NMOS transistor P28. The gate of transistor N28 is connected to the bias signal Nb1; the drain of NMOS transistor N28 is grounded; the gate of PMOS transistor P25 is connected to the output signal EA_1 of error amplifier AE2; the source of PMOS transistor P25 is connected to the source of power transistor Pn2 as the output signal VoutD. When the source of PMOS transistor P25 detects a change in VoutD, the voltage difference between VoutD and signal EA_1 will introduce an error signal. The error signal is amplified by two cascaded common-gate amplifiers composed of PMOS transistors P25 and P27 to adjust the gate voltage of power transistor Pn2. Finally, the drain current of power transistor Pn2 changes to compensate for VoutD.

[0049] like Figure 1 As shown, the input terminal of the power switching switch circuit is also connected to protection circuits, and the input terminal of the protection circuits is connected to the signal Vin; the output terminal of the protection circuits is connected to the drain of power transistor Pn1 and the drain of power transistor Pn2.

[0050] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An LDO without external capacitors, characterized in that, It includes a constant transconductance circuit Gmc, a constant transconductance error amplifier AE1, a first output circuit, an error amplifier AE2, a second output circuit, a bandgap reference circuit BGR, power transistors Pn1 and Pn2; The constant transconductance circuit Gmc is used to generate a bias voltage signal; the constant transconductance circuit Gmc is connected to the constant transconductance error amplifier AE1 and the error amplifier AE2 respectively. The bandgap reference circuit BGR, the constant transconductance error amplifier AE1, the first output circuit and the power transistor Pn1 are connected in sequence. The bandgap reference circuit BGR, error amplifier AE2, second output circuit and power transistor Pn2 are connected in sequence; The bandgap reference circuit BGR is used to generate multiple independent outputs to provide reference voltages for the constant transconductance error amplifiers AE1 and AE2; the constant transconductance error amplifier AE1 is used to generate a first output signal, which is transmitted through the first output circuit to drive the power transistor Pn1. The error amplifier AE2 is used to generate a second output signal, which is transmitted through the second output circuit to drive the power transistor Pn2. The first output circuit includes a SUM circuit, an auxiliary operational amplifier AUX, and an analog load buffer Buffer1. The SUM circuit is connected to the constant transconductance error amplifier AE1 and the auxiliary operational amplifier AUX, respectively. The analog load buffer Buffer1 is connected to the SUM circuit and the power transistor Pn1, respectively. The SUM circuit is used to sum the signal of the auxiliary operational amplifier AUX and the signal generated by the constant transconductance error amplifier AE1 and output it to the analog load buffer Buffer1. The second output circuit includes a digital load buffer Buffer2; the digital load buffer Buffer2 includes PMOS transistors P24, PMOS transistor P25, NMOS transistor N27, and NMOS transistor N28; the source of PMOS transistor P24 is connected to the input signal Vin, and the drain of power transistor Pn2 is connected to the input signal Vin; the gate of PMOS transistor P24 is connected to the bias signal Pb1, and the drain of PMOS transistor P24 is connected to the drain of NMOS transistor N27 and the gate of power transistor Pn2; the source of NMOS transistor N27 is connected to the drain of NMOS transistor N28 and the drain of PMOS transistor P25; the gate of N27 and the gate of NMOS transistor N28 are connected to the bias signal Nb1; the drain of NMOS transistor N28 is grounded; the gate of PMOS transistor P25 is connected to the output signal EA_1 of error amplifier AE2; the source of PMOS transistor P25 is connected to the source of power transistor Pn2 as the output signal VoutD.

2. The LDO without external capacitors according to claim 1, characterized in that, The bandgap reference circuit BGR includes a power switching switch circuit, PMOS transistors P26~P31, NMOS transistors N29~N30, resistors R3~R4, transistors PNP1 and PNP2; the sources of PMOS transistors P26~P31 are all connected to the output terminal of the switch; the gates of PMOS transistors P26~P31 are connected; the drain of PMOS transistor P26 is connected to the gate of PMOS transistor P31 and the emitter of PNP1; The drains of PMOS transistors P27, P31, and P32 are connected; the drain of PMOS transistor P31 is connected to the drain of NMOS transistor N29 and to the gates of PMOS transistors P26-P31; the source of NMOS transistor N29 is grounded, and its gate is connected to the gate of NMOS transistor N30; the gate-drain connection of NMOS transistor N30 is shorted and connected to the drain of PMOS transistor P32; the source of NMOS transistor N30 is grounded; the drain of PMOS transistor P28 is connected to the drain of PMOS transistor P26-P32. The gate of transistor P32 is connected to one end of resistor R3 and one end of resistor R4; the other end of resistor R4 is grounded; the other end of resistor R3 is connected to the emitter of transistor PNP2; the drain of PMOS transistor P29 is connected to one end of resistor R5, and a reference voltage Vn+ is generated across resistor R5; the drain of PMOS transistor P30 is connected to one end of resistor R6, and a reference voltage Vn1+ is generated across resistor R6; the drain of PMOS transistor P31 is connected to one end of resistor R7, and a reference voltage Vrefx is generated across resistor R7.

3. The LDO without external capacitors according to claim 2, characterized in that, The constant transconductance circuit Gmc includes PMOS transistors P15~P19 and NMOS transistors N16~N19; PMOS transistors P15 and P16 are connected to the input signal Vin, the gate and drain of PMOS transistor P15 are shorted and connected to the gate of PMOS transistor P16 and the drain of NMOS transistor N16; the source of PMOS transistor P17 is connected to the input signal Vin, the gate of PMOS transistor P17 is connected to the control signal Pb2, and the drain of PMOS transistor P17 is connected to the source of PMOS transistors P18 and P19 respectively; The gate and drain of PMOS transistor P18 are shorted and connected to the gate of NMOS transistor N16 and the drain of NMOS transistor N18; the gate and drain of NMOS transistor N17 are shorted and connected to the gate of PMOS transistor P19 and the drain of PMOS transistor P16; the gate and drain of NMOS transistor N19 are shorted and connected to the drain of PMOS transistor P19 and the gate of NMOS transistor N18; the sources of NMOS transistors N16 to N19 are all grounded; the gate of PMOS transistor P16 is the bias signal Pb1, and the gate of NMOS transistor N18 is the bias signal Nb1.

4. The LDO without external capacitors according to claim 3, characterized in that, The constant transconductance error amplifier AE1 includes PMOS transistors P1~P14, NMOS transistors N1~N15, resistors R1 and R2; the sources of PMOS transistors P12 and P13 are connected to the drain of PMOS transistor P1, the drain of PMOS transistor P12 is connected to the drain of NMOS transistor N2, and the drain of PMOS transistor P13 is connected to the drain of NMOS transistor N3; the gate of NMOS transistor N12 is connected to Vn-, which serves as the inverting input of the constant transconductance error amplifier AE1; the gate of NMOS transistor N13 is connected to Vn+; the sources of NMOS transistors N12 and N13 are connected to the drain of NMOS transistor N1, and the drain of NMOS transistor N12... The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N13, and the drain of NMOS transistor N14 is connected to the drain of PMOS transistor P2. The sources of PMOS transistors P1, P2, P3, and P14 are all connected to the input signal Vin, and their gates are all connected to the same bias signal Pb1. The sources of NMOS transistors N1, N2, and N3 are all grounded, and their gates are all connected to the same bias signal Nb1. The gate and drain of NMOS transistor N8 are shorted and connected to the gate of NMOS transistor N9 and the drain of PMOS transistor P2. The gate and drain of PMOS transistor P8 are shorted and connected to the gate of PMOS transistor P9 and the drain of N2. The source of NMOS transistor N8 is connected to the source of PMOS transistor P8. The source of NMOS transistor N9 is connected to the source of PMOS transistor P14. The source of NMOS transistor N9 is connected to the source of PMOS transistor P4. The drain of NMOS transistor P9 is connected to the drain of NMOS transistor N5. The gate and drain of NMOS transistor N10 are shorted and connected to the gate of NMOS transistor N11 and the drain of PMOS transistor P3. The gate and drain of PMOS transistor P10 are shorted and connected to the gate of PMOS transistor P11 and the drain of NMOS transistor N3. NMOS transistor N10 is connected to the source of PMOS transistor P10. The source of NMOS transistor N11 is connected to the source of PMOS transistor P11. The drain of NMOS transistor N11 is connected to the drain of PMOS transistor P5. The drain of PMOS transistor P11 is connected to the source of N4. The drains are connected; one end of resistor R1 is connected to the drain of PMOS transistor P6, and the other end of resistor R1 is connected to the drain of NMOS transistor N6; the sources of PMOS transistors P4 and P5 are connected to the input signal Vin; the drain of PMOS transistor P4 is connected to the source of PMOS transistor P6; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P7; the gates of PMOS transistors P4 and P5 are connected together and connected to the drain of PMOS transistor P6; the gates of PMOS transistors P6 and P7 are connected together and connected to the drain of NMOS transistor N6; the source of NMOS transistor N6 is connected to the drain of NMOS transistor N4; and the source of NMOS transistor N7 is connected to the drain of N5.The gates of NMOS transistors N6 and N7 are connected to the gate of NMOS transistor N14, and the gates of NMOS transistors N4 and N5 are connected to the gate of NMOS transistor N15. One end of resistor R2 is connected to the drain of NMOS transistor N14, and the other end of resistor R2 is connected to the drain of PMOS transistor P14. The source of NMOS transistor N15 is grounded, and the drain of NMOS transistor N15 is connected to the source of NMOS transistor N14. The gate of NMOS transistor N14 is connected to the drain of PMOS transistor P14. The output terminal of the constant transconductance error amplifier AE1 is the drain of NMOS transistor N7, and the output signal is EA_O.

5. The LDO without external capacitors according to claim 1, characterized in that, The auxiliary operational amplifier (AUX) includes a Pn1_sense for sensing the current of the power transistor Pn1, an operational amplifier OTA, resistors RX1 and RX2, NMOS transistors N31 and N32. One end of resistor Rx1 is connected to the input signal Vin, and the other end of resistor Rx1 is connected to one end of resistor Rx2, which is then connected to the inverting input of the operational amplifier OTA. The drain of Pn1_sense is connected to Vin, the gate of Pn1_sense is connected to the gate of the power transistor Pn1, and the source of Pn1_sense is connected to resistor Rx2. The other end is connected to the drain of NMOS transistor N31; the output terminal Vx of the operational amplifier OTA is connected to the gate of NMOS transistor N31 and to the negative input terminal of the SUM circuit; the non-inverting input terminal of the operational amplifier OTA is connected to the signal Vrefx; the source of NMOS transistor N31 is grounded, and the drain of NMOS transistor N32 is connected to the drain of NMOS transistor N31; the source of NMOS transistor N32 is grounded, and the gate is connected to the bias signal Nb1; the positive input terminal of the SUM circuit is connected to the output signal EA_0 of the constant transconductance error amplifier AE1.

6. The LDO without external capacitors according to claim 1, characterized in that, The analog load buffer Buffer1 includes an NMOS transistor N20, a transistor NPN1, and a capacitor CM. The drain of the NMOS transistor N20 is connected to the collector of the transistor NPN1 and the drain of the power transistor Pn1, and is connected to the input signal Vin. The source of the NMOS transistor N20 is connected to the gate of the NPN1, and the emitter of the NPN1 is connected to the gate of the Pn1. The gate of the NMOS transistor N20 is connected to the output signal SUM_OUT of the SUM circuit. The source of the power transistor Pn1 serves as the output VoutA. The capacitor CM is connected across the gate of the NMOS transistor N20 and the output terminal of the power transistor Pn1.

7. An LDO without external capacitors according to claim 5, characterized in that, The operational amplifier OTA includes PMOS transistors P33-P35, NMOS transistor N33, and NMOS transistor N34. The source of PMOS transistor P33 is connected to the input signal Vin, and the gate of PMOS transistor P33 is connected to the bias signal Pb1. The drain of PMOS transistor P33 is connected to the source of PMOS transistor P34 and the source of PMOS transistor P35. The gate of PMOS transistor P34 is the inverting input terminal, and the drain of PMOS transistor P34 is connected to the drain of NMOS transistor N33, serving as the output terminal Vx. The gate of PMOS transistor P35 is the non-inverting input terminal. The drain of PMOS transistor P35 is connected to NMOS transistor N34, which has its gate and drain shorted. The sources of NMOS transistors N33 and NMOS transistor N34 are grounded.

8. An LDO without external capacitors according to claim 3, characterized in that, The error amplifier AE2 includes PMOS transistors P20-P23 and NMOS transistors N21-N26. The sources of PMOS transistors P20, P21, P22, and P23 are connected to the input signal Vin. The gate and drain of PMOS transistor P20 are shorted and then connected to the gate of PMOS transistor P21 and the drain of NMOS transistor N24. The drain of PMOS transistor P21 is connected to the drain of NMOS transistor N22 and serves as the output terminal, with the output signal being EA_1. The gate and drain of PMOS transistor P23 are shorted and then connected to the gate of PMOS transistor P22 and the gate of NMOS transistor N21. The drain of PMOS transistor P22 is connected to the drain of NMOS transistor N23. The NMOS transistors are connected as follows: the gate of NMOS transistor N21 is connected to the gate of NMOS transistor N22, serving as the inverting input of error amplifier AE2; the source of NMOS transistor N21 is connected to the drain of NMOS transistor N26 and the source of NMOS transistor N24; the gate of NMOS transistor N24 is connected to the gate of NMOS transistor N23, serving as the non-inverting input of error amplifier AE2; the source of NMOS transistor N23 is connected to the drain of NMOS transistor N25 and the source of NMOS transistor N22; the sources of NMOS transistors N25 and NMOS transistor N26 are grounded; the gates of NMOS transistors N25 and NMOS transistor N26 are connected to signal Nb1.

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