Register electrostatic interference processing system, method and storage medium

Abstract

Embodiments of the present application disclose a register electrostatic interference processing system, method and storage medium, and relate to the technical field of electronic devices. The register electrostatic interference processing system comprises a driving module; the driving module is configured to receive a signal value and drive an execution module based on the signal value; the driving module comprises a register, an electrostatic detection module, a control module and a processing module; the register is configured to store the signal value in the driving module; wherein the signal value comprises a signal value of a driving signal; the electrostatic detection module is configured to detect whether electrostatic discharge occurs in the driving module; the control module is configured to determine whether the signal value in the register is abnormal after determining that electrostatic discharge occurs in the driving module; and the processing module is configured to perform a processing operation on the register after determining that the signal value in the register is abnormal; wherein the processing operation comprises a reset operation. The system provided in the embodiments of the present application can reduce the situation that the register cannot work normally due to electrostatic interference based on electrostatic detection and reset operation.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, specifically to a register electrostatic interference processing system, method, and storage medium. Background Technology

[0002] Electrostatic interference is an objective phenomenon. Contact, friction, and the accumulation of static electricity by components themselves can all generate static electricity. Because static electricity is characterized by long-term accumulation, high voltage, and short duration, the voltage at the moment of static discharge is very high, which can cause electrical stress damage to electronic components or integrated circuits. Therefore, it is very necessary to carry out electrostatic protection for electronic components or integrated circuits.

[0003] In current electronic components or integrated circuits, electrostatic interference is generally mitigated by designing specialized hardware structures, such as adding grounding shields to or within the integrated circuit structure. Although these shields or other electrostatic shielding devices can prevent electrostatic interference to electronic components to a certain extent, there is always the possibility that after electrostatic breakdown of the shielding device, the residual voltage can still act on the electronic components, thus affecting their normal operation. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a register electrostatic interference processing system, method and storage medium to solve the problem of register signal values ​​being affected by electrostatic interference and reduce the occurrence of electronic components or integrated circuits malfunctioning due to register problems.

[0005] In a first aspect, embodiments of this application provide a register electrostatic interference processing system, the system including a driving module; the driving module is used to receive signal values ​​and drive an execution module based on the signal values; The drive module includes a register, an electrostatic detection module, a control module, and a processing module; The register is used to store signal values ​​in the drive module; wherein, the signal values ​​include the signal values ​​of the drive signals; The electrostatic detection module is used to detect whether static electricity is generated in the drive module; The control module is used to determine whether there is an abnormality in the signal value in the register after static electricity occurs in the register. The processing module is used to perform processing operations on the register after determining that there is an abnormality in the signal value in the register; wherein, the processing operation includes a reset operation.

[0006] In the technical solution of this application embodiment, the drive module receives signal values ​​and stores these signal values ​​in a register. The signal values ​​include the values ​​of the drive signals. An electrostatic discharge (ESD) detection module detects whether ESD occurs in the drive module. If ESD occurs, the control module further determines whether the signal values ​​in the register are abnormal. If the signal values ​​in the register are abnormal, the processing module performs processing operations on the register, including reset operations. Therefore, the technical solution provided in this application embodiment allows the register to return to a normal working state after a reset operation following the detection of an abnormal signal value in the drive module's register after an ESD event, effectively reducing the impact of ESD interference on the normal operation of the register.

[0007] In some alternative embodiments, the register includes a first register and a second register; The first register is used to store the signal value of the drive signal received by the drive module; The second register is used to store the initial checksum value obtained after performing a checksum operation on the signal value of the drive signal; The second register has an independent storage IP address and is located away from the external interface of the driver module.

[0008] In the above embodiments, the register further includes a first register and a second register. The first register stores the signal value of the drive signal received by the drive module, and the second register stores the initial checksum value obtained after performing a checksum operation on the signal value of the drive signal in the first register. Since the second register has its own independent storage IP address within the drive module and is located far from the external interface of the drive module, it is less susceptible to interference from static electricity, thus providing an accurate standard reference value in the subsequent process of determining whether the signal value of the drive signal in the first register is abnormal.

[0009] In some alternative embodiments, the second register includes an OTP register.

[0010] In the above embodiment, the second register includes an OTP register, which stores the initial checksum value obtained by performing a checksum operation on the signal values ​​of the drive signals stored in the first register. Since the OTP register has its own independent storage IP address within the drive module and is located far from the external interface of the drive module, it can be largely protected from interference by static electricity, thus providing an accurate standard reference value in the subsequent process of determining whether the signal values ​​of the drive signals in the first register are abnormal.

[0011] In some optional embodiments, during the process of determining whether there is an anomaly in the signal value in the register, the control module is specifically used for: Read the signal value from the register; Perform a checksum operation on the signal value in the register to obtain the current checksum value; Compare the current checksum with the initial checksum; If the current check value is different from the initial check value, it is determined that the signal value in the register is abnormal.

[0012] In the above embodiment, the process by which the control module in the drive module determines whether the signal value in the first register is abnormal is as follows: First, the signal value in the first register is read; then, a checksum operation is performed on the signal value in the first register to obtain the current checksum value; finally, the current checksum value is compared with the initial checksum value in the second register. If the current checksum value is different from the initial checksum value in the second register, it is determined that the signal value in the first register is abnormal, indicating that after static electricity occurs in the drive module, the signal value stored in the first register in the drive module is affected by static interference and changes. Conversely, if the current checksum value is the same as the initial checksum value in the second register, it indicates that the signal value in the first register is not affected by static electricity. Therefore, after static electricity occurs in the drive module, the control module in the drive module can accurately process the signal value in the first register and further accurately determine whether the signal value stored in the first register is affected by static interference.

[0013] In some optional embodiments, the algorithm for the checksum operation includes: The target signal value is divided into multiple data segments based on the length of the first preset byte. The multiple segmented data segments are concatenated in pairs in sequence to obtain multiple concatenated data. The multiple spliced ​​data are summed to obtain the accumulated data; The accumulated data is divided into two segments of equal length, and the segments are added together to obtain the summation data; Invert the summed data to obtain the target verification value; The target signal value includes the signal value of the drive signal or the signal value in the register; the target check value includes the initial check value or the current check value.

[0014] In the above embodiments, a checksum operation is performed on the target signal value to obtain the target verification value. The target signal value includes the signal value of the driving signal or the signal value in the first register, and the target verification value includes the initial verification value or the current verification value. Performing a checksum operation on the signal value of the driving signal yields the initial verification value, while performing a checksum operation on the signal value in the first register yields the current verification value. The checksum operation includes algorithms using 1 byte (8 bits), 2 bytes (16 bits), or 4 bytes (32 bits). This application uses a 2-byte (16-bit) checksum operation as an example. The specific operation process is as follows: First, the target signal value to be calculated is divided into two bytes (a first preset byte), with each two bytes forming a 16-bit value. Second, all 16-bit values ​​are concatenated pairwise and accumulated into a 32-bit value. Then, the high 16 bits and low 16 bits of the 32-bit value are added together to obtain the sum. Finally, the accumulated sum is inverted bitwise (inversion is taking the two's complement), thus obtaining the checksum value. Therefore, after the control module performs a checksum operation on the signal value of the drive signal, the result is the initial checksum value; after performing a checksum operation on the signal value in the first register, the result is the current checksum value. The checksum operation ensures that the target signal value involved in the calculation is complete and error-free, further improving the accuracy of the calculated target signal value's checksum value. This allows for accurate determination of whether the signal value in the first register is abnormal, enabling timely reset of the register and effectively reducing the impact of electrostatic interference on the normal operation of the first register.

[0015] In some optional embodiments, the algorithm for the checksum operation further includes: Obtain the number of the plurality of data segments; During the process of sequentially concatenating the multiple data segments in pairs, if it is determined that the number of the multiple data segments is odd, the last data segment in the multiple data segments is concatenated with 0 of the first preset byte length to obtain the last concatenated data.

[0016] In the above embodiment, the specific checksum calculation process further includes: First, the target signal value to be calculated is divided into two bytes (a first preset byte), with each two bytes forming a 16-bit value. If there is a single byte of data at the end, a byte of 0 is added to form two bytes. Second, all the 16-bit values ​​are concatenated in pairs and accumulated into a 32-bit value. Then, the high 16 bits and low 16 bits of the 32-bit value are added to obtain the sum. The accumulated sum is then inverted bit by bit (inversion is taking the two's complement), which yields the checksum value. Thus, when the number of data segments is odd, padding with 0s in the calculation allows the target signal value to perform the checksum algorithm normally without affecting the accuracy of the final checksum value, thereby accurately determining whether the signal value of the first register is abnormal.

[0017] In some optional embodiments, the electrostatic detection module includes a state machine and an electrical signal transmission line; The electrical signal transmission line is used to acquire the electrical signals of the drive module and transmit the electrical signals to the state machine; wherein, the electrical signals of the drive module include external electrical signals and internal electrical signals of the drive module; The state machine is used to receive the electrical signal and determine whether the electrical signal is higher than a threshold. If the electrical signal is higher than the threshold, it is determined that static electricity has occurred in the drive module.

[0018] In the above embodiment, an electrostatic discharge (ESD) detection module detects whether static electricity has occurred in the drive module. An electrical signal transmission line is used to collect the electrical signals of the drive module. These electrical signals include external and internal signals; the external signals include housing signals, and the internal signals include component signals. The state machine receives the electrical signals collected by the transmission line and determines their relationship to a threshold value set in the state machine. If the electrical signal is higher than the threshold, it is determined that static electricity has occurred in the drive module. Therefore, by connecting the ESD detection module to the electrical signal transmission line and cooperating with the state machine, the occurrence of static electricity in the drive module can be detected promptly and accurately. This allows the drive control module to determine whether there are any abnormalities in the signal values ​​in the registers, effectively reducing the impact of ESD interference on the normal operation of the registers.

[0019] In some alternative embodiments, the execution module includes an AMOLED display.

[0020] In the above embodiments, the driving module is connected to the execution module, and the driving signal value in the driving module drives the execution module. This application applies a system for handling electrostatic interference in the registers of the driving module to an AMOLED display (execution module). AMOLED displays possess advantages such as self-emissive technology, vibrant colors, fast response time, high contrast, low power consumption, wide viewing angle, high refresh rate, and thinness, making them popular among many smart display device manufacturers. Therefore, the electrostatic detection and handling system provided in the foregoing embodiments of this application can promptly detect and handle electrostatic discharge in the AMOLED display driving circuit, thereby minimizing the impact of electrostatic discharge on the AMOLED display driving circuit.

[0021] Secondly, embodiments of this application provide a register electrostatic interference processing method, the method comprising: The signal values ​​in the drive module are stored; wherein the signal values ​​include the signal values ​​of the drive signals; Detect whether static electricity is generated in the drive module; After determining that static electricity has occurred in the register, it is determined whether there is any abnormality in the signal value in the register; After determining that there is an abnormality in the signal value in the register, a processing operation is performed on the register; wherein, the processing operation includes a reset operation.

[0022] In the technical solution of this application embodiment, the solution first detects whether static electricity occurs in the drive module. If no static electricity occurs in the drive module, no processing operation is required on the register. If static electricity occurs in the drive module, it then determines whether there is an abnormality in the signal value in the register. If the signal value in the register is not abnormal, no processing operation is required on the register. If the signal value in the register is abnormal, processing operation is performed on the register, including a reset operation. Therefore, the electrostatic interference handling method provided by this application embodiment effectively reduces the impact of electrostatic interference on the normal operation of the register by timely detecting and accurately handling abnormal signal values ​​in the register caused by electrostatic interference.

[0023] Thirdly, this application provides an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the method described in the second aspect or any optional implementation thereof.

[0024] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the method described in the second aspect or any optional implementation thereof.

[0025] The above embodiments provide an electronic device and a computer-readable storage medium that have the same beneficial effects as the register electrostatic interference processing method provided by the second aspect or any optional embodiment of the second aspect, which will not be elaborated here.

[0026] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the register electrostatic interference processing system provided in the first embodiment of this application; Figure 2 This is a schematic diagram of the register structure provided in the second embodiment of this application; Figure 3 This is a schematic diagram of another register structure provided in the third embodiment of this application; Figure 4 A flowchart for handling abnormal signal values ​​in registers provided in the fourth embodiment of this application; Figure 5 This is a flowchart of the algorithm for performing checksum calculations on target signal values ​​in a drive module, provided in the fifth embodiment of this application. Figure 6 Another flowchart of the algorithm for performing checksum operation on target signal values ​​in the driving module provided in the sixth embodiment of this application; Figure 7 This is a schematic diagram of the electrostatic detection module structure provided in the seventh embodiment of this application; Figure 8 This is a schematic diagram illustrating the application of the register electrostatic interference processing system provided in the first embodiment to an AMOLED display screen. Figure 9 A flowchart of a register electrostatic interference processing method provided in an embodiment of this application; Figure 10 This is a block diagram of an electronic device provided in an embodiment of this application.

[0028] The reference numerals in the detailed embodiments are as follows: 100 - Register electrostatic interference processing system; 110 - Drive module; 120 - Register; 130 - Electrostatic detection module; 140 - Control module; 150 - Processing module; 160 - AMOLED display; 122 - First register; 124 - Second register; 126 - OTP register; 132 - State machine; 134 - Electrical signal transmission line; 01 - Electrical signal; 10 - Signal value; 20 - Drive signal value; 400 - Electronic device; 410 - Processor; 420 - Memory. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0030] During the research process, the applicant discovered that in current electronic components or integrated circuits, electrostatic interference is generally avoided by designing specialized hardware structures, such as adding grounding shields to or within the integrated circuit structure. However, there is no specific method for handling registers after electrostatic discharge occurs, so that registers in integrated circuits can be restored to a normal working state through a reset operation, thereby effectively reducing the impact of electrostatic interference on the normal operation of registers.

[0031] Based on this, embodiments of this application provide an electrostatic interference handling system. When electrostatic discharge occurs in the drive module and the signal value of the register in the drive module becomes abnormal, the system performs processing operations on the register, allowing it to be restored to a normal working state through a reset operation. This reduces the occurrence of electronic components or integrated circuits malfunctioning due to register problems. The methods provided in this application are described below through several embodiments.

[0032] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the register electrostatic interference processing system provided in the first embodiment of this application.

[0033] This application provides a register electrostatic interference processing system 100, which includes a drive module 110; wherein the drive module 110 includes a register 120, an electrostatic detection module 130, a control module 140, and a processing module 150.

[0034] For example, the drive module 110 is used to receive signal values, including the signal values ​​of drive signals. Register 120 is used to store the signal values ​​in the drive module 110. The electrostatic discharge (ESD) detection module 130 detects whether ESD occurs in the drive module 110. If ESD occurs, the control module 140 determines whether the signal values ​​stored in register 120 are abnormal. If the signal values ​​in register 120 are abnormal, it indicates that the signal values ​​in register 120 are affected by ESD interference. The processing module 150 then performs processing operations on register 120, including reset operations. Therefore, after ESD occurs in the drive module 110, the control module 140 can accurately process the signal values ​​in register 120, further accurately determining whether the signal values ​​stored in register 120 are affected by ESD interference. If affected by ESD interference, register 120 can be restored to a normal working state through a reset operation, thereby effectively reducing the impact of ESD interference on the normal operation of register 120.

[0035] It should be noted that the register 120 in this application can be one or more, and the specific number of registers 120 can be set according to the actual situation; the processing operation in this solution is not limited to a specific reset operation (for example, it may also be a set operation or other operations that can restore the data in register 120 or run the function). Those skilled in the art should know that the reset operation is only one embodiment of this solution.

[0036] Optionally, such as Figure 2 As shown, Figure 2 A schematic diagram of the register structure provided for the second embodiment of this application.

[0037] Register 120 includes a first register 122 and a second register 124; The first register 122 is used to store the signal value of the drive signal received by the drive module 110; The second register 124 is used to store the initial checksum value obtained after performing a checksum operation on the signal value of the drive signal.

[0038] Furthermore, the second register 124 has an independent storage IP address and is located far from the external interface of the driver module 110. This can ensure to a certain extent that the second register 124 is not affected by electrostatic interference on the driver module 110, thereby maintaining the correctness and integrity of the relevant data or signal values ​​stored therein.

[0039] For example, after receiving the signal value of the drive signal from the drive module 110, how does register 120 store the received signal value and perform a checksum operation on the signal value to obtain an initial checksum value, so that the initial checksum value is not affected by static electricity after static electricity occurs in the drive module 110, is as follows: The first register 122 stores the signal value of the drive signal received by the drive module 110, and the second register 124 stores the initial checksum value obtained by performing a checksum operation on the signal value of the drive signal in the first register 122. Therefore, after static electricity occurs in the drive module 110, the initial checksum value stored in the second register 124 of the drive module 110 is not affected by static electricity, thus providing an accurate standard reference value in the subsequent process of determining whether the signal value of the drive signal in the first register 122 is abnormal.

[0040] Optionally, during the process of receiving the signal value of the drive signal from the first register 122, the second register 124 may also store the signal value of the drive signal in the drive module 110.

[0041] Since the second register 124 is to some extent unaffected by electrostatic interference acting on the drive module 110, after the drive module 110 is subjected to electrostatic interference, a checksum operation is simultaneously performed on the signal values ​​of the first register 122 and the drive signal values ​​in the second register 124. Therefore, after the drive module 110 is subjected to electrostatic interference, a further checksum operation is performed on the signal values ​​of the first register 122 and the drive signal values ​​in the second register 124, and the resulting signal values ​​are compared. If they are the same, it indicates that the drive signal value in the first register 122 has not been affected by electrostatic interference and no further processing is required; if they are different, it indicates that the drive signal value in the first register 122 has been affected by electrostatic interference and processing operations such as a reset operation are required to restore the normal operation of the drive module 110.

[0042] Optionally, such as Figure 3 As shown, Figure 3 This is a schematic diagram of another register structure provided for the third embodiment of this application.

[0043] The second register 124 includes the OTP register 126.

[0044] For example, the OTP register 126 stores the initial checksum value obtained after performing a checksum operation on the signal value of the drive signal in the first register 122. Since the OTP register 126 has its own independent storage IP address within the drive module 110 and is located far from the external interface of the drive module 110, it is largely protected from interference by static electricity, thus providing an accurate standard reference value in subsequent determinations of whether the signal value of the drive signal in the first register 122 is abnormal.

[0045] It should be noted that the second register 124 is not limited to the specific OTP register 126. The OTP register 126 is just one embodiment of this scheme.

[0046] Optionally, such as Figure 4 As shown, Figure 4 A flowchart for handling abnormal signal values ​​in a register provided in the fourth embodiment of this application.

[0047] The process of determining whether there is an abnormality in the signal value in the first register 122 includes steps 210 to 240.

[0048] Step 210: Read the signal value in the first register 122.

[0049] Step 220: Perform a checksum operation on the signal value in the first register 122 to obtain the current check value.

[0050] Step 230: Compare the current check value with the initial check value.

[0051] Step 240: If the current check value is different from the initial check value, it is determined that the signal value in the first register 122 is abnormal.

[0052] For example, after static electricity occurs in the drive module 110, the process by which the control module 140 in the drive module 110 determines whether the signal value in the first register 122 is abnormal is as follows: First, the signal value in the first register 122 is read; second, a checksum operation is performed on the signal value in the first register 122 to obtain the current checksum value; finally, the current checksum value is compared with the initial checksum value in the second register 124. If the two checksum values ​​are different, it is determined that the signal value in the first register 122 is abnormal, indicating that after static electricity occurs in the drive module 110, the signal value stored in the first register 122 in the drive module 110 is affected by static electricity interference and changes; conversely, if the two checksum values ​​are the same, it indicates that the signal value in the first register 122 is not affected by static electricity. Therefore, after static electricity occurs in the drive module 110, the control module 140 in the drive module 110 can accurately process the signal value in the first register 122 and further accurately determine whether the signal value stored in the first register 122 is affected by static electricity interference.

[0053] Optionally, such as Figure 5 As shown, Figure 5 The flowchart of the algorithm for performing checksum calculation on the target signal value in the driving module is provided in the fifth embodiment of this application.

[0054] The algorithm for performing checksum operations on the target signal value includes steps 310 to 350.

[0055] Step 310: Divide the target signal value into multiple data segments based on the length of the first preset byte.

[0056] Step 320: Pair the multiple divided data segments together in sequence to obtain multiple spliced ​​data.

[0057] Step 330: Accumulate the multiple spliced ​​data to obtain accumulated data.

[0058] Step 340: Divide the accumulated data into two segments of equal length and add the segments together to obtain the summation data.

[0059] Step 350: Invert the summed data to obtain the target verification value.

[0060] For example, the checksum operation includes algorithms using 1 byte (8 bits), 2 bytes (16 bits), or 4 bytes (32 bits). This application uses the 2-byte (16-bit) checksum operation as an example. The specific operation process is as follows: First, the target signal value to be calculated is divided into 2 bytes (a first preset byte), and each 2 bytes form a 16-bit value; Second, all the 16-bit values ​​are concatenated in pairs and accumulated into a 32-bit value; Then, the high 16 bits and low 16 bits of the 32-bit value are added together to obtain the sum; The obtained sum is inverted bit by bit (inversion is taking the two's complement), which gives the checksum value. Therefore, after the control module 140 performs a checksum operation on the signal value of the drive signal, the result is the initial checksum value; after performing a checksum operation on the signal value in the first register 122, the result is the current checksum value. The checksum operation ensures that the target signal value involved in the calculation is complete and error-free, further improving the accuracy of the checksum value of the calculated target signal value, thereby accurately determining whether the signal value of the first register 122 is abnormal, thus effectively reducing the impact of electrostatic interference on the normal operation of the first register 122.

[0061] It should be noted that the target signal value includes either the signal value of the drive signal or the signal value in the first register 122, and the target checksum value includes either the initial checksum value or the current checksum value. Performing a checksum operation on the signal value of the drive signal yields the initial checksum value, while performing a checksum operation on the signal value in the first register 122 yields the current checksum value.

[0062] Optionally, such as Figure 6 As shown, Figure 6 This is another flowchart of the algorithm for performing checksum operations on target signal values ​​in a drive module, provided in the sixth embodiment of this application.

[0063] Step 322 is included in the algorithm step 320, which involves performing a checksum operation on the target signal value.

[0064] Step 322: Concatenate the multiple data segments in pairs in sequence to obtain multiple concatenated data. If the number of the multiple data segments is determined to be odd, concatenate the last data segment of the multiple data segments with the first preset byte length of empty data segment to obtain the last concatenated data.

[0065] For example, the specific checksum calculation process further includes: First, dividing the target signal value to be calculated into two bytes (a first preset byte), with each two bytes forming a 16-bit value. If there is a single byte of data at the end, padding with 0s to form two bytes. Second, concatenating all the 16-bit values ​​in pairs and accumulating them into a 32-bit value. Then, adding the high 16 bits and low 16 bits of the 32-bit value to obtain the sum. Inverting the resulting sum bit by bit (inversion is taking the two's complement) yields the checksum value. Thus, when the number of data segments is odd, padding with 0s allows the target signal value to perform the checksum algorithm normally without affecting the accuracy of the final checksum value, thereby accurately determining whether the signal value of the first register 122 is abnormal.

[0066] Optionally, such as Figure 7 As shown, Figure 7 This is a schematic diagram of the electrostatic detection module structure provided in the seventh embodiment of this application; The electrostatic detection module 130 includes a state machine 132 and an electrical signal transmission line 134. The electrical signal transmission line 134 is used to acquire the electrical signal 01 of the drive module 110 and transmit the electrical signal 01 to the state machine 132; wherein, the electrical signal 01 of the drive module 110 includes the external electrical signal of the drive module 110 and the internal electrical signal of the drive module 110. State machine 132 is used to receive electrical signal 01 and determine whether electrical signal 01 is higher than the threshold. If the electrical signal 01 is higher than the threshold, it is determined that static electricity has occurred in the drive module 110.

[0067] For example, the electrostatic discharge (ESD) detection module 130 detects whether static electricity has occurred in the drive module 110, and the electrical signal transmission line 134 collects the electrical signal 01 of the drive module 110. The state machine 132 receives the electrical signal 01 collected by the electrical signal transmission line 134 and determines the relationship between the electrical signal 01 and a threshold set in the state machine 132. If the electrical signal 01 is higher than the threshold, it is determined that static electricity has occurred in the drive module 110. Therefore, by connecting the ESD detection module 130 to the electrical signal transmission line 134 and working in cooperation with the state machine 132, the presence of static electricity in the drive module 110 can be detected promptly and accurately. This allows the drive control module 140 to further determine whether the signal value in the first register 122 is abnormal, thereby effectively reducing the impact of ESD interference on the normal operation of the first register 122.

[0068] It should be noted that the electrical signal 01 of the drive module 110 includes external electrical signals and internal electrical signals of the drive module 110. The external signals include housing electrical signals, and the internal signals include component electrical signals.

[0069] Optionally, such as Figure 8 As shown, Figure 8 This is a schematic diagram illustrating the application of the register electrostatic interference processing system provided in the first embodiment of this application to an AMOLED display screen.

[0070] Specifically, signal value 10 is input into drive module 110, and drive module 110 outputs drive signal value 20 to drive AMOLED display 160.

[0071] For example, signal value 10 is input into the driving module 110. By connecting the driving module 110 to the AMOLED display 160, the driving module 110 outputs driving signal value 20 to drive the AMOLED display 160. This application applies the electrostatic interference processing system of the register 120 in the driving module 110 to the AMOLED display 160. The AMOLED display 160 has advantages such as self-emissive technology, vibrant colors, fast response speed, high contrast, low power consumption, wide viewing angle, high refresh rate, and thinness. Therefore, the AMOLED display 160 is favored by many smart display device manufacturers. Thus, through the electrostatic detection and processing system provided in the foregoing embodiments of this application, electrostatic discharge in the driving circuit of the AMOLED display 160 can be detected and processed in a timely manner, thereby minimizing the impact of electrostatic discharge on the driving circuit of the AMOLED display 160. It should be noted that the register electrostatic interference processing system 100 of this application is not limited to a specific AMOLED display. The AMOLED display is only one embodiment of this solution.

[0072] Optionally, such as Figure 9 As shown, Figure 9 A flowchart of a register electrostatic interference processing method provided in an embodiment of this application.

[0073] The register electrostatic interference processing method provided in this application includes the following steps: The signal values ​​in the storage driver module 110; Detect whether static electricity has occurred in the drive module 110; After determining that static electricity has occurred in the drive module 110, it is determined whether there is an abnormality in the signal value in the register 120; After determining that the signal value in register 120 is abnormal, a processing operation is performed on register 120. Exemplarily, in the technical solution of this application embodiment, the solution first detects whether static electricity occurs in the drive module 110. If no static electricity occurs in the drive module 110, no processing operation is required for the register 120. If static electricity occurs in the drive module 110, it is then determined whether the signal value in the register 120 is abnormal. If the signal value in the register 120 is not abnormal, no processing operation is required for the register 120. If the signal value in the register 120 is abnormal, a processing operation is performed on the register 120, wherein the processing operation includes a reset operation. Thus, the electrostatic interference processing method provided by this application embodiment effectively reduces the impact of electrostatic interference on the normal operation of the register 120 by timely detecting and accurately processing the abnormal signal value in the register 120 caused by electrostatic interference.

[0074] Please refer to Figure 10 ,like Figure 10 As shown, Figure 10 This is a block diagram of an electronic device provided in an embodiment of this application. This application describes an electronic device used for running a test method. The electronic device 400 may include a processor 410 and a memory 420. Those skilled in the art will understand that... Figure 10 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device 400.

[0075] For example, electronic device 400 may also include more than Figure 10 The more or fewer components shown, or having the same Figure 10 The different configurations shown.

[0076] Optionally, the electronic device 400 may be a smart display device, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), etc.

[0077] The processor 410 and memory 420 described above are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The processor 410 described above is used to execute executable modules stored in the memory.

[0078] The memory 420 can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory 420 stores programs, and the processor 410 executes these programs after receiving execution instructions. The methods executed by the electronic device 400 as defined in any embodiment of this application can be applied to the processor 410, or implemented by the processor 410.

[0079] The aforementioned processor 410 may be an integrated circuit chip with signal processing capabilities. The processor 410 may be a general-purpose processor, including a central processing unit (CPU) or a network processor (NP); it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0080] The electronic device 400 in this embodiment can be used to perform the various steps in the various methods provided in the embodiments of this application.

[0081] Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of any of the methods described above.

[0082] The computer program product of the test method provided in this application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the register electrostatic interference processing method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A register electrostatic interference processing system, characterized in that, The system includes a drive module; the drive module is used to receive signal values ​​and drive an execution module based on the signal values; The drive module includes a register, an electrostatic detection module, a control module, and a processing module; The register is used to store signal values ​​in the drive module; wherein, the signal values ​​include the signal values ​​of the drive signals; The electrostatic detection module is used to detect whether static electricity is generated in the drive module; The control module is used to determine whether there is an abnormality in the signal value in the register after determining that static electricity has occurred in the drive module; The processing module is used to perform processing operations on the register after determining that there is an abnormality in the signal value in the register; wherein, the processing operation includes a reset operation; The electrostatic detection module includes a state machine and an electrical signal transmission line. The electrical signal transmission line is used to acquire the electrical signals of the drive module and transmit the electrical signals to the state machine; wherein, the electrical signals of the drive module include external electrical signals and internal electrical signals of the drive module; The state machine is used to receive the electrical signal and determine whether the electrical signal is higher than a threshold. If the electrical signal is higher than the threshold, it is determined that static electricity has occurred in the drive module.

2. The system according to claim 1, characterized in that, The register includes a first register and a second register; The first register is used to store the signal value of the drive signal received by the drive module; The second register is used to store the initial checksum value obtained after performing a checksum operation on the signal value of the drive signal; The second register has an independent storage IP address and is located away from the external interface of the driver module.

3. The system according to claim 2, characterized in that, in, The second register includes the OTP register.

4. The system according to claim 2, characterized in that, In the process of determining whether there is an anomaly in the signal value in the register, the control module is specifically used for: Read the signal value from the first register; Perform a checksum operation on the signal value in the first register to obtain the current checksum value; Compare the current checksum with the initial checksum; If the current check value is different from the initial check value, it is determined that the signal value in the first register is abnormal.

5. The system according to any one of claims 2 to 4, characterized in that, in, The algorithm for the checksum operation includes: The target signal value is divided into multiple data segments based on the length of a first preset byte. The multiple data segments are concatenated in pairs in sequence to obtain multiple concatenated data. The multiple spliced ​​data are summed to obtain the accumulated data; The accumulated data is divided into two segments of equal length, and the segments are added together to obtain the summation data; Invert the summed data to obtain the target verification value; The target signal value includes the signal value of the driving signal or the signal value in the first register; the target check value includes the initial check value or the current check value.

6. The system according to claim 5, characterized in that, in, The algorithm for the checksum operation also includes: Obtain the number of the plurality of data segments; During the process of sequentially concatenating the multiple data segments in pairs, if it is determined that the number of the multiple data segments is odd, then the last data segment in the multiple data segments is concatenated with an empty data segment of the first preset byte length.

7. The system according to claim 1, characterized in that, in, The execution module includes an AMOLED display.

8. A method for handling electrostatic interference in registers, characterized in that, The method is applied to the register electrostatic interference processing system according to claim 1; the method includes: The signal values ​​in the drive module are stored; wherein the signal values ​​include the signal values ​​of the drive signals; Detect whether static electricity is generated in the drive module; After determining that static electricity has occurred in the drive module, it is determined whether there is any abnormality in the signal value in the register; After determining that there is an abnormality in the signal value in the register, a processing operation is performed on the register; wherein, the processing operation includes a reset operation.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, perform the steps of the method of claim 8.

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