A SRIO implementation device and method based on FMQL

Abstract

The present invention discloses an SRIO implementation device and method based on FMQL, which belongs to the field of airborne universal bus, including an FMQL programmable fusion chip, and the PL data area of ​​the FMQL programmable fusion chip includes four DMA processing modules, and the four DMA processing modules are all designed in a unidirectional manner; and the four DMA processing modules are used to process Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving respectively. The present invention does not need to use FIFO in FPGA for data caching, can realize mixed sending and receiving of multiple protocols in SRIO, supports simultaneous communication with multiple nodes, and has an error recovery mechanism, and has very high stability.

Description

Technical Field

[0001] The present invention relates to the field of airborne universal buses, and more specifically, to an SRIO implementation device and method based on FMQL. Background Art

[0002] In the prior art, the FMQL series programmable fusion chip launched by Fudan Microelectronics is a fully programmable PSOC chip, which integrates four ARM Cortex A7 processing systems (PS) and programmable logic (PL) in a single chip and has been widely used in the aviation field.

[0003] As the requirements for internal bus complexity and reliability in the aviation field continue to increase, the SRIO bus plays an increasingly important role. Various processors such as PowerPC and DSP have the function of implementing SRIO nodes. However, the stability and reliability need to be improved, and there is a problem of high resource consumption. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a SRIO implementation device and method based on FMQL, which improves stability and reliability, saves resources, etc.

[0005] The object of the present invention is achieved through the following solutions:

[0006] An SRIO implementation device based on FMQL includes an FMQL programmable fusion chip and a storage module. The PL data area of ​​the FMQL programmable fusion chip includes four DMA processing modules. The four DMA processing modules are all unidirectionally designed, that is, they can only receive data or send data at the same time; and the four DMA processing modules are used to process Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving respectively;

[0007] The PL data area of ​​the FMQL programmable fusion chip includes an SRIO IP core, which provides a high-speed physical port to the outside and interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving internally;

[0008] The PS interaction area of ​​the FMQL programmable fusion chip includes interrupt management, low-speed interface GP and high-speed interface HP;

[0009] The PS processing area of ​​the FMQL programmable fusion chip includes a data processing unit, which interacts with the high-speed interface HP and the storage module for data, and interacts with the low-speed interface GP and the interrupt management for control signals;

[0010] The PL control area of ​​the FMQL programmable fusion chip includes a clock reset management module and a public transaction processing module. The clock reset management module interacts with the public transaction processing module for control signals. The clock reset management module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals; the public transaction processing module interacts with the low-speed interface GP and interrupt management for control signals respectively; the public transaction processing module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals;

[0011] The storage module is used to store SRIO data.

[0012] Furthermore, the storage module includes a DDR3 storage module.

[0013] Further, it also includes a Message / Nwrite / Nwrite_r / Swirte sending module, an Nread sending module, a Message / Nwrite / Nwrite_r / Swirte receiving module and an Nread receiving module;

[0014] The Message / Nwrite / Nwrite_r / Swirte sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, takes out the data to be sent from the storage module through the DMA processing module, assembles the data according to the protocol type, and sends the data to the SRIO IP core, and returns the sending completion flag to the public transaction processing module after the sending is completed;

[0015] The Nread sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, sends the Nread sending request to the SRIO IP core, waits for the Nread response data of the SRIO IP core, then sends the Nread response data to DDR3 through the DMA processing module, and finally returns the sending completion flag to the public transaction processing module;

[0016] The Message / Nwrite / Nwrite_r / Swirte receiving module, after receiving the SRIO data packet sent by the SRIO IP core, unpacks the data if it is an Nwrite / Nwrite_r / Swirte protocol packet, sends the data to the storage module through the DMA processing module, and sends a receiving mark to the public transaction processing module; if it is a Message packet, the data is sent to the Message packet space corresponding to the storage module through the DMA processing module according to the large and small packet sequence numbers of the packet, and when the entire Message packet has been completely received, the receiving mark is sent to the public transaction processing module, otherwise it is not sent;

[0017] After receiving the SRIO data packet sent by the SRIO IP core, the Nread receiving module, if it is an Nread protocol packet, takes out the corresponding area data in the storage module through the DMA processing module and sends it to the SRIO IP core.

[0018] Furthermore, the interrupt management is divided into sending interrupt and receiving interrupt, which correspond to the sending and receiving of SRIO respectively. It is a level interrupt. PS clears the interrupt immediately after receiving the interrupt of PL, releases the sending completion semaphore after receiving the sending interrupt, and releases the corresponding receiving semaphore according to the protocol type after receiving the receiving interrupt.

[0019] Furthermore, the clock reset management module is used to realize the frequency division of the external clock signal, so that the same FMQL platform can have the function of multi-channel SRIO simultaneous communication, and at the same time has the function of resetting the DMA processing module, Message / Nwrite / Nwrite_r / Swirte sending module, Nread sending module, Message / Nwrite / Nwrite_r / Swirte receiving module and Nread receiving module by receiving instructions from the public transaction processing module, so that when SRIO receives erroneous data, the data packet is discarded and restored to normal state.

[0020] Furthermore, the public affairs processing module includes the following functions:

[0021] When sending SRIO, it receives the sending instruction of PS through the low-speed interface GP, and transfers it to the corresponding sending module according to the sending protocol type. If it is the Doorbell protocol, it is directly sent to the SRIO IP core. After receiving the sending completion flag of each sending module, it reports the sending interrupt to the interrupt management;

[0022] When receiving SRIO, after receiving the Doorbell data from the SRIO IP core or the receiving flag from the receiving module, it reports the receiving terminal to the terminal management and updates the receiving instruction. The receiving instruction is actively obtained by the PS through the low-speed interface GP.

[0023] Used to report status information to the low-speed interface GP;

[0024] After receiving the reset command from the GP, it is used to reset the corresponding module for error recovery.

[0025] Furthermore, the data processing unit is responsible for processing Doorbell, Message, Nwrite, Nwrite_r, Swirte, and Nread protocols; when sending, it waits to obtain the sending mutex semaphore, then splits the data packet into 256-byte packets and puts them into the storage module one by one, and sends a sending instruction through the low-speed interface GP, waits for the sending semaphore, releases the sending mutex semaphore, and completes the sending; when receiving, it waits to obtain the corresponding receiving semaphore, obtains the receiving instruction through the low-speed interface GP, obtains data from the storage module through the address information in the receiving instruction, and completes the receiving;

[0026] and / or,

[0027] The data processing unit is also used to monitor the status of data transmission and reception. When an abnormality is found, a reset operation will be sent to the public affairs processing module through the low-speed interface GP to accurately reset one or part of the transceiver modules in the FPGA.

[0028] An SRIO implementation method based on FMQL, based on the above device, the DDR3 space division specifically includes the steps of:

[0029] Nwrite / Nwrite_r use the same address space when communicating with different nodes; Nread uses the same address space when communicating with different nodes; Swrite allocates a total of 32 address spaces according to the different communicating nodes, and can communicate with up to 32 nodes at the same time; Message dynamically uses different Message address spaces according to different Message packets, that is, when the first Message packet is received, the data is placed in the Message packet with sequence number 1. When the Message packets in sequence number 1 are collected and processed by PS, the address space of the Message packet with sequence number 1 is released to store the new Message packet.

[0030] An SRIO implementation method based on FMQL, based on any of the above-mentioned devices, includes the following steps in the sending process:

[0031] S1, start, PS waits to obtain the sending mutex semaphore, PS sets the sending parameters, message type, length and address;

[0032] S2, determine whether it is Nread, if so, PL sends Nread request packet and enters step S12; if not, PS moves the data to be sent to the specified DDR3 space;

[0033] S4, PS sets DMA parameters and starts sending;

[0034] S5, PL removes the data and starts the SRIO sending process;

[0035] S6, PL waits for SRIO to complete sending;

[0036] S7, PL reports the interrupt to PS;

[0037] S8, PL waits for the response packet of Nread;

[0038] S9, PL puts the response packet data into DDR3 space through DMA;

[0039] S10, PL reports the interrupt to PS;

[0040] S11, PS takes data from DDR3;

[0041] S12, PS releases the sending mutex semaphore.

[0042] S13, end.

[0043] An SRIO implementation method based on FMQL, based on any of the above-mentioned devices, comprises the following steps in the receiving process:

[0044] SS1, starts, PL receives the request packet;

[0045] SS2, determine whether it is Nread. If so, PL controls DMA to read DDR3 data according to the request packet information and enters step SS8; if not, further determine whether it is Msg. If it is Msg, PS indexes the Msg flag and enters step SS3; if it is not Msg, PL puts the request packet data into DDR3 space through DMA and enters step SS5;

[0046] SS3, determine whether it is a new large packet, if so, PL stores the data in the new address space, otherwise PL stores the data in the address space of the existing packet;

[0047] SS4, determine whether the entire Msg package is received, if not, end, if yes, go to the next step;

[0048] SS5, PL reports the interruption to PS;

[0049] SS6, PS releases the corresponding receive signal according to the protocol type;

[0050] SS7, PS takes data from DDR3;

[0051] SS8, PL sends Nread response packet;

[0052] SS9, PL reports interruption to PS;

[0053] SS10, end.

[0054] The beneficial effects of the present invention include:

[0055] The present invention does not need to use FIFO for data caching in FPGA, can realize the mixed transmission and reception of doorbell, Message, Nwrite, Nwrite_r, Swrite, and Nread protocols in SRIO, supports simultaneous communication with multiple nodes, has an error recovery mechanism, and has very high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0057] Figure 1 It is a block diagram of the overall implementation of the device according to the embodiment of the present invention;

[0058] Figure 2 A state jump diagram of a DMA processing module of an apparatus according to an embodiment of the present invention;

[0059] Figure 3 The sending process of the method of the embodiment of the present invention;

[0060] Figure 4 This is the receiving process of the method according to the embodiment of the present invention. DETAILED DESCRIPTION

[0061] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0062] The overall implementation block diagram of the device of the present invention is shown in Figure 1. The device includes three parts: PS, PL and DDR3. The PL consists of a control area and a data area. The data area is responsible for processing SRIO bus data and unpacking and assembling data according to the protocol. The control area is responsible for managing the data receiving and sending process, resetting and reporting interrupts, etc. The PS consists of an interaction area and a processing area. The interaction area is responsible for data communication with the PL, including data flow communication, control signal communication and interrupt processing, and the processing area is responsible for processing data of various protocols. DDR3 is used to store SRIO data.

[0063] In the further invention concept, in order to improve the efficiency of DMA data transmission, the DMA processing module adopts a unidirectional design, that is, it can only receive or send data at the same time. Since the Nread protocol request packet is very short, but the response packet is very long, in order to facilitate processing and save FPGA RAM resources, the reception and transmission of the Nread protocol are processed separately, so 4 DMA processing modules are used to process Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving respectively. The DMA processing module is implemented as a state machine, and the state jump diagram is shown in the figure. Figure 2 shown.

[0064] DDR3 space division, address space in each protocol DDR3, taking the receiving address space as an example (the receiving address space and the sending address space only differ in the base address, and the division method is the same), is planned as shown in Table 1:

[0065] Table 1

[0066]

[0067] Among them, Nwrite / Nwrite_r use the same address space and use this space when communicating with different nodes; Nread uses this space when communicating with different nodes; Swrite allocates a total of 32 address spaces according to different communicating nodes and can communicate with up to 32 nodes at the same time; Message dynamically uses different Message address spaces according to different Message packets, that is, when the first Message packet is received, the data is placed in the Message packet with sequence number 1. When the Message packets in sequence number 1 are collected and processed by PS, the address space of the Message packet with sequence number 1 is released to store the new Message packet.

[0068] The clock reset management module of the device of the present invention can realize the frequency division of the external clock signal, so that the same FMQL platform can have the function of multi-channel SRIO simultaneous communication, and at the same time has the function of resetting the DMA processing module, Message / Nwrite / Nwrite_r / Swirte sending module, Nread sending module, Message / Nwrite / Nwrite_r / Swirte receiving module and Nread receiving module by receiving instructions from the public transaction processing module, so that when SRIO receives erroneous data, the data packet is discarded and restored to a normal state.

[0069] The public affairs processing module of the device of the present invention includes the following functions: 1) When sending SRIO, the sending instruction (including the sending protocol type, the sending data length, the sending destination ID, the address space of the DDR3 where the sending data is located, etc.) of the PS is received through the GP and transferred to the corresponding sending module according to the sending protocol type. If it is a Doorbell protocol, it is directly sent to the SRIO IP core. After receiving the sending completion flag of each sending module, the sending interrupt is reported to the interrupt management. 2) When receiving SRIO, after receiving the Doorbell data from the SRIO IP core or the receiving flag from the receiving module, the receiving terminal is reported to the terminal management, and the receiving instruction (including the receiving protocol type, the receiving data length, the receiving source ID, and the address space of the DDR3 where the receiving data is located) is updated. The receiving instruction is actively obtained by the PS through the GP. 3) Report status information such as local ID, LINK status, sending count, and response count to the GP. 4) After receiving the reset instruction from GP (including Message / Nwrite / Nwrite_r / Swirte sending module reset, Nread sending module reset, Message / Nwrite / Nwrite_r / Swirte receiving module reset, Nread receiving module reset, DMA processing module 1 reset, DMA processing module 2 reset, DMA processing module 3 reset, DMA processing module 4 reset), reset the corresponding module for error recovery.

[0070] After receiving the SRIO sending instruction sent by the public transaction processing module, the Message / Nwrite / Nwrite_r / Swirte sending module of the device of the present invention takes out the data to be sent in DDR3 through the DMA processing module, assembles the data according to the protocol type, and sends the data to the SRIO IP core, and returns the sending completion flag to the public transaction processing module after waiting for the sending to be completed.

[0071] After receiving the SRIO sending instruction sent by the public transaction processing module, the Nread sending module of the device of the present invention sends the Nread sending request to the SRIO IP core, waits for the Nread response data of the SRIO IP core, then sends the Nread response data to DDR3 through the DMA processing module, and finally returns the sending completion flag to the public transaction processing module.

[0072] The Message / Nwrite / Nwrite_r / Swirte receiving module of the device of the present invention, after receiving the SRIO data packet sent by the SRIO IP core, unpacks the data if it is an Nwrite / Nwrite_r / Swirte protocol packet, sends the data to DDR3 through the DMA processing module, and sends a receiving mark to the public transaction processing module; if it is a Message packet, the data is sent to the Message packet space corresponding to the DDR3 through the DMA processing module according to the large packet and small packet sequence numbers of the packet, and when the entire Message packet has been completely received, the receiving mark is sent to the public transaction processing module, otherwise it is not sent.

[0073] After receiving the SRIO data packet sent by the SRIO IP core, the Nread receiving module of the device of the present invention takes out the data in the corresponding area in DDR3 through the DMA processing module and sends it to the SRIO IP core if it is an Nread protocol packet.

[0074] The SRIO IP core of the device of the present invention adopts Serial RapaidIO Gen2, which is an IP core used for developing the SRIO bus in FPGA.

[0075] The interrupt management of the device of the present invention is divided into a sending interrupt and a receiving interrupt, which correspond to the sending and receiving of SRIO respectively. It is a level interrupt. The PS clears the interrupt immediately after receiving the PL interrupt, releases the sending completion semaphore after receiving the sending interrupt, and releases the corresponding receiving semaphore (such as the Message receiving semaphore, the Nwrite receiving semaphore, etc.) according to the protocol type after receiving the receiving interrupt.

[0076] The GP and HP of the device of the present invention, in the FMQL platform, GP is a low-speed interface and HP is a high-speed interface, both of which are AXI bus protocols and are responsible for the interaction of PL and PS data.

[0077] The data processing unit of the device of the present invention is responsible for processing Doorbell, Message, Nwrite, Nwrite_r, Swirte, and Nread protocols. When sending, it waits to obtain the sending exclusive semaphore, then splits the data packet into 256-byte packets and puts them into DDR3 one by one, and sends a sending instruction through GP. After waiting for the sending semaphore, it releases the sending exclusive semaphore, and the sending is completed; when receiving, it waits to obtain the corresponding receiving semaphore, obtains the receiving instruction through GP, obtains data from DDR3 through the address information in the receiving instruction, and completes the reception. In addition, the data processing unit will also monitor the status of the receiving and sending data. When an abnormality is found, it will send a reset operation to the public transaction processing module through GP to accurately reset a certain or part of the receiving and sending modules in the FPGA, such as: after the sending operation, if the interrupt report of PL is not received within 50ms, the sending module of the corresponding protocol is reset; when a certain Message packet is received, if the Message packet is not completely received within 1s, the DDR3 space corresponding to the packet is released.

[0078] The present invention also designs a high-reliability and low-resource SRIO implementation method based on FMQL, which is particularly suitable for complex SRIO networking environments with mixed multi-protocols and mixed multi-node transmission and reception, including the transmission process and the reception process, such as Figure 3 and Figure 4 As shown. The sending process includes the following steps:

[0079] S1, start, PS waits to obtain the sending mutex semaphore, PS sets the sending parameters, message type, length, address, etc.;

[0080] S2, determine whether it is Nread, if so, PL sends Nread request packet and enters step S12; if not, PS moves the data to be sent to the specified DDR3 space;

[0081] S4, PS sets DMA parameters and starts sending;

[0082] S5, PL removes the data and starts the SRIO sending process;

[0083] S6, PL waits for SRIO to complete sending;

[0084] S7, PL reports the interrupt to PS;

[0085] S8, PL waits for the response packet of Nread;

[0086] S9, PL puts the response packet data into DDR3 space through DMA;

[0087] S10, PL reports the interrupt to PS;

[0088] S11, PS takes data from DDR3;

[0089] S12, PS releases the sending mutex semaphore.

[0090] S13, end.

[0091] The receiving process includes the following steps:

[0092] SS1, starts, PL receives the request packet;

[0093] SS2, determine whether it is Nread. If so, PL controls DMA to read DDR3 data according to the request packet information and enters step SS8; if not, further determine whether it is Msg. If it is Msg, PS indexes the Msg flag and enters step SS3; if it is not Msg, PL puts the request packet data into DDR3 space through DMA and enters step SS5;

[0094] SS3, determine whether it is a new large packet, if so, PL stores the data in the new address space, otherwise PL stores the data in the address space of the existing packet;

[0095] SS4, determine whether the entire Msg package is received, if not, end, if yes, go to the next step;

[0096] SS5, PL reports the interruption to PS;

[0097] SS6, PS releases the corresponding receive signal according to the protocol type;

[0098] SS7, PS takes data from DDR3;

[0099] SS8, PL sends Nread response packet;

[0100] SS9, PL reports interruption to PS;

[0101] SS10, end.

[0102] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0103] Example 1

[0104] An SRIO implementation device based on FMQL includes an FMQL programmable fusion chip and a storage module. The PL data area of ​​the FMQL programmable fusion chip includes four DMA processing modules. The four DMA processing modules are all unidirectionally designed, that is, they can only receive data or send data at the same time; and the four DMA processing modules are used to process Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving respectively;

[0105] The PL data area of ​​the FMQL programmable fusion chip includes an SRIO IP core, which provides a high-speed physical port to the outside and interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving internally;

[0106] The PS interaction area of ​​the FMQL programmable fusion chip includes interrupt management, low-speed interface GP and high-speed interface HP;

[0107] The PS processing area of ​​the FMQL programmable fusion chip includes a data processing unit, which interacts with the high-speed interface HP and the storage module for data, and interacts with the low-speed interface GP and the interrupt management for control signals;

[0108] The PL control area of ​​the FMQL programmable fusion chip includes a clock reset management module and a public transaction processing module. The clock reset management module interacts with the public transaction processing module for control signals. The clock reset management module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals; the public transaction processing module interacts with the low-speed interface GP and interrupt management for control signals respectively; the public transaction processing module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals;

[0109] The storage module is used to store SRIO data.

[0110] Example 2

[0111] Based on Embodiment 1, the storage module includes a DDR3 storage module.

[0112] Example 3

[0113] On the basis of Embodiment 1, it also includes a Message / Nwrite / Nwrite_r / Swirte sending module, an Nread sending module, a Message / Nwrite / Nwrite_r / Swirte receiving module and an Nread receiving module;

[0114] The Message / Nwrite / Nwrite_r / Swirte sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, takes out the data to be sent from the storage module through the DMA processing module, assembles the data according to the protocol type, and sends the data to the SRIO IP core, and returns the sending completion flag to the public transaction processing module after the sending is completed;

[0115] The Nread sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, sends the Nread sending request to the SRIO IP core, waits for the Nread response data of the SRIO IP core, then sends the Nread response data to DDR3 through the DMA processing module, and finally returns the sending completion flag to the public transaction processing module;

[0116] The Message / Nwrite / Nwrite_r / Swirte receiving module, after receiving the SRIO data packet sent by the SRIO IP core, unpacks the data if it is an Nwrite / Nwrite_r / Swirte protocol packet, sends the data to the storage module through the DMA processing module, and sends a receiving mark to the public transaction processing module; if it is a Message packet, the data is sent to the Message packet space corresponding to the storage module through the DMA processing module according to the large and small packet sequence numbers of the packet, and when the entire Message packet has been completely received, the receiving mark is sent to the public transaction processing module, otherwise it is not sent;

[0117] After receiving the SRIO data packet sent by the SRIO IP core, the Nread receiving module, if it is an Nread protocol packet, takes out the corresponding area data in the storage module through the DMA processing module and sends it to the SRIO IP core.

[0118] Example 4

[0119] On the basis of Example 1, the interrupt management is divided into sending interrupt and receiving interrupt, which correspond to the sending and receiving of SRIO respectively. It is a level interrupt. The PS clears the interrupt immediately after receiving the PL interrupt, releases the sending completion semaphore after receiving the sending interrupt, and releases the corresponding receiving semaphore according to the protocol type after receiving the receiving interrupt.

[0120] Example 5

[0121] On the basis of Example 1, the clock reset management module is used to realize the frequency division of the external clock signal, so that the same FMQL platform can have the function of simultaneous communication of multiple SRIOs, and at the same time has the function of resetting the DMA processing module, Message / Nwrite / Nwrite_r / Swirte sending module, Nread sending module, Message / Nwrite / Nwrite_r / Swirte receiving module and Nread receiving module by receiving instructions from the public transaction processing module, so that when SRIO receives erroneous data, the data packet is discarded and restored to normal state.

[0122] Example 6

[0123] Based on Example 1, the public affairs processing module includes the following functions:

[0124] When sending SRIO, it receives the sending instruction of PS through the low-speed interface GP, and transfers it to the corresponding sending module according to the sending protocol type. If it is the Doorbell protocol, it is directly sent to the SRIO IP core. After receiving the sending completion flag of each sending module, it reports the sending interrupt to the interrupt management;

[0125] When receiving SRIO, after receiving the Doorbell data from the SRIO IP core or the receiving flag from the receiving module, it reports the receiving terminal to the terminal management and updates the receiving instruction. The receiving instruction is actively obtained by the PS through the low-speed interface GP.

[0126] Used to report status information to the low-speed interface GP;

[0127] After receiving the reset command from the GP, it is used to reset the corresponding module for error recovery.

[0128] Example 7

[0129] On the basis of Example 1, the data processing unit is responsible for the processing of Doorbell, Message, Nwrite, Nwrite_r, Swirte, and Nread protocols; when sending, wait for the sending mutex semaphore, then split the data packet into 256-byte packets and put them into the storage module one by one, and send the sending instruction through the low-speed interface GP, wait for the sending semaphore, release the sending mutex semaphore, and complete the sending; when receiving, wait for the corresponding receiving semaphore, obtain the receiving instruction through the low-speed interface GP, obtain the data from the storage module through the address information in the receiving instruction, and complete the receiving;

[0130] and / or,

[0131] The data processing unit is also used to monitor the status of data transmission and reception. When an abnormality is found, a reset operation will be sent to the public affairs processing module through the low-speed interface GP to accurately reset one or part of the transceiver modules in the FPGA.

[0132] Example 8

[0133] An SRIO implementation method based on FMQL, based on the device described in Example 2, wherein the DDR3 space division specifically includes the following steps:

[0134] Nwrite / Nwrite_r use the same address space when communicating with different nodes; Nread uses the same address space when communicating with different nodes; Swrite allocates a total of 32 address spaces according to the different communicating nodes, and can communicate with up to 32 nodes at the same time; Message dynamically uses different Message address spaces according to different Message packets, that is, when the first Message packet is received, the data is placed in the Message packet with sequence number 1. When the Message packets in sequence number 1 are collected and processed by PS, the address space of the Message packet with sequence number 1 is released to store the new Message packet.

[0135] Example 9

[0136] An SRIO implementation method based on FMQL, based on the device described in any one of Embodiments 2 to 7, includes the following steps in the sending process:

[0137] S1, start, PS waits to obtain the sending mutex semaphore, PS sets the sending parameters, message type, length and address;

[0138] S2, determine whether it is Nread, if so, PL sends Nread request packet and enters step S12; if not, PS moves the data to be sent to the specified DDR3 space;

[0139] S4, PS sets DMA parameters and starts sending;

[0140] S5, PL removes the data and starts the SRIO sending process;

[0141] S6, PL waits for SRIO to complete sending;

[0142] S7, PL reports the interrupt to PS;

[0143] S8, PL waits for the response packet of Nread;

[0144] S9, PL puts the response packet data into DDR3 space through DMA;

[0145] S10, PL reports the interrupt to PS;

[0146] S11, PS takes data from DDR3;

[0147] S12, PS releases the sending mutex semaphore.

[0148] S13, end.

[0149] Example 10

[0150] An SRIO implementation method based on FMQL, based on the device according to any one of Embodiments 2 to 7, comprises the following steps in the receiving process:

[0151] SS1, starts, PL receives the request packet;

[0152] SS2, determine whether it is Nread. If so, PL controls DMA to read DDR3 data according to the request packet information and enters step SS8; if not, further determine whether it is Msg. If it is Msg, PS indexes the Msg flag and enters step SS3; if it is not Msg, PL puts the request packet data into DDR3 space through DMA and enters step SS5;

[0153] SS3, determine whether it is a new large packet, if so, PL stores the data in the new address space, otherwise PL stores the data in the address space of the existing packet;

[0154] SS4, determine whether the entire Msg package is received, if not, end, if yes, go to the next step;

[0155] SS5, PL reports the interruption to PS;

[0156] SS6, PS releases the corresponding receive signal according to the protocol type;

[0157] SS7, PS takes data from DDR3;

[0158] SS8, PL sends Nread response packet;

[0159] SS9, PL reports interruption to PS;

[0160] SS10, end.

[0161] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0162] According to one aspect of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above-mentioned various optional implementations.

[0163] As another aspect, the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

[0164] The parts not involved in the present invention are the same as the prior art or can be implemented by using the prior art.

[0165] The above technical solution is only one implementation mode of the present invention. For those skilled in the art, it is easy to make various types of improvements or modifications based on the application methods and principles disclosed in the present invention, and it is not limited to the method described in the above specific implementation mode of the present invention. Therefore, the method described above is only preferred and does not have a restrictive meaning.

[0166] In addition to the above examples, those skilled in the art may obtain other embodiments based on the above disclosure or by using the knowledge or technology in the relevant field to make changes. The features of each embodiment may be interchangeable or replaced. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention and should be within the scope of protection of the claims attached to the present invention.

Claims

1. An SRIO implementation device based on FMQL, comprising an FMQL programmable fusion chip and a storage module, characterized in that: The PL data area of ​​the FMQL programmable fusion chip includes four DMA processing modules, and the four DMA processing modules are all unidirectionally designed, that is, they can only receive data or send data at the same time; and the four DMA processing modules are used to process Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving respectively; The PL data area of ​​the FMQL programmable fusion chip includes an SRIO IP core, which provides a high-speed physical port to the outside and interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving internally; The PS interaction area of ​​the FMQL programmable fusion chip includes interrupt management, low-speed interface GP and high-speed interface HP; The PS processing area of ​​the FMQL programmable fusion chip includes a data processing unit, which interacts with the high-speed interface HP and the storage module for data, and interacts with the low-speed interface GP and the interrupt management for control signals; The PL control area of ​​the FMQL programmable fusion chip includes a clock reset management module and a public transaction processing module. The clock reset management module interacts with the public transaction processing module for control signals. The clock reset management module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals; the public transaction processing module interacts with the low-speed interface GP and interrupt management for control signals respectively; the public transaction processing module interacts with Message / Nwrite / Nwrite_r / Swirte sending, Nread sending, Message / Nwrite / Nwrite_r / Swirte receiving and Nread receiving for control signals; The storage module is used to store SRIO data.

2. The SRIO implementation device based on FMQL according to claim 1, characterized in that: The memory module comprises a DDR3 memory module.

3. The SRIO implementation device based on FMQL according to claim 1, characterized in that: Also includes a Message / Nwrite / Nwrite_r / Swirte sending module, an Nread sending module, a Message / Nwrite / Nwrite_r / Swirte receiving module and an Nread receiving module; The Message / Nwrite / Nwrite_r / Swirte sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, takes out the data to be sent from the storage module through the DMA processing module, assembles the data according to the protocol type, and sends the data to the SRIO IP core, and returns the sending completion flag to the public transaction processing module after the sending is completed; The Nread sending module, after receiving the SRIO sending instruction sent by the public transaction processing module, sends the Nread sending request to the SRIO IP core, waits for the Nread response data of the SRIO IP core, then sends the Nread response data to DDR3 through the DMA processing module, and finally returns the sending completion flag to the public transaction processing module; The Message / Nwrite / Nwrite_r / Swirte receiving module, after receiving the SRIO data packet sent by the SRIO IP core, unpacks the data if it is an Nwrite / Nwrite_r / Swirte protocol packet, sends the data to the storage module through the DMA processing module, and sends a receiving mark to the public transaction processing module; if it is a Message packet, the data is sent to the Message packet space corresponding to the storage module through the DMA processing module according to the large and small packet sequence numbers of the packet, and when the entire Message packet has been completely received, the receiving mark is sent to the public transaction processing module, otherwise it is not sent; After receiving the SRIO data packet sent by the SRIO IP core, the Nread receiving module, if it is an Nread protocol packet, takes out the corresponding area data in the storage module through the DMA processing module and sends it to the SRIO IP core.

4. The SRIO implementation device based on FMQL according to claim 1, characterized in that: The interrupt management is divided into sending interrupt and receiving interrupt, which correspond to the sending and receiving of SRIO respectively. It is a level interrupt. PS clears the interrupt immediately after receiving the PL interrupt, releases the sending completion semaphore after receiving the sending interrupt, and releases the corresponding receiving semaphore according to the protocol type after receiving the receiving interrupt.

5. The FMQL-based SRIO implementation device according to claim 3, characterized in that: The clock reset management module is used to realize the frequency division of the external clock signal, so that the same FMQL platform can have the function of multi-channel SRIO simultaneous communication, and at the same time has the function of resetting the DMA processing module, Message / Nwrite / Nwrite_r / Swirte sending module, Nread sending module, Message / Nwrite / Nwrite_r / Swirte receiving module and Nread receiving module by receiving instructions from the public transaction processing module, so that when SRIO receives erroneous data, the data packet is discarded and restored to normal state.

6. The SRIO implementation device based on FMQL according to claim 1, characterized in that: The public affairs processing module includes the following functions: When sending SRIO, it receives the sending instruction of PS through the low-speed interface GP, and transfers it to the corresponding sending module according to the sending protocol type. If it is the Doorbell protocol, it is directly sent to the SRIO IP core. After receiving the sending completion flag of each sending module, it reports the sending interrupt to the interrupt management; When receiving SRIO, after receiving Doorbell data from the SRIO IP core or receiving the receiving flag from the receiving module, it reports the receiving interrupt to the interrupt management and updates the receiving instruction. The receiving instruction is actively obtained by the PS through the low-speed interface GP. Used to report status information to the low-speed interface GP; After receiving the reset command from the GP, it is used to reset the corresponding module for error recovery.

7. The SRIO implementation device based on FMQL according to claim 1, characterized in that: The data processing unit is used to process Doorbell, Message, Nwrite, Nwrite_r, Swirte, and Nread protocols; when sending, it waits to obtain the sending mutex semaphore, then splits the data packet into 256-byte packets and puts them into the storage module one by one, and sends a sending instruction through the low-speed interface GP, waits for the sending semaphore, releases the sending mutex semaphore, and completes the sending; when receiving, it waits to obtain the corresponding receiving semaphore, obtains the data receiving instruction through the low-speed interface GP, obtains data from the storage module through the address information in the receiving instruction, and completes the receiving; and / or, The data processing unit is also used to monitor the status of receiving and sending data. When an abnormality is found, a reset operation will be sent to the public transaction processing module through the low-speed interface GP to accurately reset one or part of the receiving and sending modules in the FMQL.

8. A SRIO implementation method based on FMQL, characterized in that: Based on the device of claim 2, the DDR3 space division specifically includes the steps of: Nwrite / Nwrite_r use the same address space, and use the address space of 0x1F000000~0x1F3FFFFF when communicating with different nodes; Nread uses the address space of 0x1F400000~0x1F7FFFFF when communicating with different nodes; Swrite allocates a total of 32 address spaces according to different communicating nodes, and can communicate with up to 32 nodes at the same time; Message dynamically uses different Message address spaces according to different Message packets, that is, when the first Message packet is received, the data is placed in the Message packet with sequence number 1. When the Message packets in sequence number 1 are collected and processed by PS, the address space of the Message packet with sequence number 1 is released to store new Message packets.

9. A SRIO implementation method based on FMQL, characterized in that: Based on the device described in any one of claims 2 to 7, the sending process includes the following steps: S1, start, PS waits to obtain the sending mutex semaphore, PS sets the sending parameters, message type, length and address; S2, determine whether it is Nread, if so, PL sends Nread request packet and enters step S12; if not, PS moves the data to be sent to the specified DDR3 space; S4, PS sets DMA parameters and starts sending; S5, PL removes the data and starts the SRIO sending process; S6, PL waits for SRIO to complete sending; S7, PL reports the interrupt to PS; S8, PL waits for the response packet of Nread; S9, PL puts the response packet data into DDR3 space through DMA; S10, PL reports the interrupt to PS; S11, PS takes data from DDR3; S12, PS releases the sending mutex semaphore; S13, end.

10. A SRIO implementation method based on FMQL, characterized in that: The device according to any one of claims 2 to 7 comprises the following steps in the receiving process: SS1, starts, PL receives the request packet; SS2, determine whether it is Nread. If so, PL controls DMA to read DDR3 data according to the request packet information and enters step SS8; if not, further determine whether it is Message. If it is Message, PS indexes the Message flag and enters step SS3; if it is not Message, PL puts the request packet data into DDR3 space through DMA and enters step SS5; SS3, determine whether it is a new large packet, if so, PL stores the data in the new address space, otherwise PL stores the data in the address space of the existing packet; SS4, determine whether the entire message package is received, if not, end, if yes, go to the next step; SS5, PL reports the interruption to PS; SS6, PS releases the corresponding receive signal according to the protocol type; SS7, PS takes data from DDR3; SS8, PL sends Nread response packet; SS9, PL reports interruption to PS; SS10, end.

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