A multi-threshold voltage cell assignment method
By using a method based on cell delay-power ratio and path set constraints, threshold voltage cells are allocated point by point, solving the problem of multi-threshold voltage cell allocation in integrated circuits. This achieves static power consumption reduction and timing optimization, and is suitable for large-scale integrated circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2023-01-03
- Publication Date
- 2026-06-02
AI Technical Summary
In integrated circuits, it is difficult to achieve efficient allocation of multiple threshold voltage units to reduce static power consumption and optimize timing, especially in large-scale integrated circuits, where existing methods struggle to find a balance between optimization time and effectiveness.
By using a method based on cell delay-power ratio and path set constraints, threshold voltage cells are allocated point by point. First, the path with the largest path weight is found, and then the cell with the largest weight in the path is replaced. The path and cell weights are updated until the timing requirements are met. If necessary, the path set is updated to ensure that the timing is convergent.
It significantly reduces static power consumption while meeting frequency requirements and optimizes time complexity, making the algorithm feasible in engineering design. It is suitable for three-threshold expansion, including the allocation of high, medium, and low threshold voltage units.
Smart Images
Figure CN116127890B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of low-power technology in integrated circuit design, and relates to a method for allocating multiple threshold voltage units. Background Technology
[0002] In the development of integrated circuits, power consumption has gradually become a design challenge. To improve the battery life of portable devices, reduce the high packaging difficulty caused by heat dissipation issues, and lower energy consumption costs, low-power design of integrated circuits is receiving increasing attention.
[0003] Integrated circuit power consumption is divided into dynamic power consumption and static power consumption. With advanced manufacturing processes, static power consumption accounts for an increasingly larger proportion. Multi-threshold voltage technology is an effective method to reduce the static power consumption of integrated circuits. High-threshold voltage cells have low static power consumption but are slower, while low-threshold voltage cells have the opposite effect. Therefore, low-threshold voltage cells are used in critical paths to meet timing requirements, while high-threshold voltage cells are used in non-critical paths to reduce static power consumption. However, the current scale of integrated circuits is very large, making it difficult to achieve good multi-threshold voltage allocation results, and requiring optimization in both time and effectiveness. Summary of the Invention
[0004] The purpose of this invention is to provide a method for allocating multiple threshold voltage units to solve the above-mentioned technical problems.
[0005] To solve the above-mentioned technical problems, the specific technical solution of the multi-threshold voltage unit allocation method of the present invention is as follows:
[0006] A multi-threshold voltage cell allocation method, the method being based on cell delay-power ratio and path set constraints, includes the following steps:
[0007] Step 1: Data preparation: Obtain a simplified path set based on the full high threshold circuit, and obtain the unit delay, timing increment / decrement factor, and static power consumption value of the full high / low threshold circuit;
[0008] Step 2: Allocate thresholds based on the path set: In the full-height threshold circuit, allocate thresholds point by point according to the path weight and the unit weight until all paths in the path set meet the timing requirements;
[0009] Step 3: Update the path set; apply the threshold allocation results and perform static time series analysis. If the static time series analysis results do not meet the time series requirements, update the path set and perform the threshold allocation operation based on the path set again until the static time series analysis results meet the time series requirements.
[0010] Furthermore, step 1 includes the following specific steps:
[0011] Step 1.1: Convert the circuit state into the full high threshold voltage (HVT) and the full low threshold voltage (LVT) respectively, and calculate the delay, static power consumption, and timing increment / decrement factor of each unit in each state; the delay is represented by timing arcs;
[0012] Step 1.2: Convert the state of the circuit to full-high threshold voltage to obtain a simplified path set. Find the worst path traversed by each unit and use it as the initial path set.
[0013] Furthermore, step 2 includes the following specific steps:
[0014] Step 2.1: Calculate the path weight based on the unit's delay, timing increment / decrement factor, and path set; Step 2.2: Calculate the unit weight based on the unit's delay, timing increment / decrement factor, static power consumption, and path weight R;
[0015] Step 2.3: Find the path with the largest path weight R;
[0016] Step 2.4: Find the cell with the largest cell weight W in this path;
[0017] Step 2.5: Convert the cell to an LVT and update the associated path weights and cell weights; Step 2.6: If the timing of the path set does not meet the requirements, repeat steps 2.3-2.5 until the circuit timing meets the requirements;
[0018] Step 2.7: Output the unit replacement results.
[0019] Furthermore, step 2.1 includes the following specific steps:
[0020] For a path i, all its units are denoted as set CIP. i The time margin formula is: Where t slack For time margin, t r To determine the required arrival time, t s Let α represent the timing increment / decrement factor of the timing unit, d represent the unit delay, and the timing gain obtained when the path is transformed from full HVT to full LVT be denoted as the repairable time. Then, we can obtain... Where t repairable For repairable time, α L and d L The value corresponding to LVT, α H and d H The path weight formula is as follows, corresponding to the HVT value: The expected path is a full LVT, and the timing must meet the requirements, therefore R... i No greater than 1.
[0021] Furthermore, step 2.2 includes the following specific steps:
[0022] For a given unit j, all the paths it traverses are denoted as the set PTC. j The formula for the unit weight is:
[0023] Where p L and p H These represent the static power consumption when the unit is an LVT and HVT, respectively, and the unit weight is the sum of the weights given to each path it traverses.
[0024] Furthermore, the update method in step 2.5 is to subtract the temporal gain brought about by the replacement from both the numerator and denominator of the path weight formula, and the unit weight changes accordingly due to the change in the path weight value.
[0025] Furthermore, step 3 includes the following specific steps:
[0026] Step 3.1: Apply the output of the "Assign threshold based on path set" process to the static time series analysis. Based on the current results, obtain the sub-path set, which is also the worst path traversed by each unit. Add this set to the original path set, and then execute the "Assign threshold based on path set" process again based on the new path set until the static time series analysis results meet the time series requirements.
[0027] Step 3.2: Output the final result that satisfies the timing sequence.
[0028] The multi-threshold voltage unit allocation method of the present invention has the following advantages:
[0029] 1) The total number of paths is too large. Simplifying the operation of the path set makes the algorithm feasible in terms of time.
[0030] 2) When selecting nodes to replace with LVTs, this invention first finds the path with the highest path weight, and then finds the unit with the highest weight within that path. A higher path weight means a higher proportion of LVTs are needed within that path; prioritizing stricter constraints reduces redundant replacements. The unit with the highest weight in the path has a greater impact on the overall circuit timing, and therefore is replaced first than other units within the same path. Real-time updates of path and unit weights also ensure that the currently replaced unit has the greatest impact on the current timing.
[0031] 3) The simplified path set cannot fully reflect the timing of all paths, so the path set is updated. Updating the path set ensures the convergence of the timing sequence.
[0032] 4) This method can be expanded from a dual-threshold approach to a triple-threshold approach by introducing a standard threshold SVT (delay and power consumption between HVT and LVT). The original calculation of HVT-to-LVT cell weights is replaced by calculating the weights of HVT-to-SVT and SVT-to-LVT separately. A cell is only considered for replacement from SVT to LVT after it has been replaced from HVT to SVT. Furthermore, the initial weight of the cell is equal to the HVT-to-SVT weight, and the weight after replacement with SVT is equal to the SVT-to-LVT weight. Attached Figure Description
[0033] Figure 1 This is a flowchart of the multi-threshold voltage unit allocation method of the present invention. Detailed Implementation
[0034] To better understand the purpose, structure, and function of this invention, a multi-threshold voltage unit allocation method of this invention will be described in further detail below with reference to the accompanying drawings.
[0035] like Figure 1 As shown, the present invention provides a multi-threshold voltage cell allocation method based on cell delay-power ratio and path set constraints, comprising the following steps:
[0036] Step 1: Data Preparation: Obtain a simplified path set based on the full-high threshold circuit, and obtain the cell delay, timing increment / decrement factor, and static power consumption values for the full-high / low threshold circuits. This includes the following steps:
[0037] Step 1.1: Convert the circuit state to full HVT (high threshold voltage) and full LVT (low threshold voltage) respectively, and calculate the delay (in terms of timing arcs), static power consumption, and timing increment / decrement factor of each unit in each state;
[0038] Step 1.2: Transform the circuit state into a fully HVT (High-Voltage Time) state to obtain a simplified path set. The number of paths in a mesh structure is much larger than the number of cells, making a simplified path set necessary to ensure the time feasibility of the method. Obtain the worst path traversed by each cell and use it as the initial path set.
[0039] Step 2: Allocate thresholds based on the path set: In the full-height threshold circuit, thresholds are allocated point-by-point according to the path weight and cell weight until all paths in the path set meet the timing requirements. This includes the following steps:
[0040] Step 2.1: Calculate the path weights based on the cell delay, timing increment / decrement factors, and path set. For a path i, all cells on it are denoted as the set CIP. i The time margin formula is: Where t slack For time margin, tr To determine the required arrival time, t s Let α represent the timing increment / decrement factor of the timing unit, and d represent the unit delay. The timing gain obtained when the path is transformed from full HVT to full LVT is denoted as the recoverable time. We can then obtain... Where t repairable For repairable time, α L and d L The value corresponding to LVT, α H and d H The value corresponding to HVT. The path weight formula is: The expected path is a full LVT, and the timing must meet the requirements, so the result is no greater than 1.
[0041] Step 2.2: Calculate the weight of the cell based on its delay, timing increment / decrement factor, static power consumption, and path weight R. For a cell j, all paths it traverses are denoted as the set PTC. j The formula for unit weight is: Where p L and p H These represent the static power consumption when the cell is an LVT and HVT, respectively. The cell weight is the sum of the weights assigned to each path it traverses;
[0042] Step 2.3: Find the path with the largest path weight R;
[0043] Step 2.4: Find the cell with the largest cell weight W in this path;
[0044] Step 2.5: Transform the cell into an LVT and update the associated path weights and cell weights. The update method involves subtracting the timing gain from the substitution from both the numerator and denominator of the path weight formula. The cell weights then change accordingly based on the changes in the path weight values.
[0045] Step 2.6: If the timing of the path set does not meet the requirements, repeat steps 2.3-2.5 until the circuit timing meets the requirements;
[0046] Step 2.7: Output the unit replacement results.
[0047] Step 3: Update the path set: Apply the threshold allocation results and perform static time series analysis. If the static time series analysis results do not meet the timing requirements, update the path set and perform the threshold allocation operation based on the path set again until the static time series analysis results meet the timing requirements. Specifically, this includes the following steps:
[0048] Step 3.1: Apply the output of the "Assign Thresholds Based on Path Set" process to the static time series analysis. Since the path set is a simplification of the entire path, there may still be paths that do not meet the timing requirements. Based on the current results, obtain a sub-path set (which is also the worst path traversed by each unit), and add this set to the original path set. Then, execute the "Assign Thresholds Based on Path Set" process again based on the new path set until the static time series analysis results meet the timing requirements.
[0049] Step 3.2: Output the final result that satisfies the timing sequence.
[0050] Example:
[0051] The present invention was applied to test a CPU IP based on a 28nm process. The chip has a total of 385,781 standard cells, uses three different threshold voltages, and has a performance requirement of 1GHz. The implementation is based on the Perl scripting language and STA's EDA tools.
[0052] First, data preparation is performed. The circuit is transformed into full HVT, full SVT, and full LVT respectively. In each state, the delay (timing arc), static power consumption, and timing increment / decrement factor of each cell are calculated. When the circuit is in full HVT, the initial path set is obtained, which is the set of the worst timing paths traversed by each cell.
[0053] Then, weights are calculated based on the path set. The initial circuit state is full HVT. Path weights and cell weights are calculated based on the path set and the cell's delay, static power consumption, and timing increment / decrement factors. When calculating path weights, the timing gain is the gain obtained from replacing full HVT with full LVT. When calculating cell weights, the weights for a cell transitioning from HVT to SVT and from SVT to LVT are calculated separately. Because the delay-to-power ratio of transitioning from HVT to SVT is significantly greater than that of transitioning from SVT to LVT, the weight for transitioning from HVT to SVT is significantly greater than the weight for transitioning from SVT to LVT. Therefore, each cell is only considered for transitioning to LVT after it has been transitioned to SVT. Specifically, in the process, if the cell is currently HVT, the cell weight is equal to the weight for transitioning from HVT to SVT; if the cell is currently SVT, the cell weight is equal to the weight for transitioning from SVT to LVT.
[0054] Then, the process iterates based on the weight values. The initial state is all HVTs (High-Voltage Transmissions), and the iteration ends when all paths in the path set satisfy the timing requirements. The worst-performing path (i.e., the one with the largest R) is selected, and the cell with the largest weight is replaced with an SVT (Short-Voltage Transmission) or LVT (Low-Voltage Transmission). After the replacement, the path and cell weights are updated, and the iteration continues until all paths satisfy the timing requirements. Note that the iteration and weight update operations are performed in a Perl script, avoiding frequent timing updates in the STA's EDA tools, thus saving significant time.
[0055] The results of the above traversal (threshold voltage allocation results) are applied to the STA's EDA tool to update the timing. It is then determined whether the STA's timing meets the requirements; if so, it is output as the final result. If the timing does not meet the requirements, the path set is updated. The path set is updated by obtaining the worst timing path traversed by each cell under the current conditions, adding it to the original path set, and then repeating the operations of calculating weights, traversing, and applying to the STA.
[0056] The final results are as follows. The initial static power consumption of the full LVT circuit was 19.7909 mW. After applying the three-threshold voltage distribution using this invention, the LVT ratio of the circuit was 4.95%, the SVT ratio was 29.61%, and the static power consumption was reduced to 1.9289 mW. This invention significantly reduces static power consumption while still meeting the performance requirements at a frequency of 1 GHz. The execution time of the invention is 4.4 hours, which is acceptable for engineering design.
[0057] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.
Claims
1. A method for allocating multi-threshold voltage units, characterized in that, The method is based on the cell delay-power ratio and path set constraints, and includes the following steps: Step 1: Data preparation: Obtain a simplified path set based on the full high threshold circuit, and obtain the unit delay, timing increment / decrement factor, and static power consumption value of the full high / low threshold circuit; Step 2: Allocate thresholds based on the path set: In the full-height threshold circuit, allocate thresholds point by point according to the path weight and the unit weight until all paths in the path set meet the timing requirements; Step 2.1: Calculate the weight of the path based on the unit's delay, timing increment / decrement factor, and path set; For a path i, all its units are denoted as set CIP. i The time margin formula is: , where t slack For time margin, t r To determine the required arrival time, t s Let α represent the timing increment / decrement factor of the timing cell, and d represent the delay of the timing cell. The timing gain obtained when the path transitions from a full-high threshold voltage (HVT) to a full-low threshold voltage (LVT) is denoted as the recoverable time. The result is... , where t repairable For repairable time, α L and d L The value corresponding to LVT, α H and d H The path weight formula is as follows, corresponding to the HVT value: The expected path is that the timing must meet the requirements when using a full low threshold voltage LVT, therefore... Not greater than 1; Step 2.2: Calculate the weight of the unit based on the unit's delay, timing increment / decrement factor, static power consumption, and path weight R; For a given unit j, all the paths it traverses are denoted as the set PTC. j The formula for unit weight is: , where p L and p H These represent the static power consumption when the unit is an LVT and HVT, respectively, and the unit weight is the sum of the weights given to each path it traverses; Step 2.3: Find the path with the largest path weight R; Step 2.4: Find the cell with the largest cell weight W in this path; Step 2.5: Convert the cell to a full low threshold voltage LVT and update the associated path weights and cell weights; Step 2.6: If the timing of the path set does not meet the requirements, repeat steps 2.3-2.5 until the circuit timing meets the requirements; Step 2.7: Output the cell replacement results; Step 3: Update the path set; apply the threshold allocation results and perform static time series analysis. If the static time series analysis results do not meet the time series requirements, update the path set and perform the threshold allocation operation based on the path set again until the static time series analysis results meet the time series requirements.
2. The multi-threshold voltage unit allocation method according to claim 1, characterized in that, Step 1 includes the following specific steps: Step 1.1: Convert the circuit state into full high threshold voltage (HVT) and full low threshold voltage (LVT) respectively, and calculate the delay, static power consumption, and timing increment / decrement factor of each unit in each state; the delay is represented by timing arcs; Step 1.2: Convert the state of the circuit to full-high threshold voltage to obtain a simplified path set. Find the worst path traversed by each unit and use it as the initial path set.
3. The multi-threshold voltage unit allocation method according to claim 1, characterized in that, The update method in step 2.5 is to subtract the temporal gain brought by the replacement from both the numerator and denominator of the path weight formula, and the unit weight changes accordingly due to the change in the path weight value.
4. The multi-threshold voltage unit allocation method according to claim 1, characterized in that, Step 3 includes the following specific steps: Step 3.1: Apply the output of the "Assign threshold based on path set" process to the static time series analysis. Based on the current results, obtain the sub-path set, which is also the worst path traversed by each unit. Add this set to the original path set, and then execute the "Assign threshold based on path set" process again based on the new path set until the static time series analysis results meet the time series requirements. Step 3.2: Output the final result that satisfies the timing sequence.