Clock tree deployment method, device, electronic device and storage medium

Abstract

The embodiments of the present application provide a clock tree placement method, device, electronic device and storage medium, which relate to the field of chips. Among them, the clock tree placement method is applied to the clock tree placement device, and the clock tree placement device is used to place the clock tree unit on the target chip. The target chip includes several clock tree placement points. The method includes: obtaining the voltage drop data of each of the clock tree placement points; obtaining the target clock tree placement point from the several clock tree placement points according to the voltage drop data; and placing the clock tree unit on the target clock tree placement point. Compared with the prior art, the clock tree placement method, device, electronic device and storage medium provided by the embodiments of the present invention have the advantages of reducing the voltage margin of the chip while avoiding affecting the clock tree.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular, embodiments of the present invention relate to a clock tree placement method, device, electronic device, and storage medium. Background Art

[0002] In chip design, power optimization is one of the key factors affecting chip performance and maximum current requirements. Since chip power is related to the square of the chip's operating voltage, improving the chip's operating voltage margin is one of the most critical factors for power optimization in modern advanced chip design.

[0003] In some chips, clock power typically accounts for 30% to 40% of the chip's total power. Therefore, adjusting the chip's operating voltage margin reflects issues in the chip design process, often involving corrections to the chip's voltage drop. Therefore, by correcting the chip's voltage drop, the chip's operating voltage margin can be increased, ultimately optimizing chip performance.

[0004] Figure 1 This section shows some existing chip design flows, where PG (Power Ground) analysis and CTS (Clock Tree Synthesis) are separate flows, and CTS does not use any PG analysis data. This existing technology performs voltage drop analysis after chip design is complete, and corrects for worst-case voltage drops. This approach has the disadvantage of lagging the design process, and the voltage drop correction process may affect the clock tree already completed by CTS.

[0005] Figure 2 Shows some of the chip design processes in the existing technology. Figure 2 In the chip design flow provided, a robust PG grid is created before starting floorplanning and clock tree synthesis. In this part of the existing technology, the voltage drop analysis tool is integrated into the chip design tool to perform voltage drop optimization. Although this solution is better than Figure 1 The chip design process shown in FIG2 is a process of repairing the voltage drop, which may affect the clock tree that has been completed by CTS.

[0006] Therefore, how to avoid affecting the clock tree that has completed CTS when repairing the voltage drop of the chip becomes a problem to be solved. Summary of the Invention

[0007] The purpose of the embodiments of the present invention is to provide a clock tree placement method, device, electronic device, and storage medium, which can reduce the voltage margin of a chip while avoiding affecting the clock tree.

[0008] In a first aspect, an embodiment of the present invention provides a clock tree placement method, which is applied to a clock tree placement device, wherein the clock tree placement device is used to place clock tree units on a target chip, and the target chip includes multiple clock tree placement points. The method includes: obtaining voltage drop data for each of the clock tree placement points; obtaining a target clock tree placement point from the multiple clock tree placement points based on the voltage drop data; and placing the clock tree unit on the target clock tree placement point.

[0009] In some embodiments, obtaining the voltage drop data of each of the clock tree placement points includes: obtaining a sample clock tree unit; placing the sample clock tree unit at the plurality of clock tree placement points; providing a constant power supply voltage for the target chip; providing a constant current for a unit pin of each of the sample clock tree units; obtaining a point voltage on each of the unit pins; and calculating the voltage drop data of each of the clock tree placement points based on the constant power supply voltage and the point voltage.

[0010] In some embodiments, providing a constant current to each unit pin of the sample clock tree unit includes providing an equal constant current to each unit pin. Connecting an equal constant current to each unit pin can facilitate subsequent voltage drop measurement and calculation.

[0011] In some embodiments, obtaining a sample clock tree unit includes obtaining a clock tree unit with the highest rated current among all clock tree units to be deployed on the target chip as the sample clock tree unit. Selecting the clock tree unit with the highest rated current as the sample clock tree unit can reduce the risk of the current applied to the clock tree deployment point exceeding the sample clock tree unit during testing, thereby reducing the risk of damage to the sample clock tree unit during testing. Furthermore, the larger the rated current of the sample clock tree unit, the wider the range of current it can withstand during testing, thereby reducing the requirements for the current source that applies the current during testing.

[0012] In some embodiments, providing a constant current to a cell pin of each sample clock tree unit includes: obtaining a rated current of the sample clock tree unit as a target rated current; and providing a constant current equal to the target rated current to the cell pin of each sample clock tree unit. Providing a constant current equal to the rated voltage to each sample clock tree unit ensures proper operation of the sample clock tree unit and improves the accuracy of the final measurement result.

[0013] In some embodiments, the target chip includes multiple power pins, and providing a constant power voltage to the target chip includes providing equal constant power voltages to the multiple power pins. Connecting equal constant voltages to each power pin facilitates subsequent voltage drop measurement and calculation.

[0014] In some embodiments, obtaining a target clock tree placement point from the plurality of clock tree placement points based on the voltage drop data includes: obtaining a clock tree placement point having a voltage drop data less than a preset voltage drop as the target clock tree placement point. Clock tree placement points having a voltage drop less than a preset voltage drop threshold are selected as target clock tree placement points. The voltage drop of each clock tree placement point is less than the voltage drop threshold, thereby ensuring that the overall voltage drop of the target chip is also small, thereby reducing the overall voltage drop of the target chip.

[0015] In some embodiments, placing the clock tree units at the target clock tree placement points includes placing the clock tree units at the target clock tree placement points in ascending order based on the magnitude of the voltage drop data. Placing the clock tree units at the target clock tree placement points in ascending order based on the magnitude of the voltage drop ensures that the clock tree units are placed at the target clock tree placement points with the smallest voltage drop, thereby further reducing the overall voltage drop of the target chip.

[0016] In some embodiments, obtaining a target clock tree placement point from the plurality of clock tree placement points based on the voltage drop data includes: calculating an equivalent resistance of each of the clock tree placement points based on the voltage drop data; and obtaining a clock tree placement point having an equivalent resistance less than a preset resistance as the target clock tree placement point. Using the equivalent resistance to obtain the target clock tree placement point can prevent the power supply voltage and constant current from affecting the test results during the test.

[0017] In some embodiments, placing the clock tree units at the target clock tree placement points includes placing the clock tree units at the target clock tree placement points in ascending order of equivalent resistance. Placing the clock tree units at the target clock tree placement points in ascending order of equivalent resistance ensures that the clock tree units are placed at the target clock tree placement points with lower equivalent resistance, thereby effectively reducing the overall equivalent resistance of the target chip and thereby reducing the overall voltage drop of the target chip.

[0018] In some embodiments, before placing the clock tree unit at the target clock tree placement point, the method further includes: obtaining a preset clock tree placement point; performing clock tree placement simulation on the target chip based on the preset clock tree placement point, and estimating a first voltage margin based on the simulation results; performing clock tree placement simulation on the target chip based on the target clock tree placement point, and estimating a second voltage margin based on the simulation results; if the second voltage margin is greater than the first voltage margin, executing the step of: placing the clock tree unit at the target clock tree placement point; if the second voltage margin is less than the first voltage margin, using the preset clock tree placement point as the target clock tree placement point, and then executing the step of: placing the clock tree unit at the target clock tree placement point. Simulating the preset clock tree placement point and the target clock tree placement point separately, and obtaining the voltage margins of each placement, thereby selecting the clock tree unit placement method with the smallest voltage margin, further reducing the overall voltage margin of the target chip.

[0019] In a second aspect, an embodiment of the present invention provides a clock tree placement device for placing clock tree units on a target chip, wherein the target chip includes several clock tree placement points. The device includes: a voltage drop data acquisition module, wherein the voltage drop data acquisition module is used to obtain voltage drop data of each of the clock tree placement points; a placement point acquisition module, wherein the placement point acquisition module is used to obtain a target clock tree placement point from the several clock tree placement points based on the voltage drop data; and a clock tree placement module, wherein the clock tree placement module is used to place the clock tree unit on the target clock tree placement point.

[0020] In some embodiments, the device further includes: a sample acquisition module, a voltage source, and a current source; the sample acquisition module is used to acquire a sample clock tree unit; the clock tree placement module is further used to place the sample clock tree unit at the plurality of clock tree placement points; the voltage source is used to provide a constant power supply voltage for the target chip; the current source is used to provide a constant current for the unit pins of each of the sample clock tree units; the voltage drop data acquisition module is used to calculate the voltage drop data of each of the clock tree placement points based on the constant power supply voltage and the point voltage.

[0021] In a third aspect, an embodiment of the present invention provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the clock tree placement method as described above.

[0022] In a fourth aspect, an embodiment of the present invention provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement the aforementioned clock tree placement method.

[0023] In the clock tree placement method, apparatus, electronic device, and storage medium provided by the embodiments of the present invention, before the clock tree synthesis process, an optimal target clock tree placement point is obtained based on voltage drop data of the clock tree placement point, so that clock tree units can be placed at the optimal target clock tree placement point during the clock tree synthesis process. Placing clock tree units at the optimal placement point during the clock tree synthesis process can achieve the effect of reducing the voltage drop of the target chip. The reduction in voltage drop means a reduction in voltage margin, and subsequent voltage drop correction is no longer required, which will not affect the clock tree that has already completed the clock tree synthesis process. Therefore, the technical effect of reducing the voltage margin of the target chip while avoiding affecting the clock tree that has already completed the clock tree synthesis process is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a chip design process in the prior art;

[0026] Figure 2 A schematic diagram of another chip design process in the prior art;

[0027] Figure 3 A schematic diagram of the process of clock tree deployment method provided in the first embodiment of the present invention;

[0028] Figure 4 A schematic diagram of the structure of a target chip in the clock tree placement method provided in the first embodiment of the present invention;

[0029] Figure 5 A schematic diagram of the process of obtaining voltage drop data of each clock tree placement point in the clock tree placement method provided in the first embodiment of the present invention;

[0030] Figure 6 A schematic diagram of the circuit structure of a target chip in the clock tree placement method provided in the first embodiment of the present invention;

[0031] Figure 7A schematic diagram of point voltages on unit pins of some clock tree placement units in the clock tree placement method provided in the first embodiment of the present invention;

[0032] Figure 8 A voltage heat map of point voltages on unit pins of all clock tree placement units in the clock tree placement method provided in the first embodiment of the present invention;

[0033] Figure 9 A two-dimensional representation of a voltage heat map of point voltages on unit pins of all clock tree placement units in the clock tree placement method provided in the first embodiment of the present invention;

[0034] Figure 10 A flowchart of a clock tree deployment method according to a second embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram of the structure of the clock tree deployment device provided in the third embodiment of the present invention;

[0036] Figure 12 This is a structural diagram of an electronic device provided in Example 4 of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0040] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0041] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0042] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0043] A clock tree placement method is provided in a first embodiment of the present invention and is applied to a clock tree placement device. The clock tree placement device is used to place clock tree units on a target chip. The target chip is provided with a plurality of clock tree placement points. The clock tree placement device places clock tree units on the clock tree placement points of the target chip. Figure 3 As shown, the following steps are included:

[0044] Step S101: Obtain voltage drop data of each clock tree placement point.

[0045] In some embodiments of the present invention, Figure 4 The figure shows a schematic diagram of the structure of the target chip, in which the blank areas 401 and 402 are areas where clock trees are not placed, and the grid-shaped area 403 is the area where clock trees are placed. Each grid 404 in the area 403 is a clock tree placement point in the target chip.

[0046] In some embodiments of the present invention, the process of obtaining the voltage drop data of each clock tree placement point is as follows: Figure 5 As shown, the following steps are included:

[0047] Step S201: Acquire a sample clock tree unit.

[0048] Specifically, in the process of placing clock tree units on the target chip, a variety of clock tree units of different types and different current sizes can be placed on the target chip according to the different functional requirements of the target chip. In some embodiments of the present invention, the clock tree unit with the largest rated current among all types of clock tree units placed on the target chip can be selected as the sample clock tree unit. Selecting the clock tree unit with the largest rated current as the sample clock tree unit can reduce the risk of the current applied to the clock tree placement point exceeding the sample clock tree unit during the test process, and reduce the risk of damage to the sample clock tree unit during the test process. In addition, the larger the rated current of the sample clock tree unit, the larger the range of current that can be applied during the test process, which reduces the requirements for the current source that applies the current during the test process. It is understandable that the aforementioned selection of the clock tree unit with the largest rated current as the sample clock tree unit is merely a specific example in this embodiment. In other embodiments of the present invention, other methods may be used, such as selecting the clock tree unit with the smallest rated current as the sample clock tree unit, selecting the clock tree unit with a rated current equal to the average of the rated currents of all clock tree units as the sample clock tree unit, or selecting the clock tree unit with a rated current equal to the median of the rated currents of all clock tree units as the sample clock tree unit.

[0049] Step S202: placing sample clock tree units at a number of clock tree placement points.

[0050] Specifically, in this step, the sample clock tree units are placed on all clock tree placement points, and only one sample clock tree unit is placed on each clock tree placement point.

[0051] Step S203: providing a constant power supply voltage to the target chip.

[0052] Specifically, such as Figure 6 The circuit structure diagram of the target chip is shown in FIG. 401 is the power pin of the target chip. Each target chip can be provided with multiple power pins or a single power pin. The specific configuration can be flexibly made according to the function and requirements of the target chip, such as Figure 6 The target chip includes multiple power pins. In some embodiments of the present invention, Figure 6 As shown, each power pin 401 is provided with a voltage source (ie Figure 6101, 102, 103, and 104), the voltage sources 101, 102, 103, and 104 can all output a constant power supply voltage to the power pin 401. Further, in some embodiments of the present invention, the voltage sources 101, 102, 103, and 104 can output a constant power supply voltage of equal voltage value to the power pin 401. Each power pin 401 is connected to a power supply voltage of equal value, which can be more convenient for the subsequent measurement and calculation of the voltage drop. It is understandable that in some other embodiments of the present invention, multiple power pins 401 can also be connected to the same voltage source, and one voltage source provides a constant power supply voltage to multiple power pins, in which case the power supply voltage values ​​of each power pin are also equal. In addition, in some other embodiments of the present invention, the voltage sources 101, 102, 103, and 104 can also output constant power supply voltages of different voltage values ​​to the power pin 401 respectively, and it is only necessary to ensure that the power supply voltage output by each voltage source does not change over time. It is understandable that due to the existence of errors, it is impossible for a voltage source with a completely constant voltage value to exist in the real world. Therefore, in the actual application of the present invention, a voltage source with a voltage value variation of less than 5% can be used as needed (it can be set according to actual needs, for example, for target chips with higher precision requirements, it can be set to 1% or even lower, for target chips with higher cost requirements, it can be set to 10%, etc.).

[0053] In addition, if Figure 6 In the target chip shown, 301 represents the chip package, 302 represents the redistribution layer, 303 represents the top metal layer, and 304 represents the bottom metal layer. These layers, 301 (the chip package), 302 (the redistribution layer), 303 (the top metal layer), and 304 (the bottom metal layer), are all film layers within the target chip and together constitute specific structures within the target chip, such as the clock tree placement points.

[0054] Step S204: providing a constant current to the unit pins of each sample clock tree unit.

[0055] Specifically, such as Figure 6As shown, 601, 602, 603, and 604 are current pins at the clock tree placement point. When the sample clock tree unit is placed at the clock tree placement point, 601, 602, 603, and 604 can serve as unit pins of the clock tree placement unit. 201, 202, 203, and 204 are current sources that provide constant current to the unit pins of each sample clock tree unit. Furthermore, in some embodiments of the present invention, current sources 201, 202, 203, and 204 can output constant currents of equal current values ​​to unit pins 601, 602, 603, and 604. Connecting equal currents to each unit pin 401 can facilitate subsequent voltage drop measurement and calculation. It is understandable that in some other embodiments of the present invention, multiple unit pins 601, 602, 603, and 604 can be connected to the same current source, and one current source can provide constant current to multiple unit pins. In this case, the current values ​​of each unit pin are also equal. Furthermore, in some other embodiments of the present invention, current sources 201, 202, 203, and 204 may output constant currents having different current values ​​to unit pins 601, 602, 603, and 604, respectively. It is sufficient to ensure that the current output by each current source does not change over time. It is understood that due to the existence of errors, it is impossible for a current source with a completely constant current value to exist in the real world. Therefore, in the actual application of the present invention, a current source with a current value variation of less than 5% (which can be set according to actual needs, for example, 1% or even lower for target chips with higher precision requirements, and 10% for target chips with higher cost requirements, etc.) can be used as needed.

[0056] In some embodiments of the present invention, the current value of the constant current applied to the sample clock tree unit can be set according to the rated current of the sample clock tree unit. That is, the rated current of the sample clock tree unit is obtained as the target rated current; a constant current equal to the target rated current is provided to the unit pin of each sample clock tree unit. Providing a constant current equal to the rated voltage to each sample clock tree unit can ensure the normal operation of the sample clock tree unit and improve the accuracy of the final measurement result. It can be understood that the aforementioned provision of a constant current equal to the target rated current to the unit pin of each sample clock tree unit is only a specific example in some embodiments of the present invention and does not constitute a limitation. In some other embodiments of the present invention, other values ​​such as a constant current less than the target rated current may also be provided to the unit pin of each sample clock tree unit.

[0057] Step S205: obtaining the point voltage on each unit pin.

[0058] In some embodiments of the present invention, the point voltage on each unit pin can be measured separately. Figure 7 The schematic diagram shows the voltage at the cell pins of some clock tree placement cells; Figure 8 The voltage heat map of the point voltage on the cell pins of all clock tree placement cells is shown. Figure 9 Shown is a two-dimensional representation of a voltage heat map of point voltages on cell pins for all clock tree placement cells.

[0059] Step S206: Calculate the voltage drop data of each clock tree placement point based on the constant power supply voltage and the point voltage.

[0060] Specifically, in some embodiments of the present invention, Figure 6 As shown in the figure, when the target chip has multiple voltage sources, since each clock tree placement point is only connected to one voltage source, the voltage difference between the constant power supply voltage of the voltage source connected to the clock tree placement point and the point voltage of the clock tree placement point is calculated, which is the voltage drop of this clock tree placement point. The voltage drops of all clock tree placement points together constitute the voltage drop data in this step.

[0061] Step S102: obtaining a target clock tree placement point from a plurality of clock tree placement points according to the voltage drop data.

[0062] In some embodiments of the present invention, a voltage drop threshold can be preset as needed. In some embodiments, the preset voltage drop is a preset constant, which can be flexibly set according to the voltage drop requirements of the target chip. For example, for a target chip with a high voltage drop requirement, it is necessary to ensure that its voltage drop data is as small as possible. In this case, the preset voltage drop can be set to a smaller voltage drop value constant. Conversely, for a target chip with a lower voltage drop requirement, the preset voltage drop can be set to a larger voltage drop value constant. It can be set according to actual needs, and the clock tree placement point with a voltage drop less than the preset voltage drop threshold is used as the target clock tree placement point, such as Figure 9 101 is the target clock tree placement point. Clock tree placement points with voltage drops below a preset voltage drop threshold are selected as target clock tree placement points. The voltage drop at each clock tree placement point is kept below the voltage drop threshold, ensuring that the overall voltage drop of the target chip is also small, thus reducing the overall voltage drop of the target chip.

[0063] It is understood that the aforementioned use of clock tree deployment points with voltage drops less than a preset voltage drop threshold as target clock tree deployment points is merely an example in some embodiments of the present invention. In other embodiments of the present invention, other methods may be used, such as determining the target clock tree deployment points based on the number of clock tree units to be deployed. For example, the clock tree deployment points may be sorted in ascending order based on their respective voltage drops, and the top N clock tree deployment points may be selected as the target clock tree deployment points, where N is the number of clock tree units to be deployed.

[0064] In some embodiments of the present invention, other methods may also be used, such as calculating the equivalent resistance of each clock tree placement point based on the voltage drop data, specifically, calculating the quotient between the voltage drop and the constant current as the equivalent resistance of the clock tree placement point based on the formula of voltage, current, and resistance, and obtaining the clock tree placement point whose equivalent resistance is less than the preset resistance threshold as the target clock tree placement point. In some embodiments, the preset resistance is a preset constant, which can be flexibly set according to the voltage drop requirements of the target chip. For example, for a target chip with a higher voltage drop requirement, it is necessary to ensure that its voltage drop data is as small as possible. At this time, the preset resistance can be set to a smaller resistance value constant. Conversely, for a target chip with a lower voltage drop requirement, the preset resistance can be set to a larger resistance value constant. It can be set according to actual needs. Using the equivalent resistance to obtain the target clock tree placement point can avoid the influence of the power supply voltage and constant current on the results during the test.

[0065] Step S103: placing a clock tree unit at the target clock tree placement point.

[0066] In some embodiments of the present invention, different placement methods can be used depending on the method used to obtain the target clock tree placement points. For example, for the target clock tree placement points obtained using a preset voltage drop threshold as shown in step S207, clock tree units can be placed on the target clock tree placement points in ascending order based on the voltage drop data of each target clock tree placement point. Placing clock tree units on the target clock tree placement points in ascending order based on voltage drop ensures that clock tree units are placed on target clock tree placement points with the smallest voltage drop, thereby effectively reducing the overall voltage drop of the target chip.

[0067] Furthermore, in some other embodiments of the present invention, for the target clock tree placement points obtained using a preset resistance threshold as illustrated in step S207, clock tree units may be placed at the target clock tree placement points in ascending order of equivalent resistance. Placing clock tree units at the target clock tree placement points in ascending order of equivalent resistance ensures that clock tree units are placed at target clock tree placement points with lower equivalent resistance, thereby effectively reducing the overall equivalent resistance of the target chip and, consequently, the overall voltage drop of the target chip.

[0068] Compared with the prior art, in the clock tree placement method provided in the first embodiment of the present invention, before the clock tree synthesis process, the optimal target clock tree placement point is obtained based on the voltage drop data of the clock tree placement point, so that the clock tree unit can be placed at the optimal target clock tree placement point during the clock tree synthesis process. Placing the clock tree unit at the optimal placement point during the clock tree synthesis process can achieve the effect of reducing the voltage drop of the target chip. The reduction in voltage drop means a reduction in voltage margin. There is no need to subsequently correct the voltage drop, and there is no impact on the clock tree that has already completed the clock tree synthesis process. Therefore, the technical effect of reducing the voltage margin of the target chip while avoiding impact on the clock tree that has already completed the clock tree synthesis process is achieved.

[0069] The second embodiment of the present invention provides a clock tree deployment method, specifically as follows Figure 10 As shown, the following steps are included:

[0070] Step S301: Obtain voltage drop data of each clock tree placement point.

[0071] Step S302: obtaining a target clock tree placement point from a plurality of clock tree placement points according to the voltage drop data.

[0072] Step S303: obtaining preset clock tree placement points, performing clock tree placement simulation on the target chip according to the preset clock tree placement points, and estimating a first voltage margin according to the simulation results.

[0073] Specifically, in some embodiments of the present invention, the preset clock tree placement points are based on the following Figure 1 、 Figure 2 The clock tree placement points are obtained using methods in the prior art, and the effect of clock tree placement on the target chip according to the preset clock tree placement points is simulated using simulation software. The voltage margin of the target chip under this placement method is obtained as a first voltage margin as output by the simulation software. It is understood that in some other embodiments of the present invention, the preset clock tree placement points may also be clock tree placement points determined by chip designers based on experience, or randomly generated clock tree placement points.

[0074] Step S304: performing clock tree placement simulation on the target chip according to the target clock tree placement points, and estimating a second voltage margin according to the simulation results.

[0075] Specifically, in this step, the placement effect of the clock tree on the target chip according to the target clock tree placement point is simulated by simulation software, and the voltage margin of the target chip under this placement method output by the simulation software is obtained as the second voltage margin.

[0076] Step S305: Determine whether the second voltage margin is greater than the first voltage margin; if so, execute step S307; if not, execute step S306.

[0077] Step S306: Using the preset clock tree deployment point as the target clock tree deployment point.

[0078] Step S307: Place the clock tree unit at the target clock tree placement point.

[0079] Compared with the prior art, the clock tree placement method provided in the second embodiment of the present invention simulates the preset clock tree placement points and the target clock tree placement points respectively, and obtains the voltage margin after each placement, thereby selecting the clock tree unit placement method with the smallest voltage margin, further reducing the overall voltage margin of the target chip.

[0080] The third embodiment of the present invention provides a clock tree placement device for placing clock tree units on a target chip. The target chip includes several clock tree placement points, such as Figure 11 As shown, the clock tree deployment device specifically includes:

[0081] Voltage drop data acquisition module 801, voltage drop data acquisition module 801 is used to obtain voltage drop data of each clock tree layout point; layout point acquisition module 802, layout point acquisition module 802 is used to obtain the target clock tree layout point from multiple clock tree layout points based on the voltage drop data; clock tree layout module 803, clock tree layout module 803 is used to layout clock tree units at the target clock tree layout point.

[0082] Compared with the prior art, in the clock tree placement device provided in the third embodiment of the present invention, before the clock tree synthesis process, the voltage drop data acquisition module 801 acquires the voltage drop data of each clock tree placement point. The placement point acquisition module 802 obtains the optimal target clock tree placement point based on the voltage drop data of the clock tree placement point. The clock tree placement module 803 can place clock tree units at the optimal target clock tree placement point during the clock tree synthesis process. Placing clock tree units at the optimal placement point during the clock tree synthesis process can achieve the effect of reducing the voltage drop of the target chip. The reduction in voltage drop means a reduction in voltage margin. There is no need to perform voltage drop correction subsequently, and there is no impact on the clock tree that has completed the clock tree synthesis process. Therefore, the technical effect of reducing the voltage margin of the target chip while avoiding impact on the clock tree that has completed the clock tree synthesis process is achieved.

[0083] In some embodiments of the present invention, Figure 11 As shown, the clock tree placement device also includes: a sample acquisition module 804, a voltage source 805 and a current source 806; the sample acquisition module 804 is used to obtain sample clock tree units; the clock tree placement module 803 is also used to place the sample clock tree units at several clock tree placement points; the voltage source 805 is used to provide a constant power supply voltage for the target chip; the current source 806 is used to provide a constant current to the unit pins of each sample clock tree unit; the voltage drop data acquisition module 801 is used to calculate the voltage drop data of each clock tree placement point based on the constant power supply voltage and the point voltage.

[0084] In addition, in some other embodiments of the present invention, the clock tree placement device may also include other structures such as a simulation module (used to perform clock tree placement simulation on the target chip according to preset clock tree placement points, and estimate the first voltage margin according to the simulation results, and perform clock tree placement simulation on the target chip according to the target clock tree placement points, and estimate the second voltage margin according to the simulation results).

[0085] The fourth embodiment of the present application provides an electronic device, such as Figure 12 As shown, it includes: at least one processor 901; and a memory 902 communicatively connected to the at least one processor 901; wherein the memory 902 stores instructions that can be executed by the at least one processor 901, and the instructions are executed by the at least one processor 901 to enable the at least one processor 901 to execute the clock tree placement method as described above.

[0086] The memory 902 may be a read-only memory 902 (ROM), a random access memory 902 (RAM), or other memory 902. In the embodiment of the present application, the memory 902 is used to store data and various algorithms and commands, such as the algorithm for determining the IO voltage (current) range in the embodiment of the present application, the entire process, and the final result.

[0087] In the embodiments of the present application, the memory 902 may include a physical device for storing information, typically digitizing the information and then storing it in a medium utilizing electrical, magnetic, or optical methods. The memory 902 of this embodiment may further include: devices that store information using electrical energy, such as RAM, ROM, etc.; devices that store information using magnetic energy, such as hard disks, floppy disks, magnetic tapes, magnetic core memories 902, bubble memories 902, and USB flash drives; and devices that store information optically, such as CDs or DVDs. Of course, other types of memory 902 are also available, such as quantum memories 902, graphene memories 902, and so on.

[0088] The processor 901 is configured to read a computer program from the memory 902 and execute the computer program to implement the chip testing method provided in the aforementioned embodiment.

[0089] It should be noted that the processor 901 can be a central processing unit (CPU), and the processor 901 can also be other processors 901, digital signal processors 901 (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 901 can be a microprocessor 901 or the processor 901 can also be any conventional processor 901, etc. The processor 901 can also be an integrated circuit chip with signal processing capabilities. In the implementation process, the various steps of the IO voltage (current) test method of the present application can be completed by the hardware integrated logic circuit in the processor 901 or the instructions in the form of software.

[0090] A fifth embodiment of the present application provides a computer storage medium having a computer program stored thereon. When the computer program is executed by a processor, the clock tree placement method of any of the aforementioned embodiments can be implemented.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a portion of code, and the module, program segment, or a portion of code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0092] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0093] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0094] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0095] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A clock tree deployment method, characterized in that: The method is applied to placing a clock tree unit on a target chip, wherein the target chip includes a plurality of clock tree placement points. The method includes: Obtaining voltage drop data of each clock tree placement point; Obtaining a target clock tree placement point from the plurality of clock tree placement points according to the voltage drop data; Deploying a clock tree unit at the target clock tree deployment point; The obtaining of voltage drop data of each clock tree placement point includes: Get sample clock tree unit; Deploying the sample clock tree units at the plurality of clock tree deployment points; Providing a constant power supply voltage to the target chip; providing a constant current to a unit pin of each of the sample clock tree units; Obtaining the point voltage on each of the unit pins; Voltage drop data of each clock tree placement point is obtained by calculation according to the constant power supply voltage and the point voltage.

2. The method according to claim 1, wherein The step of providing a constant current to a unit pin of each of the sample clock tree units includes: A constant current of equal value is provided to each of the unit pins.

3. The method according to claim 1, wherein The acquiring sample clock tree unit includes: A clock tree unit with the largest rated current among all the clock tree units to be placed on the target chip is obtained as the sample clock tree unit.

4. The method according to claim 3, wherein The step of providing a constant current to a unit pin of each of the sample clock tree units includes: obtaining a rated current of the sample clock tree unit as a target rated current; A constant current having a value equal to the target rated current is provided to the unit pin of each of the sample clock tree units.

5. The method according to claim 1, wherein The target chip includes a plurality of power pins, and providing a constant power supply voltage for the target chip includes: A constant power supply voltage of equal value is provided to the plurality of power supply pins.

6. The method according to claim 1, wherein The acquiring a target clock tree placement point from the plurality of clock tree placement points according to the voltage drop data includes: A clock tree placement point having the voltage drop data smaller than a preset voltage drop is obtained as the target clock tree placement point.

7. The method according to claim 6, wherein The step of placing a clock tree unit at the target clock tree placement point includes: The clock tree units are placed on the target clock tree placement points in order from small to large according to the size of the voltage drop data.

8. The method according to claim 1, wherein The acquiring a target clock tree placement point from the plurality of clock tree placement points according to the voltage drop data includes: Calculate the equivalent resistance of each clock tree placement point according to the voltage drop data; A clock tree placement point having an equivalent resistance smaller than a preset resistance is obtained as the target clock tree placement point.

9. The method according to claim 8, wherein The step of placing a clock tree unit at the target clock tree placement point includes: The clock tree units are placed on the target clock tree placement points in order from small to large according to the size of the equivalent resistance.

10. The method according to claim 1, wherein Before placing the clock tree unit at the target clock tree placement point, the method further includes: Get the preset clock tree deployment point; Performing a clock tree placement simulation on the target chip according to the preset clock tree placement points, and estimating a first voltage margin according to the simulation result; Performing a clock tree placement simulation on the target chip according to the target clock tree placement point, and estimating a second voltage margin according to the simulation result; If the second voltage margin is greater than the first voltage margin, performing the steps of: placing a clock tree unit at the target clock tree placement point; If the second voltage margin is smaller than the first voltage margin, after the preset clock tree placement point is used as the target clock tree placement point, the following steps are performed: placing a clock tree unit on the target clock tree placement point.

11. A clock tree deployment device, characterized in that: The device is used to place a clock tree unit on a target chip, wherein the target chip includes a plurality of clock tree placement points. The device includes: A voltage drop data acquisition module, configured to acquire voltage drop data of each of the clock tree placement points; A placement point acquisition module, configured to acquire a target clock tree placement point from the plurality of clock tree placement points according to the voltage drop data; A clock tree placement module, configured to place a clock tree unit on the target clock tree placement point; The device further comprises: a sample acquisition module, a voltage source and a current source; The sample acquisition module is used to acquire a sample clock tree unit; The clock tree placement module is further configured to place the sample clock tree units at the plurality of clock tree placement points; The voltage source is used to provide a constant power supply voltage for the target chip; The current source is used to provide a constant current to the unit pin of each of the sample clock tree units; The voltage drop data acquisition module is further used to acquire the point voltage on each of the unit pins; and calculate the voltage drop data of each clock tree placement point based on the constant power supply voltage and the point voltage.

12. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the clock tree placement method according to any one of claims 1 to 10.

13. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the clock tree placement method according to any one of claims 1 to 10 can be implemented.

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