Method and apparatus for power analysis of integrated circuit chip designs

Abstract

A power consumption analysis method and device for the design of an integrated circuit chip, a power integrity design method of the integrated circuit chip, an electronic device, and a storage medium. The power consumption analysis method comprises: performing a mapping operation on a register transfer level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transfer level simulation waveform file; performing a power consumption analysis operation on the integrated circuit chip according to the gate level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing a current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip. The power consumption analysis method can obtain the power consumption and the current characteristic of the integrated circuit chip at an early stage of the design process of the integrated circuit chip, which helps to reduce the power consumption of the integrated circuit chip at an early stage, solve the voltage drop problem of the integrated circuit chip, optimize chip design, and reduce design cost.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a power consumption analysis method and apparatus for designing integrated circuit chips, a power integrity design method for integrated circuit chips, electronic devices, and non-transitory computer-readable storage media. Background Technology

[0002] With the continuous upgrading of semiconductor technology, the design scale of high-performance chips such as central processing units (CPUs) and graphics processing units (GPUs) is constantly increasing, the number of transistors on a unit area of ​​the chip is increasing, and the complexity of chip design is also increasing exponentially.

[0003] As chip size and integration density increase, chip power consumption also rises. Excessive power consumption not only puts enormous strain on the power supply network but also causes voltage drop (IR Drop) issues during chip operation. IR Drop problems can lead to insufficient operating voltage, preventing logic gates from toggling, or can limit clock frequency, severely impacting chip performance. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a power consumption analysis method for the design of an integrated circuit chip. The power consumption analysis method includes: performing a mapping operation on a register-transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file; performing a power consumption analysis operation on the integrated circuit chip based on the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0005] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the step of mapping the register transfer level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register transfer level simulation waveform file includes: mapping the register transfer level of the integrated circuit chip to the corresponding gate-level netlist according to the naming mapping file, thereby obtaining the gate-level netlist waveform file corresponding to the register transfer level simulation waveform file.

[0006] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the step of performing power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip includes: performing the power consumption analysis operation based on the obtained gate-level netlist waveform file using a power consumption analysis tool to obtain the time-based power consumption waveform file of the integrated circuit chip;

[0007] The step of obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip includes: obtaining a piecewise linear current file representing the current characteristics of the integrated circuit chip based on the time-based power consumption waveform file and the voltage domain arrangement of the integrated circuit chip.

[0008] For example, in at least one embodiment of the power consumption analysis method provided in this disclosure, the step of performing the power consumption analysis operation on the obtained gate-level netlist waveform file using a power consumption analysis tool to obtain a time-based power consumption waveform file of the integrated circuit chip includes: obtaining a power consumption analysis input file set including the gate-level netlist waveform file; and performing the power consumption analysis operation on the integrated circuit chip using a power consumption analysis tool based on the power consumption analysis input file set to generate the time-based power consumption waveform file of the integrated circuit chip.

[0009] For example, at least one embodiment of the power consumption analysis method provided in this disclosure further includes: setting a sampling time interval according to the clock of the gate-level netlist waveform file; and generating a time-based power consumption waveform file according to the sampling time interval.

[0010] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the power consumption analysis input file set further includes standard delay format files, library files, data files, and script files.

[0011] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the integrated circuit chip includes multiple voltage domains. The step of obtaining a piecewise linear current file representing the current characteristics of the integrated circuit chip based on the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip includes: obtaining the operating voltage of each voltage domain and multiple time-based power consumption waveform files; and for each voltage domain, obtaining multiple piecewise linear current files for the multiple voltage domains based on the multiple time-based power consumption waveform files.

[0012] For example, at least one embodiment of the power consumption analysis method provided in this disclosure further includes: selecting multiple operating conditions of the integrated circuit chip and obtaining time-based power consumption waveform files corresponding to the multiple operating conditions; and obtaining multiple current piecewise linear files for the multiple voltage domains based on the time-based power consumption waveform files corresponding to the multiple operating conditions.

[0013] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the plurality of operating conditions include the best case, the normal case, and the worst case.

[0014] For example, in the power consumption analysis method provided in at least one embodiment of this disclosure, the integrated circuit chip includes multiple modules, and the power consumption analysis method further includes: integrating multiple current piecewise linear files of the multiple voltage domains to obtain current piecewise linear files of the multiple modules; and integrating the current piecewise linear files of the multiple modules to obtain current piecewise linear files of the entire integrated circuit chip.

[0015] At least one embodiment of this disclosure also provides a design method for the power integrity of an integrated circuit chip, the design method comprising: obtaining a current characteristic file of the integrated circuit chip according to a power consumption analysis method provided in at least one embodiment of this disclosure; and adjusting or designing a power module for the integrated circuit chip according to the current characteristic file of the integrated circuit chip.

[0016] For example, in a design method provided in at least one embodiment of this disclosure, the power module includes a power supply and a voltage regulator module.

[0017] At least one embodiment of this disclosure also provides a power consumption analysis device for the design of an integrated circuit chip. The power consumption analysis device includes: a mapping module configured to perform a mapping operation on a register-transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file; a power consumption analysis module configured to perform a power consumption analysis operation on the integrated circuit chip based on the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and a current characteristic acquisition module configured to obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0018] At least one embodiment of this disclosure also provides an electronic device, including a memory that non-transitoryly stores computer-executable instructions; and a processor configured to run the computer-executable instructions, wherein the computer-executable instructions are executed by the processor to implement the power consumption analysis method or the design method described in any embodiment of this disclosure.

[0019] At least one embodiment of this disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the power consumption analysis method or the design method according to any embodiment of this disclosure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A flowchart illustrating a power consumption analysis method for designing integrated circuit chips, provided in at least one embodiment of this disclosure, is shown.

[0022] Figure 2 A schematic diagram of a mapping operation provided in at least one embodiment of this disclosure is shown;

[0023] Figure 3 A flowchart illustrating a power consumption analysis method for designing integrated circuit chips according to another embodiment of this disclosure is shown.

[0024] Figure 4 A schematic flowchart illustrating a power integrity design method for an integrated circuit chip according to at least one embodiment of the present disclosure is shown.

[0025] Figure 5 A schematic block diagram of a power consumption analysis device for designing integrated circuit chips, provided for at least one embodiment of this disclosure;

[0026] Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0027] Figure 7 This is a schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numerals in each drawing.

[0031] Voltage drop (IR drop) refers to the voltage decrease caused by line resistance on the power supply and ground lines in an integrated circuit. Voltage drop includes static voltage drop and dynamic voltage drop. Static voltage drop is mainly caused by voltage division in the metal interconnects of the power network. The metal interconnects themselves have high resistance, and current flowing through them generates a voltage drop. Dynamic voltage drop refers to the voltage drop caused by current fluctuations during circuit switching, typically occurring at the clock edge. Clock edge transitions not only cause numerous transistors to turn on and off in the circuit but also cause transitions in combinational logic circuits, often resulting in a large current flowing across the chip in a short period. This instantaneous large current causes the voltage drop. The more transistors switching simultaneously, the more likely dynamic voltage drop will be triggered.

[0032] Regarding static voltage drop, as semiconductor technology continues to evolve, the width of metal interconnects is becoming narrower, and the resistance of the interconnects is constantly increasing. Since the power network is a global network with a relatively long average length, if a device is far from the power supply point, the equivalent resistance of its interconnects will inevitably be relatively large. Consequently, the further a device is from the power supply point, the lower the supply voltage it can obtain. In other words, remote areas of the chip may face insufficient operating voltage, leading to a decrease in the switching speed of logic gates in that area, or, in more severe cases, the logic gates may fail to switch normally.

[0033] Regarding dynamic voltage drop, since the current of each logic gate cell causes varying degrees of voltage drop to other logic gate cells, when a large number of logic gate cells connected to the metal interconnects flip simultaneously, the chip will generate a large current in a short period of time. This excessive instantaneous current will lead to a large voltage drop, causing the chip to malfunction. In this situation, although the chip can be restored to normal operation by reducing the clock frequency, this comes at the cost of degraded chip performance and increased time costs.

[0034] The voltage drop problem mentioned above can currently be solved by methods such as reducing the load, redesigning the chip's power network, or adding a voltage regulator module.

[0035] Power network design refers to reserving a margin within a certain range (e.g., 3%–5%) for voltage drops, such as providing sufficient routing resources when planning the power supply. However, the degree of power network design is often difficult to assess. If the reserved margin is too small, the actual voltage drop will exceed a certain range, and the chip will not function properly. If the reserved margin is too large, it may occupy routing resources, forcing an increase in chip area, which will indirectly affect the chip cost.

[0036] Another common approach is to incorporate a voltage regulator module into the chip's power system. This involves adding a voltage regulator during the chip design phase to ensure voltage stability and meet voltage drop limitations. For this, during Electronic Design Automation (EDA) simulation, a Chip Power Model (CPM) is obtained from the post-simulation waveforms of the entire chip. This CPM model is then used to verify whether the voltage regulator module can withstand power consumption variations, and subsequently, voltage drop (IR Drop) analysis is performed based on the CPM model. Therefore, evaluating chip power consumption is a crucial step in chip design.

[0037] Currently, using tools such as voltage drop analysis to generate chip power consumption models requires inputting the waveforms from the post-simulation, that is, obtaining the simulation waveforms with correct timing after placement and routing (P&R) is completed.

[0038] However, generating a complete chip power consumption model is not only a significant challenge for the project but also offers limited assistance to chip design. On one hand, due to the large scale and complexity of high-performance chips such as the Central Processing Unit (CPU) and Graphics Processing Unit (GPU), directly obtaining a complete chip power consumption model using voltage drop analysis tools is extremely difficult, requiring substantial investment of manpower, resources, and time. On the other hand, the formation of post-simulation waveforms signifies that the chip design is nearing completion. Obtaining a chip power consumption model at this stage offers little help in addressing voltage drop issues, as tape-out is imminent, meaning the internal design is largely finished and mass production is imminent. Designing power consumption and external circuitry at this point would waste considerable time, or require redesigning due to chip-external circuitry mismatches, leading to excessively high design costs. Therefore, it is desirable to incorporate power consumption reduction into the chip project design process as early as possible.

[0039] Since chip power consumption models can help reduce system-level power consumption, obtaining a chip power consumption model as early as possible can effectively reduce power budgets, avoid the cost waste of redesign, and also facilitate voltage drop analysis, guiding external power supply design. How to obtain chip power consumption models early in integrated circuit chip projects has become a pressing issue.

[0040] At least one embodiment of this disclosure provides a power consumption analysis method for the design of integrated circuit chips. The method includes: performing a mapping operation on a register-transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file; performing a power consumption analysis operation on the integrated circuit chip based on the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0041] At least one embodiment of this disclosure provides a power consumption analysis apparatus for designing integrated circuit chips. The apparatus includes a mapping module, a power consumption analysis module, and a current characteristic acquisition module. The mapping module is configured to perform a mapping operation on a register-transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file. The power consumption analysis module is configured to perform power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip. The current characteristic acquisition module is configured to obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0042] The power consumption analysis method and power consumption analysis apparatus for integrated circuit chip design provided in at least one embodiment of this disclosure can obtain the power consumption and current characteristics of the integrated circuit chip in the early stage of the integrated circuit chip design process. In addition, in at least one embodiment, the current characteristics of each module of the integrated circuit chip can be obtained, thereby helping to reduce the power consumption of the integrated circuit chip at an earlier stage, helping to solve the voltage drop problem of the integrated circuit chip, optimizing the chip design, and reducing the design cost.

[0043] At least one embodiment of this disclosure also provides a power integrity design method for an integrated circuit chip, the design method comprising: obtaining a power consumption waveform file of the integrated circuit chip according to the power consumption analysis method described above; and adjusting or designing a power supply module for the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip.

[0044] The power integrity design method for integrated circuit chips provided in at least one embodiment of this disclosure can obtain the power consumption and current characteristics of integrated circuit chips in the early stages of the integrated circuit chip design process, assist in the design of power integrity of integrated circuit chips, guide the design of external circuits of chips, rationally plan resource allocation, prevent over-design of circuits, and effectively shorten the design cycle, improve design efficiency, and save design costs.

[0045] Simulation and verification are also important steps in the design process of integrated circuits, and are an essential part of checking whether the designed circuit meets the requirements.

[0046] Integrated circuit design involves two processes: pre-simulation and post-simulation. Pre-simulation, also known as functional simulation, is performed at the Register Transfer Level (RTL). RTL simulation is based on RTL files and tests the logic function to verify the correctness of the circuit's logic relationships. This simulation is relatively fast. Post-simulation, also known as timing simulation, is performed on the Gate-level Netlist. It takes into account the circuit's gate delay parameters and clock delays. The simulation results can determine the correctness of the timing sequence and directly affect the accuracy of power consumption assessment and voltage drop analysis.

[0047] In one example, integrated circuit design can also include post-synthesis simulation, meaning that post-synthesis simulation can be performed between pre-simulation and post-simulation. Post-synthesis simulation involves annotating a standard delay file into the synthesis simulation model to estimate the impact of gate delays on the circuit. In this example, post-simulation mainly refers to simulating the netlist after placement and routing, which more closely resembles the actual operation of real circuit devices.

[0048] As mentioned earlier, power consumption analysis in integrated circuits primarily utilizes post-simulation waveforms from the later stages of design to generate a power consumption model for the entire chip, thereby analyzing the power consumption at the package level or system level. Since post-simulation is a simulation of the gate-level netlist, it requires considering the interconnections between various circuit units and circuit delays before simulation. Therefore, although the simulation results obtained from post-simulation are closer to real-world applications, the post-simulation cycle is very long and requires significant hardware resources and time. This is especially true in very large-scale integrated circuits, such as CPU (Central Processing Unit) or GPU (Graphics Processing Unit) chips, where designers find it difficult to perform simulation verification of the entire circuit under various modes. Furthermore, in actual chip design, completing accurate power consumption analysis usually occurs late, potentially delaying the design schedule and negatively impacting the time cost and efficiency of chip design.

[0049] In comparison, pre-simulation takes significantly less time. Therefore, the power consumption analysis method proposed in at least one embodiment of this disclosure can obtain post-simulation waveforms from pre-simulation waveforms early in the chip design process. That is, the simulation waveform of the gate-level netlist is obtained based on the simulation waveform of the pre-simulation, thereby obtaining the current characteristics of the chip. This allows for earlier evaluation of power consumption, enabling power consumption analysis to be performed synchronously with automatic placement and routing in the project, greatly improving the speed of power consumption analysis and playing a key role in reducing circuit power consumption. Furthermore, the obtained chip current characteristic file can also be used for subsequent chip analysis and verification, helping to analyze and improve voltage drop issues, and helping to guide the design of power networks and power supplies. This helps to better adapt to design changes and improve design efficiency.

[0050] Figure 1 A flowchart illustrating a power consumption analysis method for integrated circuit chip design provided in at least one embodiment of this disclosure is shown. Figure 1 As shown, the power consumption analysis method provided in at least one embodiment of this disclosure includes steps S100 to S300.

[0051] Step S100: Perform a mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register transfer level simulation waveform file.

[0052] Step S200: Perform power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip.

[0053] Step S300: Obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0054] For example, the integrated circuit chip can be a large-scale integrated circuit or a very large-scale integrated circuit, such as a high-performance chip like a central processing unit (CPU) or a graphics processing unit (GPU).

[0055] For example, step S100, which involves mapping the register-transfer-level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register-transfer-level simulation waveform file, can be performed early in the chip design project, thereby enabling the gate-level netlist waveform file corresponding to the register-transfer-level simulation waveform file to be obtained earlier.

[0056] In embodiments of this disclosure, the early stage of a project refers to the phase prior to digital back-end design, such as layout and routing, for example, the synthesis phase.

[0057] In integrated circuit design, digital front-end design starts with the design architecture and ends with generating a netlist suitable for placement and routing. Digital back-end design, on the other hand, starts with placement and routing and ends with generating files suitable for tape-out. In other words, the generated gate-level netlist can be used as a dividing line: before that is front-end design, and after that is back-end design. In the back-end design process, the gate-level netlist is further transformed into a physical layout. The gate-level netlist can be obtained through synthesis.

[0058] Synthesis mainly consists of three stages: translation, mapping, and optimization. For example, synthesis tools can first convert the Hardware Description Language (HDL) description into a process-independent RTL (Register Transfer Level) netlist (RTL modules in the netlist are interconnected by wires). Then, based on the specific process library, the RTL-level netlist is mapped onto the process library to become a gate-level netlist. Finally, the gate-level netlist is optimized according to the constraints imposed by the designer, such as delay and area.

[0059] Synthesis can be categorized into logic synthesis, RTL synthesis, and behavioral synthesis based on different levels of abstraction. Logic synthesis refers to the process of mapping Register-Transfer Level (RTL) to a gate-level netlist. In other words, in logic synthesis, the design is described as a Boolean equation, and basic units such as flip-flops and latches are expressed using instantiation, such as instances.

[0060] In at least one embodiment of this disclosure, step S100, mapping the register-transfer level simulation waveform file of the integrated circuit chip, refers to mapping the register-transfer level to a gate-level netlist, thereby obtaining a waveform file of the gate-level netlist that can be used for power consumption analysis. Here, the simulation waveform file refers to the waveform file recorded after simulation, which can be used for research or analysis in subsequent design processes. The format of the simulation waveform file can be general, such as a Fast Signal Database (FSDB) file or a Value Change Dump (VCD) file, or it can be non-general. The format of the simulation waveform file used can be selected according to the actual situation, and the embodiments of this disclosure do not limit this.

[0061] Figure 2 A schematic diagram of a mapping operation provided by at least one embodiment of this disclosure is shown. For example... Figure 2 As shown, the Register Transfer Level (RTL) netlist is converted into a gate-level netlist through mapping operations. Each register has a corresponding point in the netlist, and both the register and its state can be mapped to the gate-level netlist. Here, the mapped state means that the register is updated once every time the clock changes, defining the state of the chip. After the mapping operation, the gate-level netlist also has the corresponding state, meaning that the circuitry of the gate-level netlist will also be updated accordingly to correspond with the Register Transfer Level.

[0062] For example, in at least one embodiment of this disclosure, the mapping operation refers to selecting cells that meet the constraints from a technology library and converting a register-transfer level into a gate-level netlist. The technology library provides all the information about the standard logic cells required for the conversion; for example, the technology library may contain information such as the logical function, cell area, and timing relationships of standard logic cells under specific process conditions. For example, the mapping operation can be implemented using existing tools or written scripts, and the embodiments of this disclosure do not limit this.

[0063] Figure 3 A flowchart illustrating a power consumption analysis method for the design of an integrated circuit chip, provided in another embodiment of this disclosure, is shown.

[0064] For example, in at least one example of the embodiments of this disclosure, the above step S100, namely, mapping the register-transfer level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file, can be specifically achieved through... Figure 3 Step S110 is implemented as follows: the register transfer stage of the integrated circuit chip is mapped to the corresponding gate-level netlist according to the naming mapping file, and the gate-level netlist waveform file of the corresponding register transfer stage simulation waveform file is obtained.

[0065] As integrated circuit chip design becomes increasingly complex, hierarchical design has emerged. Hierarchical design refers to dividing an integrated circuit chip into multiple modules, then designing and developing these modules in parallel, and finally performing synthesis, placement, and routing together, which can save design time and costs. Hierarchical design includes, for example, top-level design and sub-top-level design. There is usually only one top-level design, but there may be multiple sub-top-level designs, and even deeper sub-top-level designs.

[0066] During the synthesis phase of an integrated circuit chip, the hierarchical structure of the integrated circuit may change. For example, the circuit may be re-partitioned according to specific circuit requirements, thereby changing the circuit's hierarchical structure from the first level to the second level. At this time, the naming of the register-transfer level may change with the change in the hierarchical structure. Therefore, it is necessary to find the correspondence between the register-transfer level and the gate-level netlist through a naming mapping file.

[0067] In this example, a named mapping file refers to a file containing the corresponding mapping relationships between register-transfer level and gate-level netlists. For example, it could be a file containing the naming and location mapping relationships of different components of an integrated circuit chip. The named mapping file can, for example, record the conversion process from register-transfer level to gate-level netlist by synthesis tools, and thus can be used to find and design the corresponding points between the register-transfer level and the gate-level netlist.

[0068] For example, the naming mapping file can be a Setup Verification Format (SVF) file or a file containing a table of the above mapping relationships. The embodiments of this disclosure do not limit the format and type of the naming mapping file.

[0069] For example, in at least one example of the embodiments of this disclosure, the above step S100, which is to perform a mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file of the corresponding register transfer level simulation waveform file, can also be implemented as follows: after the hierarchical structure of the integrated circuit chip is changed, a mapping operation is performed on the register transfer level simulation waveform file obtained after adjusting the hierarchical structure according to the naming mapping file to obtain the gate-level netlist waveform file of the corresponding register transfer level simulation waveform file.

[0070] For example, in a hierarchical design where an integrated circuit chip is divided into multiple modules, to obtain the optimal circuit, it may be necessary to modify the hierarchical structure of the circuit again (or multiple times) so that each partition, each module / instance, and the overall synthesis structure of the circuit can meet the expected goals. For instance, in the logic synthesis stage of the front-end design, the register transfer stage simulation waveform files are re-grouped (i.e., re-partitioned) according to the specific circumstances of the placement and routing process of the back-end design, and a new register transfer stage is generated. At this time, the hierarchical structure of the new register transfer stage is different from the hierarchical structure before the re-partitioning.

[0071] In this example, since the hierarchical structure of the register-transfer stage has been modified, the simulation waveform of the register-transfer stage before repartitioning can no longer be used directly. Therefore, the register-transfer stage with the changed hierarchical structure can be re-simulated to obtain a new register-transfer stage simulation waveform file. Alternatively, other methods can be used, such as repartitioning the register-transfer stage waveform file and integrating it to obtain a register-transfer stage simulation waveform file with the adjusted hierarchical structure. Then, the register-transfer stage simulation waveform file can be mapped according to the naming mapping file to obtain the gate-level netlist waveform file required for power consumption analysis.

[0072] In the power analysis method provided in at least one embodiment of this disclosure, the gate-level netlist waveform file corresponding to the register transfer level simulation waveform file can be directly obtained through mapping operations without simulating the netlist again (the simulation of larger integrated circuit chips takes more time). The gate-level netlist waveform file can be directly used for power analysis operations, thereby enabling power evaluation in the early stages of the project, saving a lot of time and shortening the project cycle of chip design.

[0073] For example, in at least one example of the embodiments of this disclosure, the above step S200, namely, performing power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip, can be specifically achieved through... Figure 3 Step S210 is implemented as follows: using a power analysis tool, a power analysis operation is performed based on the obtained gate-level netlist waveform file to obtain a time-based power waveform file of the integrated circuit chip.

[0074] Because the power consumption of an integrated circuit chip varies depending on its function during operation, the dynamic current distribution of the integrated circuit chip differs in different states. When performing power consumption analysis, the time periods during which the devices on the integrated circuit chip experience high switching frequencies can be captured; for example, waveforms within N system clock cycles can be captured, thus obtaining a time-based power consumption waveform file.

[0075] For example, the power analysis tool in this disclosure can be an existing power analysis tool, or it can be a power analysis tool that may be developed in the future. The embodiments of this disclosure do not limit this.

[0076] In this example, for instance, using a power analysis tool to perform power analysis based on the obtained gate-level netlist waveform file to obtain a time-based power waveform file of the integrated circuit chip, the process may include: acquiring a set of power analysis input files including the gate-level netlist waveform file; and using a power analysis tool to perform power analysis on the integrated circuit chip based on the set of power analysis input files to generate a time-based power waveform file of the integrated circuit chip.

[0077] In embodiments of this disclosure, the power analysis input file set refers to the set of input files required for power analysis operations. For example, the power analysis input file set includes the gate-level netlist waveform file obtained after the mapping operation described above.

[0078] For example, in at least one embodiment of this disclosure, the power consumption analysis input file set also includes Standard Delay Format (SDF) files, library files, data files, and script files.

[0079] For example, the standard delay file in the power analysis input file set is used to back-annotate to the integrated simulation model to estimate the impact of gate delay on the circuit. The gate-level netlist waveform file obtained after adding gate delay can be used for power analysis.

[0080] For example, standard delay files include timing information for standard cells in the design. It should be noted that the delays here only include the delays of the standard cells and not the delays of wiring, that is, clock delays are not included. Therefore, it does not require as much time as post-simulation (e.g., where the circuit needs to undergo multiple toggles to stabilize).

[0081] For example, in addition to standard delay files, power analysis operations require other configuration files, such as library files and other auxiliary data files or script files, etc. The embodiments of this disclosure do not limit this.

[0082] In this example, for instance, by using a power analysis tool to perform power analysis based on the obtained gate-level netlist waveform file to obtain a time-based power waveform file of the integrated circuit chip, it may also include: setting the sampling time interval according to the clock of the gate-level netlist waveform file; and generating a time-based power waveform file based on the sampling time interval.

[0083] For example, the sampling time for power consumption analysis can be extracted based on the operating clock of the integrated circuit chip. For example, the time period during which the device on the integrated circuit chip is in high-frequency switching can be extracted. For example, in one example, the waveform within N system clock cycles can be extracted, or in another example, the waveform within a certain period of time can be extracted, such as the waveform within 100 milliseconds (ms).

[0084] For example, the sampling time interval can be set according to the clock of the gate-level netlist waveform file. This can be done by directly setting the sampling time interval, for example, setting it to 100 microseconds (µs), or by setting the number of sampling points within the above sampling time, for example, setting 1000 sampling points. The embodiments of this disclosure are not limited in this respect.

[0085] For example Figure 1 The step S300 shown is to obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip. The power consumption waveform file can be a power consumption waveform file obtained by taking the average power consumption, or it can be the time-based power consumption waveform file mentioned above.

[0086] For example, in at least one embodiment of this disclosure, step S300 above, namely obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip, can be specifically achieved through... Figure 3 Step S310 is implemented as follows: Based on the time-based power consumption waveform file and the voltage domain arrangement of the integrated circuit chip, a piecewise linear current file representing the current characteristics of the integrated circuit chip is obtained.

[0087] Because power supply design often focuses on the current characteristics of integrated circuit chips, even at the same power consumption, the current requirements differ across different voltage domains, and also between different ports. For example, in a multi-port network, the total current is the sum of the branch currents from multiple ports. Therefore, obtaining the current of each port based on the arrangement of different voltage domains will greatly help subsequent power supply design. However, it is currently difficult to obtain the current characteristics of integrated circuit chips early in the project.

[0088] The power consumption analysis method provided in at least one embodiment of this disclosure can further obtain current characteristic files of integrated circuit chips under different voltage domains based on the power consumption waveform file obtained after power consumption analysis operations, such as current piecewise linear files. The current piecewise linear file is a format that describes the chip scenario and can reflect the current changes of integrated circuit chips under different voltage domains. This facilitates more in-depth and detailed guidance for the power integrity (PI) design of large-scale, high-performance integrated circuit chips in the early stages of the project, improves design efficiency, and saves design costs.

[0089] For example, in at least one example of the embodiments of this disclosure, the integrated circuit chip may include multiple voltage domains. In this case, obtaining a piecewise linear current file representing the current characteristics of the integrated circuit chip based on a time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip may include: obtaining the operating voltage of each voltage domain in the multiple voltage domains and multiple time-based power consumption waveform files; and for each voltage domain in the multiple voltage domains, obtaining multiple piecewise linear current files for the multiple voltage domains based on the multiple time-based power consumption waveform files.

[0090] In this example, the current characteristic file representing the current characteristics of an integrated circuit chip could be, for example, a current piecewise linear (IPWL) file. Since an integrated circuit chip can be divided into different voltage domains, each powered by a different power source—for example, high-performance circuitry can be assigned to operate in a high-voltage domain, and low-performance circuitry can be assigned to operate in a low-voltage domain—the current characteristic files differ across voltage domains; that is, the current piecewise linear files differ across voltage domains.

[0091] For example, an integrated circuit chip may include multiple voltage domains, such as a high voltage domain and a low voltage domain. The voltage domain settings may be different in different integrated circuit chips, and the embodiments of this disclosure do not limit this.

[0092] For example, based on multiple voltage domains of an integrated circuit chip, the operating voltage of each voltage domain can be obtained. Then, based on the power consumption waveform file, a current characteristic file corresponding to each voltage domain can be generated, such as a piecewise linear current file for each voltage domain. This allows for the acquisition of the integrated circuit chip's current characteristic files across multiple voltage domains. This power consumption analysis method can obtain the chip's current characteristics under different voltage domains early in the chip design project, facilitating voltage drop analysis and power supply design in the early stages of the project. This enables better adaptation to design changes and improves chip design efficiency.

[0093] In this example, power consumption waveform files for different operating conditions can also be generated based on the different operating conditions of the integrated circuit. For example, based on the time-based power consumption waveform file and the arrangement of the voltage domains of the integrated circuit chip, a piecewise linear current file representing the current characteristics of the integrated circuit chip can be obtained. It can also include: selecting multiple operating conditions of the integrated circuit chip and obtaining time-based power consumption waveform files corresponding to the multiple operating conditions; obtaining multiple piecewise linear current files for multiple voltage domains based on the time-based power consumption waveform files corresponding to the multiple operating conditions.

[0094] For example, in at least one embodiment of this disclosure, multiple operating conditions include a best case, a normal case, and a worst case.

[0095] For example, multiple operating conditions refer to the operation of an integrated circuit chip under different operating conditions, such as different voltages, temperatures, and pressures. These operating conditions may include best case, typical case, or worst case. The worst case refers to the extreme operating conditions. To ensure the chip can still operate under certain extreme conditions, it is necessary to analyze the chip's power consumption under the worst-case scenario. Therefore, obtaining the current characteristic file of the integrated circuit chip under the worst-case scenario is very meaningful, as it can help guide subsequent chip analysis and verification.

[0096] For example, in at least one example of the embodiments of this disclosure, the integrated circuit chip includes multiple modules, and the power consumption analysis method further includes: integrating multiple current piecewise linear files of multiple voltage domains to obtain current piecewise linear files of multiple modules; integrating the current piecewise linear files of multiple modules to obtain current piecewise linear files of the entire integrated circuit chip.

[0097] For example, as described above, an integrated circuit chip can be divided into multiple modules. The power consumption analysis method provided in at least one embodiment of this disclosure can obtain the current characteristic file of each module of the integrated circuit chip. Then, by integrating the current characteristic files of multiple modules, the current characteristic file of the entire integrated circuit chip (e.g., a piecewise linear current file) can be obtained. Obtaining the current characteristic file of each module of the integrated circuit chip allows for a better assessment of the chip's voltage drop problem based on the current requirements of different modules.

[0098] For example, multiple piecewise linear current files from multiple voltage domains can be integrated to obtain a piecewise linear current file for each module. For instance, a module here could include multiple sub-modules under different voltage domains. Furthermore, the current characteristic files of multiple modules can be integrated to obtain the current characteristic file for the entire integrated circuit chip.

[0099] The power consumption analysis method for integrated circuit chip design provided in at least one embodiment of this disclosure can obtain the power consumption and current characteristics of the integrated circuit chip in the early stages of the integrated circuit chip design process. In at least one embodiment, the current characteristics of each module of the integrated circuit chip can be obtained, thereby helping to reduce the power consumption of the integrated circuit chip earlier, helping to solve the voltage drop problem of the integrated circuit chip, optimizing the chip design, and reducing the design cost.

[0100] At least one embodiment of this disclosure also provides a design method for the power integrity of an integrated circuit chip.

[0101] Figure 4 A schematic flowchart illustrating a power integrity design method for an integrated circuit chip according to at least one embodiment of this disclosure is shown. Figure 4 As shown, the design method includes steps S10 and S20.

[0102] S10: Obtain the power consumption waveform file of the integrated circuit chip according to the power consumption analysis method described above;

[0103] S20: Adjust or design the power supply module for the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0104] For example, in at least one embodiment of this disclosure, the design method further includes step S30: adjusting or designing the power supply module for the integrated circuit chip according to the current characteristic file of the integrated circuit chip.

[0105] For example, in at least one example of the embodiments of this disclosure, the power module includes a power supply and a voltage regulator module.

[0106] For example, adjusting or designing a power supply module for an integrated circuit chip refers to designing the external power supply for the integrated circuit chip. For instance, a voltage regulator module can be added to the power supply module to improve power integrity (PI). Alternatively, the capacitors, windings, etc., in the power supply module can be designed to prevent over-design of the chip's power network.

[0107] The design method provided in at least one embodiment of this disclosure can obtain the power consumption and current characteristics of an integrated circuit chip in the early stages of the integrated circuit chip design process, assist in designing the power integrity of the integrated circuit chip, guide the design of external circuits of the chip, rationally plan resource allocation, prevent over-design of circuits, and effectively shorten the design cycle, improve design efficiency, and save design costs.

[0108] Corresponding to the power consumption analysis method described above, at least one embodiment of this disclosure also provides a power consumption analysis device. Figure 5 This is a schematic block diagram of a power consumption analysis device for the design of an integrated circuit chip, provided for at least one embodiment of the present disclosure.

[0109] For example, such as Figure 5 As shown, the power consumption analysis device 500 includes a mapping module 501, a power consumption analysis module 502, and a current characteristic acquisition module 503.

[0110] The mapping module 501 is configured to perform a mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register transfer level simulation waveform file.

[0111] The power consumption analysis module 502 is configured to perform power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip.

[0112] The current characteristic acquisition module 503 is configured to obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip.

[0113] For example, the mapping module 501, power consumption analysis module 502, and current characteristic acquisition module 503 include code and programs stored in memory; the processor can execute the code and programs to implement some or all of the functions of the mapping module 501, power consumption analysis module 502, and current characteristic acquisition module 503 as described above. For example, the mapping module 501, power consumption analysis module 502, and current characteristic acquisition module 503 can be dedicated hardware devices, or can be a circuit board or a combination of multiple circuit boards to implement some or all of the functions of the mapping module 501, power consumption analysis module 502, and current characteristic acquisition module 503 as described above. The circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) processor-executable firmware stored in memory.

[0114] It should be noted that the mapping module 501 can be used to implement Figure 1 In step S100, the power consumption analysis module 502 can be used to implement... Figure 1 In step S200, the current characteristic acquisition module 503 can be used to implement... Figure 1 Step S300 in the above process. For detailed descriptions of the mapping module 501, power consumption analysis module 502, and current characteristic acquisition module 503, please refer to the embodiments of the power consumption analysis method described above. Figure 1 The descriptions of steps S100, S200, and S300 shown are as follows:

[0115] The power consumption analysis device can achieve similar technical effects to the aforementioned power consumption analysis method, and will not be described in detail here.

[0116] At least one embodiment of this disclosure also provides an electronic device. Figure 6 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0117] For example, such as Figure 6As shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, communication interface 1002, and memory 1003 communicate with each other via the communication bus 1004. The processor 1001, communication interface 1002, and memory 1003 can also communicate with each other via a network connection. This disclosure does not limit the type and function of the network.

[0118] For example, memory 1003 is used to store computer-executable instructions non-transiently. When processor 1001 runs the computer-executable instructions, the computer-executable instructions are executed by processor 1001 to implement the power consumption analysis method or design method according to any of the above embodiments. For specific implementations and related explanations of the various steps of the power consumption analysis method or design method, please refer to the embodiments of the power consumption analysis method or design method described above, and will not be repeated here.

[0119] For example, the implementation of a power analysis method or a power integrity design method for an integrated circuit chip by the processor 1001 executing the program stored in the memory 1003 is the same as the implementation mentioned in the embodiments of the aforementioned power analysis method and design method, and will not be repeated here.

[0120] For example, the communication bus 1004 can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0121] For example, communication interface 1002 is used to enable communication between electronic devices and other devices.

[0122] For example, processor 1001 can control other components in an electronic device to perform desired functions. Processor 1001 can be a central processing unit (CPU), a network processor (NP), or a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be based on x86 or ARM architectures, etc.

[0123] For example, memory 1003 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and processor 1001 may execute the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data may also be stored in the storage medium.

[0124] For example, detailed descriptions of power consumption analysis methods or design methods for electronic devices can be found in the relevant descriptions in the embodiments of power consumption analysis methods or design methods, and repeated descriptions will not be repeated.

[0125] Figure 7 This is a schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. For example, such as Figure 7 As shown, one or more computer-executable instructions 1101 may be stored non-temporarily on storage medium 1100. For example, when the computer-executable instructions 1101 are executed by a processor, one or more steps in the analysis method of digital circuits described above may be performed.

[0126] For example, the storage medium 1100 can be used in the power consumption analysis device 500 of the aforementioned electronic device and / or integrated circuit chip. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

[0127] For example, the description of storage medium 1100 can be found in the description of memory in the embodiments of the electronic device, and repeated descriptions will not be repeated here.

[0128] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0129] The following points should be noted regarding this disclosure:

[0130] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0131] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0132] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0133] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A power consumption analysis method for the design of integrated circuit chips, comprising: A mapping operation is performed on the register-transfer-level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register-transfer-level simulation waveform file; The power consumption analysis of the integrated circuit chip is performed based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip; Based on the power consumption waveform file of the integrated circuit chip, a current characteristic file representing the current characteristics of the integrated circuit chip is obtained; The step of obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip includes: Based on the time-based power consumption waveform file and the voltage domain arrangement of the integrated circuit chip, a piecewise linear current file representing the current characteristics of the integrated circuit chip is obtained, wherein the piecewise linear current file is different for different voltage domains.

2. The power consumption analysis method according to claim 1, wherein, The mapping operation on the register-transfer level simulation waveform file of the integrated circuit chip to obtain the gate-level netlist waveform file corresponding to the register-transfer level simulation waveform file includes: The register transfer stage of the integrated circuit chip is mapped to the corresponding gate-level netlist according to the naming mapping file, thereby obtaining the gate-level netlist waveform file corresponding to the simulation waveform file of the register transfer stage.

3. The power consumption analysis method according to claim 1, wherein, The step of performing power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip includes: The power analysis operation is performed using a power analysis tool based on the obtained gate-level netlist waveform file to obtain a time-based power waveform file of the integrated circuit chip.

4. The power consumption analysis method according to claim 3, wherein, The step of performing power analysis using a power analysis tool based on the obtained gate-level netlist waveform file to obtain a time-based power waveform file of the integrated circuit chip includes: Obtain a set of power analysis input files, including the gate-level netlist waveform files; The power analysis tool performs the power analysis operation on the integrated circuit chip based on the power analysis input file set to generate the time-based power waveform file of the integrated circuit chip.

5. The power consumption analysis method according to claim 4, further comprising: The sampling time interval is set according to the clock of the gate-level netlist waveform file; A time-based power consumption waveform file is generated based on the sampling time interval.

6. The power consumption analysis method according to claim 4, wherein, The power consumption analysis input file set also includes standard delay format files, library files, data files, and script files.

7. The power consumption analysis method according to claim 1, wherein, The integrated circuit chip includes multiple voltage domains. The step of obtaining a piecewise linear current file representing the current characteristics of the integrated circuit chip based on the time-based power consumption waveform file and the voltage domain arrangement of the integrated circuit chip includes: Obtain the operating voltage of each of the multiple voltage domains and multiple time-based power consumption waveform files; For each of the multiple voltage domains, multiple piecewise linear current files for the multiple voltage domains are obtained based on the multiple time-based power consumption waveform files.

8. The power consumption analysis method according to claim 7, further comprising: Select multiple operating states of the integrated circuit chip and obtain time-based power consumption waveform files corresponding to the multiple operating states; Based on the time-based power consumption waveform files corresponding to the multiple operating conditions, multiple current piecewise linear files for the multiple voltage domains are obtained.

9. The power consumption analysis method according to claim 8, wherein, The various operating conditions include best-case, normal, and worst-case scenarios.

10. The power consumption analysis method according to claim 7, wherein, The integrated circuit chip includes multiple modules. The power consumption analysis method further includes: By integrating multiple piecewise linear current files from the multiple voltage domains, the piecewise linear current files of the multiple modules are obtained. By integrating the current piecewise linear files of the multiple modules, the current piecewise linear file of the entire integrated circuit chip is obtained.

11. A power integrity design method for an integrated circuit chip, comprising: The current characteristic file of the integrated circuit chip is obtained according to the power consumption analysis method as described in any one of claims 1-10; The power supply module for the integrated circuit chip is adjusted or designed based on the current characteristic file of the integrated circuit chip.

12. The design method according to claim 11, wherein, The power module includes a power supply and a voltage regulator module.

13. A power consumption analysis device for the design of integrated circuit chips, comprising: The mapping module is configured to perform a mapping operation on the register transfer level simulation waveform file of the integrated circuit chip to obtain a gate-level netlist waveform file corresponding to the register transfer level simulation waveform file; The power consumption analysis module is configured to perform power consumption analysis on the integrated circuit chip based on the gate-level netlist waveform file to obtain the power consumption waveform file of the integrated circuit chip; The current characteristic acquisition module is configured to obtain a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip. The step of obtaining a current characteristic file representing the current characteristics of the integrated circuit chip based on the power consumption waveform file of the integrated circuit chip includes: Based on the time-based power consumption waveform file and the voltage domain arrangement of the integrated circuit chip, a piecewise linear current file representing the current characteristics of the integrated circuit chip is obtained, wherein the piecewise linear current file is different for different voltage domains.

14. An electronic device comprising: Memory stores computer-executable instructions non-transiently; The processor is configured to run computer-executable instructions. The computer-executable instructions are implemented by the processor at runtime according to the power consumption analysis method of any one of claims 1-10 or the design method of any one of claims 11-12.

15. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the power consumption analysis method according to any one of claims 1-10 or the design method according to any one of claims 11-12.

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