Pixel circuit and driving method thereof, display substrate and display device

Abstract

A pixel circuit and a driving method thereof, a display substrate and a display device, wherein the pixel circuit includes: a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; the node control subcircuit includes: a writing subcircuit, the node control subcircuit is configured to provide a signal of a second node to a first node, provide a signal of a data signal line to a third node, provide a signal of an initial signal line to a fourth node, and store a voltage difference between the signals of the first node and the fourth node under the control of signals of a first scanning signal line and a second scanning signal line, and the writing subcircuit is electrically connected to the first scanning signal line, the second scanning signal line, the data signal line and the third node, respectively, and is configured to provide a signal of the data signal line to the third node under the control of signals of the first scanning signal line and the second scanning signal line.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a pixel circuit configured to drive a light-emitting device to emit light, the pixel circuit comprising: a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; the node control subcircuit comprises: a writing subcircuit;

[0005] The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node;

[0006] The light-emitting control subcircuit is electrically connected to the second node, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first power line, respectively, and is configured to provide a signal of the third node to the fourth node and a signal of the first power line to the second node under the control of the first light-emitting signal line and the second light-emitting signal line;

[0007] The node control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the initial signal line, the first node, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the second node to the first node, provide the signal of the data signal line to the third node, provide the signal of the initial signal line to the fourth node, and store the voltage difference between the signals of the first node and the fourth node under the control of the signals of the first scan signal line and the second scan signal line;

[0008] The writing subcircuit is electrically connected to the first scanning signal line, the second scanning signal line, the data signal line and the third node respectively, and is configured to provide the signal of the data signal line to the third node under the control of the signal of the first scanning signal line and the second scanning signal line;

[0009] The light emitting device is electrically connected to the fourth node and the second power line respectively.

[0010] In an exemplary embodiment, the node control subcircuit further includes: a reset subcircuit, a compensation subcircuit, and a storage subcircuit;

[0011] The compensation subcircuit is electrically connected to the first scan signal line, the first node and the second node respectively, and is configured to provide a signal of the second node to the first node under the control of the first scan signal line;

[0012] The reset subcircuit is electrically connected to one of the first scan signal line and the second scan signal line, the initial signal line and the fourth node respectively, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of one of the first scan signal line and the second scan signal line;

[0013] The storage sub-circuit is electrically connected to the first node and the fourth node, respectively, and is configured to store a voltage difference between the signals of the first node and the fourth node.

[0014] In an exemplary embodiment, the write subcircuit includes: a third transistor and a fourth transistor;

[0015] A control electrode of the third transistor is electrically connected to one of the first scan signal line and the second scan signal line, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor;

[0016] A control electrode of the fourth transistor is electrically connected to the other of the first scanning signal line and the second scanning signal line, and a second electrode of the fourth transistor is electrically connected to the data signal line.

[0017] In an exemplary embodiment, the compensation subcircuit includes: a first transistor, the storage subcircuit includes: a capacitor, the capacitor includes: a first plate and a second plate, the reset subcircuit includes: a seventh transistor;

[0018] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node;

[0019] A control electrode of the seventh transistor is electrically connected to one of the first scan signal line and the second scan signal line, a first electrode of the seventh transistor is electrically connected to the initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node;

[0020] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fourth node.

[0021] In an exemplary embodiment, the driving subcircuit includes: a second transistor, and the light emission control subcircuit includes: a fifth transistor and a sixth transistor;

[0022] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the third node;

[0023] The control electrode of the fifth transistor is electrically connected to the second light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power line, and the second electrode of the fifth transistor is electrically connected to the second node;

[0024] The control electrode of the sixth transistor is electrically connected to the first light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0025] In an exemplary embodiment, the duration of the signal of the first scan signal line being the effective level signal includes: a first time period and a second time period that occur sequentially and continuously, the duration of the signal of the second scan signal line being the effective level signal includes: a third time period and a fourth time period that occur sequentially and continuously, the sum of the first time period and the second time period is equal to the sum of the third time period and the fourth time period, and the second time period and the third time period at least partially overlap;

[0026] When the signal of the first scanning signal line is a valid level signal, the signal of the first light-emitting signal line is an invalid level signal; when the signal of the second scanning signal line is a valid level signal, the signal of the second light-emitting signal line is an invalid level signal;

[0027] The duration that the signal of the first scanning signal line is a valid level signal is equal to the duration that the signal of the second scanning signal line is a valid level signal, the duration that the signal of the first light-emitting signal line is an invalid level signal is equal to the duration that the signal of the second light-emitting signal line is an invalid level signal, and the duration that the signal of the first light-emitting signal line is an invalid level signal is greater than or equal to the duration that the signal of the first scanning signal line is a valid level signal.

[0028] In an exemplary embodiment, the first to seventh transistors are N-type transistors.

[0029] In a second aspect, the present disclosure further provides a display substrate, comprising: a plurality of the above-mentioned pixel circuits arranged in an array, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of first light-emitting signal lines, a plurality of second light-emitting signal lines, a plurality of initial signal lines, a plurality of first power lines, a plurality of data signal lines, a first gate driving circuit and a second gate driving circuit, wherein the first light-emitting signal lines and the second light-emitting signal lines extend along a first direction, the initial signal lines, the first power lines and the data signal lines extend along a second direction, and the first direction intersects with the second direction;

[0030] The first gate driving circuit is electrically connected to a plurality of first scanning signal lines and a plurality of second scanning signal lines respectively; the second gate driving circuit is electrically connected to a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines respectively.

[0031] In an exemplary embodiment, the second scanning signal line electrically connected to the pixel circuits in the i-th row is electrically connected to the first scanning signal line electrically connected to the pixel circuits in the (i+1)-th row, 1≤i≤M-1, and M is the total number of rows of pixel circuits.

[0032] In an exemplary embodiment, the display substrate includes: a substrate, and a circuit structure layer and a light emitting structure layer disposed on the substrate, the circuit structure layer includes: a plurality of pixel circuits, the light emitting structure layer includes: a plurality of light emitting devices, and the pixel circuit includes: a plurality of transistors and at least one capacitor;

[0033] The circuit structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially on a substrate;

[0034] The semiconductor layer at least includes: an active layer of a plurality of transistors;

[0035] The first conductive layer at least includes: a first electrode plate of a capacitor, control electrodes of a plurality of transistors, a first light-emitting signal line, a second light-emitting signal line, a first scanning signal line, and a second scanning signal line;

[0036] The second conductive layer at least includes: an initial signal line and a second plate of a capacitor;

[0037] The third conductive layer includes at least: a first power line, a data signal line and a signal connection line, wherein the signal connection line is electrically connected to a first scanning signal line electrically connected to one pixel circuit and a second scanning signal line electrically connected to another pixel circuit in adjacent pixel circuits located in the same column.

[0038] In an exemplary embodiment, the pixel circuit includes: first to seventh transistors, and the seventh transistor is electrically connected to the second scan signal line;

[0039] The first scanning signal line extends along the second direction, the second scanning signal line extends along the first direction, the second scanning signal line is located at a side of the first scanning signal line away from the second light-emitting signal line, and the second scanning signal line and the control electrode of the fourth transistor are spaced apart;

[0040] The positive projection of the initial signal line electrically connected to the jth column of pixel circuits on the substrate is located between the positive projections of the data signal line electrically connected to the jth column of pixel circuits and the first power line electrically connected to the j+1th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

[0041] In an exemplary embodiment, at least a portion of the signal connection line extends along the second direction, and the signal connection line is respectively electrically connected to the control electrode of the fourth transistor of the i-th row and j-th column pixel circuit, the second scanning signal line electrically connected to the i-th row and j-th column pixel circuit, and the first scanning signal line electrically connected to the i+1-th row and j-th column pixel circuit, 1≤i≤M-1.

[0042] In an exemplary embodiment, the pixel circuit includes: first to seventh transistors, and the seventh transistor is electrically connected to the first scan signal line.

[0043] The first scanning signal line and the second scanning signal line extend along a first direction, the second scanning signal line is located on a side of the first scanning signal line close to the second light-emitting signal line, and the second scanning signal line and the control electrode of the fourth transistor are integrally formed;

[0044] The positive projection of the initial signal line electrically connected to the jth column of pixel circuits on the substrate is located between the positive projections of the data signal line electrically connected to the jth column of pixel circuits and the first power line electrically connected to the j+1th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

[0045] In an exemplary embodiment, the first conductive layer further includes: a first electrode connection block, and the third conductive layer further includes: a second electrode connection block;

[0046] The first electrode connection block extends along the second direction and is electrically connected to the signal connection line;

[0047] At least a portion of the second electrode connection block extends along the second direction, and the second electrode connection block is electrically connected to the first electrode connection block and the first scan signal line respectively.

[0048] In an exemplary embodiment, at least a portion of the signal connection line extends along the second direction, and the signal connection line is electrically connected to the control electrode of the fourth transistor of the pixel circuit in the i-th row and j-th column and the first electrode connection block of the pixel circuit in the (i+1)-th row and j-th column, respectively.

[0049] In a third aspect, the present disclosure further provides a display device, comprising the above-mentioned display substrate.

[0050] In a fourth aspect, the present disclosure further provides a method for driving a pixel circuit, which is configured to drive the above-mentioned pixel circuit, and the method includes:

[0051] Under the control of the signals of the first scanning signal line and the second scanning signal line, the node control subcircuit provides the signal of the second node to the first node, provides the signal of the data signal line to the third node, provides the signal of the initial signal line to the fourth node, and stores the voltage difference between the signals of the first node and the fourth node;

[0052] Under the control of the signals at the first node and the second node, the driving subcircuit provides a driving current to the third node;

[0053] Under the control of the first light-emitting signal line and the second light-emitting signal line, the light-emitting control subcircuit provides the signal of the third node to the fourth node, and provides the signal of the first power line to the second node.

[0054] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0056] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure;

[0057] Figure 2 A schematic diagram of the structure of a node control subcircuit provided by an exemplary embodiment;

[0058] Figure 3 An equivalent circuit of a node control subcircuit provided for an exemplary embodiment Figure 1 ;

[0059] Figure 4 An equivalent circuit of a node control subcircuit provided for an exemplary embodiment Figure 2 ;

[0060] Figure 5 An equivalent circuit diagram of a driving subcircuit and a light emitting control subcircuit provided for an exemplary embodiment;

[0061] Figure 6 An equivalent circuit of a pixel circuit provided for an exemplary embodiment Figure 1 ;

[0062] Figure 7An equivalent circuit of a pixel circuit provided for an exemplary embodiment Figure 2 ;

[0063] Figure 8 A working timing of a pixel circuit Figure 1 ;

[0064] Fig. 9 A working timing of a pixel circuit Figure 2 ;

[0065] Fig.10 A schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure Figure 1 ;

[0066] Fig.11 A schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure Figure 2 ;

[0067] Fig.12 for Fig.10 and Fig.11 A schematic diagram of a display substrate provided after a semiconductor layer pattern is formed;

[0068] Fig.13 for Fig.10 A schematic diagram of a first conductive layer pattern of a display substrate is provided;

[0069] Fig.14 for Fig.10 A schematic diagram of a display substrate provided after a first conductive layer pattern is formed;

[0070] Fig.15 for Fig.11 A schematic diagram of a first conductive layer pattern of a display substrate is provided;

[0071] Fig.16 for Fig.11 A schematic diagram of a display substrate provided after a first conductive layer pattern is formed;

[0072] Fig.17 for Fig.10 and Fig.11 A schematic diagram of a second conductive layer pattern of a display substrate is provided;

[0073] Fig.18 for Fig.10 A schematic diagram of a display substrate provided after a second conductive layer pattern is formed;

[0074] Fig.19 for Fig.11 A schematic diagram of a display substrate provided after a second conductive layer pattern is formed;

[0075] Fig. 20 for Fig.10A schematic diagram of a display substrate after a third insulating layer is formed is provided;

[0076] Fig.21 for Fig.11 A schematic diagram of a display substrate after a third insulating layer is formed is provided;

[0077] Fig. 22 for Fig.10 A schematic diagram of a third conductive layer pattern of a display substrate is provided;

[0078] Fig.23 for Fig.10 A schematic diagram of a display substrate provided after a third conductive layer pattern is formed;

[0079] Fig.24 for Fig.11 A schematic diagram of a third conductive layer pattern of a display substrate is provided;

[0080] Fig.25 for Fig.11 A schematic diagram of a display substrate after a third conductive layer pattern is formed is provided. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0082] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0083] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0084] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0085] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0086] In this specification, a transistor refers to an element including at least three elements: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode element, drain region, or drain electrode) and a source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0087] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0088] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0089] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0090] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0091] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0092] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0093] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0094] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure, Figure 2 FIG. 1 is a schematic diagram of a node control subcircuit provided by an exemplary embodiment. Figure 1 and Figure 2 As shown, the embodiment of the present disclosure provides a pixel circuit configured to drive a light-emitting device to emit light, and the pixel circuit may include: a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit. The node control subcircuit may include: a writing subcircuit.

[0095] like Figure 1As shown, the driving subcircuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the light emitting control subcircuit is electrically connected to the second node N2, the third node N3, the fourth node N4, the first light emitting signal line EM1, the second light emitting signal line EM2 and the first power line VDD, respectively, and is configured to provide the signal of the third node N3 to the fourth node N4 and the signal of the first power line VDD to the second node N2 under the control of the first light emitting signal line EM1 and the second light emitting signal line EM2; the node control subcircuit is electrically connected to the first scanning signal line EM1, the third node N3, the fourth node N4, the first light emitting signal line EM1, the second light emitting signal line EM2 and the first power line VDD, respectively. The scanning signal line Gate1, the second scanning signal line Gate2, the data signal line Data, the initial signal line INIT, the first node N1, the second node N2, the third node N3 and the fourth node N4 are electrically connected, and are configured to provide the signal of the second node N2 to the first node N1, provide the signal of the data signal line Data to the third node N3, provide the signal of the initial signal line INIT to the fourth node N4, and store the voltage difference between the signals of the first node N1 and the fourth node N4 under the control of the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2; the light emitting device is electrically connected to the fourth node N4 and the second power line VSS, respectively.

[0096] like Figure 2 As shown, the write sub-circuit is electrically connected to the first scan signal line Gate1, the second scan signal line Gate2, the data signal line Data and the third node N3, respectively, and is configured to provide the signal of the data signal line Data to the third node N3 under the control of the signals of the first scan signal line Gate1 and the second scan signal line Gate2.

[0097] In an exemplary embodiment, the first power line VDD may continuously provide a high voltage power signal, and the second power line VSS may continuously provide a low voltage power signal.

[0098] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED), including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. Exemplarily, the anode of the organic light emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light emitting diode is electrically connected to the second power line VSS.

[0099] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0100] The pixel circuit provided in the embodiment of the present disclosure is configured to drive the light-emitting device to emit light, and the pixel circuit includes: a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; the node control subcircuit includes: a writing subcircuit, a driving subcircuit, which is electrically connected to the first node, the second node and the third node, respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node; the light-emitting control subcircuit is electrically connected to the second node, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first power line, respectively, and is configured to provide the signal of the third node to the fourth node and the signal of the first power line to the second node under the control of the first light-emitting signal line and the second light-emitting signal line; the node control subcircuit is electrically connected to the first node, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first power line, respectively, and is configured to provide the signal of the third node to the fourth node and the signal of the first power line to the second node; A scanning signal line, a second scanning signal line, a data signal line, an initial signal line, a first node, a second node, a third node and a fourth node are electrically connected, and are configured to provide the signal of the second node to the first node, provide the signal of the data signal line to the third node, provide the signal of the initial signal line to the fourth node under the control of the signal of the first scanning signal line and the second scanning signal line, and store the voltage difference between the signals of the first node and the fourth node; a writing subcircuit is electrically connected to the first scanning signal line, the second scanning signal line, the data signal line and the third node respectively, and is configured to provide the signal of the data signal line to the third node under the control of the signal of the first scanning signal line and the second scanning signal line; a light-emitting device is electrically connected to the fourth node and the second power line respectively. The present disclosure electrically connects the driving subcircuit, the node control subcircuit and the light-emitting control subcircuit with the first scanning signal line, the second scanning signal line, the first light-emitting signal line and the second light-emitting signal line, so as to reduce the number of peripheral driving circuits connected to the pixel circuit, thereby reducing the area occupied by the peripheral driving circuit, simplifying the structure of the peripheral driving circuit, and reducing the driving risk.

[0101] In an exemplary embodiment, Figure 2 As shown, the node control subcircuit may further include: a reset subcircuit, a compensation subcircuit and a storage subcircuit.

[0102] like Figure 2As shown, the compensation sub-circuit is electrically connected to the first scan signal line Gate1, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the second node N2 to the first node N1 under the control of the first scan signal line Gate1; the reset sub-circuit is electrically connected to one of the first scan signal line Gate1 and the second scan signal line Gate2, the initial signal line INIT and the fourth node N4, respectively, and is configured to provide the signal of the initial signal line INIT to the fourth node N4 under the control of the signal of one of the first scan signal line Gate1 and the second scan signal line Gate2; the storage sub-circuit is electrically connected to the first node N1 and the fourth node N4, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the fourth node N4.

[0103] In an exemplary embodiment, the voltage value of the signal of the initial signal line INIT is less than the voltage value of the signal of the second power line VSS. Exemplarily, the voltage value of the signal of the initial signal line INIT may be slightly less than the voltage value of the signal of the second power line VSS. The voltage value of the signal of the initial signal line INIT is less than the voltage value of the signal of the second power line VSS, which can ensure that when the anode of the light-emitting device is reset, the light-emitting device does not emit light, thereby improving the display effect.

[0104] In an exemplary embodiment, the reset sub-circuit may be electrically connected to the first scan signal line Gate1 , or may be electrically connected to the second scan signal line Gate2 , which is not limited in the present disclosure.

[0105] In an exemplary embodiment, Figure 3 An equivalent circuit of a node control subcircuit provided for an exemplary embodiment Figure 1 , Figure 4 An equivalent circuit of a node control subcircuit provided for an exemplary embodiment Figure 2 .like Figure 3 and Figure 4 As shown, the compensation subcircuit may include: a first transistor T1, the storage subcircuit may include: a capacitor C, the capacitor C includes: a first plate C1 and a second plate C2, and the reset subcircuit may include: a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to one of the first scan signal line Gate1 and the second scan signal line Gate2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the fourth node N4.

[0106] In an exemplary embodiment, the first transistor T1 may be referred to as a compensation transistor. When the signal of the first scan signal line Gate1 is an effective level signal, the signal of the second node N2 is written into the first node N1 to compensate for the signal of the first node N1.

[0107] In an exemplary embodiment, the control electrode of the seventh transistor T7 may be electrically connected to the first scan signal line Gate1 , or may be electrically connected to the second scan signal line Gate2 , which is not limited in the present disclosure.

[0108] In an exemplary embodiment, the seventh transistor T7 may be referred to as a reset transistor. When the signal of the scan signal line to which the seventh transistor T7 is electrically connected is an effective level signal, the signal of the initial signal line INIT is written into the fourth node N4.

[0109] In an exemplary embodiment, Figure 3 and Figure 4 As shown, the write subcircuit may include: a third transistor T3 and a fourth transistor T4. The control electrode of the third transistor T3 is electrically connected to one of the first scan signal line Gate1 and the second scan signal line Gate2, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected to the other signal line of the first scan signal line Gate1 and the second scan signal line Gate2, and the second electrode of the fourth transistor T4 is electrically connected to the data signal line Data. Exemplarily, the control electrode of the third transistor T3 may be electrically connected to the first scan signal line Gate1, and the control electrode of the fourth transistor T4 may be electrically connected to the second scan signal line Gate2, or the control electrode of the third transistor T3 may be electrically connected to the second scan signal line Gate2, and the control electrode of the fourth transistor T4 may be electrically connected to the first scan signal line Gate1. The present disclosure does not make any limitation to this. Figure 3 The description is made by taking the example that the control electrode of the third transistor T3 is electrically connected to the first scanning signal line Gate1 and the control electrode of the fourth transistor T4 is electrically connected to the second scanning signal line Gate2. Figure 4 The description is made by taking the example that the control electrode of the third transistor T3 is electrically connected to the second scanning signal line Gate2 and the control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1.

[0110] In an exemplary embodiment, the third transistor T3 and the fourth transistor T4 may be referred to as write transistors. When the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are both active level signals, the signal of the data signal line Data is written into the third node N3.

[0111] Figure 3 and Figure 4 An exemplary structure of the node control subcircuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the node control subcircuit is not limited thereto.

[0112] In an exemplary embodiment, Figure 5 FIG. 1 is an equivalent circuit diagram of a driving subcircuit and a light emitting control subcircuit provided by an exemplary embodiment. Figure 5 As shown, the driving subcircuit may include: a second transistor T2, and the light emitting control subcircuit may include: a fifth transistor T5 and a sixth transistor T6. The control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0113] In an exemplary embodiment, the second transistor T2 may be referred to as a driving transistor. The second transistor T2 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between a control electrode and a first electrode thereof.

[0114] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When the signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are valid level signals, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0115] Figure 5 An exemplary structure of the driving subcircuit and the light-emitting control subcircuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the driving subcircuit and the light-emitting control subcircuit is not limited thereto.

[0116] In an exemplary embodiment, Figure 6 An equivalent circuit of a pixel circuit provided for an exemplary embodiment Figure 1 , Figure 7 An equivalent circuit of a pixel circuit provided for an exemplary embodiment Figure 2 .like Figure 6 and Figure 7As shown, the node control subcircuit may include: a first transistor T1, a third transistor T3, a fourth transistor T4, a seventh transistor T7 and a capacitor C, the capacitor C includes: a first electrode plate C1 and a second electrode plate C2, the driving subcircuit may include: a second transistor T2, and the light emitting control subcircuit may include: a fifth transistor T5 and a sixth transistor T6. Among them, the control electrode of the first transistor T1 is electrically connected to the first scanning signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to one of the first scanning signal line Gate1 and the second scanning signal line Gate2, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected to the other signal line of the first scanning signal line Gate1 and the second scanning signal line Gate2, and the control electrode of the fourth transistor T4 is electrically connected to the other signal line of the first scanning signal line Gate1 and the second scanning signal line Gate2. The second electrode is electrically connected to the data signal line Data; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to one of the first scanning signal line Gate1 and the second scanning signal line Gate2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the fourth node N4. Figure 6 The description is made by taking the example that the control electrode of the third transistor T3 is electrically connected to the first scanning signal line Gate1 and the control electrode of the fourth transistor T4 is electrically connected to the second scanning signal line Gate2. Figure 7 The description is made by taking the example that the control electrode of the third transistor T3 is electrically connected to the second scanning signal line Gate2 and the control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1.

[0117] In an exemplary embodiment, the duration during which the signal of the first scan signal line Gate1 is a valid level signal includes: a first time period and a second time period that occur sequentially and continuously, and the duration during which the signal of the second scan signal line Gate2 is a valid level signal includes: a third time period and a fourth time period that occur sequentially and continuously, the sum of the first time period and the second time period is equal to the sum of the third time period and the fourth time period, and the second time period and the third time period at least partially overlap.

[0118] In an exemplary embodiment, a picture displayed by a display substrate where the pixel circuit is located includes a plurality of display frames.

[0119] In an exemplary embodiment, the duration of the signal line being a valid level signal refers to the duration within one display frame. The signal line refers to at least one of the first scan signal line Gate1, the second scan signal line Gate2, the first light emitting signal line EM1, and the second light emitting signal line EM2.

[0120] In an exemplary embodiment, the first and second time periods during which the signal of the first scan signal line Gate1 is an effective level signal and the third and fourth time periods during which the signal of the second scan signal line Gate2 is an effective level signal are time periods within one display frame.

[0121] In an exemplary embodiment, when the signal of the first scanning signal line Gate1 is a valid level signal, the signal of the first light emitting signal line EM1 is an invalid level signal, and when the signal of the second scanning signal line Gate2 is a valid level signal, the signal of the second light emitting signal line EM2 is an invalid level signal;

[0122] In an exemplary embodiment, the duration that the signal of the first scan signal line Gate1 is a valid level signal is equal to the duration that the signal of the second scan signal line Gate2 is a valid level signal, the duration that the signal of the first light emitting signal line EM1 is an invalid level signal is equal to the duration that the signal of the second light emitting signal line EM2 is an invalid level signal, and the duration that the signal of the first light emitting signal line EM1 is an invalid level signal is greater than or equal to the duration that the signal of the first scan signal line Gate1 is a valid level signal.

[0123] According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0124] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0125] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be oxide thin film transistors, and the active layer of the oxide thin film transistors is oxide semiconductor (Oxide). Low temperature polysilicon thin film transistors have advantages such as high mobility and fast charging, and oxide thin film transistors have advantages such as low leakage current, which can improve display quality.

[0126] Figure 8 A working timing of a pixel circuit Figure 1 , Fig. 9 A working timing of a pixel circuit Figure 2 . Figure 8 The description is made by taking the case that the duration of the signal of the first light emitting signal line EM1 being an invalid level signal is equal to the duration of the signal of the first scanning signal line Gate1 being an effective level signal. Fig. 9 The description is made by taking the example that the duration of the signal of the first light emitting signal line EM1 being the invalid level signal is longer than the duration of the signal of the first scanning signal line Gate1 being the valid level signal. Figure 8 and Fig. 9 The difference lies in the time interval between the second stage and the third stage.

[0127] Below through Figure 6 and Figure 7 The operation process of the pixel circuit of the example is described in detail with reference to the exemplary embodiment of the present disclosure. Figure 6 and Figure 7 The pixel circuit in includes 7 transistors (a first transistor T1 to a seventh transistor T7) and a capacitor C, and all the 7 transistors are N-type transistors.

[0128] In an exemplary embodiment, when Figure 6 When the control electrode of the seventh transistor in is electrically connected to the first scanning signal line, Figure 8 and Fig. 9As shown, Figure 6 The working process of the provided pixel circuit may include:

[0129] The first stage S1 is called the initialization stage. The signals of the second light-emitting signal line EM2 and the first scanning signal line Gate1 are high-level signals, and the signals of the first light-emitting signal line EM1 and the second scanning signal line Gate2 are low-level signals. The signal of the second light-emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, the signal of the first scanning signal line Gate1 is a high-level signal, the first transistor T1 is turned on, the high-voltage power supply signal of the first power supply line VDD is written to the first node N1 through the turned-on fifth transistor T5, the second node N2 and the turned-on first transistor T1, and the capacitor C is charged. The seventh transistor T7 is turned on, and the initial signal of the initial signal line INIT is written to the fourth node N4 through the turned-on seventh transistor T7, and the fourth node N4 is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization. The signals of the first light-emitting signal line EM1 and the second scanning signal line Gate2 are low-level signals, and the fourth transistor T4 and the sixth transistor T6 are turned off. Although the third transistor T3 is turned on, the fourth transistor T4 is turned off, and the signal of the data signal line Data cannot be written to the third node N3. In this stage, the voltage value V1 of the signal of the first node N1 is Vdd, where Vdd is the voltage value of the high-voltage power supply signal. The voltage value V4 of the signal of the fourth node N4 is Vinit, where Vinit is the voltage value of the initial signal. Since the voltage value of the signal of the initial signal line INIT is less than the voltage value of the signal of the second power supply line VSS, the light-emitting device L does not emit light.

[0130] The second stage S2 is called the data writing and threshold compensation stage. The signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are high-level signals, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data signal. The signal of the first scanning signal line Gate1 is a high-level signal, the first transistor T1, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are continuously turned on, the initial signal of the initial signal line INIT is written to the fourth node N4 through the turned-on seventh transistor T7, and the signal of the data signal line Data charges the first node N1 through the turned-on fourth transistor T4, the third transistor T3, the third node N3, the turned-on second transistor T2, the second node N2 and the turned-on first transistor T1 until the voltage value of the signal at the first node N1 jumps to Vdata+Vth, where Vdata is the voltage value of the data signal. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, and the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the voltage value V1 of the signal of the first node N1 is Vdata+Vth, and the voltage value V4 of the signal of the fourth node N4 is Vinit. Since the voltage value of the signal of the initial signal line INIT is slightly smaller than the voltage value of the signal of the second power line VSS, the light-emitting device L does not emit light.

[0131] The third stage S3 is called the light-emitting stage. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the high-voltage power supply signal output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the second node N2, the turned-on second transistor T2, the third node N3, the turned-on sixth transistor T6 and the fourth node N4, driving the light-emitting device L to emit light. The signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, and the first transistor T1, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L emits light. In this stage, the voltage value V3 of the signal at the third node N3 is V OLED , V OLED is the anode voltage of the light emitting device L. The voltage value of the signal at the first node N1 changes under the action of the capacitor C. At this stage, the voltage value V1 of the signal at the first node N1 satisfies: V1 = Vdata + Vth + V OLED –Vinit, the voltage Vgs difference between the control electrode and the first electrode of the second transistor T2 satisfies

[0132] Vgs=Vdata+Vth+(Voled-Vint)-Voled=Vdata+Vth-Vint.

[0133] During the pixel circuit driving process, the driving current flowing through the second transistor T2 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Therefore, the driving current I of the second transistor T2 is:

[0134] I=K*(Vgs-Vth) 2 =K*[Vdata–Vinit] 2

[0135] Wherein, I is the driving current flowing through the second transistor T2, that is, the driving current driving the light emitting device L, and K is a constant.

[0136] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the second transistor T2 is no longer affected by the threshold voltage of the second transistor T2, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, which can ensure uniform display brightness of the display product and improve the display effect of the entire display product.

[0137] when Figure 6 When the control electrode of the seventh transistor in is electrically connected to the second scanning signal line Gate2, Figure 6 The working process of the provided pixel circuit is different from the above working process in that the seventh transistor T7 is turned off in the first stage and turned on in the second stage to initialize (reset) the fourth node N4.

[0138] when Figure 7 When the control electrode of the seventh transistor in is electrically connected to the first scanning signal line Gate1, Figure 7 The working process of the provided pixel circuit is different from the above working process in that the fourth transistor T4 is turned on in the first stage, and the third transistor T3 is turned off in the first stage.

[0139] when Figure 7 When the control electrode of the seventh transistor in is electrically connected to the second scanning signal line Gate2, Figure 7 The working process of the provided pixel circuit is different from the above working process in that the fourth transistor T4 is turned on in the first stage, and the third transistor T3 and the seventh transistor T7 are turned off in the first stage.

[0140] The present disclosure also provides a display substrate. Fig.10 A schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure Figure 1 , Fig.11 A schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure Figure 2 .like Fig.10 and Fig.11 As shown, the display substrate may include: a substrate, and a circuit structure layer and a light emitting structure layer sequentially arranged on the substrate, the circuit structure layer includes a plurality of pixel circuits arranged in an array, a plurality of first light emitting signal lines EM1, a plurality of second light emitting signal lines EM2, a plurality of first scanning signal lines Gate1, a plurality of second scanning signal lines Gate2, a plurality of initial signal lines INIT, a plurality of first power supply lines VDD and a plurality of data signal lines Data, a first gate driving circuit and a second gate driving circuit. The light emitting structure layer includes: a plurality of light emitting devices. Fig.10 The following description is made by taking the example that the display substrate includes a seventh transistor in the pixel circuit and is electrically connected to the second scanning signal line. Fig.11 The description is made by taking an example that the seventh transistor in the pixel circuit of the display substrate is electrically connected to the first scanning signal line.

[0141] In an exemplary embodiment, Fig.10 and Fig.11 As shown, the first light emitting signal line EM1 and the second light emitting signal line EM2 extend along a first direction X, the initial signal line INIT, the first power line VDD and the data signal line Data extend along a second direction, and the first direction X intersects the second direction Y.

[0142] In an exemplary embodiment, the first gate driving circuit is electrically connected to the plurality of first scanning signal lines and the plurality of second scanning signal lines, respectively; and the second gate driving circuit is electrically connected to the plurality of first light emitting signal lines and the plurality of second light emitting signal lines, respectively.

[0143] In an exemplary embodiment, a pulse width modulation unit is provided in the second gate circuit, and the pulse width modulation unit is configured to adjust the pulse duration of the signal of the first light emitting signal line and the second light emitting signal line. The pulses of the signals of the first light emitting signal line and the second light emitting signal line are adjustable, and the applicable range of the display substrate can be realized.

[0144] The pixel circuit is the pixel circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0145] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate. The display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited in the present disclosure.

[0146] In an exemplary embodiment, on a plane parallel to the display substrate, the display substrate may include: a plurality of sub-pixels, at least one sub-pixel may include: a pixel circuit and a light-emitting device, the pixel circuit being configured to output a corresponding current to the connected light-emitting device so that the light-emitting device emits light of corresponding brightness.

[0147] In an exemplary embodiment, the plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns. A plurality of sub-pixels arranged in sequence along the horizontal direction may be referred to as pixel rows, a plurality of sub-pixels arranged in sequence along the vertical direction may be referred to as pixel columns, and the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0148] In an exemplary embodiment, a plurality of sub-pixels constitute one pixel unit, and the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.

[0149] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. The shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure. In the direction of the pixel row, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in an aligned manner, and in the direction of the pixel column, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in a staggered manner to form a sub-pixel layout. For example, the first sub-pixel in an odd row may be located between the adjacent second and third sub-pixels in an even row, or the first sub-pixel in an even row may be located between the adjacent second and third sub-pixels in an odd row. For another example, the second subpixel in an odd-numbered row may be located between the adjacent first and third subpixels in an even-numbered row, or the second subpixel in an even-numbered row may be located between the adjacent first and third subpixels in an odd-numbered row. For another example, the third subpixel in an odd-numbered row may be located between the adjacent first and second subpixels in an even-numbered row, or the third subpixel in an even-numbered row may be located between the adjacent first and second subpixels in an odd-numbered row.

[0150] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light, and the shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which are not limited in the present disclosure. The four sub-pixels may be arranged in a square manner to form a GGRB pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a diamond manner to form an RGGB pixel arrangement.

[0151] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0152] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and a conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0153] In an exemplary embodiment, the light emitting structure layer includes: an anode conductive layer, a pixel definition layer, an organic structure layer and a cathode layer sequentially stacked on a substrate; the anode conductive layer includes: an anode, the organic structure layer includes: an organic light emitting layer, and the cathode layer includes: a cathode.

[0154] In an exemplary embodiment, Fig.10 and Fig.11 As shown, the second scanning signal line Gate2 electrically connected to the pixel circuit in the i-th row is electrically connected to the first scanning signal line Gate1 electrically connected to the pixel circuit in the i+1-th row, 1≤i≤M-1, M is the total number of pixel circuit rows.

[0155] In an exemplary embodiment, Fig.10 and Fig.11 As shown, the display substrate includes: a substrate and a circuit structure layer and a light emitting structure layer arranged on the substrate, the circuit structure layer includes: a plurality of pixel circuits, the light emitting structure layer includes: a plurality of light emitting devices, and the pixel circuit includes: a plurality of transistors and at least one capacitor;

[0156] The circuit structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially on the substrate;

[0157] The semiconductor layer includes at least: an active layer of a plurality of transistors;

[0158] The first conductive layer at least includes: a first electrode plate of a capacitor, control electrodes of a plurality of transistors, a first light emitting signal line EM1, a second light emitting signal line EM2, a first scanning signal line Gate1 and a second scanning signal line Gate2;

[0159] The second conductive layer at least includes: an initial signal line INIT and a second plate of the capacitor;

[0160] The third conductive layer includes at least: a first power line VDD, a data signal line Data and a signal connection line VL, the signal connection line VL is electrically connected to a first scanning signal line electrically connected to one pixel circuit and a second scanning signal line electrically connected to another pixel circuit in adjacent pixel circuits located in the same column.

[0161] In an exemplary embodiment, the circuit structure layer may further include: a plurality of insulating layers, the plurality of insulating layers including: a first insulating layer arranged between the semiconductor layer and the first conductive layer, a second insulating layer arranged between the first conductive layer and the second conductive layer, a third insulating layer between the second conductive layer and the third conductive layer, and a fourth insulating layer and a planarizing layer arranged in sequence on a side of the third conductive layer away from the substrate.

[0162] In an exemplary embodiment, Fig.10 As shown, the pixel circuit includes: a first transistor to a seventh transistor, and the seventh transistor is electrically connected to the second scanning signal line Gate2; the first scanning signal line Gate1 extends along the second direction Y, the second scanning signal line Gate2 extends along the first direction X, the second scanning signal line Gate2 is located on a side of the first scanning signal line Gate1 away from the second light-emitting signal line EM2, and the second scanning signal line Gate2 and the control electrode of the fourth transistor are arranged at intervals.

[0163] In an exemplary embodiment, Fig.10 As shown, the positive projection of the initial signal line INIT electrically connected to the j-th column of pixel circuits on the substrate is located between the positive projections of the data signal line Data electrically connected to the j-th column of pixel circuits and the first power line VDD electrically connected to the j+1-th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

[0164] In an exemplary embodiment, the second insulating layer and the third insulating layer are provided with a sixth via, an eighth via and a ninth via, the sixth via exposes the first scan signal line, the eighth via exposes the control electrode of the fourth transistor, the ninth via exposes the second scan signal line, the sixth via is located at one end of the first scan signal line, and a virtual straight line extending along the second direction passes through the eighth via and the ninth via.

[0165] In an exemplary embodiment, Fig.10 As shown, at least a portion of the signal connection line VL extends along the second direction Y, and the signal connection line VL is respectively electrically connected to the control electrode of the fourth transistor of the pixel circuit of the i-th row and j-th column, the second scanning signal line Gate2 electrically connected to the pixel circuit of the i-th row and j-th column, and the first scanning signal line Gate1 electrically connected to the pixel circuit of the i+1-th row and j-th column, 1≤i≤M-1.

[0166] In an exemplary embodiment, Fig.11 As shown, the pixel circuit includes: a first transistor to a seventh transistor, and the seventh transistor is electrically connected to the first scanning signal line Gate1, the first scanning signal line Gate1 and the second scanning signal line Gate2 extend along the first direction X, the second scanning signal line Gate2 is located on the side of the first scanning signal line Gate1 close to the second light-emitting signal line EM2, and the second scanning signal line Gate2 and the control electrode of the fourth transistor are an integrated structure.

[0167] In an exemplary embodiment, Fig.11 As shown, the positive projection of the initial signal line INIT electrically connected to the j-th column of pixel circuits on the substrate is located between the positive projections of the data signal line Data electrically connected to the j-th column of pixel circuits and the first power line VDD electrically connected to the j+1-th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

[0168] In an exemplary embodiment, Fig.11 As shown, the first conductive layer may further include: a first electrode connection block VE1, and the third conductive layer may further include: a second electrode connection block VE2. The first electrode connection block VE1 extends along the second direction Y and is electrically connected to the signal connection line VL; at least a portion of the second electrode connection block VE2 extends along the second direction Y, and the second electrode connection block VE2 is electrically connected to the first electrode connection block VE1 and the first scanning signal line Gate1, respectively.

[0169] In an exemplary embodiment, the second insulating layer and the third insulating layer are provided with a sixth via hole and a ninth via hole, the sixth via hole exposes the first electrode connecting block, the ninth via hole exposes the first scanning signal line, the number of the sixth via holes is two, and they are respectively located at both ends of the first electrode connecting block; a virtual straight line extending along the second direction passes through the sixth via hole and the ninth via hole.

[0170] In an exemplary embodiment, Fig.11 As shown, at least part of the signal connection line VL extends along the second direction Y, and the signal connection line VL is electrically connected to the control electrode of the fourth transistor of the pixel circuit in the i-th row and j-th column and the first electrode connection block VE1 of the pixel circuit in the i+1-th row and j-th column respectively.

[0171] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0172] The following is an explanation of the two-row and two-column pixel circuit Fig.10 and Fig.11 A process for preparing a display substrate is provided. A process for preparing a display substrate provided by an exemplary embodiment may include:

[0173] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on the substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern, such as Fig.12 As shown, Fig.12 for Fig.10 and Fig.11 A schematic diagram of a display substrate after a semiconductor layer pattern is formed is provided.

[0174] In an exemplary embodiment, Fig.12 As shown, Fig.10 and Fig.11 The semiconductor layer pattern in the provided display substrate may include at least: an active layer T11 of the first transistor to an active layer T71 of the seventh transistor. The active layer T11 of the first transistor to the active layer T71 of the seventh transistor may be an integrated structure connected to each other.

[0175] In an exemplary embodiment, Fig.12 As shown, in the second direction Y, the active layer T11 of the first transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T21 of the second transistor in the present sub-pixel, the active layer T41 of the fourth transistor, the active layer T61 of the sixth transistor, and the seventh transistor T71 may be located on the same side of the active layer T21 of the second transistor in the present sub-pixel, and the active layer T11 of the first transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T21 of the second transistor in the present sub-pixel. In the first direction Y, the active layer T11 of the first transistor, the active layer T31 of the third transistor, and the active layer T41 of the fourth transistor may be located on the same side of the active layer T31 of the third transistor in the present sub-pixel.

[0176] In an exemplary embodiment, Fig.12 As shown, the active layer T11 of the first transistor and the active layer T71 of the seventh transistor may be in the shape of a "7", the active layer T21 of the second transistor may be in the shape of a zigzag line, the active layer T31 of the third transistor may be in the shape of an "L" after being horizontally flipped, the active layer T41 of the fourth transistor may be in the shape of an "L" after being flipped to the left, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be in the shape of a linear shape extending along the second direction Y.

[0177] In an exemplary embodiment, Fig.12As shown, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor may serve as the first region T21_1 of the active layer T21 of the second transistor and the second region T51_2 of the active layer T51 of the fifth transistor, the second region T31_2 of the active layer T31 of the third transistor may serve as the first region T41_1 of the active layer T41 of the fourth transistor, and the second region T21_2 of the active layer T21 of the second transistor may serve as the second region T41 of the active layer T41 of the fourth transistor. Region T41_2 and the first region T61_1 of the active layer T61 of the sixth transistor, the second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor, the first region T11_1 of the active layer T11 of the first transistor, the first region T31_1 of the active layer T31 of the third transistor, the first region T51_1 of the active layer T51 of the fifth transistor and the first region T71_1 of the active layer T71 of the seventh transistor can be set separately.

[0178] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, such as Figures 13 to 16 As shown, Fig.13 for Fig.10 A schematic diagram of a first conductive layer pattern of a display substrate is provided, Fig.14 for Fig.10 A schematic diagram of a display substrate after a first conductive layer pattern is formed is provided, Fig.15 for Fig.11 A schematic diagram of a first conductive layer pattern of a display substrate is provided, Fig.16 for Fig.11 A schematic diagram of a display substrate after a first conductive layer pattern is formed is provided. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal layer.

[0179] In an exemplary embodiment, Figures 13 to 16 As shown, Fig.10 and Fig.11 The first conductive layer pattern of the provided display substrate may at least include: a first light emitting signal line EM1, a second light emitting signal line EM2, a first scanning signal line Gate1, a second scanning signal line Gate2, control electrodes T12 to T72 of the first transistor and a first plate C1 of the capacitor.

[0180] In an exemplary embodiment, Fig.15 and Fig.16 As shown, Fig.11 The provided first conductive layer pattern of the display substrate may further include: a first electrode connection block VE1.

[0181] In an exemplary embodiment, Figures 13 to 16 As shown, the shape of the first plate C1 of the capacitor can be rectangular, and the orthographic projection of the first plate C1 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor T2 on the substrate. In an exemplary embodiment, the first plate C1 of the capacitor can also serve as the control electrode T22 of the second transistor T2.

[0182] In an exemplary embodiment, Figures 13 to 16 As shown, the second light-emitting signal line EM2 extends along the first direction X, and the second light-emitting signal line EM2 can be located on the side of the first electrode plate C1 of the capacitor of the sub-pixel (also the control electrode T32 of the third transistor) close to the first light-emitting signal line EM1 electrically connected to the sub-pixel in the previous row. The area where the second light-emitting signal line EM2 overlaps with the active layer of the fifth transistor T5 serves as the control electrode T52 of the fifth transistor.

[0183] In an exemplary embodiment, Figures 13 to 16 As shown, the first light-emitting signal line EM1 extends along the first direction X. The first light-emitting signal line EM1 may be located on a side of the first electrode plate C1 of the capacitor of the sub-pixel close to the second light-emitting signal line EM2 electrically connected to the next row of sub-pixels. The area where the first light-emitting signal line EM1 overlaps with the active layer of the sixth transistor serves as the control electrode T62 of the sixth transistor.

[0184] In an exemplary embodiment, Fig.13 and Fig.14 As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line Gate2, the shape of the second scanning signal line Gate2 can be a linear shape extending along the first direction X, and the second scanning signal line Gate2 can be located on a side of the first light-emitting signal line EM1 away from the first electrode plate C1 of the capacitor. The area where the second scanning signal line Gate2 overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor.

[0185] In an exemplary embodiment, Fig.13 and Fig.14 As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line Gate2, the shape of the first scanning signal line Gate1 can be a linear shape extending along the second direction Y, and the first scanning signal line Gate1 can be located on the side where the first plate of the capacitor of the current sub-pixel is close to the first plate of the capacitor of the next column of sub-pixels.

[0186] In an exemplary embodiment, Fig.13 and Fig.14 As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line Gate2, the shapes of the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are line shapes extending along the first direction X, the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are located on the side of the first scanning signal line Gate1 away from the first electrode plate of the capacitor, and are electrically connected to the first scanning signal line Gate1 respectively, and the shape of the integrated structure formed by the control electrode T12 of the first transistor, the control electrode T32 of the third transistor and the first scanning signal line Gate1 can be an inverted "F" shape.

[0187] In an exemplary embodiment, Fig.13 and Fig.14 As shown, when the control electrode of the seventh transistor is electrically connected to the second scan signal line Gate2, the control electrode T42 of the fourth transistor is independently provided and may be in a linear shape extending along the first direction X.

[0188] In an exemplary embodiment, Fig.13 and Fig.14 As shown, the first light-emitting signal line EM1, the second light-emitting signal line EM2 and the second scanning signal line Gate2 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0189] In an exemplary embodiment, Fig.15 and Fig.16 As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line Gate1, the shape of the first scanning signal line Gate1 can be a linear shape extending along the first direction X, and the first scanning signal line Gate1 can be located on a side of the first light-emitting signal line EM1 away from the first electrode plate C1 of the capacitor. The area where the first scanning signal line Gate1 overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor.

[0190] In an exemplary embodiment, Fig.15 and Fig.16As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line Gate1, the shape of the second scanning signal line Gate2 can be a linear shape extending along the first direction X, and the second scanning signal line Gate2 is located between the second light-emitting signal line EM2 and the first light-emitting signal line EM1. The second scanning signal line Gate2 and the control electrode T42 of the fourth transistor are an integrally formed structure. The area where the second scanning signal line Gate2 overlaps with the active layer of the fourth transistor serves as the control electrode T42 of the fourth transistor.

[0191] In an exemplary embodiment, Fig.15 and Fig.16 As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line Gate1, the first electrode connection block VE1 extends along the second direction Y, the control electrode T12 of the first transistor and the control electrode T32 of the third transistor extend along the first direction X, and the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are located on a side of the first electrode connection block VE1 away from the first electrode plate C1 of the capacitor, and are electrically connected to the first electrode connection block VE1 respectively. The shape of the integrated structure formed by the control electrode T12 of the first transistor, the control electrode T32 of the third transistor and the first electrode connection block VE1 can be an inverted "F" shape.

[0192] In an exemplary embodiment, Fig.15 and Fig.16 As shown, the first light-emitting signal line EM1, the second light-emitting signal line EM2 and the first scanning signal line Gate1 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0193] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductor processing on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active layer of the first transistor to the active layer of the seventh transistor are both conductorized, and the second area of ​​the active layer of the first transistor after conductorization (also the first area of ​​the active layer of the second transistor and the second area of ​​the active layer of the fifth transistor) can simultaneously serve as the first transistor of the first transistor. The diode T14, the first electrode T23 of the second transistor and the second electrode T54 of the fifth transistor, the second region of the active layer of the second transistor after conductorization (also the second region T41_2 of the active layer T41 of the fourth transistor and the first region T61_1 of the active layer T61 of the sixth transistor) can simultaneously serve as the second electrode T24 of the second transistor, the second electrode T44 of the fourth transistor and the first electrode T63 of the sixth transistor, and the second region of the active layer of the third transistor after conductorization (also the first region of the active layer of the fourth transistor) can simultaneously serve as the second electrode of the third transistor and the first electrode of the fourth transistor.

[0194] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on the second insulating layer. Figures 17 to 19 As shown, Fig.17 for Fig.10 and Fig.11 A schematic diagram of a second conductive layer pattern of a display substrate is provided, Fig.18 for Fig.10 A schematic diagram of a display substrate after a second conductive layer pattern is formed is provided, Fig.19 for Fig.11 A schematic diagram of a display substrate after a second conductive layer pattern is formed is provided. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal layer.

[0195] In an exemplary embodiment, Figures 17 to 19 As shown, Fig.10 and Fig.11 The second conductive layer pattern in the provided display substrate may at least include: an initial signal line INIT and a second electrode plate C2 of the capacitor.

[0196] In an exemplary embodiment, Figures 17 to 19As shown, the shape of the capacitor can be a rectangle including a recessed area. The orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate. The recessed area on the second plate of the capacitor can be located at the edge of the second plate C1 of the capacitor, and exposes the second insulating layer covering the first plate of the capacitor, and the orthographic projection of the first plate of the capacitor on the substrate includes the orthographic projection of the recessed area on the substrate.

[0197] In an exemplary embodiment, Figures 17 to 19 As shown, the initial signal line INIT may include: an initial signal main body INIT1 extending along the second direction Y and an initial signal connection part INIT2 extending along the first direction X, the initial signal connection part INIT2 is located on a side of the initial signal main body INIT1 close to the second electrode plate of the capacitor, and is electrically connected to the initial signal main body INIT1.

[0198] In an exemplary embodiment, Figures 17 to 19 As shown, the dummy signal line extending along the first direction X passes through the initial signal connection portion INIT2 and the first region of the active layer of the seventh transistor.

[0199] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, such as Fig. 20 and Fig.21 As shown, Fig. 20 for Fig.10 A schematic diagram of a display substrate after a third insulating layer is formed is provided, Fig.21 for Fig.11 A schematic diagram of a display substrate after a third insulating layer is formed is provided.

[0200] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, Fig.10 and Fig.11 The multiple via holes of the third insulating layer in the provided display substrate may include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10 and an eleventh via hole V11. Fig. 20 and Fig.21 Except for the sixth via hole, the eighth via hole and the ninth via hole, the exposed structures and positions of the remaining via holes are the same.

[0201] In an exemplary embodiment, Fig. 20 and Fig.21As shown, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first area of ​​the active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first area of ​​the active layer of the first transistor through the via hole.

[0202] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first area of ​​the active layer of the third transistor, and the second via hole V2 is configured to connect the first electrode of the subsequently formed third transistor T3 to the first area of ​​the active layer of the third transistor through the via hole.

[0203] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the active layer of the fifth transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active layer of the fifth transistor through the via hole.

[0204] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the sixth transistor (also the second area of ​​the seventh transistor) on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the active layer of the sixth transistor (also the second area of ​​the seventh transistor), and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active layer of the sixth transistor (also the second area of ​​the seventh transistor) through the via hole.

[0205] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the active layer of the seventh transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active layer of the seventh transistor through the via hole.

[0206] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first electrode plate of the capacitor on the substrate, the second insulating layer in the seventh via hole V7 is etched away to expose the surface of the first electrode plate of the capacitor, and the eighth via hole V8 is configured to connect the first electrode of the subsequently formed first transistor to the first electrode plate of the capacitor through the via hole.

[0207] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the tenth via V10 exposes the surface of the second plate of the capacitor, and the tenth via V10 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second plate of the capacitor through the via.

[0208] In an exemplary embodiment, Fig. 20 and Fig.21 As shown, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the initial signal connection portion of the initial signal line on the substrate, the eleventh via V11 exposes the surface of the initial signal connection portion of the initial signal line, and the eleventh via V11 is configured to connect the first electrode of the subsequently formed seventh transistor to the initial signal connection portion of the initial signal line through the via.

[0209] In an exemplary embodiment, Fig. 20 As shown, when the control electrode of the seventh transistor is electrically connected to the second scan signal line, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first scan signal line on the substrate, the second insulating layer in the sixth via hole V6 is etched away, exposing the surface of the first scan signal line, and the sixth via hole V6 is configured to connect a subsequently formed signal connection line to the first scan signal line through the via hole. The sixth via hole V6 may be located at one end of the first scan signal line, and the number may be one, and it is located at one end of the first scan signal line.

[0210] In an exemplary embodiment, Fig. 20 As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor on the substrate, the second insulating layer in the eighth via V8 is etched away to expose the surface of the control electrode of the fourth transistor, and the eighth via V8 is configured to connect the subsequently formed signal connection line to the control electrode of the fourth transistor through the via.

[0211] In an exemplary embodiment, Fig. 20 As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second scanning signal line on the substrate, the second insulating layer in the ninth via hole V9 is etched away to expose the surface of the second scanning signal line, and the ninth via hole V9 is configured to connect the subsequently formed signal connection line to the second scanning signal line through the via hole.

[0212] In an exemplary embodiment, Fig. 20 As shown, a virtual straight line extending along the second direction Y passes through the first via hole V1 , the eighth via hole V8 , and the ninth via hole V9 .

[0213] In an exemplary embodiment, Fig.21 As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first electrode connection block on the substrate, and the second insulating layer in the sixth via hole V6 is etched away, exposing the surface of the control electrode of the first transistor (also the control electrode of the third transistor). There are two sixth via holes V6, which are respectively located at both ends of the first electrode connection block, one of which is configured to connect a subsequently formed signal connection line to the first electrode connection block through the via hole, and the other sixth via hole V6 is configured to connect a subsequently formed second electrode connection block to the first electrode connection block through the via hole.

[0214] In an exemplary embodiment, Fig.21 As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second scanning signal line (also the control electrode of the fourth transistor) on the substrate, and the second insulating layer in the eighth via V8 is etched away to expose the surface of the second scanning signal line (also the control electrode of the fourth transistor), and the eighth via V8 is configured to connect the subsequently formed signal connection line to the second scanning signal line (also the control electrode of the fourth transistor) through the via.

[0215] In an exemplary embodiment, Fig.21 As shown, when the control electrode of the seventh transistor is electrically connected to the first scanning signal line, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first scanning signal line on the substrate, the second insulating layer in the ninth via hole V9 is etched away to expose the surface of the first scanning signal line, and the ninth via hole V9 is configured to connect a subsequently formed connecting electrode to the first scanning signal line through the via hole.

[0216] In an exemplary embodiment, Fig.21 As shown, a virtual straight line extending along the second direction Y passes through the sixth via hole V6 and the ninth via hole V9.

[0217] In an exemplary embodiment, Fig.21 As shown, a virtual straight line extending along the second direction Y passes through the first via hole V1 and the eighth via hole V8.

[0218] (5) Forming a third conductive layer. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, Figure 22 to Figure 25 As shown, Fig. 22 for Fig.10 A schematic diagram of a third conductive layer pattern of a display substrate is provided, Fig.23 for Fig.10 A schematic diagram of a display substrate after a third conductive layer pattern is formed is provided, Fig.24 for Fig.11 A schematic diagram of a third conductive layer pattern of a display substrate is provided, Fig.25 for Fig.11 A schematic diagram of a display substrate after a third conductive layer pattern is formed is provided. In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal (SD) layer.

[0219] In an exemplary embodiment, Figure 22 to Figure 25 As shown, Fig.10 and Fig.11 The third conductive layer pattern in the provided display substrate may include at least: a data signal line Data, a first power line VDD, a signal connection line VL, a first electrode T13 of the first transistor, a first electrode T33 of the third transistor, a first electrode T53 of the fifth transistor, a second electrode T64 of the sixth transistor, a first electrode T73 and a second electrode T74 of the seventh transistor.

[0220] In an exemplary embodiment, Fig.24 and Fig.25 As shown, Fig.11 The third conductive layer pattern in the provided display substrate may further include: a second electrode connection block VE2.

[0221] In an exemplary embodiment, Figure 22 to Figure 25 As shown, the second electrode T64 of the sixth transistor can also serve as the second electrode T74 of the seventh transistor, and the first electrode T13 of the first transistor and the first electrode T73 of the seventh transistor can be separately provided. The first electrode T13 of the first transistor, the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) and the first electrode T73 of the seventh transistor are located between the first power line VDD and the data signal line Data.

[0222] In an exemplary embodiment, Figure 22 to Figure 25As shown, the orthographic projection of the first electrode T13 of the first transistor on the substrate at least partially overlaps the orthographic projection of the second electrode plate of the capacitor on the substrate. The first electrode T13 of the first transistor is electrically connected to the first region of the active layer of the first transistor through the first via hole, and is electrically connected to the first electrode plate of the capacitor through the seventh via hole.

[0223] In an exemplary embodiment, Figure 22 to Figure 25 As shown, the shape of the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) can be "L" shaped. The second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is electrically connected to the second region of the active layer of the sixth transistor (also the second region of the seventh transistor) through the fourth via hole, and is electrically connected to the second plate of the capacitor through the tenth via hole.

[0224] In an exemplary embodiment, Figure 22 to Figure 25 As shown, the first electrode T73 of the seventh transistor extends along the first square X, and the first electrode T73 of the seventh transistor is electrically connected to the first region of the active layer of the seventh transistor through the fifth via hole, and is electrically connected to the initial signal connection portion of the initial signal line through the eleventh via hole.

[0225] In an exemplary embodiment, Fig. 22 and Fig.25 As shown, the first power line VDD may extend along the second direction Y. The orthographic projection of the first power line VDD on the substrate may at least partially overlap with the orthographic projection of the third via on the substrate. The area where the first power line VDD overlaps with the third via may serve as the first electrode T53 of the fifth transistor, and the first power line VDD is electrically connected to the first area of ​​the active layer of the fifth transistor through the third via.

[0226] In an exemplary embodiment, Figure 22 to Figure 25 As shown, the data signal line Data may extend along the second direction Y. The orthographic projection of the data signal line Data on the substrate may at least partially overlap with the orthographic projection of the second via hole on the substrate. The area where the data signal line Data overlaps with the second via hole may serve as the first electrode T33 of the third transistor, and the data signal line Data is electrically connected to the first area of ​​the active layer of the third transistor through the second via hole.

[0227] In an exemplary embodiment, Figure 22 to Figure 25 As shown, the positive projection of the initial signal line electrically connected to the Nth column pixel circuit on the substrate is located between the positive projections of the data signal line Data electrically connected to the Nth column pixel circuit and the first power line VDD electrically connected to the N+1th column pixel circuit on the substrate.

[0228] In an exemplary embodiment, Fig. 22 and Fig.23As shown, when the control electrode of the seventh transistor is electrically connected to the second scanning signal line, the signal connection line VL is electrically connected to the control electrode of the fourth transistor in the i-th row and j-th column pixel circuit through the eighth via hole of the i-th row and j-th column pixel circuit, is electrically connected to the second scanning signal line electrically connected to the i-th row and j-th column pixel circuit through the ninth via hole of the i-th row and j-th column pixel circuit, and is electrically connected to the first scanning signal line electrically connected to the i+1-th row and j-th column pixel circuit through the sixth via hole of the i+1-th row and j-th column pixel circuit.

[0229] In an exemplary embodiment, Fig.24 and Fig.25 As shown, when the control electrode of the seventh transistor is electrically connected to the instrument scanning signal line, the signal connection line VL is electrically connected to the control electrode of the fourth transistor of the i-th row and j-th column pixel circuit through the eighth via hole of the i-th row and j-th column pixel circuit, and is electrically connected to the first electrode connection block of the i+1-th row and j-th column pixel circuit through one of the sixth via holes of the i+1-th row and j-th column pixel circuit.

[0230] In an exemplary embodiment, Fig.24 and Fig.25 As shown, at least a portion of the second electrode connection block VE2 extends along the second direction Y, and the second electrode connection block VE2 is electrically connected to the first electrode connection block through another sixth via hole, and is electrically connected to the first scan signal line through a ninth via hole.

[0231] In an exemplary embodiment, the data signal line Data and the first power line VDD can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0232] (6) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: coating a fourth insulating film and a planar film on the substrate on which the aforementioned pattern is formed, patterning the planar film using a patterning process, and forming a fourth insulating layer covering the third conductive layer pattern and a planar layer covering the fourth insulating layer.

[0233] At this point, the substrate is prepared Fig.10 and Fig.11 A circuit structure layer of a display substrate is provided. In a plane parallel to the display substrate, the circuit structure layer further includes: a plurality of pixel circuits, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of first light-emitting signal lines, a plurality of second light-emitting signal lines, a plurality of initial signal lines, a plurality of data signal lines, and a plurality of first power supply lines. In a plane perpendicular to the display substrate, the circuit structure layer can be arranged on a substrate, and the substrate can include a first flexible layer, a barrier layer, a substrate conductive layer, and a second flexible layer stacked together.

[0234] The circuit structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer and a flat layer arranged in sequence on the substrate. The semiconductor layer may include at least the active layer of the first transistor to the seventh transistor, the first conductive layer may include at least the first light-emitting signal line, the second light-emitting signal line, the first scanning signal line, the second scanning signal line, the control electrode of the first transistor to the control electrode of the seventh transistor and the first electrode plate of the capacitor, the second conductive layer may include at least the initial signal line and the second electrode plate of the capacitor, and the third conductive layer may include at least the data signal line, the first power line, the signal connection line and the first electrode and the second electrode of some transistors.

[0235] In an exemplary embodiment, the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0236] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer, and the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer. The planar layer may be made of an organic material, such as a resin, etc.

[0237] In an exemplary embodiment, after the circuit structure layer is prepared, a light emitting structure layer is prepared on the circuit structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0238] (7) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns.

[0239] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0240] (8) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein a pixel opening is provided on the pixel definition layer of each sub-pixel, and the pixel definition film in the pixel opening is removed to expose the anode of the sub-pixel.

[0241] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode layer on the organic light-emitting layer, and then forming an encapsulation structure layer, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0242] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0243] The embodiment of the present disclosure further provides a method for driving a pixel circuit. The pixel circuit is set to be driven. The method for driving a pixel circuit provided by the embodiment of the present disclosure may include the following steps:

[0244] Step 100, under the control of the signals of the first scan signal line and the second scan signal line, the node control subcircuit provides the signal of the second node to the first node, provides the signal of the data signal line to the third node, provides the signal of the initial signal line to the fourth node, and stores the voltage difference between the signals of the first node and the fourth node.

[0245] Step 200: Under the control of the signals at the first node and the second node, the driving sub-circuit provides a driving current to the third node.

[0246] Step 300: Under the control of the first light-emitting signal line and the second light-emitting signal line, the light-emitting control subcircuit provides the signal of the third node to the fourth node, and provides the signal of the first power line to the second node.

[0247] The embodiment of the present disclosure further provides a display device, including: a display substrate.

[0248] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0249] In an exemplary embodiment, the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0250] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0251] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0252] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A pixel circuit, characterized in that: The pixel circuit is configured to drive the light-emitting device to emit light, the pixel circuit includes: a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; the node control subcircuit includes: a writing subcircuit; The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node; The light-emitting control subcircuit is electrically connected to the second node, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first power line, respectively, and is configured to provide a signal of the third node to the fourth node and a signal of the first power line to the second node under the control of the first light-emitting signal line and the second light-emitting signal line; The node control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the initial signal line, the first node, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the second node to the first node, provide the signal of the data signal line to the third node, provide the signal of the initial signal line to the fourth node, and store the voltage difference between the signals of the first node and the fourth node under the control of the signals of the first scan signal line and the second scan signal line; The writing subcircuit is electrically connected to the first scanning signal line, the second scanning signal line, the data signal line and the third node respectively, and is configured to provide the signal of the data signal line to the third node under the control of the signal of the first scanning signal line and the second scanning signal line; The light emitting device is electrically connected to the fourth node and the second power line respectively.

2. The pixel circuit according to claim 1, characterized in that: The node control subcircuit further includes: a reset subcircuit, a compensation subcircuit and a storage subcircuit; The compensation subcircuit is electrically connected to the first scan signal line, the first node and the second node respectively, and is configured to provide a signal of the second node to the first node under the control of the first scan signal line; The reset subcircuit is electrically connected to one of the first scan signal line and the second scan signal line, the initial signal line and the fourth node respectively, and is configured to provide the signal of the initial signal line to the fourth node under the control of the signal of one of the first scan signal line and the second scan signal line; The storage sub-circuit is electrically connected to the first node and the fourth node, respectively, and is configured to store a voltage difference between the signals of the first node and the fourth node.

3. The pixel circuit according to claim 2, characterized in that: The writing sub-circuit comprises: a third transistor and a fourth transistor; A control electrode of the third transistor is electrically connected to one of the first scan signal line and the second scan signal line, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor; A control electrode of the fourth transistor is electrically connected to the other of the first scanning signal line and the second scanning signal line, and a second electrode of the fourth transistor is electrically connected to the data signal line.

4. The pixel circuit according to claim 3, characterized in that: The compensation subcircuit includes: a first transistor, the storage subcircuit includes: a capacitor, the capacitor includes: a first plate and a second plate, and the reset subcircuit includes: a seventh transistor; A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the second node; A control electrode of the seventh transistor is electrically connected to one of the first scan signal line and the second scan signal line, a first electrode of the seventh transistor is electrically connected to the initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the fourth node.

5. The pixel circuit according to claim 4, characterized in that: The driving subcircuit includes: a second transistor, and the light emitting control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the second light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power line, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

6. The pixel circuit according to claim 1 or 5, characterized in that: The duration of the signal of the first scanning signal line being a valid level signal includes: a first time period and a second time period that occur sequentially and continuously, and the duration of the signal of the second scanning signal line being a valid level signal includes: a third time period and a fourth time period that occur sequentially and continuously, the sum of the first time period and the second time period is equal to the sum of the third time period and the fourth time period, and the second time period and the third time period at least partially overlap; When the signal of the first scanning signal line is a valid level signal, the signal of the first light-emitting signal line is an invalid level signal; when the signal of the second scanning signal line is a valid level signal, the signal of the second light-emitting signal line is an invalid level signal; The duration that the signal of the first scanning signal line is a valid level signal is equal to the duration that the signal of the second scanning signal line is a valid level signal, the duration that the signal of the first light-emitting signal line is an invalid level signal is equal to the duration that the signal of the second light-emitting signal line is an invalid level signal, and the duration that the signal of the first light-emitting signal line is an invalid level signal is greater than or equal to the duration that the signal of the first scanning signal line is a valid level signal.

7. The pixel circuit according to claim 5, characterized in that: The first transistor to the seventh transistor are N-type transistors.

8. A display substrate, characterized in that: include: A plurality of pixel circuits according to any one of claims 1 to 7, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of first light-emitting signal lines, a plurality of second light-emitting signal lines, a plurality of initial signal lines, a plurality of first power lines, a plurality of data signal lines, a first gate driving circuit and a second gate driving circuit arranged in an array, wherein the first light-emitting signal lines and the second light-emitting signal lines extend along a first direction, the initial signal lines, the first power lines and the data signal lines extend along a second direction, and the first direction intersects the second direction; The first gate driving circuit is electrically connected to a plurality of first scanning signal lines and a plurality of second scanning signal lines respectively; the second gate driving circuit is electrically connected to a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines respectively.

9. The display substrate according to claim 8, characterized in that: The second scanning signal line electrically connected to the pixel circuit in the i-th row is electrically connected to the first scanning signal line electrically connected to the pixel circuit in the i+1-th row, 1≤i≤M-1, M is the total number of pixel circuit rows.

10. The display substrate according to claim 8 or 9, characterized in that: The display substrate comprises: a substrate, and a circuit structure layer and a light emitting structure layer arranged on the substrate, wherein the circuit structure layer comprises: a plurality of pixel circuits, the light emitting structure layer comprises: a plurality of light emitting devices, and the pixel circuit comprises: a plurality of transistors and at least one capacitor; The circuit structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially on a substrate; The semiconductor layer at least includes: an active layer of a plurality of transistors; The first conductive layer at least includes: a first electrode plate of a capacitor, control electrodes of a plurality of transistors, a first light-emitting signal line, a second light-emitting signal line, a first scanning signal line, and a second scanning signal line; The second conductive layer at least includes: an initial signal line and a second plate of a capacitor; The third conductive layer includes at least: a first power line, a data signal line and a signal connection line, wherein the signal connection line is electrically connected to a first scanning signal line electrically connected to one pixel circuit and a second scanning signal line electrically connected to another pixel circuit in adjacent pixel circuits located in the same column.

11. The display substrate according to claim 10, characterized in that: The pixel circuit comprises: a first transistor to a seventh transistor, and the seventh transistor is electrically connected to the second scanning signal line; The first scanning signal line extends along the second direction, the second scanning signal line extends along the first direction, the second scanning signal line is located at a side of the first scanning signal line away from the second light-emitting signal line, and the second scanning signal line and the control electrode of the fourth transistor are spaced apart; The positive projection of the initial signal line electrically connected to the jth column of pixel circuits on the substrate is located between the positive projections of the data signal line electrically connected to the jth column of pixel circuits and the first power line electrically connected to the j+1th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

12. The display substrate according to claim 11, characterized in that: At least a portion of the signal connection line extends along the second direction, and the signal connection line is respectively electrically connected to the control electrode of the fourth transistor of the i-th row and j-th column pixel circuit, the second scanning signal line electrically connected to the i-th row and j-th column pixel circuit, and the first scanning signal line electrically connected to the i+1-th row and j-th column pixel circuit, 1≤i≤M-1.

13. The display substrate according to claim 10, characterized in that: The pixel circuit includes: a first transistor to a seventh transistor, and the seventh transistor is electrically connected to the first scanning signal line. The first scanning signal line and the second scanning signal line extend along a first direction, the second scanning signal line is located on a side of the first scanning signal line close to the second light-emitting signal line, and the second scanning signal line and the control electrode of the fourth transistor are integrally formed; The positive projection of the initial signal line electrically connected to the jth column of pixel circuits on the substrate is located between the positive projections of the data signal line electrically connected to the jth column of pixel circuits and the first power line electrically connected to the j+1th column of pixel circuits on the substrate, 1≤j≤N, N is the total number of columns of pixel circuits.

14. The display substrate according to claim 13, characterized in that: The first conductive layer further includes: a first electrode connection block, and the third conductive layer further includes: a second electrode connection block; The first electrode connection block extends along the second direction and is electrically connected to the signal connection line; At least a portion of the second electrode connection block extends along the second direction, and the second electrode connection block is electrically connected to the first electrode connection block and the first scan signal line respectively.

15. The display substrate according to claim 14, characterized in that: At least part of the signal connection line extends along the second direction, and the signal connection line is electrically connected to the control electrode of the fourth transistor of the pixel circuit of the i-th row and j-th column and the first electrode connection block of the pixel circuit of the i+1-th row and j-th column respectively.

16. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 8 to 15.

17. A method for driving a pixel circuit, characterized in that: The method is configured to drive the pixel circuit according to any one of claims 1 to 7, the method comprising: Under the control of the signals of the first scanning signal line and the second scanning signal line, the node control subcircuit provides the signal of the second node to the first node, provides the signal of the data signal line to the third node, provides the signal of the initial signal line to the fourth node, and stores the voltage difference between the signals of the first node and the fourth node; Under the control of the signals at the first node and the second node, the driving subcircuit provides a driving current to the third node; Under the control of the first light-emitting signal line and the second light-emitting signal line, the light-emitting control subcircuit provides the signal of the third node to the fourth node, and provides the signal of the first power line to the second node.

Images