A semiconductor manufacturing method with a copper diffusion preventing structure

Abstract

The embodiment of the present application discloses a semiconductor manufacturing method with a copper diffusion barrier layer structure, comprising: depositing a dielectric layer; etching the dielectric layer to open a groove; depositing a first diffusion barrier layer in the groove; forming a copper metal layer above the first diffusion barrier layer; grinding the copper metal layer to present a disc type structure; depositing a second diffusion barrier layer on the surface of the copper metal layer by a deposition method with a negative bias; and grinding the second diffusion barrier layer. The present application can completely prevent the hole phenomenon by depositing the metal barrier layer in the copper wire process in the form of a process with a negative bias and covering the exposed copper metal surface after chemical grinding, forming a full-enclosing structure with the side and bottom to the copper metal, effectively inhibiting the copper diffusion phenomenon caused by the hole problem, preventing copper pollution in the subsequent process, and ensuring the product yield and device performance.

Description

Technical Field

[0001] This application relates to a semiconductor manufacturing method, specifically a semiconductor manufacturing method having a structure that prevents copper diffusion. Background Technology

[0002] As the integration density of integrated circuits continues to increase, the performance of Al as an interconnect material is no longer sufficient to meet the requirements of integrated circuits. Cu, with its lower resistivity and higher electromigration resistance compared to Al, is widely used in deep submicron technology. However, Cu is also a major cause of device failure, mainly because Cu is a heavy metal that can rapidly diffuse in semiconductor silicon wafers and silicon dioxide under high temperature and electric field conditions, causing problems with device reliability. Therefore, a diffusion barrier layer material, such as TaN, TiSiN, or Ta, must be added between the Cu wiring layer and the dielectric isolation layer to prevent Cu diffusion.

[0003] Meanwhile, as chip integration density increases, interconnect leads become thinner, narrower, and more precise, resulting in higher current densities. Under high current densities, metal atoms in the interconnect leads migrate along the direction of electron movement; this phenomenon is called electromigration (EM). Electromigration can cause open or short circuits in the interconnect leads during operation, and is a significant mechanism leading to integrated circuit failure. Therefore, adding a diffusion barrier layer between the Cu wiring layer and the dielectric isolation layer can prevent Cu electromigration and also improve the adhesion between Cu and the dielectric isolation layer.

[0004] For the reasons mentioned above, copper interconnects are frequently used in semiconductor manufacturing processes below 90nm to reduce resistance. Copper interconnects are typically achieved using the damascus process, which involves first forming trenches in the dielectric layer, then electroplating copper into these trenches. This patterning of copper interconnects is achieved through the trenches in the dielectric layer, without the need for etching the copper layer itself. The most significant characteristic of damascene technology is that it eliminates the need for etching the metal layer. When the material of the metal conductor changes from aluminum to copper, which has a lower resistivity, dry etching of copper is quite difficult; therefore, damascene technology becomes extremely important for copper processes.

[0005] refer to Figures 1A to 1C These are schematic diagrams illustrating the electroplating copper process, grinding process, and barrier layer deposition process in the existing Damascus steel process. Figure 1A As shown, the copper-filling process typically employs electroplated copper (ECP) technology. Before electroplating, a copper seed layer A1 needs to be formed. Simultaneously, to prevent copper from diffusing into the dielectric layer A3 (such as an interlayer film), a copper diffusion barrier layer A2 needs to be formed before the formation of the copper seed layer A1. The electroplating of copper... Figures 1A to 1CIt is represented by the copper metal layer Cu.

[0006] Next, as Figure 1B As shown, after the electroplating copper (ECP) process, a chemical mechanical polishing (CMP) process is used to planarize the surface, exposing the dielectric layer A3 and the copper metal layer Cu. During CMP, because the polishing rate of metallic copper is faster than that of the dielectric layer A3, after surface planarization, the dielectric layer A3 and the copper metal layer Cu are not on the same horizontal plane, but rather exhibit a dish-shaped concave structure (referred to as a dish structure). Figure 1B The recessed portion above the semiconductor is shown. Next, as... Figure 1C As shown, the presence of the "disc-like" structure causes voids to form at the corners during the subsequent deposition of the copper diffusion barrier layer A2, as shown by void H1. At high temperatures, copper diffuses through void H1, affecting process yield and device performance. Therefore, a novel copper interconnect process is needed to improve semiconductor manufacturing yield and device performance. Summary of the Invention

[0007] To address the above issues, this application employs a semiconductor manufacturing method with a copper diffusion prevention structure and real-time detection capabilities, which effectively improves upon the problems of the prior art.

[0008] Specifically, this application discloses a semiconductor manufacturing method with a copper diffusion prevention structure, comprising: depositing a dielectric layer; etching the dielectric layer to create trenches; depositing a first diffusion barrier layer in the trenches; forming a copper metal layer above the first diffusion barrier layer; polishing the copper metal layer, wherein the copper metal layer and the dielectric layer are not at the same height after polishing; depositing a second diffusion barrier layer on the surface of the copper metal layer using a negative bias deposition method; and polishing the second diffusion barrier layer.

[0009] Optionally, in some embodiments of this application, the semiconductor manufacturing method further includes: sequentially depositing an adhesive layer and a copper seed layer on the first diffusion barrier layer.

[0010] Optionally, in some embodiments of this application, the semiconductor manufacturing method further includes: forming a copper filler layer over the copper seed layer to serve as a copper metal layer.

[0011] Optionally, in some embodiments of this application, the copper filler layer is electroplated onto the copper seed layer using the ECP method.

[0012] Optionally, in some embodiments of this application, the polishing of the copper metal layer is chemical mechanical polishing to give the copper metal layer the recessed structure.

[0013] Optionally, in some embodiments of this application, the second diffusion barrier layer is ground to the same height as the dielectric layer.

[0014] Optionally, in some embodiments of this application, the material of either the first diffusion barrier layer or the second diffusion barrier layer is one of the following materials: tantalum, tantalum nitride, titanium, titanium nitride, titanium tungstenide, tungsten, tungsten nitride, titanium-titanium nitride, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride, and silicon nitride.

[0015] Optionally, in some embodiments of this application, the material of either the first diffusion barrier layer or the second diffusion barrier layer is composed of at least two of tantalum nitride, tantalum, and ruthenium.

[0016] Optionally, in some embodiments of this application, the deposition of either the first diffusion barrier layer or the second diffusion barrier layer is performed by at least one of the following processes: physical vapor deposition, chemical vapor deposition, atomic layer deposition, and metal-organic chemical vapor deposition.

[0017] Optionally, in some embodiments of this application, the thickness of either the first diffusion barrier layer or the second diffusion barrier layer is 0.5 nm to 200 nm.

[0018] In summary, this application discloses a copper diffusion barrier layer structure and its preparation method. In the copper wire process, a metal barrier layer is deposited in the form of a negative bias voltage and covers the exposed copper metal surface after chemical mechanical polishing. Together with the sides and bottom, it forms a "fully enclosed structure" for the copper metal, which can completely prevent the phenomenon of voids. Therefore, it can effectively suppress the copper diffusion phenomenon caused by voids, thereby preventing copper contamination in subsequent processes and ensuring product yield and device performance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the following description of the embodiments will be briefly introduced. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figures 1A to 1C These are schematic diagrams of the electroplating copper process, grinding process, and barrier layer deposition process in the existing damascus process.

[0021] Figures 2A to 2G These are schematic diagrams of each stage of the semiconductor manufacturing method in this application.

[0022] Figure 3 This is a schematic diagram of the ionization PVD principle of this application.

[0023] Figure 4 For the corresponding Figures 2A to 2G A flowchart of a semiconductor manufacturing process.

[0024] Explanation of the labels in the diagram:

[0025] 1: Power supply; 2: Metal target; 3: Argon plasma; 4: Radio frequency power supply; 5: Silicon wafer; 6: Silicon wafer holder; 7: Substrate power supply; A1: Copper seed layer; A3: Dielectric layer; A2: Copper diffusion barrier layer; Cu: Copper metal layer; H1: Hole; D1: Dielectric layer; D2: First diffusion barrier layer; D3: Adhesive layer; D4: Copper seed layer; D5: Second diffusion barrier layer; S302-S314: Steps. Detailed Implementation

[0026] The following embodiments are merely illustrative examples, as various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims. Throughout the specification and claims, unless explicitly specified, the terms "a" and "described" include a description comprising "a or at least one" of the stated components or ingredients. Furthermore, as used in this disclosure, the singular article also includes a description of a plurality of components or ingredients unless clearly excluded from the specific context. Moreover, when applied in this description and all the following claims, unless explicitly specified, "in which" may include both "in which" and "therein". The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the art, in the content of this disclosure, and in the specific context. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this disclosure. Examples found anywhere in this specification, including examples of any terms used in discussion herein, are merely illustrative and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0027] The terms “approximately,” “about,” or “nearly” as used herein should generally mean that a given value or error range is within 20%, preferably within 10%. Furthermore, the quantities provided herein may be approximate, and therefore mean that unless otherwise stated, they may be expressed using the terms “approximately,” “about,” or “nearly.” When a quantity, concentration, or other numerical value or parameter has a specified range, preferred range, or lists upper and lower ideal values, it should be considered as specifically disclosing all ranges consisting of any pairs of upper and lower limits or ideal values, regardless of whether such ranges are separately disclosed. For example, if a range of length X cm to Y cm is disclosed, it should be considered as disclosing a length of H cm, where H can be any real number between X and Y.

[0028] Furthermore, "electrical coupling" or "electrical connection" herein includes any direct and indirect means of electrical connection. For example, if a first device is described as electrically coupled to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. Additionally, in descriptions concerning the transmission or provision of electrical signals, those skilled in the art will understand that attenuation or other non-ideal variations may occur during the transmission of electrical signals, but unless otherwise specified, the source and receiver of the transmitted or provided electrical signal should be considered substantially the same signal. For example, if an electrical signal S is transmitted (or provided) from terminal A of an electronic circuit to terminal B of the same electronic circuit, a voltage drop may occur across the source and drain of a transistor switch and / or possible stray capacitance. However, unless the purpose of this design is to intentionally utilize attenuation or other non-ideal variations during transmission to achieve certain specific technical effects, the electrical signal S at terminals A and B of the electronic circuit should be considered substantially the same signal.

[0029] It is understood that terms such as “comprising,” “having,” and “containing,” as used herein, are open-ended terms, meaning including but not limited to. Furthermore, no embodiment or claim of this application is required to achieve all the purposes, advantages, or features disclosed herein. In addition, the abstract and headings are merely illustrative of patent document searches and are not intended to limit the scope of this application.

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings, while "inner" and "outer" refer to the outline of the device.

[0031] Please refer to the figures in the accompanying drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments illustrated in this application and should not be construed as limiting other specific embodiments not detailed herein.

[0032] Copper is harmful to transistors, so when using copper interconnect technology, it is essential to prevent copper diffusion into the transistors. Therefore, in the "Damask" process, an ionized physical vapor deposition (I-PVD) layer is deposited before copper filling. This application provides a copper diffusion barrier layer structure and its fabrication method in semiconductor manufacturing, solving the problem of dish-shaped recessed structures in chemical mechanical polishing (CMP) copper wire processes. It is particularly noteworthy that the dish-shaped structure is formed because the dielectric layer and the copper layer are not on the same horizontal plane. In the CMP process, because the polishing rate of metallic copper is faster than that of the dielectric layer, after surface planarization, the dielectric layer and the copper metal layer are not at the same height (not on the same horizontal plane), resulting in a dish-shaped structure. Furthermore, a metal barrier layer is deposited on the copper surface after CMP with a negative bias to fully cover the copper metal surface, ensuring sufficient deposition at the corners of the "dish-shaped structure," thereby avoiding the formation of voids at the corners during copper diffusion barrier layer deposition in existing technologies. Finally, CMP is used to planarize the barrier layer surface and polish down to the dielectric layer, completing the overall semiconductor manufacturing process. It should be noted that in the following description, copper is mainly used as the metal for deposition in this application, but other metals can also be used in this application.

[0033] The detailed implementation method of this application is described below.

[0034] Please refer to Figures 2A to 2G , Figures 2A to 2G The diagrams shown are schematic diagrams of each stage of the semiconductor manufacturing method (or Damascus process) of this application, and are described in detail below.

[0035] First, the steps are the same as in existing technologies, such as Figure 2A As shown, a dielectric layer is deposited first; then, as... Figure 2B As shown, the deposited dielectric layer is etched to create trenches; next, as... Figure 2C As shown, a first diffusion barrier layer D2, an adhesive layer D3, and a copper seed layer D4 are sequentially deposited on the dielectric layer D1. The first diffusion barrier layer D2 can be deposited using at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD), and its thickness can range from 0.5 nm to 200 nm, but this application is not limited to this. Furthermore, the first diffusion barrier layer D2 can be an etching stop layer and / or a CMP stop layer, such as silicon nitride (SiN) or silicon oxycarbide (SiCO). The copper seed layer D4 can be deposited using PVD or ALD methods, and its thickness ranges from 0.5 nm to 1000 nm.

[0036] Next step, such as Figure 2D As shown, copper seed layer D4 is subjected to an electroplating process, such as ECP plating with a thickness of 200nm–3000nm, or copper is deposited on top of copper seed layer D4 using a chemical method to form a copper filler layer. Since the copper filler layer is only deposited on copper seed layer D4 in the trench and both are of similar material, for simplicity... Figure 2D The subsequent diagrams refer to the copper seed layer D4 and the copper filler layer collectively as the copper metal layer Cu. Next, as... Figure 2E As shown, highly selective copper chemical mechanical polishing slurry (Cu-CMP slurry) can be further used to... Figure 2D The copper metal layer Cu that protrudes after deposition is ground to form a dish-shaped structure. In this application, the term "chemical mechanical polishing" refers to a process that includes both chemical and mechanical polishing, because CMP (chemical mechanical polishing) combines chemical and mechanical polishing, and both chemical and mechanical processes are used simultaneously for polishing metallic materials. For example, an oxidizing agent is first used to form a low-hardness metal oxide on the metal surface, and then mechanical force is used to grind away the metal oxide. Afterwards, in... Figure 2FIn this invention, a second diffusion barrier layer D5 is deposited on the surface of the copper metal layer Cu after chemical mechanical polishing in the copper wire process using a negative bias deposition method, thereby fully covering the exposed copper metal surface. The second diffusion barrier layer D5 is a copper diffusion barrier layer, which can be achieved through physical vapor deposition, but this application is not limited to this method. Because a negative bias deposition method is used, the dish-shaped structure resulting from the different polishing rates of the dielectric layer and the copper metal layer does not exhibit the void problem encountered in existing technologies.

[0037] Finally, as Figure 2G As shown, for Figure 2F The second diffusion barrier layer D5, which protrudes after deposition, is ground to make it flat; more precisely, the second diffusion barrier layer D5 is made to be at the same height as the dielectric layer D1. Similar to the first diffusion barrier layer D2, the second diffusion barrier layer D5 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or metal-organic chemical vapor deposition, and its thickness can be 0.5 nm to 200 nm, but this application is not limited to this.

[0038] The materials of the first diffusion barrier layer D2 and the second diffusion barrier layer D5 may include, but are not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungstenide (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium nitride (Ti-TiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN), and silicon nitride. In some embodiments, the materials of the first diffusion barrier layer D2 and the second diffusion barrier layer D5 may be composed of at least two of tantalum nitride, tantalum, and ruthenium.

[0039] For information on depositing metal barrier layers using negative bias, please refer to [link / reference]. Figure 3 This diagram illustrates the principle of ionization PVD in this application. First, argon gas is introduced into the process chamber. The metal target 2 is connected to the power supply 1, creating an argon plasma 3 between the metal target and the silicon wafer. Argon ions bombard the metal target, sputtering metal atoms from the target and depositing them onto the silicon wafer 5. In the inductively coupled ionization PVD process, a metal coil is added around the argon plasma and connected to an RF power supply 4 to increase the plasma density through inductive coupling, thereby increasing the ionization rate of the metal atoms. The silicon wafer holder 6 is connected to the substrate power supply 7, allowing a negative bias voltage to be applied to the silicon wafer surface. Under the attraction of the negative bias voltage, positive metal ions deposit onto the silicon wafer 5 in a more perpendicular direction, thus better covering the bottom and sidewalls of the trenches.

[0040] In summary, this application discloses a semiconductor manufacturing method with a copper diffusion barrier layer structure. In the copper wire process, a metal barrier layer is deposited in the form of a negative bias voltage and covers the exposed copper metal surface after chemical mechanical polishing. Together with the sides and bottom, it forms a "fully enclosed structure" for the copper metal, which can completely prevent the phenomenon of voids. Therefore, it can effectively suppress the copper diffusion phenomenon caused by void problems, thereby preventing copper contamination in subsequent processes and ensuring product yield and device performance.

[0041] Please refer to Figure 4 , which is the corresponding Figures 2A to 2G A flowchart of a semiconductor manufacturing method, including the following steps:

[0042] Step S302: Deposit medium layer;

[0043] Step S304: Etch the deposited dielectric layer to create trenches;

[0044] Step S306: Sequentially deposit the first diffusion barrier layer, the adhesive layer, and the copper seed layer in the trench;

[0045] Step S308: A copper filler layer is formed above the copper seed layer to serve as a copper metal layer;

[0046] Step S310: Grind the deposited copper metal layer to make it present a dish-shaped structure;

[0047] Step S312: Deposit a second diffusion barrier layer on the surface of the copper metal layer using a negative bias deposition method;

[0048] Step S314: Grind the second diffusion barrier layer to make it the same height as the dielectric layer.

[0049] Please note that as long as the same / similar effects can be achieved, this application does not limit the requirement to completely follow the above steps. For example, some additional steps can be inserted, and some steps can be omitted under certain conditions.

[0050] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The embodiments described above are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort, except for designs consistent with the solutions of the embodiments of this application mentioned in this application, are within the scope of protection of this application.

[0051] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0052] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A semiconductor manufacturing method with a structure to prevent copper diffusion, characterized in that, include: Deposition medium layer; The dielectric layer is etched to create trenches; A first diffusion barrier layer is deposited in the trench; A copper metal layer is formed above the first diffusion barrier layer; The copper metal layer is polished, wherein the copper metal layer and the dielectric layer are not at the same height after polishing; A second diffusion barrier layer is deposited on the surface of the copper metal layer using a negative bias deposition method; as well as The second diffusion barrier layer is ground, and together with the side and bottom surfaces of the first diffusion barrier layer, they form a fully enclosed structure around the copper metal layer.

2. The semiconductor manufacturing method according to claim 1, characterized in that, Also includes: An adhesive layer and a copper seed layer are sequentially deposited on the first diffusion barrier layer.

3. The semiconductor manufacturing method according to claim 2, characterized in that, Also includes: A copper filler layer is formed above the copper seed layer to serve as a copper metal layer.

4. The semiconductor manufacturing method according to claim 3, characterized in that, The copper filler layer is electroplated onto the copper seed layer using the ECP method.

5. The semiconductor manufacturing method according to claim 3, characterized in that, The polishing of the copper metal layer is chemical mechanical polishing, which causes the copper metal layer to have a concave structure.

6. The semiconductor manufacturing method according to claim 1, characterized in that, After being polished, the second diffusion barrier layer is at the same height as the dielectric layer.

7. The semiconductor manufacturing method according to claim 1, characterized in that, The material of either the first diffusion barrier layer or the second diffusion barrier layer is one of the following: tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, tungsten, tungsten nitride, titanium-titanium nitride, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride, and silicon nitride.

8. The semiconductor manufacturing method according to claim 1, characterized in that, The material of either the first diffusion barrier layer or the second diffusion barrier layer is composed of at least two of tantalum nitride, tantalum, and ruthenium.

9. The semiconductor manufacturing method according to claim 1, characterized in that, The deposition of either the first diffusion barrier layer or the second diffusion barrier layer is accomplished by at least one of the following processes: Physical vapor deposition, chemical vapor deposition, atomic layer deposition, and organometallic chemical vapor deposition.

10. The semiconductor manufacturing method according to claim 1, characterized in that, The thickness of either the first diffusion barrier layer or the second diffusion barrier layer is 0.5 nm to 200 nm.

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