A cascode gallium nitride device and chip with integrated capacitor

Abstract

The present application belongs to the field of semiconductor technology and provides a cascode gallium nitride device and chip with integrated capacitors. A stacked nucleation layer, a gallium nitride drift layer, and a barrier layer are formed on the front surface of a semiconductor substrate; a first source metal layer and a first drain metal layer are formed on both sides of the nucleation layer, the gallium nitride drift layer, and the barrier layer; a first gate metal layer is formed on the barrier layer; and a non-contacting source doped region and drain doped region are formed on the back surface of the semiconductor substrate. A P-type doped region and a P-type base region are located between the source doped region and the semiconductor substrate. The first gate metal layer and the second source metal layer are connected by a first metal trace, and a dielectric layer is provided between the first metal trace and the second drain metal layer. Thus, capacitors are integrated within the cascode gallium nitride device, avoiding the problem of capacitance mismatch that occurs when a cascode gallium nitride device is formed by packaging a MOSFET and a GaN device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a cascode gallium nitride device and chip with integrated capacitors. Background Art

[0002] As a representative of third-generation semiconductor materials, gallium nitride (GaN) possesses many excellent properties, including a high critical breakdown field, high electron mobility, high two-dimensional electron gas concentration, and excellent high-temperature operation. GaN cascode devices, due to their high electron mobility and low parasitic capacitance, can achieve very low on-state voltage and switching losses in high-frequency applications.

[0003] However, in order to achieve zero-voltage turn-on in some topological circuits, the source-drain charge of the GaN device must be less than the sum of the output capacitance of the MOSFET device and the gate-source charge of the GaN device. Therefore, if the parasitic charges in the packaged cascode GaN device are mismatched, there will be a risk of avalanche loss. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a cascode GaN device and chip with integrated capacitors, aiming to solve the problem of internal capacitance mismatch in existing cascode GaN devices.

[0005] A first aspect of an embodiment of the present application provides a cascode GaN device with integrated capacitors, the cascode GaN device comprising:

[0006] semiconductor substrates;

[0007] A nucleation layer, a gallium nitride drift layer, and a barrier layer are stacked on the front surface of the semiconductor substrate;

[0008] a first source metal layer and a first drain metal layer, wherein the first source metal layer and the first drain metal layer are respectively provided on both sides of the nucleation layer, the gallium nitride drift layer and the barrier layer;

[0009] a first gate metal layer, disposed on the barrier layer and located between the first source metal layer and the first drain metal layer;

[0010] A drain doping region, a source doping region, a P-type base region, and a P-type doping region are provided on the back side of the semiconductor substrate; wherein the source doping region and the drain doping region do not contact each other, and the P-type doping region and the P-type base region are provided between the source doping region and the semiconductor substrate;

[0011] a second drain metal layer, contacting the drain doped region and connected to the first source metal layer;

[0012] a second source metal layer, contacting the source doped region and connected to the first gate metal layer through a first metal trace; wherein a dielectric layer is provided between the first metal trace and the second drain metal layer to form a matching capacitor;

[0013] A gate dielectric layer and a second gate metal layer; wherein the gate dielectric layer is provided between the second gate metal layer and the P-type base region and the source doped region.

[0014] In one embodiment, the second drain metal layer is connected to the first source metal layer through a first connection metal layer; wherein the first connection metal layer is filled in a first through hole in the semiconductor substrate.

[0015] In one embodiment, the first metal trace includes a first metal field plate layer and a plurality of first interdigitated metal strips, wherein the first interdigitated metal strips are connected to the first metal field plate layer;

[0016] The second drain metal layer includes a second drain field plate layer and a plurality of second drain interdigitated metal strips, and the second drain interdigitated metal strips are connected to the second drain field plate layer;

[0017] The plurality of second drain interdigitated metal strips and the plurality of first interdigitated metal strips are alternately arranged, and the dielectric layer is filled between adjacent second drain interdigitated metal strips and the first interdigitated metal strips.

[0018] In one embodiment, a second gate electrode layer connected to the second gate metal layer is provided on the second gate metal layer, and the first metal trace further includes a plurality of second interdigitated metal strips;

[0019] The second gate electrode layer includes a second gate field plate layer and a plurality of second gate interdigitated metal strips, the second gate interdigitated metal strips are connected to the second gate field plate layer, and dielectric material is provided between the plurality of second gate interdigitated metal strips and the second interdigitated metal strips.

[0020] In one embodiment, the dielectric material is further disposed between the second gate interdigitated metal strips and the second drain metal layer.

[0021] In one embodiment, a first gate electrode layer connected to the first gate metal layer is provided on the first gate metal layer, and a first drain electrode layer connected to the first drain metal layer is provided on the first drain metal layer;

[0022] Wherein, an interdigital capacitor is formed between the first gate electrode layer and the first drain electrode layer.

[0023] In one embodiment, the first gate electrode layer includes a first gate field plate layer and a plurality of first gate interdigitated metal strips, wherein the first gate interdigitated metal strips are connected to the first gate field plate layer;

[0024] The first drain electrode layer includes a first drain field plate layer and a plurality of first drain interdigitated metal strips, wherein the first drain interdigitated metal strips are connected to the first drain field plate layer;

[0025] The plurality of first drain interdigital metal strips and the plurality of first gate interdigital metal strips are alternately arranged, and a dielectric material is provided between adjacent first drain interdigital metal strips and first gate interdigital metal strips.

[0026] In one embodiment, the dielectric material is silicon oxide.

[0027] In one embodiment, the second drain metal layer is disposed opposite to the first source metal layer.

[0028] A second aspect of an embodiment of the present application further provides a chip, in which the cascode gallium nitride device as described above is integrated.

[0029] Compared with the prior art, the embodiments of the present application have the following beneficial effects: a nucleation layer, a gallium nitride drift layer, and a barrier layer are stacked on the front side of a semiconductor substrate, a first source metal layer and a first drain metal layer are formed on both sides of the nucleation layer, the gallium nitride drift layer, and the barrier layer, a first gate metal layer is formed on the barrier layer, and a source doped region and a drain doped region that do not contact each other are formed on the back side of the semiconductor substrate, and the P-type doped region and the P-type base region are located between the source doped region and the semiconductor substrate, the first gate metal layer and the second source metal layer are connected by a first metal trace, and a dielectric layer is provided between the first metal trace and the second drain metal layer, thereby integrating capacitance in a cascode gallium nitride device, thereby avoiding the problem of capacitance mismatch when a cascode gallium nitride device is formed by packaging a MOSFET and a GaN device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of a vertical cross-section structure of a cascode GaN device provided by one embodiment of the present application;

[0031] Figure 2 is a schematic diagram of a matching capacitor provided by an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of the second gate electrode layer and the first metal trace provided by one embodiment of the present application;

[0033] Figure 4This is a schematic diagram of a first gate electrode layer and a first drain electrode layer provided in one embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0035] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0036] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0038] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0039] Because cascode GaN devices have high electron mobility and small parasitic capacitance, they are expected to achieve very low conduction and switching losses in high-frequency applications. When used in some topological circuits, certain conditions must be met to achieve zero-voltage turn on (ZVS). Namely, the source-drain charge of the GaN device must be less than the sum of the output capacitance of the MOSFET and the gate-source charge of the GaN device. Otherwise, even if ZVS is achieved in the switching waveform, internal losses will still occur during the turn-on process, thus not truly zero-voltage turn on.

[0040] Because the charge on the MOSFET's output capacitance is smaller than the sum of the GaN device's gate-source charge, Qgs, and its source-drain charge, Qds, during the turn-on process of the cascode GaN device, the GaN device's source-drain charge, Qds, and the excess charge on the GaN device will be consumed through the GaN HEMT's two-dimensional electron gas (2DEG) channel, resulting in turn-on losses. Similarly, if the charges are mismatched, during the turn-off process of the cascode GaN device, because the charge on the MOSFET's output capacitance and the GaN device's gate-source charge, Qgs, are relatively small, the excess charge that continues to charge the GaN device's source-drain capacitance will pass through the MOSFET's body diode, resulting in avalanche losses.

[0041] In order to solve the above technical problems, the present invention provides a cascode GaN device with integrated capacitors. Figure 1 As shown, the cascode GaN device in this embodiment includes: a semiconductor substrate 100, a nucleation layer 110, a GaN drift layer 120, a barrier layer 130, a first source metal layer 160, a first drain metal layer 140, a first gate metal layer 150, a drain doping region 280, a source doping region 220, a P-type base region 210, a P-type doping region 220, a second drain metal layer 270, a second source metal layer 260, a gate dielectric layer 240, and a second gate metal layer 250.

[0042] In this embodiment, the nucleation layer 110, the gallium nitride drift layer 120, and the barrier layer 130 are stacked on the front surface of the semiconductor substrate 100, the first source metal layer 160 and the first drain metal layer 140 are respectively arranged on both sides of the nucleation layer 110, the gallium nitride drift layer 120, and the barrier layer 130, and the first gate metal layer 150 is arranged on the barrier layer 130, and the first gate metal layer 150 is located between the first source metal layer 160 and the first drain metal layer 140.

[0043] The drain doping region 280, the source doping region 220, the P-type base region 210 and the P-type doping region 230 are arranged on the back side of the semiconductor substrate 100. The source doping region 220 and the drain doping region 280 do not contact each other, and the P-type doping region 230 and the P-type base region 210 are arranged between the source doping region 220 and the semiconductor substrate 100. The second drain metal layer 270 contacts the drain doping region 280. The second drain metal layer 270 is also connected to the first source metal layer 160. The second source metal layer 260 contacts the source doping region 220, and the second source metal layer 260 is connected to the first gate metal layer 150 through the first metal wiring 350. A dielectric layer 290 is provided between the first metal wiring 350 and the second drain metal layer 270 to form a matching capacitor. The gate dielectric layer 290 is provided between the second gate metal layer 250 and the P-type base region 210 and the source doping region 220.

[0044] In this embodiment, a stacked nucleation layer 110, a gallium nitride drift layer 120, and a barrier layer 130 are formed on the front surface of the semiconductor substrate 100, a first source metal layer 160 and a first drain metal layer 140 are formed on both sides of the nucleation layer 110, the gallium nitride drift layer 120, and the barrier layer 130, a first gate metal layer 150 is formed on the barrier layer 130, and a source doping region 220 and a drain doping region 280 that do not contact each other are formed on the back surface of the semiconductor substrate 100, and a P-type The doped region 230 and the P-type base region 210 are located between the source doped region 220 and the semiconductor substrate 100. The first gate metal layer 150 and the second source metal layer 260 are connected via a first metal trace 350. A dielectric layer 290 is provided between the first metal trace 350 and the second drain metal layer 270. This integrates capacitance within the cascode GaN device, thereby avoiding the capacitance mismatch problem that occurs when a cascode GaN device is formed by packaging a MOSFET and a GaN device.

[0045] In one embodiment, the semiconductor substrate 100 is made of P-type silicon material.

[0046] In this embodiment, the concentration of the P-type dopant ions in the semiconductor substrate 100 is lower than the concentration of the P-type dopant ions in the P-type base region 210 .

[0047] In one embodiment, the P-type dopant ions may be aluminum ions or magnesium ions.

[0048] In one embodiment, the dielectric layer 290 may be silicon oxide, and the matching capacitor formed between the first metal trace 350 and the second drain metal layer 270 is a metal oxide metal (MOM) capacitor.

[0049] In one embodiment, the nucleation layer 110 may be made of aluminum nitride (AlN) material.

[0050] In one embodiment, the gallium nitride drift layer 120 may be made of gallium nitride material.

[0051] In one embodiment, the barrier layer 130 may be made of aluminum gallium nitride (AlGaN) material.

[0052] In one embodiment, a P-type base region 210 can be formed by injecting P-type dopant ions into the back side of the semiconductor substrate 100 at a position opposite to the first drain metal layer 140, and then injecting P-type dopant ions with a higher concentration into a portion of the P-type base region 210 to form a P-type dopant region 230 adjacent to the P-type base region 210.

[0053] In one embodiment, the P-type base region 210 has an L-shaped structure, and the source doped region 220 is located between the vertical portion of the P-type base region 210 and the P-type doped region 230 .

[0054] In one embodiment, the thickness of the P-type doping region 230 is equal to the thickness of the P-type base region 210 .

[0055] In this embodiment, the gate dielectric layer 240 is located on a portion of the surface of the vertical portion of the P-type base region 210 and a portion of the surface of the source doped region 220 , and the gate dielectric layer 240 and the second source metal layer 260 are not in contact with each other.

[0056] In one embodiment, N-type doping ions are implanted into a partial area adjacent to the P-type doping region 230 to form a source doping region 220 in the P-type base region 210. The thickness of the source doping region 220 is less than the thickness of the P-type base region 210, the width of the source doping region 220 is less than the width of the P-type base region 210, and the source doping region 220 is adjacent to the P-type doping region 230.

[0057] In one embodiment, the concentration of the P-type dopant ions in the P-type doping region 230 is greater than the concentration of the P-type dopant ions in the P-type base region 210 .

[0058] In one embodiment, see Figure 1 As shown, the second drain metal layer 270 is connected to the first source metal layer 160 through the first connection metal layer 301 , and the first connection metal layer 301 is filled in the first through hole in the semiconductor substrate 100 .

[0059] In this embodiment, the first source metal layer 160 and the first drain metal layer 140 are located on the front side of the semiconductor substrate 100 and form a GaN HEMT device together with the nucleation layer 110, the gallium nitride drift layer 120, the barrier layer 130, and the first gate metal layer 150 on the front side of the semiconductor substrate 100. Then, the source doped region 220, the drain doped region 280, the P-type doped region 230, and the P-type base region 210 on the back side of the semiconductor substrate 100 form a MOSFET device. The second drain metal layer 270 is connected to the first source metal layer 160 via the first connecting metal layer 301. The second source metal layer 260 is connected to the first gate metal layer 150 via the first metal trace 350 to form a cascode gallium nitride device.

[0060] In one embodiment, the first metal trace 350 is connected to the first gate metal layer 150 through the second metal trace 302. The second metal trace 302 can be arranged in parallel with the first connection metal layer 301, and the second metal trace 302 can also be electrically connected on the front and back sides of the semiconductor substrate 100 through the second through hole in the semiconductor substrate 100.

[0061] In one embodiment, the second metal trace 302 is parallel to the semiconductor substrate 100, and the second metal trace 302 and the second drain metal layer 280 are at different horizontal planes, thereby forming a parasitic matching capacitor within the device by forming a dielectric layer 290 between the second metal trace 302 and the second drain metal layer 280.

[0062] In one embodiment, see Figure 2 As shown, the first metal trace 350 includes a first metal field plate layer 351 and a plurality of first interdigitated metal strips 352 , and the first interdigitated metal strips 352 are connected to the first metal field plate layer 351 . The second drain metal layer 270 includes a second drain field plate layer 271 and a plurality of second drain interdigitated metal strips 272 , and the second drain interdigitated metal strips 272 are connected to the second drain field plate layer 271 .

[0063] In this embodiment, a plurality of second drain interdigitated metal strips 272 and a plurality of first interdigitated metal strips 252 are alternately arranged, and a dielectric layer 290 is filled between adjacent second drain interdigitated metal strips 272 and first interdigitated metal strips 352, thereby forming a matching capacitor between the second drain metal layer and the second source metal layer 260.

[0064] In one embodiment, see Figure 1 and Figure 3 As shown, a second gate electrode layer 340 connected to the second gate metal layer 250 is provided on the second gate metal layer 250 , and the first metal trace 350 further includes a plurality of second interdigitated metal strips 353 .

[0065] In this embodiment, the second gate electrode layer 340 includes a second gate field plate layer 341 and a plurality of second gate interdigitated metal strips 342. The second gate interdigitated metal strips 342 are connected to the second gate field plate layer 341. A dielectric material is provided between the plurality of second gate interdigitated metal strips 342 and the second interdigitated metal strips 353, thereby forming a gate-source matching capacitor between the second gate metal layer 240 and the second source metal layer 260.

[0066] In one embodiment, a dielectric material is further disposed between the second gate interdigitated metal strips 342 and the second drain metal layer 270 .

[0067] In this embodiment, see Figure 3 As shown, a gate-drain matching capacitor is formed between the second gate interdigitated metal strip 342 and the second source metal layer 270 by filling a dielectric material.

[0068] In one embodiment, see Figure 1 As shown, a first gate electrode layer 330 connected to the first gate metal layer 150 is provided on the first gate metal layer 150 , and a first drain electrode layer 320 connected to the first drain metal layer 140 is provided on the first drain metal layer 140 .

[0069] In this embodiment, an interdigital capacitor is formed between the first gate electrode layer 330 and the first drain electrode layer 320 .

[0070] In one embodiment, see Figure 4 As shown, the first gate electrode layer 330 includes a first gate field plate layer 321 and a plurality of first gate interdigitated metal strips 322, and the first gate interdigitated metal strips 322 are connected to the first gate field plate layer 321. The first drain electrode layer 320 includes a first drain field plate layer 321 and a plurality of first drain interdigitated metal strips 322, and the first drain interdigitated metal strips 321 are connected to the first drain field plate layer 322.

[0071] In this embodiment, a plurality of first drain interdigitated metal strips 321 and a plurality of first gate interdigitated metal strips 322 are alternately arranged, and a dielectric material is provided between adjacent first drain interdigitated metal strips 321 and first gate interdigitated metal strips 322, thereby forming a gate-drain matching capacitor between the drain and gate of the GaN HEMT device.

[0072] In one embodiment, the dielectric material may be silicon oxide or silicon nitride.

[0073] In one embodiment, the second drain metal layer 270 is disposed opposite to the first source metal layer 160 .

[0074] In this embodiment, the second drain metal layer 270 and the first source metal layer 160 are respectively located on opposite sides of the semiconductor substrate 100, and the second drain metal layer 270 and the first source metal layer 160 are respectively located on both sides of the first through hole in the semiconductor substrate 100, and the second drain metal layer 270 and the first source metal layer 160 are connected by the first metal connection layer 301.

[0075] In one embodiment, the first through-hole is perpendicular to the front and back surfaces of the semiconductor substrate 100 .

[0076] An embodiment of the present application further provides a chip, in which the cascode gallium nitride device as described in any of the above embodiments is integrated.

[0077] In one embodiment, the chip integrates a cascode GaN device manufactured using the manufacturing method described in the above embodiment.

[0078] In this embodiment, the chip includes a chip substrate, on which one or more cascode GaN devices are provided. The cascode GaN devices can be prepared by the preparation method of any of the above embodiments, or the cascode GaN devices of any of the above embodiments can be provided on the chip substrate.

[0079] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with the cascode GaN device.

[0080] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0081] Compared with the prior art, the embodiments of the present application have the following beneficial effects: a nucleation layer, a gallium nitride drift layer, and a barrier layer are stacked on the front side of a semiconductor substrate, a first source metal layer and a first drain metal layer are formed on both sides of the nucleation layer, the gallium nitride drift layer, and the barrier layer, a first gate metal layer is formed on the barrier layer, and a source doped region and a drain doped region that do not contact each other are formed on the back side of the semiconductor substrate, and the P-type doped region and the P-type base region are located between the source doped region and the semiconductor substrate, the first gate metal layer and the second source metal layer are connected by a first metal trace, and a dielectric layer is provided between the first metal trace and the second drain metal layer, thereby integrating capacitance in a cascode gallium nitride device, thereby avoiding the problem of capacitance mismatch when a cascode gallium nitride device is formed by packaging a MOSFET and a GaN device.

[0082] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0083] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0084] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A cascode GaN device with integrated capacitor, characterized in that: The cascode GaN device comprises: semiconductor substrates; A nucleation layer, a gallium nitride drift layer, and a barrier layer are stacked on the front surface of the semiconductor substrate; a first source metal layer and a first drain metal layer, wherein the first source metal layer and the first drain metal layer are respectively provided on both sides of the nucleation layer, the gallium nitride drift layer and the barrier layer; a first gate metal layer, disposed on the barrier layer and located between the first source metal layer and the first drain metal layer; A drain doping region, a source doping region, a P-type base region, and a P-type doping region are provided on the back side of the semiconductor substrate; wherein the source doping region and the drain doping region do not contact each other, and the P-type doping region and the P-type base region are provided between the source doping region and the semiconductor substrate; a second drain metal layer, contacting the drain doped region and connected to the first source metal layer; a second source metal layer, contacting the source doped region and connected to the first gate metal layer through a first metal trace; wherein a dielectric layer is provided between the first metal trace and the second drain metal layer to form a matching capacitor; A gate dielectric layer and a second gate metal layer; wherein the gate dielectric layer is provided between the second gate metal layer and the P-type base region and the source doped region.

2. The cascode GaN device according to claim 1, wherein: The second drain metal layer is connected to the first source metal layer through a first connection metal layer; wherein the first connection metal layer is filled in a first through hole in the semiconductor substrate.

3. The cascode GaN device according to claim 1, wherein: The first metal trace includes a first metal field plate layer and a plurality of first interdigitated metal strips, wherein the first interdigitated metal strips are connected to the first metal field plate layer; The second drain metal layer includes a second drain field plate layer and a plurality of second drain interdigitated metal strips, and the second drain interdigitated metal strips are connected to the second drain field plate layer; The plurality of second drain interdigitated metal strips and the plurality of first interdigitated metal strips are alternately arranged, and the dielectric layer is filled between adjacent second drain interdigitated metal strips and the first interdigitated metal strips.

4. The cascode GaN device according to claim 3, wherein: A second gate electrode layer connected to the second gate metal layer is provided on the second gate metal layer, and the first metal trace further includes a plurality of second interdigitated metal strips; The second gate electrode layer includes a second gate field plate layer and a plurality of second gate interdigitated metal strips, the second gate interdigitated metal strips are connected to the second gate field plate layer, and dielectric material is provided between the plurality of second gate interdigitated metal strips and the second interdigitated metal strips.

5. The cascode GaN device according to claim 4, wherein: The dielectric material is also disposed between the second gate interdigitated metal strips and the second drain metal layer.

6. The cascode GaN device according to any one of claims 1 to 5, wherein: A first gate electrode layer connected to the first gate metal layer is provided on the first gate metal layer, and a first drain electrode layer connected to the first drain metal layer is provided on the first drain metal layer; Wherein, an interdigital capacitor is formed between the first gate electrode layer and the first drain electrode layer.

7. The cascode GaN device according to claim 6, wherein: The first gate electrode layer includes a first gate field plate layer and a plurality of first gate interdigitated metal strips, wherein the first gate interdigitated metal strips are connected to the first gate field plate layer; The first drain electrode layer includes a first drain field plate layer and a plurality of first drain interdigitated metal strips, wherein the first drain interdigitated metal strips are connected to the first drain field plate layer; The plurality of first drain interdigital metal strips and the plurality of first gate interdigital metal strips are alternately arranged, and a dielectric material is provided between adjacent first drain interdigital metal strips and first gate interdigital metal strips.

8. The cascode GaN device according to claim 4 or 7, wherein: The dielectric material is silicon oxide.

9. The cascode GaN device according to any one of claims 1 to 5, wherein: The second drain metal layer is arranged opposite to the first source metal layer.

10. A chip, characterized in that: The chip integrates the cascode GaN device according to any one of claims 1 to 9.

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