SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure with second-order oxide layer and preparation process thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a SiC MOSFET structure with a second-order oxide layer and a preparation process thereof. BACKGROUND

[0002] Traditional SiC MOSFET devices often face the contradictory problem between the concentration of the electric field below the gate oxide, the limited breakdown voltage and the on-resistance in high-voltage applications. The existing technology attempts to improve device performance through single doping or structure optimization, but it is still difficult to effectively suppress the electric field peak while improving the withstand voltage, reducing the on-resistance and ensuring the reliability of the gate oxide, which restricts the performance of the device in high-temperature, high-frequency and high-power applications.

[0003] The existing patent discloses a SiC MOSFET structure with a second-order oxide layer (publication number CN115832025A), which increases the thickness of the oxide layer at the center above the JFET region based on the conventional SiC MOSFET structure, forming a second-order oxide layer structure. The second-order oxide layer structure in the existing patent only improves the UIS reliability by locally thickening the gate oxide above the JFET region, but does not fully optimize the overall electrical performance of the device. This is specifically embodied in the following aspects: the comparative structure cannot effectively suppress the electric field peak directly below the gate, cannot significantly reduce the specific on-resistance, cannot improve the uniformity of the lateral withstand voltage, and also does not provide a low-resistance vertical current path and a high-frequency switching performance enhancement mechanism, resulting in that it only improves the reliability in limited scenarios, but lacks a substantial improvement in comprehensive performance. SUMMARY

[0004] The present application provides a SiC MOSFET structure with a second-order oxide layer and a preparation process thereof to solve the existing technical problems, which solves the problem of difficult to effectively suppress the electric field peak while improving the withstand voltage.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a SiC MOSFET structure with a second-order oxide layer, comprising a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a source and a gate oxide layer, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, a P+ layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of a single MOS cell by ion implantation, and the N-doped layer is located directly below the gate. The inside of the N-doped layer is formed with a plurality of non-contact doped N+ isolation layers by ion implantation.

[0006] Further, the doped N+ isolation layers are arranged in a row.

[0007] Further, the gate oxide layer is a second-order oxide layer.

[0008] Further, the N-doped layer further comprises a contact doped layer, a bottom end of the contact doped layer is in direct contact with the N-substrate layer, and a top end of the contact doped layer is in direct contact with the gate oxide layer.

[0009] Further, the N-doped layer further comprises a through doped layer, a bottom end of the through doped layer is in contact with the drain ohmic contact, and a top end of the through doped layer is in direct contact with the gate oxide layer.

[0010] Further, the N-drift layer is covered with an N+ doped layer in the inside and on the surface of the N-doped layer, and a top end of the N+ doped layer is in direct contact with the gate oxide layer.

[0011] Further, the N-drift layer further comprises a covering drift layer, the covering drift layer is located between two adjacent P-well layers, and a cross-sectional profile of the covering drift layer is in a "U" shape.

[0012] Further, a bottom end of the covering drift layer in a single MOS cell is formed with two contact P-layers by ion implantation, and bottom ends of the two contact P-layers are both in contact with the drain ohmic contact.

[0013] A preparation process of a SiC MOSFET structure with a second-order oxide layer, specifically comprising the following steps: S1, epitaxially growing an N-drift layer on an N-substrate layer; S2, forming P-well layers and N-well layers in the N-drift layer by a photoetching and ion implantation process; S3, forming P+ layers in the P-well layers by ion implantation; S4, forming an N-doped layer in the N-drift layer by ion implantation, and injecting a plurality of doped N+ isolation layers in the inside of the N-doped layer and not in contact with each other; S5, forming a covering drift layer in the N-drift layer between two adjacent P-well layers by ion implantation, and the cross-sectional profile of the covering drift layer is in a "U" shape; S6, forming two contact P-layers at a bottom end of the covering drift layer by ion implantation, and bottom ends of the two contact P-layers are in contact with a subsequently formed drain ohmic contact; S7, growing a second-order gate oxide layer on the surface of the structure; S8, forming a gate electrode on the gate oxide layer, forming a source electrode on the front surface of the structure, and forming a drain electrode on the back surface, and completing the preparation of the device.

[0014] The SiC MOSFET structure with a second-order oxide layer and the preparation process thereof provided by the application have the following effects compared with the prior art: 1. The present invention effectively modulates the electric field distribution under the gate oxide and suppresses the electric field spike by introducing an N-doped layer located directly below the gate and an N+ doped isolation layer arranged and distributed inside the gate oxide, thereby significantly improving the breakdown voltage of the device and enhancing the reliability of the gate oxide layer while maintaining a low specific on-resistance.

[0015] 2. The present invention provides a low-resistance vertical current path from the substrate to the gate oxide layer by setting a contact doping layer in the N-doped layer, thereby optimizing the current flow in the on state, effectively reducing the overall on-resistance of the device, and improving the current transmission capability.

[0016] 3. The present invention establishes a low-resistance channel from the drain directly to the gate oxide layer through the design of penetrating the doped layer, so that part of the current can bypass the traditional high-resistance JFET area, significantly reducing the JFET resistance and further optimizing the conduction characteristics of the device.

[0017] 4. The present invention effectively reduces the interface contact resistance and improves the inversion layer mobility by covering the surface of the N-doped layer with an N+ doped layer, thereby providing good interface conditions for the formation of the accumulation layer, thereby improving the high-frequency switching performance of the device.

[0018] 5. The present invention expands the lateral width of the depletion region by forming a covering drift layer with a "U"-shaped cross-section, alleviates the electric field concentration at the bottom corner of the P-well, makes the electric field distribution more uniform, and significantly improves the lateral voltage withstand capability of the cell without increasing the on-resistance.

[0019] 6. The present invention introduces two contact P-layers in ohmic contact with the drain at the bottom of the "U"-shaped drift layer, which effectively assists in depleting the drift region and enhances the electric field modulation in the blocking state, and works synergistically with the "U"-shaped structure to achieve higher breakdown voltage and better device stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of Example 1 of the present invention; Figure 2 This is a schematic diagram of Example 2 of the present invention; Figure 3 This is a schematic diagram of Example 3 of the present invention; Figure 4 This is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of Example 5 of the present invention; Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0021] In the figure: 1. drain; 2. gate; 3. source; 4. N substrate layer; 5. N drift layer; 6. P+ layer; 7. P well layer; 8. N well layer; 9. doped N+ isolation layer; 10. N- doped layer; 11. gate oxide layer; 12. N+ doped layer; 13. contact P- layer; 101. contact doped layer; 102. through doped layer; 501. covering drift layer. DETAILED DESCRIPTION

[0022] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 6 As shown, a preparation process of a SiC MOSFET structure with a second-order oxide layer specifically includes: Step 1: Epitaxially grow an N drift layer 5 on the N substrate layer 4. This step provides a uniform and high-quality drift region foundation for the subsequent cell structure by precisely controlling the thickness and doping concentration of the N drift layer 5 during the epitaxial growth process. This ensures a balance between the device's withstand voltage performance and conduction characteristics at high voltage, laying the foundation for overall performance optimization.

[0024] Step 2: Form a P-well layer 7 and an N-well layer 8 in the N-drift layer 5 through photolithography and ion implantation processes. Utilize photolithography and ion implantation techniques to achieve precise positioning and doping control of the P-well and N-well regions, forming a well-region interface with a clear structure, effectively improving the threshold voltage stability and channel control capability of the device, and enhancing the isolation between cells and overall reliability.

[0025] Step 3: Form a P+ layer 6 in the P-well layer 7 by ion implantation; the P+ layer is formed by high-concentration P-type ion implantation, which significantly reduces the contact resistance between the source and the P-well, improves the conduction characteristics of the device, and at the same time enhances the electrical contact effect between the body region and the source, thereby improving the current carrying capacity and stability of the device.

[0026] Step 4: An N-doped layer 10 is formed in the N-drift layer 5 by ion implantation, and multiple non-contact doped N+ isolation layers 9 are implanted inside it; this step constructs an N-doped layer directly below the gate and embeds the N+ isolation layer structure, effectively modulating the electric field distribution, suppressing the electric field peak below the gate oxide, significantly improving the breakdown voltage and gate oxide reliability, while maintaining good on-resistance characteristics.

[0027] Step 5: A covering drift layer 501 is formed in the N drift layer 5 between two adjacent P well layers 7 by ion implantation, and its cross-sectional profile is in the shape of a "U"; by forming a covering drift layer with a "U"-shaped cross-section, the lateral width of the depletion region is expanded, the electric field concentration at the corner of the P well is alleviated, the lateral withstand voltage capability is optimized, and the blocking performance of the cell is significantly improved without increasing the on-resistance.

[0028] Step 6: Two contact P-layers 13 are formed at the bottom of the drift layer 501 by ion implantation, and the bottom ends of the two contact P-layers 13 are in ohmic contact with the drain 1 formed subsequently; the P-layer structure in ohmic contact with the drain is introduced to effectively assist in depleting the drift region and enhance the electric field modulation in the blocking state, and synergize with the "U"-shaped drift layer to jointly improve the breakdown voltage and blocking stability of the device without affecting the performance in the on state.

[0029] Step seven: growing a second-order gate oxide layer 11 on the surface of the structure; using a second-order oxide process to grow the gate oxide layer significantly improves the gate oxide interface quality and dielectric uniformity, reduces the interface state density, and enhances the reliability and long-term stability of the device, which is particularly suitable for high-frequency and high-voltage application scenarios.

[0030] Step 8: Form a gate 2 on the gate oxide layer 11, and form a source 3 on the front of the structure and a drain 1 on the back to complete the device preparation. The electrode preparation is completed through the metallization process, achieving good ohmic contact and device interconnection, ensuring uniform current distribution and efficient transmission, and finally forming a SiC MOSFET device with excellent performance and stable structure, and excellent comprehensive electrical characteristics.

[0031] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a SiC MOSFET structure with a second-order oxide layer is provided, including a plurality of mutually parallel MOS cells, wherein a single MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, a source 3, and a gate oxide layer 11, the semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, a P well layer 7, and an N well layer 8, an N-doped layer 10 is formed in the N drift layer 5 of the single MOS cell by ion implantation, and the N-doped layer 10 is located directly below the gate 2; a plurality of mutually non-contact doped N+ isolation layers 9 are formed in the N-doped layer 10 by ion implantation; the doped N+ isolation layers 9 are arranged and distributed; and the gate oxide layer 11 is a second-order oxide layer.

[0032] An N-doped layer 10 with a built-in doped N+ isolation layer 9 is formed in the N-drift layer 5 directly below the gate 2; this structure effectively suppresses the electric field spike under the gate oxide through the redistribution of the electric field by the doped N+ isolation layer 9, thereby significantly improving the breakdown voltage of the device while improving the reliability of the gate oxide layer 11 and achieving a lower specific on-resistance.

[0033] Example 2 like Figure 2As shown, the N-doped layer 10 further includes a contact doped layer 101 . The bottom of the contact doped layer 101 is in direct contact with the N substrate layer 4 , and the top of the contact doped layer 101 is in direct contact with the gate oxide layer 11 .

[0034] By adding a contact doping layer connecting the N substrate layer 4 and the gate oxide layer 11 in the N-doped layer 10, this structure provides a low-resistance vertical current path for the device, optimizes the current flow path when it is turned on, effectively reduces the overall on-resistance of the device, and improves the current density.

[0035] Example 3 like Figure 3 As shown, the N-doped layer 10 further includes a through-doped layer 102 . The bottom of the through-doped layer 102 is in ohmic contact with the drain electrode 1 , and the top of the through-doped layer 102 is in direct contact with the gate oxide layer 11 .

[0036] By forming a through-doped layer in the N-doped layer 10 that extends directly from the drain 1 to the gate oxide layer 11, this design creates a low-resistance channel that penetrates the drift region, allowing part of the current to bypass the high-resistance JFET region and flow directly from the drain 1 to the channel, thereby significantly reducing the JFET resistance and further optimizing the device's conduction performance.

[0037] Example 4 like Figure 4 As shown, the interior of the N drift layer 5 and the surface of the N- doped layer 10 are covered with an N+ doped layer 12 , and the top of the N+ doped layer 12 is in direct contact with the gate oxide layer 11 .

[0038] By covering the surface of the N-doped layer 10 with an N+ doped layer 12; the N+ doped layer 12 can effectively reduce the contact resistance between the N-doped layer 10 and the interface, and provide an excellent interface for the formation of the accumulation layer, thereby improving the inversion layer mobility and switching characteristics of the device, and enhancing the performance in high-frequency applications.

[0039] Example 5 like Figure 5 As shown, the N drift layer 5 further includes a cap drift layer 501 . The cap drift layer 501 is located between two adjacent P well layers 7 , and the cross-sectional profile of the cap drift layer 501 is in a “U” shape.

[0040] A covering drift layer 501 with a "U"-shaped cross-section is formed in the N-drift layer 5 between adjacent P-well layers 7; the "U"-shaped structure expands the lateral width of the depletion region, effectively alleviates the electric field concentration phenomenon at the bottom corner of the P-well layer 7, and makes the lateral distribution of the electric field more uniform, thereby significantly improving the lateral voltage withstand capability of the cell without sacrificing the on-resistance.

[0041] Example 6 As shown in Figure 6 The N-drift layer 5 also includes a covering drift layer 501 between two adjacent P-well layers 7, and the cross-sectional profile of the covering drift layer 501 is in the shape of a "U". The bottom end of the covering drift layer 501 in a single MOS cell is formed by ion implantation with two contact P-layers 13, and the bottom end of the two contact P-layers 13 is in ohmic contact with the drain 1.

[0042] By introducing two contact P-layers 13 in ohmic contact with the drain 1 at the bottom of the "U" shaped covering drift layer 501, the two contact P-layers 13 can be depleted when the device is turned on, and almost do not affect the on-resistance, but when the device is blocked, they can effectively assist in depleting the "U" shaped drift region below, and strengthen the modulation of the electric field, thereby achieving higher breakdown voltage and better stability in cooperation with the "U" shaped structure.

[0043] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A SiC MOSFET structure with a second-order oxide layer, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a semiconductor epitaxial layer, a gate (2), a source (3) and a gate oxide layer (11), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a P+ layer (6), a P well layer (7) and an N well layer (8), and wherein: An N-doping layer (10) is formed in the N drift layer (5) of a single MOS cell by ion implantation, and the N-doping layer (10) is located directly below the gate (2); A plurality of mutually non-contacting doped N+ isolation layers (9) are formed inside the N-doped layer (10) by ion implantation.

2. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The doped N+ isolation layers (9) are arranged and distributed.

3. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The gate oxide layer (11) is a second-order oxide layer.

4. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The N-doped layer (10) further comprises a contact doped layer (101), the bottom end of the contact doped layer (101) is in direct contact with the N substrate layer (4), and the top end of the contact doped layer (101) is in direct contact with the gate oxide layer (11).

5. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The N-doped layer (10) further includes a through-doped layer (102), the bottom end of the through-doped layer (102) is in ohmic contact with the drain (1), and the top end of the through-doped layer (102) is in direct contact with the gate oxide layer (11).

6. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The interior of the N drift layer (5) and the surface of the N- doped layer (10) are covered with an N+ doped layer (12), and the top of the N+ doped layer (12) is in direct contact with the gate oxide layer (11).

7. The SiC MOSFET structure with a second-order oxide layer according to claim 1, wherein: The N drift layer (5) further comprises a covering drift layer (501), the covering drift layer (501) being located between two adjacent P well layers (7), and the cross-sectional profile of the covering drift layer (501) being in a "U" shape.

8. The SiC MOSFET structure with a second-order oxide layer according to claim 7, wherein: Two contact P-layers (13) are formed at the bottom of the drift layer (501) in a single MOS cell by ion implantation, and the bottoms of the two contact P-layers (13) are both in ohmic contact with the drain (1).

9. A process for preparing a SiC MOSFET structure having a second-order oxide layer, characterized in that: The SiC MOSFET structure with a second-order oxide layer as claimed in claim 8, wherein the preparation process of the SiC MOSFET structure with a second-order oxide layer specifically comprises: S1. epitaxially growing an N drift layer (5) on an N substrate layer (4); S2, forming a P-well layer (7) and an N-well layer (8) in the N-drift layer (5) through photolithography and ion implantation processes; S3, forming a P+ layer (6) in the P well layer (7) by ion implantation; S4, forming an N-doped layer (10) in the N drift layer (5) by ion implantation, and implanting a plurality of mutually non-contacting doped N+ isolation layers (9) therein; S5, forming a covering drift layer (501) in the N drift layer (5) between two adjacent P well layers (7) by ion implantation, wherein the cross-sectional profile thereof is in a "U" shape; S6. Forming two contact P-layers (13) at the bottom of the covering drift layer (501) by ion implantation, and making the bottoms of the two contact P-layers (13) in ohmic contact with the drain (1) formed subsequently; S7, growing a second-order gate oxide layer (11) on the surface of the structure; S8. Forming a gate electrode (2) on the gate oxide layer (11), forming a source electrode (3) on the front side of the structure, and forming a drain electrode (1) on the back side, thereby completing the device preparation.

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