Rapid verification of VCSEL epitaxial wafer process

Abstract

The present invention discloses a process method for quickly verifying VCSEL epitaxial wafers, specifically: deposit a passivation layer on the front of the epitaxial wafer, perform the first MESA lithography on the front to form a MESA layer, then use an ICP etcher to etch, expose the high aluminum layer, and then perform wet oxidation; then perform a second lithography to expose a 15-25 micron ring, the inner diameter area of ​​the ring is a light outlet, so that the morphology of the lithography is wide below and narrow above, and finally perform ICP etching to etch off the passivation layer, etch to the P-type ohmic contact layer of the epitaxial wafer, evaporate metal and anneal after completion, and now the front and back sides form a relatively good ohmic contact. The method of the present invention quickly verifies the quality of the purchased epitaxial wafer, saving verification time and cost; the electrical data of the rapid verification of the chip factory is fed back to the epitaxial plant, and the epitaxial plant can quickly optimize the epitaxial structure, shorten the product development cycle, and enhance the product competitiveness of the epitaxial plant.

Description

Technical Field

[0001] The invention belongs to the technical field of chip processing methods, and in particular relates to a process method for quickly verifying a VCSEL epitaxial wafer. Background Art

[0002] After the growth of GaAs-based VCSEL epitaxial wafers is completed, the epitaxial manufacturer only provides the wavelength and surface granularity parameters of the epitaxial wafers, and cannot provide the electrical parameters of the epitaxial wafers, such as voltage, optical power, threshold current, etc. For chip manufacturers, the parameters provided by the epitaxial manufacturer cannot verify the quality of the epitaxial wafers. The chip manufacturer can only test its performance after tape-out, that is, verify the quality of the epitaxial wafers.

[0003] After the chip factory gets the VCSEL epitaxial wafer, it usually takes 15-20 days to tape out and test electrical data, such as voltage, optical power, electro-optical conversion efficiency, threshold current and other parameters, and to check the quality of the epitaxial wafer based on the electrical data. If the electrical data meets expectations, the chip factory quickly feeds back to the epitaxial manufacturer, and the epitaxial manufacturer adjusts the epitaxial process based on the electrical results to obtain a better epitaxial wafer; if the electrical properties do not meet expectations, the chip does not lasing or the electrical properties are very poor, then the epitaxial manufacturer waits for 15-20 days before getting the results. For adjusting the epitaxial process, the time period is too long, which is not conducive to improving the epitaxial process. Therefore, a very fast chip process is needed to manufacture chips in a very short time (1-3 days), test their electrical properties, and then quickly feed back to the epitaxial manufacturer, which adjusts and optimizes the epitaxial process based on the tested electrical properties, which is conducive to improving the competitiveness of epitaxial manufacturers and shortening the R&D cycle.

[0004] Conventional VCSEL chip manufacturing processes have nearly 100 steps, and the photolithography process has 8-9 steps. In order to obtain a very high chip yield, the chip manufacturing cycle is long and the process is very complicated, but this is not conducive to quickly verifying the quality of epitaxial wafers. For chip factories, it is a very urgent task to develop a process flow with a very short manufacturing cycle, which can quickly verify the quality of purchased epitaxial wafers and save time and cost. Summary of the invention

[0005] The purpose of the present invention is to provide a process method for quickly verifying a VCSEL epitaxial wafer, thereby solving the problem that the cycle of the existing epitaxial wafer verification process method is too long.

[0006] The technical solution adopted by the present invention is: a process method for quickly verifying VCSEL epitaxial wafers, and the specific operation steps are as follows:

[0007] Step 1, cleaning the epitaxial wafer with a cleaning solution, wherein the epitaxial wafer structure from bottom to top is: substrate, buffer layer, N-type doped DBR layer, quantum well, high aluminum layer, P-type doped DBR layer and ohmic contact layer;

[0008] Step 2: Place the epitaxial wafer cleaned in step 1 in a PECVD machine, and deposit a passivation layer on the front of the epitaxial wafer, wherein the passivation layer is a Si3N4 or SiO2 film;

[0009] Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it;

[0010] Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation;

[0011] Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue and positive photoresist or negative photoresist to photolithograph a 15-25 micron ring. The inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top;

[0012] Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, and etch to the P-type ohmic contact layer of the epitaxial wafer. After taking it out from the ICP etching machine, put it into an acidic liquid for cleaning. The cleaned epitaxial wafer is put into the evaporation machine, and Ti / Pt / Au is evaporated on the front side. After the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side. After the evaporation is completed, the adhesive is removed and cleaned;

[0013] Step 7: After completing step 6, place the epitaxial wafer in a rapid annealing furnace for annealing, at which point a relatively good ohmic contact is formed between the front and back surfaces;

[0014] Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

[0015] The present invention is also characterized in that:

[0016] The cleaning solution in step 1 includes any one of acetone, isopropanol and deionized water.

[0017] The thickness of the passivation layer in step 2 is 10nm-40nm; the deposition temperature is 250℃-350℃.

[0018] The wet oxidation in step 4 is carried out for 1-2 hours at a temperature of 300-450° C. and a water vapor flow rate of 1-3 L / min, with an oxidation rate of 0.5-1 um / min.

[0019] The LOR glue applied in step 5 is a water-soluble photoresist, model number SUN-LOR001.

[0020] The annealing temperature of step 7 is 300° C.-500° C., and the annealing time is 60s-300s.

[0021] The beneficial effects of the present invention are:

[0022] (1) The new process flow shortens the chip manufacturing cycle, using 2 photolithography steps, 1 etching step, and 1 passivation film.

[0023] (2) Chip factories can quickly verify the quality of purchased epitaxial wafers, saving verification time and costs.

[0024] (3) The chip factory quickly verifies the electrical data and feeds it back to the epitaxial plant, which can quickly optimize the epitaxial structure, shorten the product development cycle, and enhance the competitiveness of the epitaxial plant's products. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a SEM image of a VCSEL chip prepared using conventional technology;

[0026] Figure 2 This is the manufacturing flow chart of a conventional VCSEL chip;

[0027] Figure 3 This is a structural diagram of the invention for quickly verifying the process preparation of VCSEL chips;

[0028] FIG4( a ) is a LIV curve diagram of a VCSEL chip (thinning + back gold) obtained by conventional process;

[0029] FIG. 4( b ) is a LIV curve diagram of a chip (not thinned + back gold) obtained by the process of the present invention. DETAILED DESCRIPTION

[0030] The process method for rapidly verifying a VCSEL epitaxial wafer of the present invention is specifically implemented according to the following steps:

[0031] Step 1, cleaning the epitaxial wafer with a cleaning solution, wherein the epitaxial wafer structure is, from bottom to top, a substrate, a buffer layer, an N-type doped DBR layer, a quantum well, a high aluminum layer, a P-type doped DBR layer, and an ohmic contact layer; the cleaning solution in step 1 includes any one of acetone, isopropanol, and deionized water;

[0032] Step 2: Place the epitaxial wafer cleaned in step 1 in a PECVD machine, and deposit a passivation layer, i.e., Si3N4 or SiO2 film, on the front of the epitaxial wafer; the thickness of the passivation layer in step 2 is 10nm-40nm; and the deposition temperature is 250℃-350℃;

[0033] Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it;

[0034] Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation; wet oxidation for 1-2 hours, at a temperature of 300-450° C., a water vapor flow rate of 1-3 L / min, and an oxidation rate of 0.5-1 um / min;

[0035] Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue in combination with positive photoresist or negative photoresist to photolithograph a 15-25 micron ring. The inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top; LOR glue is a water-soluble photoresist, model SUN-LOR001;

[0036] Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, etch to the epitaxial P-type ohmic contact layer, take it out from the ICP etching machine, put it into an acidic liquid for cleaning, put the cleaned epitaxial wafer into the evaporation machine, and evaporate metal Ti / Pt / Au on the front side; after the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side, and the debonding and cleaning are performed after the evaporation is completed;

[0037] Step 7: After completing step 6, the epitaxial wafer is placed in a rapid annealing furnace for annealing, at which time a relatively good ohmic contact is formed between the front and back surfaces; the annealing temperature in step 7 is 300°C-500°C, and the annealing time is 60s-300s;

[0038] Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

[0039] The present invention will be further described below in conjunction with the embodiments.

[0040] Example 1

[0041] The process method for rapidly verifying a VCSEL epitaxial wafer of the present invention is specifically implemented according to the following steps:

[0042] Step 1, cleaning the epitaxial wafer with a cleaning solution, wherein the epitaxial wafer structure is, from bottom to top, a substrate, a buffer layer, an N-type doped DBR layer, a quantum well, a high aluminum layer, a P-type doped DBR layer, and an ohmic contact layer; the cleaning solution in step 1 includes any one of acetone, isopropanol, and deionized water;

[0043] Step 2: Place the epitaxial wafer cleaned in step 1 in a PECVD machine, and deposit a passivation layer, i.e., Si3N4 or SiO2 film, on the front of the epitaxial wafer; the thickness of the passivation layer in step 2 is 10 nm; and the deposition temperature is 250°C;

[0044] Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it;

[0045] Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation; wet oxidation for 1 hour, at a temperature of 300° C., a water vapor flow rate of 1 L / min, and an oxidation rate of 0.5 um / min;

[0046] Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue and positive photoresist or negative photoresist to photolithograph a 15-micron ring. The inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top;

[0047] Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, expose the ohmic contact layer, take it out from the ICP etching machine, put it into an acidic liquid for cleaning, put the cleaned epitaxial wafer into the evaporation machine, and evaporate metal Ti / Pt / Au on the front side; after the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side, and the debonding and cleaning are performed after the evaporation is completed;

[0048] Step 7: After completing step 6, place the epitaxial wafer in a rapid annealing furnace for annealing, at which time a relatively good ohmic contact is formed between the front and back surfaces; the annealing temperature in step 7 is 300°C, and the annealing time is 60s;

[0049] Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

[0050] Example 2

[0051] The process method for rapidly verifying a VCSEL epitaxial wafer of the present invention is specifically implemented according to the following steps:

[0052] Step 1, cleaning the epitaxial wafer with a cleaning solution, wherein the epitaxial wafer structure is, from bottom to top, a substrate, a buffer layer, an N-type doped DBR layer, a quantum well, a high aluminum layer, a P-type doped DBR layer, and an ohmic contact layer; the cleaning solution in step 1 includes any one of acetone, isopropanol, and deionized water;

[0053] Step 2: Place the epitaxial wafer cleaned in step 1 in a PECVD machine, and deposit a passivation layer, i.e., Si3N4 or SiO2 film, on the front of the epitaxial wafer; the thickness of the passivation layer in step 2 is 40nm; and the deposition temperature is 350°C;

[0054] Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it;

[0055] Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation; wet oxidation for 2 hours, at a temperature of 450° C., a water vapor flow rate of 3 L / min, and an oxidation rate of 1 um / min;

[0056] Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue and positive photoresist or negative photoresist to photolithograph a 15-25 micron ring. The inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top;

[0057] Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, expose the ohmic contact layer, take it out from the ICP etching machine, put it into an acidic liquid for cleaning, put the cleaned epitaxial wafer into the evaporation machine, and evaporate metal Ti / Pt / Au on the front side; after the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side, and the debonding and cleaning are performed after the evaporation is completed;

[0058] Step 7: After completing step 6, the epitaxial wafer is placed in a rapid annealing furnace for annealing, at which time a relatively good ohmic contact is formed between the front and back surfaces; the annealing temperature in step 7 is 300°C-500°C, and the annealing time is 60s-300s;

[0059] Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

[0060] Example 3

[0061] The process method for rapidly verifying a VCSEL epitaxial wafer of the present invention is specifically implemented according to the following steps:

[0062] Step 1, cleaning the epitaxial wafer with a cleaning solution, wherein the epitaxial wafer structure is, from bottom to top, a substrate, a buffer layer, an N-type doped DBR layer, a quantum well, a high aluminum layer, a P-type doped DBR layer, and an ohmic contact layer; the cleaning solution in step 1 includes any one of acetone, isopropanol, and deionized water;

[0063] Step 2: Place the epitaxial wafer cleaned in step 1 in a PECVD machine, and deposit a passivation layer, i.e., Si3N4 or SiO2 film, on the front of the epitaxial wafer; the thickness of the passivation layer in step 2 is 25nm; and the deposition temperature is 300°C;

[0064] Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it;

[0065] Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation; wet oxidation for 1.5 hours, at a temperature of 400° C., a water vapor flow rate of 1-3 L / min, and an oxidation rate of 0.8 um / min;

[0066] Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue and positive photoresist or negative photoresist to photolithograph a 20-micron ring, the inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top;

[0067] Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, expose the ohmic contact layer, take it out from the ICP etching machine, put it into an acidic liquid for cleaning, put the cleaned epitaxial wafer into the evaporation machine, and evaporate metal Ti / Pt / Au on the front side; after the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side, and the debonding and cleaning are performed after the evaporation is completed;

[0068] Step 7: After completing step 6, the epitaxial wafer is placed in a rapid annealing furnace for annealing, at which time a relatively good ohmic contact is formed between the front and back surfaces; the annealing temperature in step 7 is 400°C, and the annealing time is 200s;

[0069] Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

[0070] like Figure 1 The conventional chip structure is shown, and the process flow is briefly shown as follows Figure 2 As shown, there are nearly 100 processes, which have high time and economic costs. The chip structure obtained by the process method of the present application is as follows: Figure 3 As shown, the process only has a dozen steps.

[0071] like Figure 3The figure shows a schematic diagram of the chip structure prepared by the method of the present invention. The structural advantages of the present invention are: 1. No thinning is required, which shortens the tape-out time; 2. The front electrode and the back electrode are evaporated simultaneously and successively, and there is no need to break the vacuum to open the cavity, which shortens the tape-out time; 3. The electrode structure is more simplified, shortening the tape-out process flow and shortening the tape-out time.

[0072] like Figure 4(a)-Figure 4(b) The following are the electrical properties of conventional process flow and the electrical properties of the fast process flow of the present invention. The electrical curves of the two processes after flow are compared through the data in Table 1. The fast process flow of the present invention: the wafer is not ground and thinned. During the electrical test, because the wafer is relatively thick, there will be a thermal effect, resulting in a high voltage, but almost no effect on the optical power.

[0073] According to the electrical property comparison of the two processes, under different current test conditions, the voltage has a different difference Δ. After each rapid process tape-out, the voltage difference Δ is subtracted to obtain the voltage of the conventional process, while the optical power output has hardly changed. In Table 1, under the same current I, the electrical parameters of the rapid process of the present invention are mainly voltage V1 and optical power P1, and the electrical parameters of the conventional process are mainly voltage V2 and optical power P2. ΔV is V2 minus V1, and ΔP is P2 minus P1. For example, the comparison data is based on the working current of 6mA, the voltage difference ΔV is -2.36, and the optical power difference ΔP is almost negligible. Therefore, the electrical properties of the rapid process of the present invention after tape-out are equivalent to those of the conventional process.

[0074] The rapid process of the present invention is a feasible, simple and efficient method for verifying VCSEL epitaxial wafers, and has a very fast timeliness for verifying epitaxial wafers.

[0075] Table 1

[0076]

[0077] Table 1 is a comparison of electrical data between the fast process of the present invention and the conventional process. The output optical power is almost not affected, and only the voltage is affected.

Claims

1. A process method for rapidly verifying VCSEL epitaxial wafers, characterized in that: The specific steps are as follows: Step 1: Clean the epitaxial wafer with a cleaning solution. The epitaxial wafer is cleaned from bottom to top in the following order: It is: substrate, buffer layer, N-type doped DBR layer, quantum well, high aluminum layer, P-type doped DBR layer and ohmic contact layer; Step 2: placing the epitaxial wafer cleaned in step 1 in a PECVD machine, and depositing a passivation layer on the front of the epitaxial wafer, wherein the passivation layer is a Si3N4 or SiO2 film; Step 3: Perform the first MESA photolithography on the front side of the epitaxial wafer processed in step 2 to form a MESA layer on the photoresist layer, and then use an ICP etcher to etch out the MESA table to expose the high aluminum layer, and then perform a degumming and cleaning process to clean it; Step 4: placing the epitaxial wafer cleaned in step 3 in a wet oxidation furnace for wet oxidation; Step 5: Perform the second photolithography on the epitaxial wafer processed in step 4, using LOR glue and positive photoresist or negative photoresist to photolithograph a 15-25 micron ring. The inner diameter area of ​​the ring is the light outlet, so that the photolithography morphology is wide at the bottom and narrow at the top; Step 6: ICP etch the epitaxial wafer after photolithography in step 5, etch off the passivation layer, and etch to the P-type ohmic contact layer of the epitaxial wafer. After taking it out from the ICP etching machine, put it into an acidic liquid for cleaning. The cleaned epitaxial wafer is put into the evaporation machine, and Ti / Pt / Au is evaporated on the front side. After the front metal evaporation is completed, Ni / Ge / Au is evaporated on the back side. After the evaporation is completed, the adhesive is removed and cleaned; Step 7: After completing step 6, the epitaxial wafer is placed in a rapid annealing furnace for annealing, at which time ohmic contact is formed between the front and back surfaces; Step 8: After completing step 7, electrical properties of the epitaxial wafer are tested to obtain electrical properties data of the epitaxial wafer.

2. The process for rapidly verifying a VCSEL epitaxial wafer according to claim 1, characterized in that: The cleaning solution in step 1 includes any one of acetone, isopropanol and deionized water.

3. The process for rapidly verifying VCSEL epitaxial wafer according to claim 1, characterized in that: In step 2, the thickness of the passivation layer is 10nm-40nm; the deposition temperature is 250℃-350℃.

4. The process for rapidly verifying a VCSEL epitaxial wafer according to claim 1, characterized in that: The wet oxidation in step 4 is carried out for 1-2 hours at a temperature of 300-450° C. and a water vapor flow rate of 1-3 L / min, with an oxidation rate of 0.5-1 um / min.

5. The process for rapidly verifying VCSEL epitaxial wafer according to claim 1, characterized in that: The LOR glue applied in step 5 is a water-soluble photoresist, model number is SUN-LOR001.

6. The process for rapid verification of VCSEL epitaxial wafer according to claim 1, characterized in that: Step 7: Annealing temperature is 300°C-500°C, annealing time is 60s-300s.

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